| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.97 | 99.19 | 94.27 | 99.72 | 100.00 | 96.03 | 99.12 | 97.44 |
| T1009 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1772360056 | Aug 23 03:51:08 PM UTC 24 | Aug 23 03:51:10 PM UTC 24 | 13361319 ps | ||
| T1010 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3946472328 | Aug 23 03:51:08 PM UTC 24 | Aug 23 03:51:13 PM UTC 24 | 1421119470 ps | ||
| T146 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.211947629 | Aug 23 03:51:11 PM UTC 24 | Aug 23 03:51:14 PM UTC 24 | 165438001 ps | ||
| T1011 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3213884818 | Aug 23 03:51:12 PM UTC 24 | Aug 23 03:51:14 PM UTC 24 | 56076956 ps | ||
| T1012 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3938830653 | Aug 23 03:51:11 PM UTC 24 | Aug 23 03:51:14 PM UTC 24 | 215598247 ps | ||
| T1013 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1943007016 | Aug 23 03:51:13 PM UTC 24 | Aug 23 03:51:15 PM UTC 24 | 25873100 ps | ||
| T1014 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.4169972948 | Aug 23 03:51:15 PM UTC 24 | Aug 23 03:51:17 PM UTC 24 | 226067037 ps | ||
| T1015 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1007469774 | Aug 23 03:51:16 PM UTC 24 | Aug 23 03:51:17 PM UTC 24 | 13735768 ps | ||
| T1016 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.330403753 | Aug 23 03:51:15 PM UTC 24 | Aug 23 03:51:18 PM UTC 24 | 34253301 ps | ||
| T1017 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2413906071 | Aug 23 03:51:14 PM UTC 24 | Aug 23 03:51:19 PM UTC 24 | 357293316 ps | ||
| T1018 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.61656787 | Aug 23 03:51:18 PM UTC 24 | Aug 23 03:51:20 PM UTC 24 | 37591175 ps | ||
| T1019 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1038013071 | Aug 23 03:51:20 PM UTC 24 | Aug 23 03:51:22 PM UTC 24 | 22911576 ps | ||
| T142 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.48969630 | Aug 23 03:51:20 PM UTC 24 | Aug 23 03:51:24 PM UTC 24 | 667325175 ps | ||
| T1020 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.502307638 | Aug 23 03:51:18 PM UTC 24 | Aug 23 03:51:24 PM UTC 24 | 357127797 ps | ||
| T1021 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2535815564 | Aug 23 03:51:20 PM UTC 24 | Aug 23 03:51:24 PM UTC 24 | 325719199 ps | ||
| T1022 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3867972463 | Aug 23 03:51:23 PM UTC 24 | Aug 23 03:51:24 PM UTC 24 | 44517418 ps | ||
| T103 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.354974839 | Aug 23 03:50:30 PM UTC 24 | Aug 23 03:51:27 PM UTC 24 | 7164269926 ps | ||
| T1023 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2134372227 | Aug 23 03:50:54 PM UTC 24 | Aug 23 03:51:27 PM UTC 24 | 28433702932 ps | ||
| T143 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.4184577962 | Aug 23 03:51:25 PM UTC 24 | Aug 23 03:51:28 PM UTC 24 | 483964979 ps | ||
| T1024 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3725230709 | Aug 23 03:51:25 PM UTC 24 | Aug 23 03:51:29 PM UTC 24 | 33261961 ps | ||
| T1025 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1974330404 | Aug 23 03:51:27 PM UTC 24 | Aug 23 03:51:29 PM UTC 24 | 14684438 ps | ||
| T1026 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.589360663 | Aug 23 03:51:27 PM UTC 24 | Aug 23 03:51:29 PM UTC 24 | 98208447 ps | ||
| T1027 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3519697097 | Aug 23 03:51:25 PM UTC 24 | Aug 23 03:51:29 PM UTC 24 | 1548148029 ps | ||
| T98 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3961208808 | Aug 23 03:51:30 PM UTC 24 | Aug 23 03:51:32 PM UTC 24 | 13816923 ps | ||
| T1028 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1026756627 | Aug 23 03:51:30 PM UTC 24 | Aug 23 03:51:33 PM UTC 24 | 1226710733 ps | ||
| T1029 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.4163000242 | Aug 23 03:51:29 PM UTC 24 | Aug 23 03:51:33 PM UTC 24 | 934012512 ps | ||
| T1030 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3755086160 | Aug 23 03:51:04 PM UTC 24 | Aug 23 03:51:34 PM UTC 24 | 15394966562 ps | ||
| T1031 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1793423171 | Aug 23 03:51:33 PM UTC 24 | Aug 23 03:51:35 PM UTC 24 | 13603622 ps | ||
| T1032 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1191837576 | Aug 23 03:51:30 PM UTC 24 | Aug 23 03:51:36 PM UTC 24 | 1034721135 ps | ||
| T1033 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.287311456 | Aug 23 03:50:38 PM UTC 24 | Aug 23 03:51:37 PM UTC 24 | 29431178175 ps | ||
| T1034 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3074130405 | Aug 23 03:51:10 PM UTC 24 | Aug 23 03:51:40 PM UTC 24 | 3816771144 ps | ||
| T1035 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2558004217 | Aug 23 03:51:35 PM UTC 24 | Aug 23 03:51:40 PM UTC 24 | 1429708696 ps | ||
| T104 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1799633367 | Aug 23 03:50:47 PM UTC 24 | Aug 23 03:51:43 PM UTC 24 | 14079815439 ps | ||
| T105 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2899692177 | Aug 23 03:51:15 PM UTC 24 | Aug 23 03:51:54 PM UTC 24 | 36820905436 ps | ||
| T106 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1933348465 | Aug 23 03:51:25 PM UTC 24 | Aug 23 03:51:58 PM UTC 24 | 14182221358 ps | ||
| T1036 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3425705785 | Aug 23 03:51:30 PM UTC 24 | Aug 23 03:52:01 PM UTC 24 | 7406664930 ps | ||
| T1037 | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1897276867 | Aug 23 03:51:19 PM UTC 24 | Aug 23 03:52:15 PM UTC 24 | 7482821379 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.2305048796 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 2797243313 ps |
| CPU time | 6.76 seconds |
| Started | Aug 23 12:53:09 PM UTC 24 |
| Finished | Aug 23 12:53:17 PM UTC 24 |
| Peak memory | 221780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2305048796 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ throughput_w_partial_write.2305048796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/0.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1226948038 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 7247935286 ps |
| CPU time | 84.1 seconds |
| Started | Aug 23 12:53:31 PM UTC 24 |
| Finished | Aug 23 12:54:57 PM UTC 24 |
| Peak memory | 231128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226948038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.1226948038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/1.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.3996909442 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 200676608 ps |
| CPU time | 1.81 seconds |
| Started | Aug 23 12:53:15 PM UTC 24 |
| Finished | Aug 23 12:53:18 PM UTC 24 |
| Peak memory | 246952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996909442 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_sec_cm.3996909442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.2095222216 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 10348815789 ps |
| CPU time | 150.08 seconds |
| Started | Aug 23 01:01:30 PM UTC 24 |
| Finished | Aug 23 01:04:03 PM UTC 24 |
| Peak memory | 221872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095222216 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_mem_walk.2095222216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/5.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_regwen.3695167534 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 14957490618 ps |
| CPU time | 228.95 seconds |
| Started | Aug 23 12:53:11 PM UTC 24 |
| Finished | Aug 23 12:57:04 PM UTC 24 |
| Peak memory | 368092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695167534 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.3695167534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/0.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.316968140 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 29506357641 ps |
| CPU time | 46.92 seconds |
| Started | Aug 23 12:53:19 PM UTC 24 |
| Finished | Aug 23 12:54:07 PM UTC 24 |
| Peak memory | 221736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316968140 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_escalation.316968140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/1.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.3449398916 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 5774444403 ps |
| CPU time | 64.91 seconds |
| Started | Aug 23 12:53:15 PM UTC 24 |
| Finished | Aug 23 12:54:21 PM UTC 24 |
| Peak memory | 221856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449398916 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_mem_partial_access.3449398916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/0.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3329185414 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 666937701 ps |
| CPU time | 2.12 seconds |
| Started | Aug 23 03:49:08 PM UTC 24 |
| Finished | Aug 23 03:49:11 PM UTC 24 |
| Peak memory | 223840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329 185414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_tl_ intg_err.3329185414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/0.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.2733566297 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 4320320411 ps |
| CPU time | 58.98 seconds |
| Started | Aug 23 12:54:50 PM UTC 24 |
| Finished | Aug 23 12:55:51 PM UTC 24 |
| Peak memory | 228408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733566297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.2733566297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/2.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.3026221652 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 48123825020 ps |
| CPU time | 298.02 seconds |
| Started | Aug 23 12:53:18 PM UTC 24 |
| Finished | Aug 23 12:58:20 PM UTC 24 |
| Peak memory | 211756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026221652 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_partial_ac cess_b2b.3026221652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/1.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_executable.144002614 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 29441979744 ps |
| CPU time | 587.05 seconds |
| Started | Aug 23 12:53:21 PM UTC 24 |
| Finished | Aug 23 01:03:14 PM UTC 24 |
| Peak memory | 386540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144002614 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executable.144002614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/1.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.574169782 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 6254020234 ps |
| CPU time | 65.03 seconds |
| Started | Aug 23 03:20:50 PM UTC 24 |
| Finished | Aug 23 03:21:56 PM UTC 24 |
| Peak memory | 368208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574169782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.574169782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/42.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2145677875 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 14990098157 ps |
| CPU time | 28.43 seconds |
| Started | Aug 23 03:48:56 PM UTC 24 |
| Finished | Aug 23 03:49:26 PM UTC 24 |
| Peak memory | 223696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 145677875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ passthru_mem_tl_intg_err.2145677875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/0.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.2323981611 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1250272465 ps |
| CPU time | 3.25 seconds |
| Started | Aug 23 12:54:42 PM UTC 24 |
| Finished | Aug 23 12:54:47 PM UTC 24 |
| Peak memory | 211644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323981611 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.2323981611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/2.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_regwen.3814616877 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 19626528888 ps |
| CPU time | 318.59 seconds |
| Started | Aug 23 01:09:41 PM UTC 24 |
| Finished | Aug 23 01:15:03 PM UTC 24 |
| Peak memory | 384488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814616877 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.3814616877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/8.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2963255261 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 990309271 ps |
| CPU time | 2.34 seconds |
| Started | Aug 23 03:49:38 PM UTC 24 |
| Finished | Aug 23 03:49:41 PM UTC 24 |
| Peak memory | 223572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963 255261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_ intg_err.2963255261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/3.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all.3323085438 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 104601281744 ps |
| CPU time | 461.54 seconds |
| Started | Aug 23 01:01:49 PM UTC 24 |
| Finished | Aug 23 01:09:35 PM UTC 24 |
| Peak memory | 388648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33230854 38 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all.3323085438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/5.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_alert_test.3877271219 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 45583685 ps |
| CPU time | 0.56 seconds |
| Started | Aug 23 12:53:15 PM UTC 24 |
| Finished | Aug 23 12:53:17 PM UTC 24 |
| Peak memory | 210736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877271219 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_alert_test.3877271219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/0.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3425323777 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 256227703 ps |
| CPU time | 1.3 seconds |
| Started | Aug 23 03:50:43 PM UTC 24 |
| Finished | Aug 23 03:50:46 PM UTC 24 |
| Peak memory | 222772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425 323777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl _intg_err.3425323777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/11.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all.1585500278 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 33510564730 ps |
| CPU time | 2826.56 seconds |
| Started | Aug 23 12:53:15 PM UTC 24 |
| Finished | Aug 23 01:40:48 PM UTC 24 |
| Peak memory | 398300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15855002 78 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all.1585500278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/0.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3166582220 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 110405652 ps |
| CPU time | 1.4 seconds |
| Started | Aug 23 03:49:15 PM UTC 24 |
| Finished | Aug 23 03:49:17 PM UTC 24 |
| Peak memory | 222768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166 582220 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_ intg_err.3166582220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/1.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.51733126 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 11771683185 ps |
| CPU time | 295.94 seconds |
| Started | Aug 23 12:53:07 PM UTC 24 |
| Finished | Aug 23 12:58:07 PM UTC 24 |
| Peak memory | 388200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51733126 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multiple_keys.51733126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/0.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.354974839 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 7164269926 ps |
| CPU time | 55.3 seconds |
| Started | Aug 23 03:50:30 PM UTC 24 |
| Finished | Aug 23 03:51:27 PM UTC 24 |
| Peak memory | 213536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 54974839 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ passthru_mem_tl_intg_err.354974839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/10.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.655567770 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 25128541 ps |
| CPU time | 0.58 seconds |
| Started | Aug 23 03:49:12 PM UTC 24 |
| Finished | Aug 23 03:49:13 PM UTC 24 |
| Peak memory | 211836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6555677 70 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_ali asing.655567770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.345359635 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 135060620 ps |
| CPU time | 1.19 seconds |
| Started | Aug 23 03:49:12 PM UTC 24 |
| Finished | Aug 23 03:49:14 PM UTC 24 |
| Peak memory | 212504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453596 35 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_bit _bash.345359635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2003466891 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 50235163 ps |
| CPU time | 0.6 seconds |
| Started | Aug 23 03:49:08 PM UTC 24 |
| Finished | Aug 23 03:49:09 PM UTC 24 |
| Peak memory | 212808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003466 891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_hw _reset.2003466891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3897991327 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 374264708 ps |
| CPU time | 3.39 seconds |
| Started | Aug 23 03:49:13 PM UTC 24 |
| Finished | Aug 23 03:49:17 PM UTC 24 |
| Peak memory | 223696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=3897991327 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.3897991327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.97142950 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 13716173 ps |
| CPU time | 0.61 seconds |
| Started | Aug 23 03:49:10 PM UTC 24 |
| Finished | Aug 23 03:49:11 PM UTC 24 |
| Peak memory | 212464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97142950 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_rw.97142950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1078002130 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 31905881 ps |
| CPU time | 0.77 seconds |
| Started | Aug 23 03:49:12 PM UTC 24 |
| Finished | Aug 23 03:49:14 PM UTC 24 |
| Peak memory | 212048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1078002130 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram _ctrl_same_csr_outstanding.1078002130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/0.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.860698277 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 64112245 ps |
| CPU time | 2.23 seconds |
| Started | Aug 23 03:49:04 PM UTC 24 |
| Finished | Aug 23 03:49:07 PM UTC 24 |
| Peak memory | 224040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860698277 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_tl_errors.860698277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/0.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2459903253 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 15104481 ps |
| CPU time | 0.6 seconds |
| Started | Aug 23 03:49:20 PM UTC 24 |
| Finished | Aug 23 03:49:22 PM UTC 24 |
| Peak memory | 213164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459903 253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_al iasing.2459903253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/1.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.952729335 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 117701200 ps |
| CPU time | 1.25 seconds |
| Started | Aug 23 03:49:19 PM UTC 24 |
| Finished | Aug 23 03:49:21 PM UTC 24 |
| Peak memory | 212464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9527293 35 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_bit _bash.952729335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/1.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.4219161622 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 21580778 ps |
| CPU time | 0.56 seconds |
| Started | Aug 23 03:49:18 PM UTC 24 |
| Finished | Aug 23 03:49:20 PM UTC 24 |
| Peak memory | 212428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219161 622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_hw _reset.4219161622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/1.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.104493698 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 356798717 ps |
| CPU time | 3.68 seconds |
| Started | Aug 23 03:49:22 PM UTC 24 |
| Finished | Aug 23 03:49:27 PM UTC 24 |
| Peak memory | 223644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=104493698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.104493698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.379357024 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 49382085 ps |
| CPU time | 0.58 seconds |
| Started | Aug 23 03:49:18 PM UTC 24 |
| Finished | Aug 23 03:49:20 PM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379357024 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_rw.379357024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/1.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.993523100 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 3699270120 ps |
| CPU time | 29.39 seconds |
| Started | Aug 23 03:49:14 PM UTC 24 |
| Finished | Aug 23 03:49:45 PM UTC 24 |
| Peak memory | 213324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9 93523100 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_p assthru_mem_tl_intg_err.993523100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/1.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3439604373 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 47540811 ps |
| CPU time | 0.59 seconds |
| Started | Aug 23 03:49:20 PM UTC 24 |
| Finished | Aug 23 03:49:22 PM UTC 24 |
| Peak memory | 212528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3439604373 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram _ctrl_same_csr_outstanding.3439604373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/1.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3550779749 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 55932133 ps |
| CPU time | 3.47 seconds |
| Started | Aug 23 03:49:14 PM UTC 24 |
| Finished | Aug 23 03:49:19 PM UTC 24 |
| Peak memory | 213380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550779749 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_errors.3550779749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/1.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3975286131 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 1080808346 ps |
| CPU time | 3.55 seconds |
| Started | Aug 23 03:50:37 PM UTC 24 |
| Finished | Aug 23 03:50:43 PM UTC 24 |
| Peak memory | 223568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=3975286131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.3975286131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3292304036 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 41972640 ps |
| CPU time | 0.56 seconds |
| Started | Aug 23 03:50:35 PM UTC 24 |
| Finished | Aug 23 03:50:37 PM UTC 24 |
| Peak memory | 212740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292304036 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_rw.3292304036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/10.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.174705479 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 185185667 ps |
| CPU time | 0.6 seconds |
| Started | Aug 23 03:50:37 PM UTC 24 |
| Finished | Aug 23 03:50:40 PM UTC 24 |
| Peak memory | 212528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=174705479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram _ctrl_same_csr_outstanding.174705479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/10.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1859103962 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 256112188 ps |
| CPU time | 2.09 seconds |
| Started | Aug 23 03:50:30 PM UTC 24 |
| Finished | Aug 23 03:50:33 PM UTC 24 |
| Peak memory | 223892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859103962 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl_errors.1859103962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/10.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1824791189 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 227364259 ps |
| CPU time | 2.1 seconds |
| Started | Aug 23 03:50:34 PM UTC 24 |
| Finished | Aug 23 03:50:37 PM UTC 24 |
| Peak memory | 213340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824 791189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl _intg_err.1824791189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/10.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2724052316 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 1368695061 ps |
| CPU time | 3.83 seconds |
| Started | Aug 23 03:50:47 PM UTC 24 |
| Finished | Aug 23 03:50:52 PM UTC 24 |
| Peak memory | 223832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=2724052316 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.2724052316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1431370230 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 13748161 ps |
| CPU time | 0.54 seconds |
| Started | Aug 23 03:50:45 PM UTC 24 |
| Finished | Aug 23 03:50:46 PM UTC 24 |
| Peak memory | 212460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431370230 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_rw.1431370230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/11.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.287311456 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 29431178175 ps |
| CPU time | 56.8 seconds |
| Started | Aug 23 03:50:38 PM UTC 24 |
| Finished | Aug 23 03:51:37 PM UTC 24 |
| Peak memory | 213464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 87311456 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ passthru_mem_tl_intg_err.287311456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/11.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1809859493 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 33047514 ps |
| CPU time | 0.65 seconds |
| Started | Aug 23 03:50:46 PM UTC 24 |
| Finished | Aug 23 03:50:47 PM UTC 24 |
| Peak memory | 212048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1809859493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sra m_ctrl_same_csr_outstanding.1809859493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/11.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2301908400 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 37089217 ps |
| CPU time | 3.09 seconds |
| Started | Aug 23 03:50:40 PM UTC 24 |
| Finished | Aug 23 03:50:45 PM UTC 24 |
| Peak memory | 213532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301908400 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl_errors.2301908400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/11.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.4172128977 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 1440940187 ps |
| CPU time | 4.35 seconds |
| Started | Aug 23 03:50:54 PM UTC 24 |
| Finished | Aug 23 03:51:00 PM UTC 24 |
| Peak memory | 223772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=4172128977 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.4172128977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3020743822 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 22158934 ps |
| CPU time | 0.54 seconds |
| Started | Aug 23 03:50:52 PM UTC 24 |
| Finished | Aug 23 03:50:54 PM UTC 24 |
| Peak memory | 212740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020743822 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_rw.3020743822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/12.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1799633367 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 14079815439 ps |
| CPU time | 55.18 seconds |
| Started | Aug 23 03:50:47 PM UTC 24 |
| Finished | Aug 23 03:51:43 PM UTC 24 |
| Peak memory | 213516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 799633367 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl _passthru_mem_tl_intg_err.1799633367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/12.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.506900013 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 69208924 ps |
| CPU time | 0.61 seconds |
| Started | Aug 23 03:50:53 PM UTC 24 |
| Finished | Aug 23 03:50:55 PM UTC 24 |
| Peak memory | 212808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=506900013 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram _ctrl_same_csr_outstanding.506900013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/12.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2981250294 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 171629484 ps |
| CPU time | 3.14 seconds |
| Started | Aug 23 03:50:48 PM UTC 24 |
| Finished | Aug 23 03:50:52 PM UTC 24 |
| Peak memory | 223620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981250294 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl_errors.2981250294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/12.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1626215489 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 689605801 ps |
| CPU time | 1.97 seconds |
| Started | Aug 23 03:50:50 PM UTC 24 |
| Finished | Aug 23 03:50:53 PM UTC 24 |
| Peak memory | 222772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626 215489 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl _intg_err.1626215489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/12.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1476124245 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 376613373 ps |
| CPU time | 3.16 seconds |
| Started | Aug 23 03:51:03 PM UTC 24 |
| Finished | Aug 23 03:51:07 PM UTC 24 |
| Peak memory | 223568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=1476124245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.1476124245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3661061069 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 53465105 ps |
| CPU time | 0.53 seconds |
| Started | Aug 23 03:51:00 PM UTC 24 |
| Finished | Aug 23 03:51:02 PM UTC 24 |
| Peak memory | 212460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661061069 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_rw.3661061069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/13.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2134372227 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 28433702932 ps |
| CPU time | 31.2 seconds |
| Started | Aug 23 03:50:54 PM UTC 24 |
| Finished | Aug 23 03:51:27 PM UTC 24 |
| Peak memory | 213516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 134372227 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl _passthru_mem_tl_intg_err.2134372227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/13.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.425055591 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 19357686 ps |
| CPU time | 0.65 seconds |
| Started | Aug 23 03:51:03 PM UTC 24 |
| Finished | Aug 23 03:51:04 PM UTC 24 |
| Peak memory | 212528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=425055591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram _ctrl_same_csr_outstanding.425055591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/13.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3127380492 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 71998817 ps |
| CPU time | 2.23 seconds |
| Started | Aug 23 03:50:55 PM UTC 24 |
| Finished | Aug 23 03:50:59 PM UTC 24 |
| Peak memory | 213532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127380492 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl_errors.3127380492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/13.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2274771311 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 257506638 ps |
| CPU time | 1.24 seconds |
| Started | Aug 23 03:50:59 PM UTC 24 |
| Finished | Aug 23 03:51:02 PM UTC 24 |
| Peak memory | 222772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274 771311 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl _intg_err.2274771311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/13.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3946472328 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 1421119470 ps |
| CPU time | 3.6 seconds |
| Started | Aug 23 03:51:08 PM UTC 24 |
| Finished | Aug 23 03:51:13 PM UTC 24 |
| Peak memory | 213328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=3946472328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.3946472328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2026829682 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 43955114 ps |
| CPU time | 0.57 seconds |
| Started | Aug 23 03:51:06 PM UTC 24 |
| Finished | Aug 23 03:51:08 PM UTC 24 |
| Peak memory | 212460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026829682 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_rw.2026829682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/14.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3755086160 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 15394966562 ps |
| CPU time | 29.25 seconds |
| Started | Aug 23 03:51:04 PM UTC 24 |
| Finished | Aug 23 03:51:34 PM UTC 24 |
| Peak memory | 213452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 755086160 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl _passthru_mem_tl_intg_err.3755086160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/14.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1772360056 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 13361319 ps |
| CPU time | 0.64 seconds |
| Started | Aug 23 03:51:08 PM UTC 24 |
| Finished | Aug 23 03:51:10 PM UTC 24 |
| Peak memory | 212528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1772360056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sra m_ctrl_same_csr_outstanding.1772360056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/14.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3807715581 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 60161976 ps |
| CPU time | 3.16 seconds |
| Started | Aug 23 03:51:05 PM UTC 24 |
| Finished | Aug 23 03:51:09 PM UTC 24 |
| Peak memory | 213396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807715581 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_tl_errors.3807715581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/14.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1115740066 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 259141377 ps |
| CPU time | 2.2 seconds |
| Started | Aug 23 03:51:06 PM UTC 24 |
| Finished | Aug 23 03:51:09 PM UTC 24 |
| Peak memory | 223576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115 740066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_tl _intg_err.1115740066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/14.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2413906071 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 357293316 ps |
| CPU time | 3.33 seconds |
| Started | Aug 23 03:51:14 PM UTC 24 |
| Finished | Aug 23 03:51:19 PM UTC 24 |
| Peak memory | 213324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=2413906071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.2413906071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3213884818 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 56076956 ps |
| CPU time | 0.58 seconds |
| Started | Aug 23 03:51:12 PM UTC 24 |
| Finished | Aug 23 03:51:14 PM UTC 24 |
| Peak memory | 212460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213884818 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_rw.3213884818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/15.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3074130405 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 3816771144 ps |
| CPU time | 28.73 seconds |
| Started | Aug 23 03:51:10 PM UTC 24 |
| Finished | Aug 23 03:51:40 PM UTC 24 |
| Peak memory | 213448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 074130405 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl _passthru_mem_tl_intg_err.3074130405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/15.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1943007016 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 25873100 ps |
| CPU time | 0.64 seconds |
| Started | Aug 23 03:51:13 PM UTC 24 |
| Finished | Aug 23 03:51:15 PM UTC 24 |
| Peak memory | 212528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1943007016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sra m_ctrl_same_csr_outstanding.1943007016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/15.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3938830653 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 215598247 ps |
| CPU time | 1.91 seconds |
| Started | Aug 23 03:51:11 PM UTC 24 |
| Finished | Aug 23 03:51:14 PM UTC 24 |
| Peak memory | 212528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938830653 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl_errors.3938830653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/15.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.211947629 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 165438001 ps |
| CPU time | 1.79 seconds |
| Started | Aug 23 03:51:11 PM UTC 24 |
| Finished | Aug 23 03:51:14 PM UTC 24 |
| Peak memory | 222852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119 47629 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl_ intg_err.211947629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/15.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.502307638 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 357127797 ps |
| CPU time | 4.55 seconds |
| Started | Aug 23 03:51:18 PM UTC 24 |
| Finished | Aug 23 03:51:24 PM UTC 24 |
| Peak memory | 223700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=502307638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.502307638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1007469774 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 13735768 ps |
| CPU time | 0.58 seconds |
| Started | Aug 23 03:51:16 PM UTC 24 |
| Finished | Aug 23 03:51:17 PM UTC 24 |
| Peak memory | 212468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007469774 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_rw.1007469774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/16.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2899692177 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 36820905436 ps |
| CPU time | 38.15 seconds |
| Started | Aug 23 03:51:15 PM UTC 24 |
| Finished | Aug 23 03:51:54 PM UTC 24 |
| Peak memory | 213736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 899692177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl _passthru_mem_tl_intg_err.2899692177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/16.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.61656787 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 37591175 ps |
| CPU time | 0.72 seconds |
| Started | Aug 23 03:51:18 PM UTC 24 |
| Finished | Aug 23 03:51:20 PM UTC 24 |
| Peak memory | 212528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=61656787 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ ctrl_same_csr_outstanding.61656787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/16.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.330403753 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 34253301 ps |
| CPU time | 2.38 seconds |
| Started | Aug 23 03:51:15 PM UTC 24 |
| Finished | Aug 23 03:51:18 PM UTC 24 |
| Peak memory | 223584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330403753 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl_errors.330403753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/16.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.4169972948 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 226067037 ps |
| CPU time | 1.22 seconds |
| Started | Aug 23 03:51:15 PM UTC 24 |
| Finished | Aug 23 03:51:17 PM UTC 24 |
| Peak memory | 222772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169 972948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl _intg_err.4169972948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/16.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3519697097 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 1548148029 ps |
| CPU time | 3.11 seconds |
| Started | Aug 23 03:51:25 PM UTC 24 |
| Finished | Aug 23 03:51:29 PM UTC 24 |
| Peak memory | 225284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=3519697097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.3519697097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1038013071 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 22911576 ps |
| CPU time | 0.6 seconds |
| Started | Aug 23 03:51:20 PM UTC 24 |
| Finished | Aug 23 03:51:22 PM UTC 24 |
| Peak memory | 212460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038013071 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_rw.1038013071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/17.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1897276867 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 7482821379 ps |
| CPU time | 54.14 seconds |
| Started | Aug 23 03:51:19 PM UTC 24 |
| Finished | Aug 23 03:52:15 PM UTC 24 |
| Peak memory | 213520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 897276867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl _passthru_mem_tl_intg_err.1897276867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/17.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3867972463 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 44517418 ps |
| CPU time | 0.58 seconds |
| Started | Aug 23 03:51:23 PM UTC 24 |
| Finished | Aug 23 03:51:24 PM UTC 24 |
| Peak memory | 212528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3867972463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sra m_ctrl_same_csr_outstanding.3867972463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/17.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2535815564 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 325719199 ps |
| CPU time | 2.31 seconds |
| Started | Aug 23 03:51:20 PM UTC 24 |
| Finished | Aug 23 03:51:24 PM UTC 24 |
| Peak memory | 213460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535815564 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_errors.2535815564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/17.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.48969630 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 667325175 ps |
| CPU time | 2.1 seconds |
| Started | Aug 23 03:51:20 PM UTC 24 |
| Finished | Aug 23 03:51:24 PM UTC 24 |
| Peak memory | 223656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4896 9630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_i ntg_err.48969630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/17.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.4163000242 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 934012512 ps |
| CPU time | 3.7 seconds |
| Started | Aug 23 03:51:29 PM UTC 24 |
| Finished | Aug 23 03:51:33 PM UTC 24 |
| Peak memory | 223552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=4163000242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.4163000242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.589360663 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 98208447 ps |
| CPU time | 0.56 seconds |
| Started | Aug 23 03:51:27 PM UTC 24 |
| Finished | Aug 23 03:51:29 PM UTC 24 |
| Peak memory | 212460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589360663 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_rw.589360663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/18.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1933348465 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 14182221358 ps |
| CPU time | 31.57 seconds |
| Started | Aug 23 03:51:25 PM UTC 24 |
| Finished | Aug 23 03:51:58 PM UTC 24 |
| Peak memory | 213340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 933348465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl _passthru_mem_tl_intg_err.1933348465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/18.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1974330404 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 14684438 ps |
| CPU time | 0.63 seconds |
| Started | Aug 23 03:51:27 PM UTC 24 |
| Finished | Aug 23 03:51:29 PM UTC 24 |
| Peak memory | 212808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1974330404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sra m_ctrl_same_csr_outstanding.1974330404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/18.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3725230709 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 33261961 ps |
| CPU time | 2.72 seconds |
| Started | Aug 23 03:51:25 PM UTC 24 |
| Finished | Aug 23 03:51:29 PM UTC 24 |
| Peak memory | 213468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725230709 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_tl_errors.3725230709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/18.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.4184577962 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 483964979 ps |
| CPU time | 1.94 seconds |
| Started | Aug 23 03:51:25 PM UTC 24 |
| Finished | Aug 23 03:51:28 PM UTC 24 |
| Peak memory | 222772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184 577962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_tl _intg_err.4184577962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/18.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2558004217 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 1429708696 ps |
| CPU time | 4.01 seconds |
| Started | Aug 23 03:51:35 PM UTC 24 |
| Finished | Aug 23 03:51:40 PM UTC 24 |
| Peak memory | 225948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=2558004217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.2558004217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3961208808 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 13816923 ps |
| CPU time | 0.59 seconds |
| Started | Aug 23 03:51:30 PM UTC 24 |
| Finished | Aug 23 03:51:32 PM UTC 24 |
| Peak memory | 212812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961208808 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_rw.3961208808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/19.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3425705785 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 7406664930 ps |
| CPU time | 29.6 seconds |
| Started | Aug 23 03:51:30 PM UTC 24 |
| Finished | Aug 23 03:52:01 PM UTC 24 |
| Peak memory | 213456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 425705785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl _passthru_mem_tl_intg_err.3425705785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/19.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1793423171 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 13603622 ps |
| CPU time | 0.6 seconds |
| Started | Aug 23 03:51:33 PM UTC 24 |
| Finished | Aug 23 03:51:35 PM UTC 24 |
| Peak memory | 212528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1793423171 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sra m_ctrl_same_csr_outstanding.1793423171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/19.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1191837576 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 1034721135 ps |
| CPU time | 4.61 seconds |
| Started | Aug 23 03:51:30 PM UTC 24 |
| Finished | Aug 23 03:51:36 PM UTC 24 |
| Peak memory | 223772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191837576 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl_errors.1191837576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/19.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1026756627 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 1226710733 ps |
| CPU time | 2.04 seconds |
| Started | Aug 23 03:51:30 PM UTC 24 |
| Finished | Aug 23 03:51:33 PM UTC 24 |
| Peak memory | 223840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026 756627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl _intg_err.1026756627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/19.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3813823814 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 17859363 ps |
| CPU time | 0.57 seconds |
| Started | Aug 23 03:49:31 PM UTC 24 |
| Finished | Aug 23 03:49:32 PM UTC 24 |
| Peak memory | 212700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813823 814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_al iasing.3813823814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/2.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.148512946 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 520921470 ps |
| CPU time | 1.35 seconds |
| Started | Aug 23 03:49:31 PM UTC 24 |
| Finished | Aug 23 03:49:33 PM UTC 24 |
| Peak memory | 212048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485129 46 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_bit _bash.148512946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/2.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2583973302 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 27660444 ps |
| CPU time | 0.59 seconds |
| Started | Aug 23 03:49:27 PM UTC 24 |
| Finished | Aug 23 03:49:30 PM UTC 24 |
| Peak memory | 212304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583973 302 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_hw _reset.2583973302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/2.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2578929023 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 371699764 ps |
| CPU time | 3.32 seconds |
| Started | Aug 23 03:49:33 PM UTC 24 |
| Finished | Aug 23 03:49:37 PM UTC 24 |
| Peak memory | 223560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=2578929023 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.2578929023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.502589351 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 14145532 ps |
| CPU time | 0.55 seconds |
| Started | Aug 23 03:49:29 PM UTC 24 |
| Finished | Aug 23 03:49:30 PM UTC 24 |
| Peak memory | 212988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502589351 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_rw.502589351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/2.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1761319702 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 15019658715 ps |
| CPU time | 59.47 seconds |
| Started | Aug 23 03:49:22 PM UTC 24 |
| Finished | Aug 23 03:50:23 PM UTC 24 |
| Peak memory | 213772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 761319702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ passthru_mem_tl_intg_err.1761319702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/2.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1045916888 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 29709345 ps |
| CPU time | 0.65 seconds |
| Started | Aug 23 03:49:32 PM UTC 24 |
| Finished | Aug 23 03:49:34 PM UTC 24 |
| Peak memory | 212528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1045916888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram _ctrl_same_csr_outstanding.1045916888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/2.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.4214829744 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 151867445 ps |
| CPU time | 4.2 seconds |
| Started | Aug 23 03:49:22 PM UTC 24 |
| Finished | Aug 23 03:49:28 PM UTC 24 |
| Peak memory | 223708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214829744 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_errors.4214829744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/2.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3677303469 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 1660225053 ps |
| CPU time | 2.21 seconds |
| Started | Aug 23 03:49:27 PM UTC 24 |
| Finished | Aug 23 03:49:31 PM UTC 24 |
| Peak memory | 213260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677 303469 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_ intg_err.3677303469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/2.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2776504269 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 28046699 ps |
| CPU time | 0.58 seconds |
| Started | Aug 23 03:49:42 PM UTC 24 |
| Finished | Aug 23 03:49:44 PM UTC 24 |
| Peak memory | 212808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776504 269 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_al iasing.2776504269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/3.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1644160710 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 82383495 ps |
| CPU time | 1.25 seconds |
| Started | Aug 23 03:49:42 PM UTC 24 |
| Finished | Aug 23 03:49:44 PM UTC 24 |
| Peak memory | 213064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644160 710 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_bi t_bash.1644160710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/3.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2996077539 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 15305457 ps |
| CPU time | 0.54 seconds |
| Started | Aug 23 03:49:38 PM UTC 24 |
| Finished | Aug 23 03:49:40 PM UTC 24 |
| Peak memory | 213164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996077 539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_hw _reset.2996077539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/3.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.256091164 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 695815324 ps |
| CPU time | 3.48 seconds |
| Started | Aug 23 03:49:44 PM UTC 24 |
| Finished | Aug 23 03:49:49 PM UTC 24 |
| Peak memory | 213396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=256091164 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.256091164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.754524794 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 51563967 ps |
| CPU time | 0.56 seconds |
| Started | Aug 23 03:49:40 PM UTC 24 |
| Finished | Aug 23 03:49:42 PM UTC 24 |
| Peak memory | 212460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754524794 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_rw.754524794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/3.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1148012747 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 117330689872 ps |
| CPU time | 85.56 seconds |
| Started | Aug 23 03:49:34 PM UTC 24 |
| Finished | Aug 23 03:51:01 PM UTC 24 |
| Peak memory | 213516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 148012747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ passthru_mem_tl_intg_err.1148012747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/3.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3971760265 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 16380144 ps |
| CPU time | 0.59 seconds |
| Started | Aug 23 03:49:42 PM UTC 24 |
| Finished | Aug 23 03:49:44 PM UTC 24 |
| Peak memory | 212808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3971760265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram _ctrl_same_csr_outstanding.3971760265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/3.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3906721029 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 26219836 ps |
| CPU time | 1.83 seconds |
| Started | Aug 23 03:49:34 PM UTC 24 |
| Finished | Aug 23 03:49:37 PM UTC 24 |
| Peak memory | 212524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906721029 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_errors.3906721029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/3.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2993510406 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 15416468 ps |
| CPU time | 0.59 seconds |
| Started | Aug 23 03:49:52 PM UTC 24 |
| Finished | Aug 23 03:49:53 PM UTC 24 |
| Peak memory | 212380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993510 406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_al iasing.2993510406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/4.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3875189540 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 94669404 ps |
| CPU time | 1.05 seconds |
| Started | Aug 23 03:49:51 PM UTC 24 |
| Finished | Aug 23 03:49:53 PM UTC 24 |
| Peak memory | 212892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875189 540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_bi t_bash.3875189540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/4.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1134706184 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 29122383 ps |
| CPU time | 0.56 seconds |
| Started | Aug 23 03:49:50 PM UTC 24 |
| Finished | Aug 23 03:49:51 PM UTC 24 |
| Peak memory | 212468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134706 184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_hw _reset.1134706184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/4.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.4106646104 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 700365515 ps |
| CPU time | 3.23 seconds |
| Started | Aug 23 03:49:54 PM UTC 24 |
| Finished | Aug 23 03:49:58 PM UTC 24 |
| Peak memory | 223564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=4106646104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.4106646104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3429036498 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 56490166 ps |
| CPU time | 0.56 seconds |
| Started | Aug 23 03:49:50 PM UTC 24 |
| Finished | Aug 23 03:49:51 PM UTC 24 |
| Peak memory | 212740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429036498 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_rw.3429036498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/4.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.947626249 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 17677746939 ps |
| CPU time | 26.47 seconds |
| Started | Aug 23 03:49:44 PM UTC 24 |
| Finished | Aug 23 03:50:12 PM UTC 24 |
| Peak memory | 213596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9 47626249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_p assthru_mem_tl_intg_err.947626249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/4.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3376918818 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 48349326 ps |
| CPU time | 0.67 seconds |
| Started | Aug 23 03:49:52 PM UTC 24 |
| Finished | Aug 23 03:49:53 PM UTC 24 |
| Peak memory | 212528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3376918818 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram _ctrl_same_csr_outstanding.3376918818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/4.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1129833441 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 126039238 ps |
| CPU time | 3.51 seconds |
| Started | Aug 23 03:49:45 PM UTC 24 |
| Finished | Aug 23 03:49:50 PM UTC 24 |
| Peak memory | 223780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129833441 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_errors.1129833441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/4.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.31934615 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 166494591 ps |
| CPU time | 1.85 seconds |
| Started | Aug 23 03:49:45 PM UTC 24 |
| Finished | Aug 23 03:49:48 PM UTC 24 |
| Peak memory | 222768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193 4615 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_in tg_err.31934615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/4.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3357361515 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 1392917330 ps |
| CPU time | 3.61 seconds |
| Started | Aug 23 03:50:01 PM UTC 24 |
| Finished | Aug 23 03:50:06 PM UTC 24 |
| Peak memory | 223556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=3357361515 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.3357361515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3938304711 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 14999206 ps |
| CPU time | 0.57 seconds |
| Started | Aug 23 03:49:59 PM UTC 24 |
| Finished | Aug 23 03:50:01 PM UTC 24 |
| Peak memory | 212464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938304711 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_rw.3938304711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/5.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1369798423 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 7354879604 ps |
| CPU time | 53.71 seconds |
| Started | Aug 23 03:49:54 PM UTC 24 |
| Finished | Aug 23 03:50:49 PM UTC 24 |
| Peak memory | 213596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 369798423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ passthru_mem_tl_intg_err.1369798423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/5.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3479194807 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 19537988 ps |
| CPU time | 0.6 seconds |
| Started | Aug 23 03:49:59 PM UTC 24 |
| Finished | Aug 23 03:50:01 PM UTC 24 |
| Peak memory | 212808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3479194807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram _ctrl_same_csr_outstanding.3479194807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/5.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.257084268 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 31295615 ps |
| CPU time | 2.88 seconds |
| Started | Aug 23 03:49:54 PM UTC 24 |
| Finished | Aug 23 03:49:58 PM UTC 24 |
| Peak memory | 223976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257084268 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_errors.257084268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/5.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3368910011 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 353775970 ps |
| CPU time | 2.41 seconds |
| Started | Aug 23 03:49:58 PM UTC 24 |
| Finished | Aug 23 03:50:01 PM UTC 24 |
| Peak memory | 223712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368 910011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_ intg_err.3368910011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/5.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2800132476 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 6840879722 ps |
| CPU time | 4.68 seconds |
| Started | Aug 23 03:50:08 PM UTC 24 |
| Finished | Aug 23 03:50:13 PM UTC 24 |
| Peak memory | 223828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=2800132476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.2800132476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2469801414 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 44468024 ps |
| CPU time | 0.59 seconds |
| Started | Aug 23 03:50:05 PM UTC 24 |
| Finished | Aug 23 03:50:07 PM UTC 24 |
| Peak memory | 212740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469801414 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_rw.2469801414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/6.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2355532424 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 15355220395 ps |
| CPU time | 33.58 seconds |
| Started | Aug 23 03:50:01 PM UTC 24 |
| Finished | Aug 23 03:50:36 PM UTC 24 |
| Peak memory | 212452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 355532424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ passthru_mem_tl_intg_err.2355532424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/6.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3013835218 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 44501301 ps |
| CPU time | 0.7 seconds |
| Started | Aug 23 03:50:06 PM UTC 24 |
| Finished | Aug 23 03:50:08 PM UTC 24 |
| Peak memory | 212528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3013835218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram _ctrl_same_csr_outstanding.3013835218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/6.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.755153297 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 127604496 ps |
| CPU time | 4.05 seconds |
| Started | Aug 23 03:50:01 PM UTC 24 |
| Finished | Aug 23 03:50:06 PM UTC 24 |
| Peak memory | 223968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755153297 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_errors.755153297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/6.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.641066875 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 591376743 ps |
| CPU time | 1.42 seconds |
| Started | Aug 23 03:50:02 PM UTC 24 |
| Finished | Aug 23 03:50:05 PM UTC 24 |
| Peak memory | 222768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6410 66875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_i ntg_err.641066875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/6.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1597820632 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 2191955702 ps |
| CPU time | 3.97 seconds |
| Started | Aug 23 03:50:16 PM UTC 24 |
| Finished | Aug 23 03:50:21 PM UTC 24 |
| Peak memory | 223608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=1597820632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.1597820632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.808866289 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 48597892 ps |
| CPU time | 0.57 seconds |
| Started | Aug 23 03:50:14 PM UTC 24 |
| Finished | Aug 23 03:50:15 PM UTC 24 |
| Peak memory | 212460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808866289 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_rw.808866289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/7.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1043688634 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 32051521511 ps |
| CPU time | 55.76 seconds |
| Started | Aug 23 03:50:08 PM UTC 24 |
| Finished | Aug 23 03:51:05 PM UTC 24 |
| Peak memory | 213664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 043688634 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ passthru_mem_tl_intg_err.1043688634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/7.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.605113939 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 38843038 ps |
| CPU time | 0.68 seconds |
| Started | Aug 23 03:50:14 PM UTC 24 |
| Finished | Aug 23 03:50:16 PM UTC 24 |
| Peak memory | 212524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=605113939 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ ctrl_same_csr_outstanding.605113939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/7.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.974361473 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 157468050 ps |
| CPU time | 2.66 seconds |
| Started | Aug 23 03:50:09 PM UTC 24 |
| Finished | Aug 23 03:50:13 PM UTC 24 |
| Peak memory | 223968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974361473 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_tl_errors.974361473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/7.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2700587847 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 143299255 ps |
| CPU time | 1.22 seconds |
| Started | Aug 23 03:50:13 PM UTC 24 |
| Finished | Aug 23 03:50:15 PM UTC 24 |
| Peak memory | 212528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700 587847 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_tl_ intg_err.2700587847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/7.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3128383946 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 1371754050 ps |
| CPU time | 4.07 seconds |
| Started | Aug 23 03:50:22 PM UTC 24 |
| Finished | Aug 23 03:50:28 PM UTC 24 |
| Peak memory | 223772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=3128383946 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.3128383946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3959504862 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 16015475 ps |
| CPU time | 0.56 seconds |
| Started | Aug 23 03:50:20 PM UTC 24 |
| Finished | Aug 23 03:50:22 PM UTC 24 |
| Peak memory | 212860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959504862 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_rw.3959504862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/8.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3416990492 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 3908232144 ps |
| CPU time | 26.68 seconds |
| Started | Aug 23 03:50:16 PM UTC 24 |
| Finished | Aug 23 03:50:44 PM UTC 24 |
| Peak memory | 213384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 416990492 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ passthru_mem_tl_intg_err.3416990492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/8.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.411201220 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 48218466 ps |
| CPU time | 0.65 seconds |
| Started | Aug 23 03:50:21 PM UTC 24 |
| Finished | Aug 23 03:50:23 PM UTC 24 |
| Peak memory | 212808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=411201220 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ ctrl_same_csr_outstanding.411201220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/8.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1606238874 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 100821837 ps |
| CPU time | 2.13 seconds |
| Started | Aug 23 03:50:16 PM UTC 24 |
| Finished | Aug 23 03:50:19 PM UTC 24 |
| Peak memory | 213476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606238874 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_errors.1606238874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/8.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1132699062 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 190994854 ps |
| CPU time | 2.11 seconds |
| Started | Aug 23 03:50:17 PM UTC 24 |
| Finished | Aug 23 03:50:20 PM UTC 24 |
| Peak memory | 223636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132 699062 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_ intg_err.1132699062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/8.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1347658760 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 1420351453 ps |
| CPU time | 4.28 seconds |
| Started | Aug 23 03:50:29 PM UTC 24 |
| Finished | Aug 23 03:50:34 PM UTC 24 |
| Peak memory | 225816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=1347658760 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.1347658760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.4095635454 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 39347311 ps |
| CPU time | 0.59 seconds |
| Started | Aug 23 03:50:28 PM UTC 24 |
| Finished | Aug 23 03:50:29 PM UTC 24 |
| Peak memory | 211964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095635454 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_rw.4095635454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/9.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.779417672 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 41019834864 ps |
| CPU time | 41.15 seconds |
| Started | Aug 23 03:50:22 PM UTC 24 |
| Finished | Aug 23 03:51:05 PM UTC 24 |
| Peak memory | 223956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7 79417672 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_p assthru_mem_tl_intg_err.779417672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/9.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3736695840 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 40615318 ps |
| CPU time | 0.6 seconds |
| Started | Aug 23 03:50:28 PM UTC 24 |
| Finished | Aug 23 03:50:29 PM UTC 24 |
| Peak memory | 212040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3736695840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram _ctrl_same_csr_outstanding.3736695840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/9.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1260394493 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 75342517 ps |
| CPU time | 2.04 seconds |
| Started | Aug 23 03:50:23 PM UTC 24 |
| Finished | Aug 23 03:50:27 PM UTC 24 |
| Peak memory | 213460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260394493 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_errors.1260394493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/9.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3415585784 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 303305594 ps |
| CPU time | 1.2 seconds |
| Started | Aug 23 03:50:25 PM UTC 24 |
| Finished | Aug 23 03:50:27 PM UTC 24 |
| Peak memory | 213004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415 585784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_ intg_err.3415585784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/9.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.2856442677 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 23734529767 ps |
| CPU time | 514.66 seconds |
| Started | Aug 23 12:53:09 PM UTC 24 |
| Finished | Aug 23 01:01:50 PM UTC 24 |
| Peak memory | 384660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856442677 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_access_durin g_key_req.2856442677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/0.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_bijection.1064138072 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 73647404930 ps |
| CPU time | 1030.7 seconds |
| Started | Aug 23 12:53:07 PM UTC 24 |
| Finished | Aug 23 01:10:28 PM UTC 24 |
| Peak memory | 213180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064138072 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.1064138072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/0.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_executable.2416185711 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 5513237049 ps |
| CPU time | 88.12 seconds |
| Started | Aug 23 12:53:11 PM UTC 24 |
| Finished | Aug 23 12:54:42 PM UTC 24 |
| Peak memory | 347688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416185711 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executable.2416185711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/0.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.2848526651 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 7947114591 ps |
| CPU time | 40.94 seconds |
| Started | Aug 23 12:53:09 PM UTC 24 |
| Finished | Aug 23 12:53:52 PM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848526651 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_escalation.2848526651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/0.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.3899351485 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 741378620 ps |
| CPU time | 10.02 seconds |
| Started | Aug 23 12:53:09 PM UTC 24 |
| Finished | Aug 23 12:53:21 PM UTC 24 |
| Peak memory | 249444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3899351485 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_m ax_throughput.3899351485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/0.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.2140109460 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 21011004494 ps |
| CPU time | 267.4 seconds |
| Started | Aug 23 12:53:15 PM UTC 24 |
| Finished | Aug 23 12:57:46 PM UTC 24 |
| Peak memory | 221892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140109460 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_mem_walk.2140109460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/0.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access.1461031283 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5233343255 ps |
| CPU time | 22.98 seconds |
| Started | Aug 23 12:53:08 PM UTC 24 |
| Finished | Aug 23 12:53:32 PM UTC 24 |
| Peak memory | 211556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461031283 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_partial_access.1461031283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/0.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.1699140061 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 47977011519 ps |
| CPU time | 403.06 seconds |
| Started | Aug 23 12:53:08 PM UTC 24 |
| Finished | Aug 23 12:59:56 PM UTC 24 |
| Peak memory | 213248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699140061 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_partial_ac cess_b2b.1699140061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/0.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.3045059141 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 1408357036 ps |
| CPU time | 3.34 seconds |
| Started | Aug 23 12:53:12 PM UTC 24 |
| Finished | Aug 23 12:53:17 PM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045059141 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.3045059141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/0.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_smoke.3102861224 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 6631014385 ps |
| CPU time | 9.19 seconds |
| Started | Aug 23 12:53:06 PM UTC 24 |
| Finished | Aug 23 12:53:17 PM UTC 24 |
| Peak memory | 211628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102861224 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.3102861224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/0.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.3060517275 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 2497614661 ps |
| CPU time | 117.15 seconds |
| Started | Aug 23 12:53:15 PM UTC 24 |
| Finished | Aug 23 12:55:14 PM UTC 24 |
| Peak memory | 276064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060517275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.3060517275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/0.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.1424254164 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 4663053168 ps |
| CPU time | 350.52 seconds |
| Started | Aug 23 12:53:08 PM UTC 24 |
| Finished | Aug 23 12:59:03 PM UTC 24 |
| Peak memory | 211808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424254164 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_pipeline.1424254164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/0.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.3170046823 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 5444036014 ps |
| CPU time | 242.85 seconds |
| Started | Aug 23 12:53:21 PM UTC 24 |
| Finished | Aug 23 12:57:27 PM UTC 24 |
| Peak memory | 370132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170046823 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_access_durin g_key_req.3170046823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/1.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_alert_test.1677035959 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 38703364 ps |
| CPU time | 0.57 seconds |
| Started | Aug 23 12:53:41 PM UTC 24 |
| Finished | Aug 23 12:53:43 PM UTC 24 |
| Peak memory | 208960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677035959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_alert_test.1677035959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/1.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_bijection.2415995700 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 194828467651 ps |
| CPU time | 2379.33 seconds |
| Started | Aug 23 12:53:18 PM UTC 24 |
| Finished | Aug 23 01:33:20 PM UTC 24 |
| Peak memory | 213168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415995700 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection.2415995700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/1.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.2376205564 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 3177598215 ps |
| CPU time | 64.72 seconds |
| Started | Aug 23 12:53:18 PM UTC 24 |
| Finished | Aug 23 12:54:24 PM UTC 24 |
| Peak memory | 382632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2376205564 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_m ax_throughput.2376205564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/1.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.1023262321 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 1601952211 ps |
| CPU time | 114.02 seconds |
| Started | Aug 23 12:53:30 PM UTC 24 |
| Finished | Aug 23 12:55:26 PM UTC 24 |
| Peak memory | 221808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023262321 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_mem_partial_access.1023262321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/1.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.4124415843 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 6921935927 ps |
| CPU time | 137.72 seconds |
| Started | Aug 23 12:53:29 PM UTC 24 |
| Finished | Aug 23 12:55:49 PM UTC 24 |
| Peak memory | 222068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124415843 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_mem_walk.4124415843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/1.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.1810764892 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 9995673220 ps |
| CPU time | 286.24 seconds |
| Started | Aug 23 12:53:17 PM UTC 24 |
| Finished | Aug 23 12:58:07 PM UTC 24 |
| Peak memory | 378332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810764892 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multiple_keys.1810764892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/1.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access.205667386 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 3143919489 ps |
| CPU time | 8.92 seconds |
| Started | Aug 23 12:53:18 PM UTC 24 |
| Finished | Aug 23 12:53:28 PM UTC 24 |
| Peak memory | 211572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205667386 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_partial_access.205667386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/1.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.809680447 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 1350845760 ps |
| CPU time | 3.17 seconds |
| Started | Aug 23 12:53:26 PM UTC 24 |
| Finished | Aug 23 12:53:31 PM UTC 24 |
| Peak memory | 211696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809680447 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.809680447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/1.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_regwen.179125221 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 51271056945 ps |
| CPU time | 313.64 seconds |
| Started | Aug 23 12:53:24 PM UTC 24 |
| Finished | Aug 23 12:58:42 PM UTC 24 |
| Peak memory | 378332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179125221 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.179125221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/1.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.138355213 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 462384549 ps |
| CPU time | 1.87 seconds |
| Started | Aug 23 12:53:37 PM UTC 24 |
| Finished | Aug 23 12:53:40 PM UTC 24 |
| Peak memory | 245936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138355213 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_sec_cm.138355213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_smoke.3812472673 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 887494385 ps |
| CPU time | 19.49 seconds |
| Started | Aug 23 12:53:16 PM UTC 24 |
| Finished | Aug 23 12:53:37 PM UTC 24 |
| Peak memory | 211752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812472673 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.3812472673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/1.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all.1987910296 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 270541521819 ps |
| CPU time | 3907.55 seconds |
| Started | Aug 23 12:53:33 PM UTC 24 |
| Finished | Aug 23 01:59:17 PM UTC 24 |
| Peak memory | 390116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19879102 96 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all.1987910296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/1.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.3010929913 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 33425455821 ps |
| CPU time | 237.95 seconds |
| Started | Aug 23 12:53:18 PM UTC 24 |
| Finished | Aug 23 12:57:19 PM UTC 24 |
| Peak memory | 211752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010929913 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_pipeline.3010929913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/1.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.383444136 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 3137378284 ps |
| CPU time | 58.59 seconds |
| Started | Aug 23 12:53:19 PM UTC 24 |
| Finished | Aug 23 12:54:19 PM UTC 24 |
| Peak memory | 380448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =383444136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_t hroughput_w_partial_write.383444136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/1.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.2689972810 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 21214914977 ps |
| CPU time | 991.94 seconds |
| Started | Aug 23 01:15:09 PM UTC 24 |
| Finished | Aug 23 01:31:51 PM UTC 24 |
| Peak memory | 388624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689972810 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_access_duri ng_key_req.2689972810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/10.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_alert_test.554014859 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 69794205 ps |
| CPU time | 0.58 seconds |
| Started | Aug 23 01:16:47 PM UTC 24 |
| Finished | Aug 23 01:16:49 PM UTC 24 |
| Peak memory | 210876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554014859 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_alert_test.554014859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/10.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_bijection.2415604031 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 574744482708 ps |
| CPU time | 2049.01 seconds |
| Started | Aug 23 01:14:06 PM UTC 24 |
| Finished | Aug 23 01:48:35 PM UTC 24 |
| Peak memory | 213160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415604031 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection.2415604031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/10.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_executable.2397539428 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 5566374564 ps |
| CPU time | 18.37 seconds |
| Started | Aug 23 01:15:14 PM UTC 24 |
| Finished | Aug 23 01:15:34 PM UTC 24 |
| Peak memory | 245276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397539428 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executable.2397539428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/10.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.668991881 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 55275879097 ps |
| CPU time | 90.5 seconds |
| Started | Aug 23 01:15:04 PM UTC 24 |
| Finished | Aug 23 01:16:37 PM UTC 24 |
| Peak memory | 211556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668991881 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_escalation.668991881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/10.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.197939638 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 796778805 ps |
| CPU time | 6.66 seconds |
| Started | Aug 23 01:14:56 PM UTC 24 |
| Finished | Aug 23 01:15:04 PM UTC 24 |
| Peak memory | 227940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 197939638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_m ax_throughput.197939638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/10.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.2735587231 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 4967022658 ps |
| CPU time | 118.59 seconds |
| Started | Aug 23 01:16:30 PM UTC 24 |
| Finished | Aug 23 01:18:31 PM UTC 24 |
| Peak memory | 221924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735587231 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_mem_partial_access.2735587231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/10.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.4118629073 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 20910627805 ps |
| CPU time | 303.83 seconds |
| Started | Aug 23 01:15:52 PM UTC 24 |
| Finished | Aug 23 01:20:59 PM UTC 24 |
| Peak memory | 221864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118629073 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_mem_walk.4118629073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/10.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.2278859100 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 5338928137 ps |
| CPU time | 377.56 seconds |
| Started | Aug 23 01:13:53 PM UTC 24 |
| Finished | Aug 23 01:20:15 PM UTC 24 |
| Peak memory | 380456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278859100 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multiple_keys.2278859100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/10.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access.962837848 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 1830383552 ps |
| CPU time | 39.29 seconds |
| Started | Aug 23 01:14:28 PM UTC 24 |
| Finished | Aug 23 01:15:09 PM UTC 24 |
| Peak memory | 339424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962837848 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_partial_access.962837848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/10.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.177631229 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 23115471589 ps |
| CPU time | 456.68 seconds |
| Started | Aug 23 01:14:28 PM UTC 24 |
| Finished | Aug 23 01:22:10 PM UTC 24 |
| Peak memory | 211708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177631229 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_partial_ac cess_b2b.177631229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/10.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.3576255384 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 355704080 ps |
| CPU time | 2.98 seconds |
| Started | Aug 23 01:15:47 PM UTC 24 |
| Finished | Aug 23 01:15:51 PM UTC 24 |
| Peak memory | 211696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576255384 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.3576255384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/10.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_regwen.1932023909 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 11396609004 ps |
| CPU time | 392.14 seconds |
| Started | Aug 23 01:15:35 PM UTC 24 |
| Finished | Aug 23 01:22:11 PM UTC 24 |
| Peak memory | 388760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932023909 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.1932023909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/10.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_smoke.2014837237 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 743102492 ps |
| CPU time | 9.42 seconds |
| Started | Aug 23 01:13:42 PM UTC 24 |
| Finished | Aug 23 01:13:52 PM UTC 24 |
| Peak memory | 211576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014837237 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.2014837237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/10.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all.1098443719 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 41823599645 ps |
| CPU time | 2385.24 seconds |
| Started | Aug 23 01:16:41 PM UTC 24 |
| Finished | Aug 23 01:56:47 PM UTC 24 |
| Peak memory | 390260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10984437 19 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_a ll.1098443719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/10.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1768360277 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 592661944 ps |
| CPU time | 8.51 seconds |
| Started | Aug 23 01:16:37 PM UTC 24 |
| Finished | Aug 23 01:16:47 PM UTC 24 |
| Peak memory | 222072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768360277 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.1768360277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/10.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.1996261704 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 37248608788 ps |
| CPU time | 379.84 seconds |
| Started | Aug 23 01:14:23 PM UTC 24 |
| Finished | Aug 23 01:20:47 PM UTC 24 |
| Peak memory | 211628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996261704 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_pipeline.1996261704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/10.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.4164773356 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 3276048946 ps |
| CPU time | 40.27 seconds |
| Started | Aug 23 01:15:04 PM UTC 24 |
| Finished | Aug 23 01:15:46 PM UTC 24 |
| Peak memory | 339420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =4164773356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl _throughput_w_partial_write.4164773356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/10.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.1482079753 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 12731733157 ps |
| CPU time | 609.74 seconds |
| Started | Aug 23 01:18:27 PM UTC 24 |
| Finished | Aug 23 01:28:43 PM UTC 24 |
| Peak memory | 388636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482079753 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_access_duri ng_key_req.1482079753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/11.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_alert_test.1319477137 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 24901248 ps |
| CPU time | 0.57 seconds |
| Started | Aug 23 01:21:00 PM UTC 24 |
| Finished | Aug 23 01:21:02 PM UTC 24 |
| Peak memory | 210740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319477137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_alert_test.1319477137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/11.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_bijection.1449527122 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 364419568891 ps |
| CPU time | 1764.1 seconds |
| Started | Aug 23 01:16:54 PM UTC 24 |
| Finished | Aug 23 01:46:36 PM UTC 24 |
| Peak memory | 213300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449527122 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection.1449527122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/11.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_executable.4294136680 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 24654994266 ps |
| CPU time | 386.79 seconds |
| Started | Aug 23 01:18:32 PM UTC 24 |
| Finished | Aug 23 01:25:03 PM UTC 24 |
| Peak memory | 384544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294136680 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executable.4294136680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/11.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.1194897015 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 24187870353 ps |
| CPU time | 13.4 seconds |
| Started | Aug 23 01:18:12 PM UTC 24 |
| Finished | Aug 23 01:18:26 PM UTC 24 |
| Peak memory | 211628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194897015 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_escalation.1194897015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/11.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.2890703831 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 738548240 ps |
| CPU time | 16.51 seconds |
| Started | Aug 23 01:17:44 PM UTC 24 |
| Finished | Aug 23 01:18:02 PM UTC 24 |
| Peak memory | 282216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2890703831 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ max_throughput.2890703831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/11.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.663723601 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 1398938132 ps |
| CPU time | 63.19 seconds |
| Started | Aug 23 01:20:15 PM UTC 24 |
| Finished | Aug 23 01:21:20 PM UTC 24 |
| Peak memory | 221740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663723601 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_mem_partial_access.663723601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/11.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.2790572968 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 32916157124 ps |
| CPU time | 140.73 seconds |
| Started | Aug 23 01:19:44 PM UTC 24 |
| Finished | Aug 23 01:22:07 PM UTC 24 |
| Peak memory | 221876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790572968 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_mem_walk.2790572968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/11.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.1031351776 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 19789727162 ps |
| CPU time | 765.71 seconds |
| Started | Aug 23 01:16:52 PM UTC 24 |
| Finished | Aug 23 01:29:45 PM UTC 24 |
| Peak memory | 386592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031351776 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multiple_keys.1031351776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/11.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access.280810787 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 2194294745 ps |
| CPU time | 9.98 seconds |
| Started | Aug 23 01:17:32 PM UTC 24 |
| Finished | Aug 23 01:17:43 PM UTC 24 |
| Peak memory | 211632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280810787 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_partial_access.280810787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/11.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.1893022680 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 98590150991 ps |
| CPU time | 589.3 seconds |
| Started | Aug 23 01:17:44 PM UTC 24 |
| Finished | Aug 23 01:27:40 PM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893022680 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_partial_a ccess_b2b.1893022680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/11.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.4175517071 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 1356828254 ps |
| CPU time | 3.55 seconds |
| Started | Aug 23 01:19:38 PM UTC 24 |
| Finished | Aug 23 01:19:43 PM UTC 24 |
| Peak memory | 211888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175517071 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.4175517071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/11.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_regwen.696086990 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 10889514082 ps |
| CPU time | 141.49 seconds |
| Started | Aug 23 01:18:42 PM UTC 24 |
| Finished | Aug 23 01:21:06 PM UTC 24 |
| Peak memory | 374228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696086990 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.696086990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/11.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_smoke.567371369 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 359309565 ps |
| CPU time | 3.11 seconds |
| Started | Aug 23 01:16:49 PM UTC 24 |
| Finished | Aug 23 01:16:53 PM UTC 24 |
| Peak memory | 211228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567371369 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.567371369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/11.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all.3348080716 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 213747792520 ps |
| CPU time | 2749.46 seconds |
| Started | Aug 23 01:20:59 PM UTC 24 |
| Finished | Aug 23 02:07:15 PM UTC 24 |
| Peak memory | 390228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33480807 16 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_a ll.3348080716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/11.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1665697351 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1051611102 ps |
| CPU time | 26.6 seconds |
| Started | Aug 23 01:20:48 PM UTC 24 |
| Finished | Aug 23 01:21:16 PM UTC 24 |
| Peak memory | 221884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665697351 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.1665697351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/11.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.1301461364 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 9351054520 ps |
| CPU time | 242.9 seconds |
| Started | Aug 23 01:17:25 PM UTC 24 |
| Finished | Aug 23 01:21:32 PM UTC 24 |
| Peak memory | 211632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301461364 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_pipeline.1301461364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/11.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.3959376103 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 762171037 ps |
| CPU time | 37.19 seconds |
| Started | Aug 23 01:18:03 PM UTC 24 |
| Finished | Aug 23 01:18:41 PM UTC 24 |
| Peak memory | 347612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3959376103 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl _throughput_w_partial_write.3959376103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/11.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.3669590666 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 52809939428 ps |
| CPU time | 425.79 seconds |
| Started | Aug 23 01:22:11 PM UTC 24 |
| Finished | Aug 23 01:29:22 PM UTC 24 |
| Peak memory | 380364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669590666 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_access_duri ng_key_req.3669590666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/12.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_alert_test.3443626637 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 24383915 ps |
| CPU time | 0.57 seconds |
| Started | Aug 23 01:24:03 PM UTC 24 |
| Finished | Aug 23 01:24:04 PM UTC 24 |
| Peak memory | 210876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443626637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_alert_test.3443626637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/12.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_bijection.2596808085 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 374118109165 ps |
| CPU time | 1296.52 seconds |
| Started | Aug 23 01:21:18 PM UTC 24 |
| Finished | Aug 23 01:43:07 PM UTC 24 |
| Peak memory | 213172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596808085 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection.2596808085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/12.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_executable.1536190855 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 86091282085 ps |
| CPU time | 258.52 seconds |
| Started | Aug 23 01:22:12 PM UTC 24 |
| Finished | Aug 23 01:26:34 PM UTC 24 |
| Peak memory | 359908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536190855 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executable.1536190855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/12.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.2154069572 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 31076280531 ps |
| CPU time | 58.63 seconds |
| Started | Aug 23 01:22:08 PM UTC 24 |
| Finished | Aug 23 01:23:08 PM UTC 24 |
| Peak memory | 221872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154069572 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_escalation.2154069572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/12.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.272803445 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 3059349015 ps |
| CPU time | 55.77 seconds |
| Started | Aug 23 01:21:32 PM UTC 24 |
| Finished | Aug 23 01:22:29 PM UTC 24 |
| Peak memory | 382424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 272803445 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_m ax_throughput.272803445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/12.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.1255781997 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 3087044450 ps |
| CPU time | 68.36 seconds |
| Started | Aug 23 01:23:10 PM UTC 24 |
| Finished | Aug 23 01:24:20 PM UTC 24 |
| Peak memory | 221924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255781997 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_mem_partial_access.1255781997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/12.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.4067878884 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 5416561540 ps |
| CPU time | 258.98 seconds |
| Started | Aug 23 01:22:35 PM UTC 24 |
| Finished | Aug 23 01:26:58 PM UTC 24 |
| Peak memory | 221824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067878884 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_mem_walk.4067878884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/12.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.2824997864 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 54121980176 ps |
| CPU time | 689.26 seconds |
| Started | Aug 23 01:21:07 PM UTC 24 |
| Finished | Aug 23 01:32:43 PM UTC 24 |
| Peak memory | 388564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824997864 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multiple_keys.2824997864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/12.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access.401914703 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 3633948310 ps |
| CPU time | 11.92 seconds |
| Started | Aug 23 01:21:20 PM UTC 24 |
| Finished | Aug 23 01:21:33 PM UTC 24 |
| Peak memory | 211488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401914703 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_partial_access.401914703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/12.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.711261870 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 11878176684 ps |
| CPU time | 474.88 seconds |
| Started | Aug 23 01:21:21 PM UTC 24 |
| Finished | Aug 23 01:29:21 PM UTC 24 |
| Peak memory | 211552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711261870 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_partial_ac cess_b2b.711261870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/12.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.1556056422 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 1554589968 ps |
| CPU time | 3.14 seconds |
| Started | Aug 23 01:22:30 PM UTC 24 |
| Finished | Aug 23 01:22:35 PM UTC 24 |
| Peak memory | 211888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556056422 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.1556056422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/12.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_regwen.2790054139 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 6771992715 ps |
| CPU time | 357.33 seconds |
| Started | Aug 23 01:22:17 PM UTC 24 |
| Finished | Aug 23 01:28:19 PM UTC 24 |
| Peak memory | 384476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790054139 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.2790054139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/12.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_smoke.1464336842 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 1637779567 ps |
| CPU time | 13.8 seconds |
| Started | Aug 23 01:21:03 PM UTC 24 |
| Finished | Aug 23 01:21:18 PM UTC 24 |
| Peak memory | 211512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464336842 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.1464336842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/12.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all.1459659050 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 185167376713 ps |
| CPU time | 3180.47 seconds |
| Started | Aug 23 01:23:37 PM UTC 24 |
| Finished | Aug 23 02:17:06 PM UTC 24 |
| Peak memory | 400488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14596590 50 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_a ll.1459659050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/12.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.958644949 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 24059694231 ps |
| CPU time | 45.85 seconds |
| Started | Aug 23 01:23:15 PM UTC 24 |
| Finished | Aug 23 01:24:02 PM UTC 24 |
| Peak memory | 282396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958644949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.958644949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/12.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.2668074544 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 3686397098 ps |
| CPU time | 135.25 seconds |
| Started | Aug 23 01:21:19 PM UTC 24 |
| Finished | Aug 23 01:23:36 PM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668074544 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_pipeline.2668074544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/12.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.3898385341 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 814966056 ps |
| CPU time | 40.91 seconds |
| Started | Aug 23 01:21:34 PM UTC 24 |
| Finished | Aug 23 01:22:16 PM UTC 24 |
| Peak memory | 351844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3898385341 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl _throughput_w_partial_write.3898385341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/12.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.1460770273 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 14638056101 ps |
| CPU time | 533.35 seconds |
| Started | Aug 23 01:27:45 PM UTC 24 |
| Finished | Aug 23 01:36:44 PM UTC 24 |
| Peak memory | 388844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460770273 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_access_duri ng_key_req.1460770273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/13.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_alert_test.3088187660 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 63220517 ps |
| CPU time | 0.58 seconds |
| Started | Aug 23 01:29:20 PM UTC 24 |
| Finished | Aug 23 01:29:22 PM UTC 24 |
| Peak memory | 210876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088187660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_alert_test.3088187660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/13.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_bijection.3364221236 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 147248163265 ps |
| CPU time | 1372.85 seconds |
| Started | Aug 23 01:24:40 PM UTC 24 |
| Finished | Aug 23 01:47:47 PM UTC 24 |
| Peak memory | 213256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364221236 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection.3364221236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/13.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_executable.1101727863 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 11881915549 ps |
| CPU time | 317.92 seconds |
| Started | Aug 23 01:27:46 PM UTC 24 |
| Finished | Aug 23 01:33:08 PM UTC 24 |
| Peak memory | 380464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101727863 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executable.1101727863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/13.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.808750464 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 15106081610 ps |
| CPU time | 50.92 seconds |
| Started | Aug 23 01:27:41 PM UTC 24 |
| Finished | Aug 23 01:28:33 PM UTC 24 |
| Peak memory | 221800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808750464 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_escalation.808750464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/13.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.2421908517 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 737355058 ps |
| CPU time | 19.26 seconds |
| Started | Aug 23 01:26:59 PM UTC 24 |
| Finished | Aug 23 01:27:19 PM UTC 24 |
| Peak memory | 294504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2421908517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ max_throughput.2421908517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/13.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.2043930597 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 2708418678 ps |
| CPU time | 63.8 seconds |
| Started | Aug 23 01:28:43 PM UTC 24 |
| Finished | Aug 23 01:29:49 PM UTC 24 |
| Peak memory | 221800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043930597 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_mem_partial_access.2043930597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/13.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.3775961451 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 10109890939 ps |
| CPU time | 130.6 seconds |
| Started | Aug 23 01:28:39 PM UTC 24 |
| Finished | Aug 23 01:30:52 PM UTC 24 |
| Peak memory | 221892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775961451 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_mem_walk.3775961451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/13.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.1978640793 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 6725289249 ps |
| CPU time | 272.8 seconds |
| Started | Aug 23 01:24:20 PM UTC 24 |
| Finished | Aug 23 01:28:56 PM UTC 24 |
| Peak memory | 362020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978640793 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multiple_keys.1978640793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/13.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access.2042661559 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 511729323 ps |
| CPU time | 11.64 seconds |
| Started | Aug 23 01:26:36 PM UTC 24 |
| Finished | Aug 23 01:26:48 PM UTC 24 |
| Peak memory | 211624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042661559 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_partial_access.2042661559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/13.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.4131082658 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 27280575434 ps |
| CPU time | 374.29 seconds |
| Started | Aug 23 01:26:50 PM UTC 24 |
| Finished | Aug 23 01:33:08 PM UTC 24 |
| Peak memory | 211568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131082658 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_partial_a ccess_b2b.4131082658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/13.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.188894391 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 1363296426 ps |
| CPU time | 3.09 seconds |
| Started | Aug 23 01:28:34 PM UTC 24 |
| Finished | Aug 23 01:28:38 PM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188894391 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.188894391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/13.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_regwen.2849294667 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 37882745129 ps |
| CPU time | 474.2 seconds |
| Started | Aug 23 01:28:20 PM UTC 24 |
| Finished | Aug 23 01:36:20 PM UTC 24 |
| Peak memory | 382492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849294667 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.2849294667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/13.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_smoke.2031056717 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 1211655720 ps |
| CPU time | 33.03 seconds |
| Started | Aug 23 01:24:05 PM UTC 24 |
| Finished | Aug 23 01:24:39 PM UTC 24 |
| Peak memory | 335324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031056717 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.2031056717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/13.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all.3557488149 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 49062999976 ps |
| CPU time | 2737.93 seconds |
| Started | Aug 23 01:28:57 PM UTC 24 |
| Finished | Aug 23 02:15:00 PM UTC 24 |
| Peak memory | 400412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35574881 49 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_a ll.3557488149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/13.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.3189079220 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 1556390857 ps |
| CPU time | 25.7 seconds |
| Started | Aug 23 01:28:52 PM UTC 24 |
| Finished | Aug 23 01:29:19 PM UTC 24 |
| Peak memory | 221864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189079220 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.3189079220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/13.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.1748316378 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 23920529504 ps |
| CPU time | 224.52 seconds |
| Started | Aug 23 01:25:04 PM UTC 24 |
| Finished | Aug 23 01:28:52 PM UTC 24 |
| Peak memory | 211652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748316378 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_pipeline.1748316378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/13.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.3552142525 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 2924693565 ps |
| CPU time | 23.19 seconds |
| Started | Aug 23 01:27:20 PM UTC 24 |
| Finished | Aug 23 01:27:44 PM UTC 24 |
| Peak memory | 302812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3552142525 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl _throughput_w_partial_write.3552142525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/13.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.3190065675 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 163927169587 ps |
| CPU time | 528.91 seconds |
| Started | Aug 23 01:30:34 PM UTC 24 |
| Finished | Aug 23 01:39:29 PM UTC 24 |
| Peak memory | 380464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190065675 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_access_duri ng_key_req.3190065675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/14.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_alert_test.197996163 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 21712985 ps |
| CPU time | 0.57 seconds |
| Started | Aug 23 01:33:08 PM UTC 24 |
| Finished | Aug 23 01:33:11 PM UTC 24 |
| Peak memory | 210740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197996163 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_alert_test.197996163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/14.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_bijection.1033773454 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 37044348468 ps |
| CPU time | 735.3 seconds |
| Started | Aug 23 01:29:23 PM UTC 24 |
| Finished | Aug 23 01:41:46 PM UTC 24 |
| Peak memory | 211496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033773454 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection.1033773454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/14.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_executable.1266833406 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 99151581839 ps |
| CPU time | 497.15 seconds |
| Started | Aug 23 01:30:53 PM UTC 24 |
| Finished | Aug 23 01:39:16 PM UTC 24 |
| Peak memory | 384472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266833406 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executable.1266833406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/14.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.58741685 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 6447976429 ps |
| CPU time | 37.97 seconds |
| Started | Aug 23 01:30:25 PM UTC 24 |
| Finished | Aug 23 01:31:04 PM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58741685 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_escalation.58741685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/14.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.1761056725 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 772514047 ps |
| CPU time | 38.99 seconds |
| Started | Aug 23 01:29:53 PM UTC 24 |
| Finished | Aug 23 01:30:33 PM UTC 24 |
| Peak memory | 351720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1761056725 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ max_throughput.1761056725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/14.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.82901939 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 21756433332 ps |
| CPU time | 146.3 seconds |
| Started | Aug 23 01:31:57 PM UTC 24 |
| Finished | Aug 23 01:34:25 PM UTC 24 |
| Peak memory | 222064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82901939 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_mem_partial_access.82901939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/14.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.2762388542 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 2771788485 ps |
| CPU time | 127.65 seconds |
| Started | Aug 23 01:31:52 PM UTC 24 |
| Finished | Aug 23 01:34:02 PM UTC 24 |
| Peak memory | 221888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762388542 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_mem_walk.2762388542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/14.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.1857852891 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 24206508967 ps |
| CPU time | 314.21 seconds |
| Started | Aug 23 01:29:23 PM UTC 24 |
| Finished | Aug 23 01:34:40 PM UTC 24 |
| Peak memory | 366052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857852891 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multiple_keys.1857852891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/14.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access.3232078969 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 1343310897 ps |
| CPU time | 6.45 seconds |
| Started | Aug 23 01:29:46 PM UTC 24 |
| Finished | Aug 23 01:29:53 PM UTC 24 |
| Peak memory | 211308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232078969 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_partial_access.3232078969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/14.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.968261346 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 15796369854 ps |
| CPU time | 296.31 seconds |
| Started | Aug 23 01:29:50 PM UTC 24 |
| Finished | Aug 23 01:34:50 PM UTC 24 |
| Peak memory | 211628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968261346 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_partial_ac cess_b2b.968261346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/14.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.674170396 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 1410149045 ps |
| CPU time | 3.53 seconds |
| Started | Aug 23 01:31:51 PM UTC 24 |
| Finished | Aug 23 01:31:55 PM UTC 24 |
| Peak memory | 211844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674170396 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.674170396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/14.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_regwen.2201343913 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 82338444742 ps |
| CPU time | 967.06 seconds |
| Started | Aug 23 01:31:05 PM UTC 24 |
| Finished | Aug 23 01:47:22 PM UTC 24 |
| Peak memory | 390328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201343913 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.2201343913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/14.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_smoke.661710857 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 689466329 ps |
| CPU time | 9.64 seconds |
| Started | Aug 23 01:29:23 PM UTC 24 |
| Finished | Aug 23 01:29:33 PM UTC 24 |
| Peak memory | 211576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661710857 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.661710857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/14.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_all.3496379017 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 214168231284 ps |
| CPU time | 4052.66 seconds |
| Started | Aug 23 01:32:55 PM UTC 24 |
| Finished | Aug 23 02:41:05 PM UTC 24 |
| Peak memory | 398448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34963790 17 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_a ll.3496379017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/14.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.4039951673 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 1003531363 ps |
| CPU time | 8.87 seconds |
| Started | Aug 23 01:32:44 PM UTC 24 |
| Finished | Aug 23 01:32:54 PM UTC 24 |
| Peak memory | 228100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039951673 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.4039951673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/14.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.272597777 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 4131373459 ps |
| CPU time | 133.66 seconds |
| Started | Aug 23 01:29:34 PM UTC 24 |
| Finished | Aug 23 01:31:50 PM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272597777 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_pipeline.272597777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/14.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.2263031209 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 776029748 ps |
| CPU time | 29.01 seconds |
| Started | Aug 23 01:29:54 PM UTC 24 |
| Finished | Aug 23 01:30:24 PM UTC 24 |
| Peak memory | 329104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2263031209 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl _throughput_w_partial_write.2263031209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/14.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.1858692108 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 50504371395 ps |
| CPU time | 386.71 seconds |
| Started | Aug 23 01:34:56 PM UTC 24 |
| Finished | Aug 23 01:41:27 PM UTC 24 |
| Peak memory | 380452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858692108 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_access_duri ng_key_req.1858692108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/15.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_alert_test.3582094644 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 23429288 ps |
| CPU time | 0.58 seconds |
| Started | Aug 23 01:37:25 PM UTC 24 |
| Finished | Aug 23 01:37:27 PM UTC 24 |
| Peak memory | 210740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582094644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_alert_test.3582094644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/15.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_bijection.1249463703 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 33476639876 ps |
| CPU time | 645.07 seconds |
| Started | Aug 23 01:33:21 PM UTC 24 |
| Finished | Aug 23 01:44:13 PM UTC 24 |
| Peak memory | 211644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249463703 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection.1249463703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/15.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_executable.3987544981 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 25563394872 ps |
| CPU time | 270.76 seconds |
| Started | Aug 23 01:35:14 PM UTC 24 |
| Finished | Aug 23 01:39:48 PM UTC 24 |
| Peak memory | 386528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987544981 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executable.3987544981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/15.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.1239746337 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 6417841012 ps |
| CPU time | 39.41 seconds |
| Started | Aug 23 01:34:51 PM UTC 24 |
| Finished | Aug 23 01:35:31 PM UTC 24 |
| Peak memory | 211568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239746337 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_escalation.1239746337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/15.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.4289527801 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 2805299500 ps |
| CPU time | 26.93 seconds |
| Started | Aug 23 01:34:27 PM UTC 24 |
| Finished | Aug 23 01:34:55 PM UTC 24 |
| Peak memory | 312884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4289527801 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ max_throughput.4289527801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/15.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.321201862 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 5763733560 ps |
| CPU time | 63.14 seconds |
| Started | Aug 23 01:36:25 PM UTC 24 |
| Finished | Aug 23 01:37:30 PM UTC 24 |
| Peak memory | 221956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321201862 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_mem_partial_access.321201862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/15.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.2724802853 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 4111481121 ps |
| CPU time | 107.86 seconds |
| Started | Aug 23 01:36:22 PM UTC 24 |
| Finished | Aug 23 01:38:12 PM UTC 24 |
| Peak memory | 221820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724802853 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_mem_walk.2724802853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/15.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.3038120640 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 59793086810 ps |
| CPU time | 455.45 seconds |
| Started | Aug 23 01:33:11 PM UTC 24 |
| Finished | Aug 23 01:40:52 PM UTC 24 |
| Peak memory | 388564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038120640 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multiple_keys.3038120640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/15.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access.3336037499 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 8788668517 ps |
| CPU time | 21.83 seconds |
| Started | Aug 23 01:34:02 PM UTC 24 |
| Finished | Aug 23 01:34:25 PM UTC 24 |
| Peak memory | 211640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336037499 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_partial_access.3336037499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/15.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.3213710198 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 15445263200 ps |
| CPU time | 234.68 seconds |
| Started | Aug 23 01:34:27 PM UTC 24 |
| Finished | Aug 23 01:38:24 PM UTC 24 |
| Peak memory | 211456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213710198 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_partial_a ccess_b2b.3213710198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/15.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.4214472175 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 1414619743 ps |
| CPU time | 3.26 seconds |
| Started | Aug 23 01:36:20 PM UTC 24 |
| Finished | Aug 23 01:36:24 PM UTC 24 |
| Peak memory | 211824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214472175 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.4214472175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/15.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_regwen.3033330110 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 62513293675 ps |
| CPU time | 276.13 seconds |
| Started | Aug 23 01:35:32 PM UTC 24 |
| Finished | Aug 23 01:40:11 PM UTC 24 |
| Peak memory | 362020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033330110 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.3033330110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/15.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_smoke.3272768670 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 953219997 ps |
| CPU time | 15.23 seconds |
| Started | Aug 23 01:33:09 PM UTC 24 |
| Finished | Aug 23 01:33:26 PM UTC 24 |
| Peak memory | 263668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272768670 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.3272768670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/15.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all.744124210 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 112139771491 ps |
| CPU time | 2612.81 seconds |
| Started | Aug 23 01:36:46 PM UTC 24 |
| Finished | Aug 23 02:20:44 PM UTC 24 |
| Peak memory | 394420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74412421 0 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all.744124210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/15.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.4111059654 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 4083456493 ps |
| CPU time | 37.36 seconds |
| Started | Aug 23 01:36:45 PM UTC 24 |
| Finished | Aug 23 01:37:24 PM UTC 24 |
| Peak memory | 221928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111059654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.4111059654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/15.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.2825463827 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 12466093833 ps |
| CPU time | 195.24 seconds |
| Started | Aug 23 01:33:27 PM UTC 24 |
| Finished | Aug 23 01:36:45 PM UTC 24 |
| Peak memory | 211832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825463827 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_pipeline.2825463827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/15.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.2415128662 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 3013587134 ps |
| CPU time | 30.38 seconds |
| Started | Aug 23 01:34:42 PM UTC 24 |
| Finished | Aug 23 01:35:13 PM UTC 24 |
| Peak memory | 335396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2415128662 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl _throughput_w_partial_write.2415128662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/15.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.3252804536 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 69221356980 ps |
| CPU time | 608.75 seconds |
| Started | Aug 23 01:39:29 PM UTC 24 |
| Finished | Aug 23 01:49:44 PM UTC 24 |
| Peak memory | 388712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252804536 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_access_duri ng_key_req.3252804536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/16.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_alert_test.4208257301 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 36642718 ps |
| CPU time | 0.54 seconds |
| Started | Aug 23 01:40:56 PM UTC 24 |
| Finished | Aug 23 01:40:57 PM UTC 24 |
| Peak memory | 210740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208257301 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_alert_test.4208257301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/16.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_executable.3307826674 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 27018157718 ps |
| CPU time | 830.13 seconds |
| Started | Aug 23 01:39:49 PM UTC 24 |
| Finished | Aug 23 01:53:48 PM UTC 24 |
| Peak memory | 390316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307826674 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executable.3307826674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/16.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.1970921282 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 16928905434 ps |
| CPU time | 88.17 seconds |
| Started | Aug 23 01:39:16 PM UTC 24 |
| Finished | Aug 23 01:40:46 PM UTC 24 |
| Peak memory | 211648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970921282 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_escalation.1970921282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/16.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.3485859878 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 3020581988 ps |
| CPU time | 23.36 seconds |
| Started | Aug 23 01:38:42 PM UTC 24 |
| Finished | Aug 23 01:39:07 PM UTC 24 |
| Peak memory | 302820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3485859878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ max_throughput.3485859878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/16.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.1235452098 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 2480762419 ps |
| CPU time | 126.24 seconds |
| Started | Aug 23 01:40:47 PM UTC 24 |
| Finished | Aug 23 01:42:56 PM UTC 24 |
| Peak memory | 221872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235452098 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_mem_partial_access.1235452098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/16.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.3614081353 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 4937735741 ps |
| CPU time | 107.74 seconds |
| Started | Aug 23 01:40:17 PM UTC 24 |
| Finished | Aug 23 01:42:07 PM UTC 24 |
| Peak memory | 221824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614081353 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_mem_walk.3614081353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/16.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.3215261052 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 39703187007 ps |
| CPU time | 720.12 seconds |
| Started | Aug 23 01:37:31 PM UTC 24 |
| Finished | Aug 23 01:49:38 PM UTC 24 |
| Peak memory | 384640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215261052 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multiple_keys.3215261052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/16.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access.4126098741 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 474613694 ps |
| CPU time | 26.62 seconds |
| Started | Aug 23 01:38:13 PM UTC 24 |
| Finished | Aug 23 01:38:41 PM UTC 24 |
| Peak memory | 310676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126098741 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_partial_access.4126098741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/16.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.1103753513 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 31029569331 ps |
| CPU time | 686.73 seconds |
| Started | Aug 23 01:38:25 PM UTC 24 |
| Finished | Aug 23 01:49:59 PM UTC 24 |
| Peak memory | 211812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103753513 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_partial_a ccess_b2b.1103753513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/16.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.367803560 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 357986066 ps |
| CPU time | 3.15 seconds |
| Started | Aug 23 01:40:12 PM UTC 24 |
| Finished | Aug 23 01:40:17 PM UTC 24 |
| Peak memory | 211708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367803560 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.367803560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/16.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_regwen.802912973 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 13465546229 ps |
| CPU time | 569.38 seconds |
| Started | Aug 23 01:39:56 PM UTC 24 |
| Finished | Aug 23 01:49:32 PM UTC 24 |
| Peak memory | 368072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802912973 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.802912973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/16.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_smoke.2568723067 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 685704817 ps |
| CPU time | 7.2 seconds |
| Started | Aug 23 01:37:27 PM UTC 24 |
| Finished | Aug 23 01:37:36 PM UTC 24 |
| Peak memory | 220644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568723067 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.2568723067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/16.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all.545631753 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 390324552036 ps |
| CPU time | 4676.93 seconds |
| Started | Aug 23 01:40:53 PM UTC 24 |
| Finished | Aug 23 02:59:34 PM UTC 24 |
| Peak memory | 390324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54563175 3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all.545631753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/16.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.1833570348 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 262711528 ps |
| CPU time | 8.25 seconds |
| Started | Aug 23 01:40:49 PM UTC 24 |
| Finished | Aug 23 01:40:58 PM UTC 24 |
| Peak memory | 221936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833570348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.1833570348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/16.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.1762849319 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 11154112131 ps |
| CPU time | 182.6 seconds |
| Started | Aug 23 01:38:07 PM UTC 24 |
| Finished | Aug 23 01:41:12 PM UTC 24 |
| Peak memory | 211760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762849319 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_pipeline.1762849319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/16.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.4068372117 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 3090002964 ps |
| CPU time | 47.18 seconds |
| Started | Aug 23 01:39:07 PM UTC 24 |
| Finished | Aug 23 01:39:56 PM UTC 24 |
| Peak memory | 364196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =4068372117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl _throughput_w_partial_write.4068372117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/16.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.2027915511 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 11582799709 ps |
| CPU time | 503.44 seconds |
| Started | Aug 23 01:42:14 PM UTC 24 |
| Finished | Aug 23 01:50:43 PM UTC 24 |
| Peak memory | 382428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027915511 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_access_duri ng_key_req.2027915511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/17.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_alert_test.2600240181 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 26803948 ps |
| CPU time | 0.55 seconds |
| Started | Aug 23 01:44:14 PM UTC 24 |
| Finished | Aug 23 01:44:16 PM UTC 24 |
| Peak memory | 210816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600240181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_alert_test.2600240181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/17.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_bijection.1456551964 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 101564973084 ps |
| CPU time | 628.69 seconds |
| Started | Aug 23 01:41:13 PM UTC 24 |
| Finished | Aug 23 01:51:49 PM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456551964 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection.1456551964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/17.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_executable.3948152402 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 46602116135 ps |
| CPU time | 247.77 seconds |
| Started | Aug 23 01:42:16 PM UTC 24 |
| Finished | Aug 23 01:46:27 PM UTC 24 |
| Peak memory | 378340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948152402 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executable.3948152402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/17.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.3431455744 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 39480561361 ps |
| CPU time | 47.61 seconds |
| Started | Aug 23 01:42:08 PM UTC 24 |
| Finished | Aug 23 01:42:58 PM UTC 24 |
| Peak memory | 221740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431455744 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_escalation.3431455744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/17.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.466242349 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 3072982611 ps |
| CPU time | 26.46 seconds |
| Started | Aug 23 01:41:46 PM UTC 24 |
| Finished | Aug 23 01:42:14 PM UTC 24 |
| Peak memory | 321200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 466242349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_m ax_throughput.466242349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/17.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.2652710688 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 10109060851 ps |
| CPU time | 127.33 seconds |
| Started | Aug 23 01:43:02 PM UTC 24 |
| Finished | Aug 23 01:45:11 PM UTC 24 |
| Peak memory | 221936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652710688 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_mem_partial_access.2652710688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/17.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.3164070110 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 18473568872 ps |
| CPU time | 297.7 seconds |
| Started | Aug 23 01:42:59 PM UTC 24 |
| Finished | Aug 23 01:48:00 PM UTC 24 |
| Peak memory | 211912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164070110 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_mem_walk.3164070110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/17.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.3191038886 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 65510587694 ps |
| CPU time | 596.92 seconds |
| Started | Aug 23 01:40:59 PM UTC 24 |
| Finished | Aug 23 01:51:02 PM UTC 24 |
| Peak memory | 384564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191038886 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multiple_keys.3191038886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/17.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access.1799058655 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 1250189101 ps |
| CPU time | 14.24 seconds |
| Started | Aug 23 01:41:28 PM UTC 24 |
| Finished | Aug 23 01:41:44 PM UTC 24 |
| Peak memory | 211712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799058655 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_partial_access.1799058655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/17.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.3837822900 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 15442107798 ps |
| CPU time | 280.87 seconds |
| Started | Aug 23 01:41:44 PM UTC 24 |
| Finished | Aug 23 01:46:29 PM UTC 24 |
| Peak memory | 211644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837822900 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_partial_a ccess_b2b.3837822900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/17.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.315256015 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 705870329 ps |
| CPU time | 3.27 seconds |
| Started | Aug 23 01:42:57 PM UTC 24 |
| Finished | Aug 23 01:43:01 PM UTC 24 |
| Peak memory | 211708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315256015 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.315256015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/17.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_regwen.4170296825 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 21034236548 ps |
| CPU time | 356.58 seconds |
| Started | Aug 23 01:42:40 PM UTC 24 |
| Finished | Aug 23 01:48:41 PM UTC 24 |
| Peak memory | 388908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170296825 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.4170296825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/17.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_smoke.3928702949 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 744961004 ps |
| CPU time | 23.02 seconds |
| Started | Aug 23 01:40:58 PM UTC 24 |
| Finished | Aug 23 01:41:22 PM UTC 24 |
| Peak memory | 306672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928702949 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.3928702949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/17.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all.3255095157 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 152800689257 ps |
| CPU time | 859.15 seconds |
| Started | Aug 23 01:44:09 PM UTC 24 |
| Finished | Aug 23 01:58:38 PM UTC 24 |
| Peak memory | 215292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32550951 57 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_a ll.3255095157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/17.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.2396967532 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 5524954821 ps |
| CPU time | 58.75 seconds |
| Started | Aug 23 01:43:08 PM UTC 24 |
| Finished | Aug 23 01:44:08 PM UTC 24 |
| Peak memory | 327520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396967532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.2396967532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/17.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.821010208 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 9845360956 ps |
| CPU time | 273.88 seconds |
| Started | Aug 23 01:41:23 PM UTC 24 |
| Finished | Aug 23 01:46:01 PM UTC 24 |
| Peak memory | 211816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821010208 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_pipeline.821010208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/17.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.1177056201 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 1416061121 ps |
| CPU time | 10.68 seconds |
| Started | Aug 23 01:42:03 PM UTC 24 |
| Finished | Aug 23 01:42:15 PM UTC 24 |
| Peak memory | 249308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1177056201 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl _throughput_w_partial_write.1177056201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/17.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.4139729701 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 28699691531 ps |
| CPU time | 681.34 seconds |
| Started | Aug 23 01:47:22 PM UTC 24 |
| Finished | Aug 23 01:58:51 PM UTC 24 |
| Peak memory | 388772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139729701 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_access_duri ng_key_req.4139729701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/18.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_alert_test.1665417301 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 65032755 ps |
| CPU time | 0.59 seconds |
| Started | Aug 23 01:49:32 PM UTC 24 |
| Finished | Aug 23 01:49:34 PM UTC 24 |
| Peak memory | 210876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665417301 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_alert_test.1665417301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/18.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_bijection.694931051 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 79127427545 ps |
| CPU time | 1577.36 seconds |
| Started | Aug 23 01:45:14 PM UTC 24 |
| Finished | Aug 23 02:11:47 PM UTC 24 |
| Peak memory | 213428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694931051 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection.694931051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/18.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_executable.3453467261 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 4347018635 ps |
| CPU time | 169.35 seconds |
| Started | Aug 23 01:47:45 PM UTC 24 |
| Finished | Aug 23 01:50:37 PM UTC 24 |
| Peak memory | 364052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453467261 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executable.3453467261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/18.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.79208834 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 11108203919 ps |
| CPU time | 69.87 seconds |
| Started | Aug 23 01:46:45 PM UTC 24 |
| Finished | Aug 23 01:47:57 PM UTC 24 |
| Peak memory | 211500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79208834 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_escalation.79208834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/18.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.2513412180 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 4187488599 ps |
| CPU time | 7.03 seconds |
| Started | Aug 23 01:46:36 PM UTC 24 |
| Finished | Aug 23 01:46:44 PM UTC 24 |
| Peak memory | 221752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2513412180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ max_throughput.2513412180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/18.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.1985120975 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 5070606711 ps |
| CPU time | 127.86 seconds |
| Started | Aug 23 01:48:03 PM UTC 24 |
| Finished | Aug 23 01:50:13 PM UTC 24 |
| Peak memory | 228940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985120975 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_mem_partial_access.1985120975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/18.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.1735109706 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 10517671167 ps |
| CPU time | 138.22 seconds |
| Started | Aug 23 01:48:01 PM UTC 24 |
| Finished | Aug 23 01:50:21 PM UTC 24 |
| Peak memory | 221940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735109706 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_mem_walk.1735109706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/18.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.4053257641 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 24077147880 ps |
| CPU time | 770.54 seconds |
| Started | Aug 23 01:45:13 PM UTC 24 |
| Finished | Aug 23 01:58:11 PM UTC 24 |
| Peak memory | 386656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053257641 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multiple_keys.4053257641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/18.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access.2332332185 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 3371640781 ps |
| CPU time | 13.1 seconds |
| Started | Aug 23 01:46:27 PM UTC 24 |
| Finished | Aug 23 01:46:41 PM UTC 24 |
| Peak memory | 211544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332332185 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_partial_access.2332332185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/18.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.222477456 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 9130252111 ps |
| CPU time | 246.61 seconds |
| Started | Aug 23 01:46:29 PM UTC 24 |
| Finished | Aug 23 01:50:39 PM UTC 24 |
| Peak memory | 211624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222477456 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_partial_ac cess_b2b.222477456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/18.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.3457654464 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 706038011 ps |
| CPU time | 3.42 seconds |
| Started | Aug 23 01:47:58 PM UTC 24 |
| Finished | Aug 23 01:48:02 PM UTC 24 |
| Peak memory | 211692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457654464 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.3457654464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/18.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_regwen.298166661 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 5222739266 ps |
| CPU time | 423.28 seconds |
| Started | Aug 23 01:47:48 PM UTC 24 |
| Finished | Aug 23 01:54:56 PM UTC 24 |
| Peak memory | 384660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298166661 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.298166661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/18.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_smoke.1678653910 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 8461302725 ps |
| CPU time | 54.7 seconds |
| Started | Aug 23 01:44:16 PM UTC 24 |
| Finished | Aug 23 01:45:13 PM UTC 24 |
| Peak memory | 378528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678653910 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.1678653910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/18.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all.1996174618 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 1311968191998 ps |
| CPU time | 3917.78 seconds |
| Started | Aug 23 01:48:41 PM UTC 24 |
| Finished | Aug 23 02:54:36 PM UTC 24 |
| Peak memory | 382140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19961746 18 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_a ll.1996174618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/18.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.3717738035 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 1698508954 ps |
| CPU time | 70.58 seconds |
| Started | Aug 23 01:48:36 PM UTC 24 |
| Finished | Aug 23 01:49:48 PM UTC 24 |
| Peak memory | 306924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717738035 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.3717738035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/18.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.229985733 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 14717189321 ps |
| CPU time | 259.38 seconds |
| Started | Aug 23 01:46:01 PM UTC 24 |
| Finished | Aug 23 01:50:24 PM UTC 24 |
| Peak memory | 211644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229985733 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_pipeline.229985733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/18.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.909189741 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 2789265309 ps |
| CPU time | 60.37 seconds |
| Started | Aug 23 01:46:42 PM UTC 24 |
| Finished | Aug 23 01:47:44 PM UTC 24 |
| Peak memory | 382420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =909189741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ throughput_w_partial_write.909189741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/18.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.2536211822 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 31880512629 ps |
| CPU time | 305.02 seconds |
| Started | Aug 23 01:50:25 PM UTC 24 |
| Finished | Aug 23 01:55:33 PM UTC 24 |
| Peak memory | 388560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536211822 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_access_duri ng_key_req.2536211822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/19.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_alert_test.3677990068 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 42902008 ps |
| CPU time | 0.57 seconds |
| Started | Aug 23 01:51:33 PM UTC 24 |
| Finished | Aug 23 01:51:35 PM UTC 24 |
| Peak memory | 210876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677990068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_alert_test.3677990068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/19.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_bijection.372788491 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 55529883158 ps |
| CPU time | 820.67 seconds |
| Started | Aug 23 01:49:45 PM UTC 24 |
| Finished | Aug 23 02:03:35 PM UTC 24 |
| Peak memory | 213236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372788491 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection.372788491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/19.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_executable.3675445826 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 74240825085 ps |
| CPU time | 214.18 seconds |
| Started | Aug 23 01:50:38 PM UTC 24 |
| Finished | Aug 23 01:54:15 PM UTC 24 |
| Peak memory | 384548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675445826 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executable.3675445826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/19.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.47171574 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 22995662415 ps |
| CPU time | 72.91 seconds |
| Started | Aug 23 01:50:22 PM UTC 24 |
| Finished | Aug 23 01:51:36 PM UTC 24 |
| Peak memory | 211564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47171574 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_escalation.47171574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/19.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.1935885434 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 3034949495 ps |
| CPU time | 46.32 seconds |
| Started | Aug 23 01:50:14 PM UTC 24 |
| Finished | Aug 23 01:51:01 PM UTC 24 |
| Peak memory | 366116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1935885434 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ max_throughput.1935885434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/19.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.2099644459 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 1453191308 ps |
| CPU time | 66.35 seconds |
| Started | Aug 23 01:50:53 PM UTC 24 |
| Finished | Aug 23 01:52:01 PM UTC 24 |
| Peak memory | 221852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099644459 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_mem_partial_access.2099644459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/19.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.4263973314 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 4590533672 ps |
| CPU time | 109.34 seconds |
| Started | Aug 23 01:50:49 PM UTC 24 |
| Finished | Aug 23 01:52:41 PM UTC 24 |
| Peak memory | 222020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263973314 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_mem_walk.4263973314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/19.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.2957073488 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 22044845703 ps |
| CPU time | 563.35 seconds |
| Started | Aug 23 01:49:39 PM UTC 24 |
| Finished | Aug 23 01:59:09 PM UTC 24 |
| Peak memory | 380448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957073488 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multiple_keys.2957073488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/19.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access.2141405154 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 1518446247 ps |
| CPU time | 20.2 seconds |
| Started | Aug 23 01:49:52 PM UTC 24 |
| Finished | Aug 23 01:50:14 PM UTC 24 |
| Peak memory | 211500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141405154 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_partial_access.2141405154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/19.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.2543085427 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 4998562584 ps |
| CPU time | 260.29 seconds |
| Started | Aug 23 01:49:59 PM UTC 24 |
| Finished | Aug 23 01:54:23 PM UTC 24 |
| Peak memory | 211496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543085427 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_partial_a ccess_b2b.2543085427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/19.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.803646228 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 364315691 ps |
| CPU time | 3.26 seconds |
| Started | Aug 23 01:50:44 PM UTC 24 |
| Finished | Aug 23 01:50:48 PM UTC 24 |
| Peak memory | 211628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803646228 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.803646228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/19.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_regwen.4202969515 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 11093796291 ps |
| CPU time | 425.88 seconds |
| Started | Aug 23 01:50:40 PM UTC 24 |
| Finished | Aug 23 01:57:51 PM UTC 24 |
| Peak memory | 384476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202969515 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.4202969515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/19.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_smoke.2740001450 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 3655441037 ps |
| CPU time | 15.9 seconds |
| Started | Aug 23 01:49:34 PM UTC 24 |
| Finished | Aug 23 01:49:51 PM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740001450 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.2740001450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/19.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all.3049196061 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 258886316038 ps |
| CPU time | 2929.15 seconds |
| Started | Aug 23 01:51:03 PM UTC 24 |
| Finished | Aug 23 02:40:21 PM UTC 24 |
| Peak memory | 384104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30491960 61 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_a ll.3049196061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/19.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.558791666 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 15985755314 ps |
| CPU time | 28.72 seconds |
| Started | Aug 23 01:51:02 PM UTC 24 |
| Finished | Aug 23 01:51:32 PM UTC 24 |
| Peak memory | 221940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558791666 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.558791666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/19.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.3157734798 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 3126598903 ps |
| CPU time | 171.03 seconds |
| Started | Aug 23 01:49:49 PM UTC 24 |
| Finished | Aug 23 01:52:43 PM UTC 24 |
| Peak memory | 211644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157734798 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_pipeline.3157734798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/19.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.4081827486 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 1571485233 ps |
| CPU time | 36.74 seconds |
| Started | Aug 23 01:50:15 PM UTC 24 |
| Finished | Aug 23 01:50:53 PM UTC 24 |
| Peak memory | 351836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =4081827486 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl _throughput_w_partial_write.4081827486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/19.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.2928173802 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 10360992369 ps |
| CPU time | 503.95 seconds |
| Started | Aug 23 12:54:22 PM UTC 24 |
| Finished | Aug 23 01:02:51 PM UTC 24 |
| Peak memory | 386532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928173802 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_access_durin g_key_req.2928173802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/2.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_alert_test.1726873353 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 19684757 ps |
| CPU time | 0.56 seconds |
| Started | Aug 23 12:55:01 PM UTC 24 |
| Finished | Aug 23 12:55:03 PM UTC 24 |
| Peak memory | 210824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726873353 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_alert_test.1726873353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/2.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_bijection.94922899 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 307289641127 ps |
| CPU time | 1537.63 seconds |
| Started | Aug 23 12:53:44 PM UTC 24 |
| Finished | Aug 23 01:19:37 PM UTC 24 |
| Peak memory | 213212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94922899 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection.94922899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/2.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_executable.1414872710 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 4918154997 ps |
| CPU time | 36.66 seconds |
| Started | Aug 23 12:54:25 PM UTC 24 |
| Finished | Aug 23 12:55:04 PM UTC 24 |
| Peak memory | 259552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414872710 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executable.1414872710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/2.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.1782441413 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 15044435914 ps |
| CPU time | 28.19 seconds |
| Started | Aug 23 12:54:20 PM UTC 24 |
| Finished | Aug 23 12:54:49 PM UTC 24 |
| Peak memory | 221812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782441413 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_escalation.1782441413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/2.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.1406272245 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 1525632039 ps |
| CPU time | 41.53 seconds |
| Started | Aug 23 12:54:11 PM UTC 24 |
| Finished | Aug 23 12:54:54 PM UTC 24 |
| Peak memory | 351732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1406272245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_m ax_throughput.1406272245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/2.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.971867490 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 1593521054 ps |
| CPU time | 110.52 seconds |
| Started | Aug 23 12:54:47 PM UTC 24 |
| Finished | Aug 23 12:56:40 PM UTC 24 |
| Peak memory | 221804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971867490 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_mem_partial_access.971867490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/2.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.1608276762 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 20687756059 ps |
| CPU time | 304.94 seconds |
| Started | Aug 23 12:54:47 PM UTC 24 |
| Finished | Aug 23 12:59:56 PM UTC 24 |
| Peak memory | 221848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608276762 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_mem_walk.1608276762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/2.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.3508819371 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 26962094204 ps |
| CPU time | 279.7 seconds |
| Started | Aug 23 12:53:44 PM UTC 24 |
| Finished | Aug 23 12:58:27 PM UTC 24 |
| Peak memory | 386500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3508819371 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multiple_keys.3508819371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/2.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access.2620890223 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 2491927521 ps |
| CPU time | 18.44 seconds |
| Started | Aug 23 12:53:57 PM UTC 24 |
| Finished | Aug 23 12:54:16 PM UTC 24 |
| Peak memory | 286420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620890223 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_partial_access.2620890223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/2.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.3025158202 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 27316885636 ps |
| CPU time | 303.74 seconds |
| Started | Aug 23 12:54:08 PM UTC 24 |
| Finished | Aug 23 12:59:15 PM UTC 24 |
| Peak memory | 211572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025158202 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_partial_ac cess_b2b.3025158202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/2.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_regwen.3314637606 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 3751816390 ps |
| CPU time | 122.16 seconds |
| Started | Aug 23 12:54:27 PM UTC 24 |
| Finished | Aug 23 12:56:31 PM UTC 24 |
| Peak memory | 370208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314637606 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.3314637606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/2.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.1584963246 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 261700311 ps |
| CPU time | 1.73 seconds |
| Started | Aug 23 12:54:58 PM UTC 24 |
| Finished | Aug 23 12:55:01 PM UTC 24 |
| Peak memory | 246960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584963246 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_sec_cm.1584963246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_smoke.1986972001 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 1054294611 ps |
| CPU time | 12.98 seconds |
| Started | Aug 23 12:53:42 PM UTC 24 |
| Finished | Aug 23 12:53:56 PM UTC 24 |
| Peak memory | 211544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986972001 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.1986972001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/2.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all.4082228556 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 157438096573 ps |
| CPU time | 784.31 seconds |
| Started | Aug 23 12:54:54 PM UTC 24 |
| Finished | Aug 23 01:08:07 PM UTC 24 |
| Peak memory | 388920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40822285 56 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all.4082228556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/2.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.92061083 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 3140274994 ps |
| CPU time | 171.14 seconds |
| Started | Aug 23 12:53:53 PM UTC 24 |
| Finished | Aug 23 12:56:46 PM UTC 24 |
| Peak memory | 211620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92061083 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_pipeline.92061083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/2.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.4069408795 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 721848128 ps |
| CPU time | 8.29 seconds |
| Started | Aug 23 12:54:17 PM UTC 24 |
| Finished | Aug 23 12:54:26 PM UTC 24 |
| Peak memory | 239004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =4069408795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ throughput_w_partial_write.4069408795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/2.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.493176441 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 3743542524 ps |
| CPU time | 97.43 seconds |
| Started | Aug 23 01:53:40 PM UTC 24 |
| Finished | Aug 23 01:55:19 PM UTC 24 |
| Peak memory | 284200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493176441 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_access_durin g_key_req.493176441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/20.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_alert_test.1507384824 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 43249180 ps |
| CPU time | 0.54 seconds |
| Started | Aug 23 01:55:34 PM UTC 24 |
| Finished | Aug 23 01:55:35 PM UTC 24 |
| Peak memory | 210740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507384824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_alert_test.1507384824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/20.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_bijection.1974992372 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 19420262308 ps |
| CPU time | 545.74 seconds |
| Started | Aug 23 01:51:49 PM UTC 24 |
| Finished | Aug 23 02:01:01 PM UTC 24 |
| Peak memory | 211564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974992372 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection.1974992372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/20.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_executable.3559041306 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 8323482832 ps |
| CPU time | 466.36 seconds |
| Started | Aug 23 01:53:48 PM UTC 24 |
| Finished | Aug 23 02:01:39 PM UTC 24 |
| Peak memory | 382580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559041306 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executable.3559041306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/20.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.3480606825 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 4422551349 ps |
| CPU time | 24.04 seconds |
| Started | Aug 23 01:53:24 PM UTC 24 |
| Finished | Aug 23 01:53:49 PM UTC 24 |
| Peak memory | 211740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480606825 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_escalation.3480606825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/20.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.1627483344 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 3230368025 ps |
| CPU time | 37.61 seconds |
| Started | Aug 23 01:52:44 PM UTC 24 |
| Finished | Aug 23 01:53:23 PM UTC 24 |
| Peak memory | 343720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1627483344 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ max_throughput.1627483344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/20.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.1401460988 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 6041134872 ps |
| CPU time | 141.79 seconds |
| Started | Aug 23 01:54:24 PM UTC 24 |
| Finished | Aug 23 01:56:48 PM UTC 24 |
| Peak memory | 221944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401460988 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_mem_partial_access.1401460988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/20.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.3461666916 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 18771041840 ps |
| CPU time | 220.32 seconds |
| Started | Aug 23 01:54:21 PM UTC 24 |
| Finished | Aug 23 01:58:05 PM UTC 24 |
| Peak memory | 221816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461666916 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_mem_walk.3461666916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/20.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.1963559007 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 9392314839 ps |
| CPU time | 365.27 seconds |
| Started | Aug 23 01:51:37 PM UTC 24 |
| Finished | Aug 23 01:57:47 PM UTC 24 |
| Peak memory | 388564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963559007 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multiple_keys.1963559007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/20.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access.2838216637 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 3606290245 ps |
| CPU time | 45.81 seconds |
| Started | Aug 23 01:52:33 PM UTC 24 |
| Finished | Aug 23 01:53:20 PM UTC 24 |
| Peak memory | 362008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838216637 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_partial_access.2838216637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/20.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.3858074888 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 13222850843 ps |
| CPU time | 347.12 seconds |
| Started | Aug 23 01:52:42 PM UTC 24 |
| Finished | Aug 23 01:58:33 PM UTC 24 |
| Peak memory | 211576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858074888 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_partial_a ccess_b2b.3858074888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/20.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.2773521387 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 1345235007 ps |
| CPU time | 3.57 seconds |
| Started | Aug 23 01:54:16 PM UTC 24 |
| Finished | Aug 23 01:54:21 PM UTC 24 |
| Peak memory | 211692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773521387 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.2773521387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/20.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_regwen.2279604881 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 40833609348 ps |
| CPU time | 926.92 seconds |
| Started | Aug 23 01:53:50 PM UTC 24 |
| Finished | Aug 23 02:09:26 PM UTC 24 |
| Peak memory | 390112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279604881 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.2279604881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/20.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_smoke.3684503025 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 997695736 ps |
| CPU time | 54.8 seconds |
| Started | Aug 23 01:51:35 PM UTC 24 |
| Finished | Aug 23 01:52:32 PM UTC 24 |
| Peak memory | 370076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684503025 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.3684503025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/20.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all.3651061730 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 302927991921 ps |
| CPU time | 6545.24 seconds |
| Started | Aug 23 01:55:21 PM UTC 24 |
| Finished | Aug 23 03:45:28 PM UTC 24 |
| Peak memory | 388284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36510617 30 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_a ll.3651061730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/20.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.1574160961 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 948009114 ps |
| CPU time | 46.39 seconds |
| Started | Aug 23 01:54:56 PM UTC 24 |
| Finished | Aug 23 01:55:44 PM UTC 24 |
| Peak memory | 224120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574160961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.1574160961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/20.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.2157836594 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 11147617741 ps |
| CPU time | 335.7 seconds |
| Started | Aug 23 01:52:03 PM UTC 24 |
| Finished | Aug 23 01:57:42 PM UTC 24 |
| Peak memory | 211648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157836594 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_pipeline.2157836594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/20.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.1090649795 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 4206964170 ps |
| CPU time | 17.49 seconds |
| Started | Aug 23 01:53:21 PM UTC 24 |
| Finished | Aug 23 01:53:40 PM UTC 24 |
| Peak memory | 282076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1090649795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl _throughput_w_partial_write.1090649795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/20.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.3613164533 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 18336644624 ps |
| CPU time | 352.87 seconds |
| Started | Aug 23 01:58:06 PM UTC 24 |
| Finished | Aug 23 02:04:03 PM UTC 24 |
| Peak memory | 370132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613164533 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_access_duri ng_key_req.3613164533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/21.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_alert_test.127577889 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 28829755 ps |
| CPU time | 0.59 seconds |
| Started | Aug 23 01:58:52 PM UTC 24 |
| Finished | Aug 23 01:58:54 PM UTC 24 |
| Peak memory | 210816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127577889 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_alert_test.127577889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/21.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_bijection.2199359755 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 151106096375 ps |
| CPU time | 1428.95 seconds |
| Started | Aug 23 01:55:50 PM UTC 24 |
| Finished | Aug 23 02:19:53 PM UTC 24 |
| Peak memory | 213440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199359755 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection.2199359755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/21.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_executable.846402948 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 41946266125 ps |
| CPU time | 680.31 seconds |
| Started | Aug 23 01:58:12 PM UTC 24 |
| Finished | Aug 23 02:09:39 PM UTC 24 |
| Peak memory | 388932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846402948 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executable.846402948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/21.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.1003734121 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 25549071808 ps |
| CPU time | 45.95 seconds |
| Started | Aug 23 01:57:51 PM UTC 24 |
| Finished | Aug 23 01:58:39 PM UTC 24 |
| Peak memory | 211628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003734121 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_escalation.1003734121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/21.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.3373892734 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 3455254352 ps |
| CPU time | 48.26 seconds |
| Started | Aug 23 01:57:43 PM UTC 24 |
| Finished | Aug 23 01:58:33 PM UTC 24 |
| Peak memory | 370140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3373892734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ max_throughput.3373892734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/21.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.2954461420 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 19925713330 ps |
| CPU time | 70.06 seconds |
| Started | Aug 23 01:58:39 PM UTC 24 |
| Finished | Aug 23 01:59:51 PM UTC 24 |
| Peak memory | 222128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954461420 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_mem_partial_access.2954461420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/21.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.1844470171 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 5363897245 ps |
| CPU time | 265.63 seconds |
| Started | Aug 23 01:58:38 PM UTC 24 |
| Finished | Aug 23 02:03:07 PM UTC 24 |
| Peak memory | 221816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844470171 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_mem_walk.1844470171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/21.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.2748616922 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 223857348379 ps |
| CPU time | 673.85 seconds |
| Started | Aug 23 01:55:45 PM UTC 24 |
| Finished | Aug 23 02:07:06 PM UTC 24 |
| Peak memory | 388668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748616922 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multiple_keys.2748616922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/21.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access.853871386 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 769931455 ps |
| CPU time | 13.64 seconds |
| Started | Aug 23 01:56:49 PM UTC 24 |
| Finished | Aug 23 01:57:04 PM UTC 24 |
| Peak memory | 261580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853871386 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_partial_access.853871386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/21.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.382485006 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 52256278142 ps |
| CPU time | 296.13 seconds |
| Started | Aug 23 01:57:05 PM UTC 24 |
| Finished | Aug 23 02:02:05 PM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382485006 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_partial_ac cess_b2b.382485006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/21.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.1092191036 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 349720012 ps |
| CPU time | 3.25 seconds |
| Started | Aug 23 01:58:34 PM UTC 24 |
| Finished | Aug 23 01:58:38 PM UTC 24 |
| Peak memory | 211692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092191036 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.1092191036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/21.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_regwen.3715780242 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 14191256878 ps |
| CPU time | 672.69 seconds |
| Started | Aug 23 01:58:34 PM UTC 24 |
| Finished | Aug 23 02:09:53 PM UTC 24 |
| Peak memory | 388804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715780242 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.3715780242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/21.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_smoke.3517450479 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 2217956399 ps |
| CPU time | 12.22 seconds |
| Started | Aug 23 01:55:36 PM UTC 24 |
| Finished | Aug 23 01:55:49 PM UTC 24 |
| Peak memory | 211748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517450479 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.3517450479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/21.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all.4034449660 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 374954880429 ps |
| CPU time | 1807.58 seconds |
| Started | Aug 23 01:58:40 PM UTC 24 |
| Finished | Aug 23 02:29:04 PM UTC 24 |
| Peak memory | 400572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40344496 60 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_a ll.4034449660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/21.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.140816137 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 4107495977 ps |
| CPU time | 27.48 seconds |
| Started | Aug 23 01:58:39 PM UTC 24 |
| Finished | Aug 23 01:59:08 PM UTC 24 |
| Peak memory | 221932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140816137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.140816137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/21.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.4042492623 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 2816771044 ps |
| CPU time | 143.27 seconds |
| Started | Aug 23 01:56:48 PM UTC 24 |
| Finished | Aug 23 01:59:14 PM UTC 24 |
| Peak memory | 211632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042492623 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_pipeline.4042492623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/21.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.2288520177 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 3215387521 ps |
| CPU time | 48.55 seconds |
| Started | Aug 23 01:57:47 PM UTC 24 |
| Finished | Aug 23 01:58:37 PM UTC 24 |
| Peak memory | 370212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2288520177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl _throughput_w_partial_write.2288520177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/21.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.1778435216 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 12560072050 ps |
| CPU time | 414.13 seconds |
| Started | Aug 23 02:00:14 PM UTC 24 |
| Finished | Aug 23 02:07:12 PM UTC 24 |
| Peak memory | 386596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778435216 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_access_duri ng_key_req.1778435216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/22.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_alert_test.2884718540 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 36116391 ps |
| CPU time | 0.53 seconds |
| Started | Aug 23 02:02:06 PM UTC 24 |
| Finished | Aug 23 02:02:08 PM UTC 24 |
| Peak memory | 210740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884718540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_alert_test.2884718540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/22.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_bijection.1286119677 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 27409460748 ps |
| CPU time | 1580.25 seconds |
| Started | Aug 23 01:59:08 PM UTC 24 |
| Finished | Aug 23 02:25:44 PM UTC 24 |
| Peak memory | 213232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286119677 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection.1286119677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/22.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_executable.4140457038 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 37138310544 ps |
| CPU time | 383.88 seconds |
| Started | Aug 23 02:00:40 PM UTC 24 |
| Finished | Aug 23 02:07:08 PM UTC 24 |
| Peak memory | 388572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140457038 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executable.4140457038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/22.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.526238836 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 27163704106 ps |
| CPU time | 46.28 seconds |
| Started | Aug 23 02:00:09 PM UTC 24 |
| Finished | Aug 23 02:00:56 PM UTC 24 |
| Peak memory | 211644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526238836 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_escalation.526238836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/22.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.2128869728 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 3059836423 ps |
| CPU time | 50.44 seconds |
| Started | Aug 23 01:59:21 PM UTC 24 |
| Finished | Aug 23 02:00:13 PM UTC 24 |
| Peak memory | 380452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2128869728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ max_throughput.2128869728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/22.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.1874989378 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 5226862575 ps |
| CPU time | 142.94 seconds |
| Started | Aug 23 02:01:30 PM UTC 24 |
| Finished | Aug 23 02:03:56 PM UTC 24 |
| Peak memory | 228996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874989378 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_mem_partial_access.1874989378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/22.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.3947244749 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 137927611946 ps |
| CPU time | 285.2 seconds |
| Started | Aug 23 02:01:07 PM UTC 24 |
| Finished | Aug 23 02:05:56 PM UTC 24 |
| Peak memory | 221884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947244749 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_mem_walk.3947244749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/22.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.3893880005 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 47835969403 ps |
| CPU time | 344.78 seconds |
| Started | Aug 23 01:58:59 PM UTC 24 |
| Finished | Aug 23 02:04:48 PM UTC 24 |
| Peak memory | 382500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893880005 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multiple_keys.3893880005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/22.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access.915419571 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 449652892 ps |
| CPU time | 5 seconds |
| Started | Aug 23 01:59:14 PM UTC 24 |
| Finished | Aug 23 01:59:20 PM UTC 24 |
| Peak memory | 211568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915419571 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_partial_access.915419571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/22.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.983447377 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 31170032334 ps |
| CPU time | 379.44 seconds |
| Started | Aug 23 01:59:17 PM UTC 24 |
| Finished | Aug 23 02:05:41 PM UTC 24 |
| Peak memory | 211552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983447377 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_partial_ac cess_b2b.983447377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/22.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.233583343 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 357522066 ps |
| CPU time | 3.18 seconds |
| Started | Aug 23 02:01:02 PM UTC 24 |
| Finished | Aug 23 02:01:06 PM UTC 24 |
| Peak memory | 211708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233583343 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.233583343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/22.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_regwen.3535791158 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 1676050709 ps |
| CPU time | 30.16 seconds |
| Started | Aug 23 02:00:58 PM UTC 24 |
| Finished | Aug 23 02:01:29 PM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535791158 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.3535791158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/22.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_smoke.3555535094 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 1418326446 ps |
| CPU time | 3.56 seconds |
| Started | Aug 23 01:58:54 PM UTC 24 |
| Finished | Aug 23 01:58:59 PM UTC 24 |
| Peak memory | 211312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555535094 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.3555535094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/22.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all.1654640628 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 127575846657 ps |
| CPU time | 831.39 seconds |
| Started | Aug 23 02:01:50 PM UTC 24 |
| Finished | Aug 23 02:15:50 PM UTC 24 |
| Peak memory | 388460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16546406 28 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_a ll.1654640628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/22.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.3420653237 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 1346135736 ps |
| CPU time | 8.02 seconds |
| Started | Aug 23 02:01:40 PM UTC 24 |
| Finished | Aug 23 02:01:49 PM UTC 24 |
| Peak memory | 221944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420653237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.3420653237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/22.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.2551609448 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 16911256647 ps |
| CPU time | 235.79 seconds |
| Started | Aug 23 01:59:09 PM UTC 24 |
| Finished | Aug 23 02:03:08 PM UTC 24 |
| Peak memory | 211512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551609448 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_pipeline.2551609448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/22.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.3637904945 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 722822388 ps |
| CPU time | 9.58 seconds |
| Started | Aug 23 01:59:51 PM UTC 24 |
| Finished | Aug 23 02:00:02 PM UTC 24 |
| Peak memory | 245208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3637904945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl _throughput_w_partial_write.3637904945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/22.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.842588947 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 34606280927 ps |
| CPU time | 180.72 seconds |
| Started | Aug 23 02:04:36 PM UTC 24 |
| Finished | Aug 23 02:07:39 PM UTC 24 |
| Peak memory | 349680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842588947 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_access_durin g_key_req.842588947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/23.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_alert_test.136464538 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 114642764 ps |
| CPU time | 0.58 seconds |
| Started | Aug 23 02:06:54 PM UTC 24 |
| Finished | Aug 23 02:06:56 PM UTC 24 |
| Peak memory | 210740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136464538 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_alert_test.136464538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/23.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_bijection.476477479 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 230820479208 ps |
| CPU time | 788.59 seconds |
| Started | Aug 23 02:03:08 PM UTC 24 |
| Finished | Aug 23 02:16:25 PM UTC 24 |
| Peak memory | 213160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476477479 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection.476477479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/23.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_executable.2804006226 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 1816712770 ps |
| CPU time | 83.44 seconds |
| Started | Aug 23 02:04:48 PM UTC 24 |
| Finished | Aug 23 02:06:13 PM UTC 24 |
| Peak memory | 374244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804006226 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executable.2804006226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/23.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.243480211 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 17642821712 ps |
| CPU time | 62.66 seconds |
| Started | Aug 23 02:04:14 PM UTC 24 |
| Finished | Aug 23 02:05:18 PM UTC 24 |
| Peak memory | 221876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243480211 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_escalation.243480211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/23.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.1964010379 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 2700630971 ps |
| CPU time | 7.85 seconds |
| Started | Aug 23 02:04:04 PM UTC 24 |
| Finished | Aug 23 02:04:13 PM UTC 24 |
| Peak memory | 228440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1964010379 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ max_throughput.1964010379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/23.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.946381197 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 5795821591 ps |
| CPU time | 141.02 seconds |
| Started | Aug 23 02:05:57 PM UTC 24 |
| Finished | Aug 23 02:08:20 PM UTC 24 |
| Peak memory | 222020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946381197 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_mem_partial_access.946381197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/23.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.2718250810 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 9865359752 ps |
| CPU time | 138.21 seconds |
| Started | Aug 23 02:05:48 PM UTC 24 |
| Finished | Aug 23 02:08:08 PM UTC 24 |
| Peak memory | 221876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718250810 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_mem_walk.2718250810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/23.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.2872910985 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 18779613420 ps |
| CPU time | 536.73 seconds |
| Started | Aug 23 02:02:37 PM UTC 24 |
| Finished | Aug 23 02:11:40 PM UTC 24 |
| Peak memory | 376352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872910985 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multiple_keys.2872910985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/23.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access.2820290404 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 5928603863 ps |
| CPU time | 30.78 seconds |
| Started | Aug 23 02:03:36 PM UTC 24 |
| Finished | Aug 23 02:04:08 PM UTC 24 |
| Peak memory | 325012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820290404 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_partial_access.2820290404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/23.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.2004790299 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 29550745322 ps |
| CPU time | 326.29 seconds |
| Started | Aug 23 02:03:57 PM UTC 24 |
| Finished | Aug 23 02:09:27 PM UTC 24 |
| Peak memory | 211552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004790299 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_partial_a ccess_b2b.2004790299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/23.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.3722338029 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 768037524 ps |
| CPU time | 3.27 seconds |
| Started | Aug 23 02:05:42 PM UTC 24 |
| Finished | Aug 23 02:05:47 PM UTC 24 |
| Peak memory | 211824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722338029 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.3722338029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/23.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_regwen.1787835409 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 26626003879 ps |
| CPU time | 358.25 seconds |
| Started | Aug 23 02:05:19 PM UTC 24 |
| Finished | Aug 23 02:11:22 PM UTC 24 |
| Peak memory | 384544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787835409 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.1787835409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/23.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_smoke.2157341508 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 2119552608 ps |
| CPU time | 26.8 seconds |
| Started | Aug 23 02:02:08 PM UTC 24 |
| Finished | Aug 23 02:02:37 PM UTC 24 |
| Peak memory | 304536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157341508 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.2157341508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/23.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all.3839847526 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 178263745223 ps |
| CPU time | 3678.98 seconds |
| Started | Aug 23 02:06:31 PM UTC 24 |
| Finished | Aug 23 03:08:25 PM UTC 24 |
| Peak memory | 388264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38398475 26 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_a ll.3839847526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/23.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.1657200533 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 487839815 ps |
| CPU time | 14.93 seconds |
| Started | Aug 23 02:06:14 PM UTC 24 |
| Finished | Aug 23 02:06:30 PM UTC 24 |
| Peak memory | 222084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657200533 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.1657200533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/23.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.4135120305 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 17942827825 ps |
| CPU time | 220.34 seconds |
| Started | Aug 23 02:03:10 PM UTC 24 |
| Finished | Aug 23 02:06:53 PM UTC 24 |
| Peak memory | 211500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135120305 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_pipeline.4135120305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/23.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.903532565 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 747218428 ps |
| CPU time | 24.39 seconds |
| Started | Aug 23 02:04:09 PM UTC 24 |
| Finished | Aug 23 02:04:36 PM UTC 24 |
| Peak memory | 306784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =903532565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ throughput_w_partial_write.903532565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/23.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.1095882721 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 9032755683 ps |
| CPU time | 323.86 seconds |
| Started | Aug 23 02:08:09 PM UTC 24 |
| Finished | Aug 23 02:13:36 PM UTC 24 |
| Peak memory | 386592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095882721 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_access_duri ng_key_req.1095882721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/24.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_alert_test.385449438 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 53460484 ps |
| CPU time | 0.57 seconds |
| Started | Aug 23 02:09:39 PM UTC 24 |
| Finished | Aug 23 02:09:41 PM UTC 24 |
| Peak memory | 210876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385449438 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_alert_test.385449438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/24.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_bijection.865882406 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 21383699556 ps |
| CPU time | 1307.84 seconds |
| Started | Aug 23 02:07:09 PM UTC 24 |
| Finished | Aug 23 02:29:10 PM UTC 24 |
| Peak memory | 213112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865882406 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection.865882406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/24.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_executable.3481322108 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 4365274934 ps |
| CPU time | 179.57 seconds |
| Started | Aug 23 02:08:21 PM UTC 24 |
| Finished | Aug 23 02:11:23 PM UTC 24 |
| Peak memory | 376364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481322108 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executable.3481322108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/24.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.563036331 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 168417373521 ps |
| CPU time | 87.37 seconds |
| Started | Aug 23 02:07:51 PM UTC 24 |
| Finished | Aug 23 02:09:21 PM UTC 24 |
| Peak memory | 226044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563036331 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_escalation.563036331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/24.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.117909444 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 2882113992 ps |
| CPU time | 21.91 seconds |
| Started | Aug 23 02:07:27 PM UTC 24 |
| Finished | Aug 23 02:07:51 PM UTC 24 |
| Peak memory | 300504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 117909444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_m ax_throughput.117909444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/24.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.453975629 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 15340286128 ps |
| CPU time | 62.7 seconds |
| Started | Aug 23 02:09:22 PM UTC 24 |
| Finished | Aug 23 02:10:26 PM UTC 24 |
| Peak memory | 221868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453975629 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_mem_partial_access.453975629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/24.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.3782055076 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 43236651051 ps |
| CPU time | 153.17 seconds |
| Started | Aug 23 02:09:17 PM UTC 24 |
| Finished | Aug 23 02:11:53 PM UTC 24 |
| Peak memory | 221884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782055076 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_mem_walk.3782055076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/24.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.92206422 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 69210223911 ps |
| CPU time | 340.15 seconds |
| Started | Aug 23 02:07:06 PM UTC 24 |
| Finished | Aug 23 02:12:50 PM UTC 24 |
| Peak memory | 384468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92206422 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multiple_keys.92206422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/24.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access.3163794330 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 803840952 ps |
| CPU time | 12.35 seconds |
| Started | Aug 23 02:07:13 PM UTC 24 |
| Finished | Aug 23 02:07:27 PM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163794330 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_partial_access.3163794330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/24.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.2278845168 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 16993571092 ps |
| CPU time | 211.5 seconds |
| Started | Aug 23 02:07:15 PM UTC 24 |
| Finished | Aug 23 02:10:50 PM UTC 24 |
| Peak memory | 211496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278845168 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_partial_a ccess_b2b.2278845168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/24.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.99922321 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 362806127 ps |
| CPU time | 3.22 seconds |
| Started | Aug 23 02:09:12 PM UTC 24 |
| Finished | Aug 23 02:09:16 PM UTC 24 |
| Peak memory | 211820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99922321 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.99922321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/24.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_regwen.395182692 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 3405087400 ps |
| CPU time | 250.84 seconds |
| Started | Aug 23 02:08:28 PM UTC 24 |
| Finished | Aug 23 02:12:42 PM UTC 24 |
| Peak memory | 351900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395182692 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.395182692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/24.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_smoke.3594319012 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 2488379497 ps |
| CPU time | 10.84 seconds |
| Started | Aug 23 02:06:56 PM UTC 24 |
| Finished | Aug 23 02:07:08 PM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594319012 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.3594319012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/24.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all.961724198 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 173518751542 ps |
| CPU time | 3216.66 seconds |
| Started | Aug 23 02:09:28 PM UTC 24 |
| Finished | Aug 23 03:03:35 PM UTC 24 |
| Peak memory | 394220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96172419 8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all.961724198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/24.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.2127474856 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 948839062 ps |
| CPU time | 28.38 seconds |
| Started | Aug 23 02:09:27 PM UTC 24 |
| Finished | Aug 23 02:09:57 PM UTC 24 |
| Peak memory | 223920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127474856 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.2127474856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/24.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.1076645353 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 15393365557 ps |
| CPU time | 207.72 seconds |
| Started | Aug 23 02:07:09 PM UTC 24 |
| Finished | Aug 23 02:10:40 PM UTC 24 |
| Peak memory | 211632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076645353 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_pipeline.1076645353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/24.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.3748190353 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 3093327208 ps |
| CPU time | 45.3 seconds |
| Started | Aug 23 02:07:40 PM UTC 24 |
| Finished | Aug 23 02:08:27 PM UTC 24 |
| Peak memory | 366116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3748190353 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl _throughput_w_partial_write.3748190353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/24.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.2596316249 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 63429763771 ps |
| CPU time | 551.01 seconds |
| Started | Aug 23 02:11:08 PM UTC 24 |
| Finished | Aug 23 02:20:25 PM UTC 24 |
| Peak memory | 384556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596316249 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_access_duri ng_key_req.2596316249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/25.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_alert_test.1860402011 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 52093390 ps |
| CPU time | 0.58 seconds |
| Started | Aug 23 02:11:53 PM UTC 24 |
| Finished | Aug 23 02:11:55 PM UTC 24 |
| Peak memory | 210816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860402011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_alert_test.1860402011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/25.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_bijection.2940971411 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 374947331869 ps |
| CPU time | 2032.69 seconds |
| Started | Aug 23 02:09:57 PM UTC 24 |
| Finished | Aug 23 02:44:10 PM UTC 24 |
| Peak memory | 213320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940971411 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection.2940971411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/25.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_executable.656507433 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 16025699180 ps |
| CPU time | 735.43 seconds |
| Started | Aug 23 02:11:09 PM UTC 24 |
| Finished | Aug 23 02:23:32 PM UTC 24 |
| Peak memory | 388804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656507433 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executable.656507433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/25.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.218326620 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 14135009755 ps |
| CPU time | 24.8 seconds |
| Started | Aug 23 02:11:03 PM UTC 24 |
| Finished | Aug 23 02:11:29 PM UTC 24 |
| Peak memory | 211572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218326620 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_escalation.218326620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/25.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.4241475024 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 2936572538 ps |
| CPU time | 15.61 seconds |
| Started | Aug 23 02:10:51 PM UTC 24 |
| Finished | Aug 23 02:11:07 PM UTC 24 |
| Peak memory | 280104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4241475024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ max_throughput.4241475024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/25.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.2018010700 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 1393958764 ps |
| CPU time | 63.86 seconds |
| Started | Aug 23 02:11:29 PM UTC 24 |
| Finished | Aug 23 02:12:35 PM UTC 24 |
| Peak memory | 221980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018010700 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_mem_partial_access.2018010700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/25.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.2772375056 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 10950520491 ps |
| CPU time | 257.01 seconds |
| Started | Aug 23 02:11:29 PM UTC 24 |
| Finished | Aug 23 02:15:50 PM UTC 24 |
| Peak memory | 221892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772375056 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_mem_walk.2772375056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/25.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.248753582 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 1908507495 ps |
| CPU time | 65.73 seconds |
| Started | Aug 23 02:09:54 PM UTC 24 |
| Finished | Aug 23 02:11:02 PM UTC 24 |
| Peak memory | 312716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248753582 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multiple_keys.248753582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/25.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access.3988819191 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 651415065 ps |
| CPU time | 17.92 seconds |
| Started | Aug 23 02:10:38 PM UTC 24 |
| Finished | Aug 23 02:10:57 PM UTC 24 |
| Peak memory | 211556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988819191 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_partial_access.3988819191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/25.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.663862137 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 4150772124 ps |
| CPU time | 205.57 seconds |
| Started | Aug 23 02:10:41 PM UTC 24 |
| Finished | Aug 23 02:14:09 PM UTC 24 |
| Peak memory | 211748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663862137 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_partial_ac cess_b2b.663862137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/25.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.2262070271 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 698938382 ps |
| CPU time | 3.2 seconds |
| Started | Aug 23 02:11:24 PM UTC 24 |
| Finished | Aug 23 02:11:28 PM UTC 24 |
| Peak memory | 211692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262070271 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.2262070271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/25.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_regwen.3786266278 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 9013232429 ps |
| CPU time | 272.22 seconds |
| Started | Aug 23 02:11:23 PM UTC 24 |
| Finished | Aug 23 02:15:59 PM UTC 24 |
| Peak memory | 384476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786266278 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.3786266278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/25.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_smoke.463527830 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 3865942779 ps |
| CPU time | 54.11 seconds |
| Started | Aug 23 02:09:41 PM UTC 24 |
| Finished | Aug 23 02:10:37 PM UTC 24 |
| Peak memory | 372468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463527830 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.463527830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/25.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all.2664848171 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 45197336735 ps |
| CPU time | 1456.9 seconds |
| Started | Aug 23 02:11:47 PM UTC 24 |
| Finished | Aug 23 02:36:19 PM UTC 24 |
| Peak memory | 386236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26648481 71 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_a ll.2664848171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/25.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.605625080 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 641664673 ps |
| CPU time | 17.99 seconds |
| Started | Aug 23 02:11:40 PM UTC 24 |
| Finished | Aug 23 02:12:00 PM UTC 24 |
| Peak memory | 221864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605625080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.605625080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/25.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.2501487864 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 4038235625 ps |
| CPU time | 222 seconds |
| Started | Aug 23 02:10:27 PM UTC 24 |
| Finished | Aug 23 02:14:13 PM UTC 24 |
| Peak memory | 211500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501487864 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_pipeline.2501487864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/25.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.834439296 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 3122990747 ps |
| CPU time | 9.17 seconds |
| Started | Aug 23 02:10:58 PM UTC 24 |
| Finished | Aug 23 02:11:08 PM UTC 24 |
| Peak memory | 239140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =834439296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ throughput_w_partial_write.834439296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/25.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.631344653 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 3377106065 ps |
| CPU time | 61.15 seconds |
| Started | Aug 23 02:14:00 PM UTC 24 |
| Finished | Aug 23 02:15:03 PM UTC 24 |
| Peak memory | 224908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631344653 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_access_durin g_key_req.631344653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/26.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_alert_test.2073183036 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 17751896 ps |
| CPU time | 0.57 seconds |
| Started | Aug 23 02:15:51 PM UTC 24 |
| Finished | Aug 23 02:15:53 PM UTC 24 |
| Peak memory | 210936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073183036 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_alert_test.2073183036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/26.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_bijection.3254115687 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 200120531007 ps |
| CPU time | 1212.57 seconds |
| Started | Aug 23 02:12:18 PM UTC 24 |
| Finished | Aug 23 02:32:43 PM UTC 24 |
| Peak memory | 213112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254115687 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection.3254115687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/26.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_executable.2758729692 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 12528460841 ps |
| CPU time | 652.84 seconds |
| Started | Aug 23 02:14:09 PM UTC 24 |
| Finished | Aug 23 02:25:09 PM UTC 24 |
| Peak memory | 386676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758729692 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executable.2758729692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/26.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.2501994577 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 15861980360 ps |
| CPU time | 50.44 seconds |
| Started | Aug 23 02:13:37 PM UTC 24 |
| Finished | Aug 23 02:14:29 PM UTC 24 |
| Peak memory | 211648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501994577 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_escalation.2501994577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/26.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.2643353877 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 761243518 ps |
| CPU time | 24.53 seconds |
| Started | Aug 23 02:12:52 PM UTC 24 |
| Finished | Aug 23 02:13:18 PM UTC 24 |
| Peak memory | 312816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2643353877 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ max_throughput.2643353877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/26.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.2766732401 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 4583241295 ps |
| CPU time | 129.51 seconds |
| Started | Aug 23 02:15:01 PM UTC 24 |
| Finished | Aug 23 02:17:12 PM UTC 24 |
| Peak memory | 221872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766732401 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_mem_partial_access.2766732401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/26.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.3881704898 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 2062408918 ps |
| CPU time | 109.97 seconds |
| Started | Aug 23 02:14:36 PM UTC 24 |
| Finished | Aug 23 02:16:28 PM UTC 24 |
| Peak memory | 221952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881704898 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_mem_walk.3881704898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/26.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.492704299 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 37348444506 ps |
| CPU time | 274.95 seconds |
| Started | Aug 23 02:12:01 PM UTC 24 |
| Finished | Aug 23 02:16:39 PM UTC 24 |
| Peak memory | 359976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492704299 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multiple_keys.492704299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/26.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access.3314175206 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 1893277675 ps |
| CPU time | 7.67 seconds |
| Started | Aug 23 02:12:43 PM UTC 24 |
| Finished | Aug 23 02:12:52 PM UTC 24 |
| Peak memory | 236948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314175206 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_partial_access.3314175206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/26.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.2334298206 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 5229294275 ps |
| CPU time | 262.72 seconds |
| Started | Aug 23 02:12:51 PM UTC 24 |
| Finished | Aug 23 02:17:17 PM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334298206 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_partial_a ccess_b2b.2334298206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/26.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.4041802864 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 677004516 ps |
| CPU time | 3.23 seconds |
| Started | Aug 23 02:14:31 PM UTC 24 |
| Finished | Aug 23 02:14:35 PM UTC 24 |
| Peak memory | 211696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041802864 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.4041802864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/26.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_regwen.3379236492 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 39038140949 ps |
| CPU time | 269.73 seconds |
| Started | Aug 23 02:14:13 PM UTC 24 |
| Finished | Aug 23 02:18:47 PM UTC 24 |
| Peak memory | 378412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379236492 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.3379236492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/26.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_smoke.3861195226 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 1591190103 ps |
| CPU time | 20.18 seconds |
| Started | Aug 23 02:11:56 PM UTC 24 |
| Finished | Aug 23 02:12:17 PM UTC 24 |
| Peak memory | 211696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861195226 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.3861195226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/26.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all.2137819621 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 208011662874 ps |
| CPU time | 5445.23 seconds |
| Started | Aug 23 02:15:22 PM UTC 24 |
| Finished | Aug 23 03:46:58 PM UTC 24 |
| Peak memory | 394224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21378196 21 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_a ll.2137819621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/26.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.126089994 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 496181228 ps |
| CPU time | 15.65 seconds |
| Started | Aug 23 02:15:04 PM UTC 24 |
| Finished | Aug 23 02:15:21 PM UTC 24 |
| Peak memory | 224096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126089994 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.126089994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/26.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.467810062 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 9532904460 ps |
| CPU time | 239.14 seconds |
| Started | Aug 23 02:12:36 PM UTC 24 |
| Finished | Aug 23 02:16:38 PM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467810062 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_pipeline.467810062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/26.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.3366026660 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 772932267 ps |
| CPU time | 39.07 seconds |
| Started | Aug 23 02:13:19 PM UTC 24 |
| Finished | Aug 23 02:14:00 PM UTC 24 |
| Peak memory | 353684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3366026660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl _throughput_w_partial_write.3366026660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/26.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.3679278936 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 17112340684 ps |
| CPU time | 753.69 seconds |
| Started | Aug 23 02:16:58 PM UTC 24 |
| Finished | Aug 23 02:29:39 PM UTC 24 |
| Peak memory | 390260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679278936 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_access_duri ng_key_req.3679278936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/27.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_alert_test.2313411498 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 29793923 ps |
| CPU time | 0.53 seconds |
| Started | Aug 23 02:17:31 PM UTC 24 |
| Finished | Aug 23 02:17:33 PM UTC 24 |
| Peak memory | 210740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313411498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_alert_test.2313411498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/27.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_bijection.4236279907 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 137970220540 ps |
| CPU time | 1917.36 seconds |
| Started | Aug 23 02:15:59 PM UTC 24 |
| Finished | Aug 23 02:48:15 PM UTC 24 |
| Peak memory | 213236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236279907 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection.4236279907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/27.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_executable.2720525576 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 18162725482 ps |
| CPU time | 644.97 seconds |
| Started | Aug 23 02:17:03 PM UTC 24 |
| Finished | Aug 23 02:27:54 PM UTC 24 |
| Peak memory | 386608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720525576 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executable.2720525576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/27.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.1941600020 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 22720445380 ps |
| CPU time | 39.2 seconds |
| Started | Aug 23 02:16:45 PM UTC 24 |
| Finished | Aug 23 02:17:26 PM UTC 24 |
| Peak memory | 211716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941600020 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_escalation.1941600020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/27.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.3028638595 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 3144410856 ps |
| CPU time | 22.08 seconds |
| Started | Aug 23 02:16:38 PM UTC 24 |
| Finished | Aug 23 02:17:02 PM UTC 24 |
| Peak memory | 298464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3028638595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ max_throughput.3028638595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/27.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.1224767351 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 17571829297 ps |
| CPU time | 132.26 seconds |
| Started | Aug 23 02:17:16 PM UTC 24 |
| Finished | Aug 23 02:19:30 PM UTC 24 |
| Peak memory | 229100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224767351 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_mem_partial_access.1224767351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/27.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.2116832520 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 39785205602 ps |
| CPU time | 152.23 seconds |
| Started | Aug 23 02:17:13 PM UTC 24 |
| Finished | Aug 23 02:19:48 PM UTC 24 |
| Peak memory | 221808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116832520 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_mem_walk.2116832520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/27.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.2054784612 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 12144128150 ps |
| CPU time | 62.44 seconds |
| Started | Aug 23 02:15:53 PM UTC 24 |
| Finished | Aug 23 02:16:57 PM UTC 24 |
| Peak memory | 382432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054784612 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multiple_keys.2054784612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/27.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access.1681036080 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 2614518563 ps |
| CPU time | 18.39 seconds |
| Started | Aug 23 02:16:25 PM UTC 24 |
| Finished | Aug 23 02:16:45 PM UTC 24 |
| Peak memory | 211564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681036080 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_partial_access.1681036080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/27.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.247705788 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 39922490223 ps |
| CPU time | 478.26 seconds |
| Started | Aug 23 02:16:28 PM UTC 24 |
| Finished | Aug 23 02:24:32 PM UTC 24 |
| Peak memory | 211760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247705788 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_partial_ac cess_b2b.247705788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/27.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.2810837028 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 1354733916 ps |
| CPU time | 3.26 seconds |
| Started | Aug 23 02:17:11 PM UTC 24 |
| Finished | Aug 23 02:17:15 PM UTC 24 |
| Peak memory | 211696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810837028 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.2810837028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/27.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_regwen.2923483181 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 8313747357 ps |
| CPU time | 69.26 seconds |
| Started | Aug 23 02:17:07 PM UTC 24 |
| Finished | Aug 23 02:18:18 PM UTC 24 |
| Peak memory | 376364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923483181 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.2923483181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/27.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_smoke.853929312 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 4193280657 ps |
| CPU time | 12.21 seconds |
| Started | Aug 23 02:15:51 PM UTC 24 |
| Finished | Aug 23 02:16:04 PM UTC 24 |
| Peak memory | 211552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853929312 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.853929312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/27.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all.3883046098 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 1498405649988 ps |
| CPU time | 5934.51 seconds |
| Started | Aug 23 02:17:27 PM UTC 24 |
| Finished | Aug 23 03:57:17 PM UTC 24 |
| Peak memory | 392288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38830460 98 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_a ll.3883046098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/27.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.3070563653 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 1001385799 ps |
| CPU time | 11.2 seconds |
| Started | Aug 23 02:17:18 PM UTC 24 |
| Finished | Aug 23 02:17:30 PM UTC 24 |
| Peak memory | 222084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070563653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.3070563653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/27.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.3807141795 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 22347479783 ps |
| CPU time | 349.44 seconds |
| Started | Aug 23 02:16:05 PM UTC 24 |
| Finished | Aug 23 02:21:59 PM UTC 24 |
| Peak memory | 211556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807141795 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_pipeline.3807141795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/27.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.1745148016 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 796203766 ps |
| CPU time | 29.52 seconds |
| Started | Aug 23 02:16:39 PM UTC 24 |
| Finished | Aug 23 02:17:10 PM UTC 24 |
| Peak memory | 329112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1745148016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl _throughput_w_partial_write.1745148016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/27.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.3321927413 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 8319518121 ps |
| CPU time | 206.54 seconds |
| Started | Aug 23 02:20:25 PM UTC 24 |
| Finished | Aug 23 02:23:54 PM UTC 24 |
| Peak memory | 384476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321927413 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_access_duri ng_key_req.3321927413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/28.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_alert_test.302105458 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 62481364 ps |
| CPU time | 0.56 seconds |
| Started | Aug 23 02:23:33 PM UTC 24 |
| Finished | Aug 23 02:23:35 PM UTC 24 |
| Peak memory | 210936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302105458 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_alert_test.302105458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/28.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_bijection.2387872264 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 24793223340 ps |
| CPU time | 715.8 seconds |
| Started | Aug 23 02:18:18 PM UTC 24 |
| Finished | Aug 23 02:30:22 PM UTC 24 |
| Peak memory | 211544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387872264 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection.2387872264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/28.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_executable.733787544 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 21964252950 ps |
| CPU time | 358.81 seconds |
| Started | Aug 23 02:20:25 PM UTC 24 |
| Finished | Aug 23 02:26:28 PM UTC 24 |
| Peak memory | 380368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733787544 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executable.733787544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/28.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.245758132 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 13710088830 ps |
| CPU time | 76.59 seconds |
| Started | Aug 23 02:20:04 PM UTC 24 |
| Finished | Aug 23 02:21:22 PM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245758132 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_escalation.245758132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/28.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.3812653461 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 734879257 ps |
| CPU time | 12.76 seconds |
| Started | Aug 23 02:19:49 PM UTC 24 |
| Finished | Aug 23 02:20:03 PM UTC 24 |
| Peak memory | 265700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3812653461 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ max_throughput.3812653461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/28.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.1822159352 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 20800570408 ps |
| CPU time | 128.92 seconds |
| Started | Aug 23 02:21:59 PM UTC 24 |
| Finished | Aug 23 02:24:11 PM UTC 24 |
| Peak memory | 221944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822159352 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_mem_partial_access.1822159352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/28.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.2512736844 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 6938883019 ps |
| CPU time | 132.74 seconds |
| Started | Aug 23 02:21:28 PM UTC 24 |
| Finished | Aug 23 02:23:43 PM UTC 24 |
| Peak memory | 221812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512736844 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_mem_walk.2512736844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/28.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.2084437242 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 98831471127 ps |
| CPU time | 927.32 seconds |
| Started | Aug 23 02:17:55 PM UTC 24 |
| Finished | Aug 23 02:33:31 PM UTC 24 |
| Peak memory | 390184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084437242 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multiple_keys.2084437242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/28.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access.4223986617 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 571543434 ps |
| CPU time | 14.02 seconds |
| Started | Aug 23 02:19:31 PM UTC 24 |
| Finished | Aug 23 02:19:47 PM UTC 24 |
| Peak memory | 211632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223986617 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_partial_access.4223986617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/28.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.983203420 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 30489262668 ps |
| CPU time | 152.66 seconds |
| Started | Aug 23 02:19:48 PM UTC 24 |
| Finished | Aug 23 02:22:23 PM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983203420 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_partial_ac cess_b2b.983203420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/28.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.2081111118 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 737255897 ps |
| CPU time | 3.39 seconds |
| Started | Aug 23 02:21:23 PM UTC 24 |
| Finished | Aug 23 02:21:28 PM UTC 24 |
| Peak memory | 211692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081111118 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.2081111118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/28.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_regwen.2676359494 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 7433485226 ps |
| CPU time | 483.72 seconds |
| Started | Aug 23 02:20:45 PM UTC 24 |
| Finished | Aug 23 02:28:54 PM UTC 24 |
| Peak memory | 388652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676359494 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.2676359494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/28.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_smoke.304555068 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 5427187402 ps |
| CPU time | 19.98 seconds |
| Started | Aug 23 02:17:33 PM UTC 24 |
| Finished | Aug 23 02:17:54 PM UTC 24 |
| Peak memory | 211752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304555068 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.304555068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/28.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all.1902551844 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 692229049817 ps |
| CPU time | 4396.84 seconds |
| Started | Aug 23 02:22:49 PM UTC 24 |
| Finished | Aug 23 03:36:46 PM UTC 24 |
| Peak memory | 392368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19025518 44 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_a ll.1902551844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/28.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.68704208 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 675011150 ps |
| CPU time | 22.4 seconds |
| Started | Aug 23 02:22:24 PM UTC 24 |
| Finished | Aug 23 02:22:47 PM UTC 24 |
| Peak memory | 221872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68704208 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.68704208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/28.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.148697306 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 26326333947 ps |
| CPU time | 387.11 seconds |
| Started | Aug 23 02:18:47 PM UTC 24 |
| Finished | Aug 23 02:25:19 PM UTC 24 |
| Peak memory | 211696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148697306 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_pipeline.148697306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/28.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.684826074 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 9274005977 ps |
| CPU time | 28.02 seconds |
| Started | Aug 23 02:19:54 PM UTC 24 |
| Finished | Aug 23 02:20:23 PM UTC 24 |
| Peak memory | 321248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =684826074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ throughput_w_partial_write.684826074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/28.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.2978741762 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 19210813360 ps |
| CPU time | 75.06 seconds |
| Started | Aug 23 02:25:10 PM UTC 24 |
| Finished | Aug 23 02:26:27 PM UTC 24 |
| Peak memory | 384468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978741762 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_access_duri ng_key_req.2978741762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/29.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_alert_test.3732837916 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 13231274 ps |
| CPU time | 0.6 seconds |
| Started | Aug 23 02:27:29 PM UTC 24 |
| Finished | Aug 23 02:27:31 PM UTC 24 |
| Peak memory | 210876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732837916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_alert_test.3732837916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/29.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_bijection.2333927701 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 219758929078 ps |
| CPU time | 1917.68 seconds |
| Started | Aug 23 02:23:52 PM UTC 24 |
| Finished | Aug 23 02:56:09 PM UTC 24 |
| Peak memory | 213156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333927701 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection.2333927701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/29.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_executable.1868037134 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 23816236568 ps |
| CPU time | 485.03 seconds |
| Started | Aug 23 02:25:21 PM UTC 24 |
| Finished | Aug 23 02:33:31 PM UTC 24 |
| Peak memory | 378400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868037134 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executable.1868037134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/29.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.2789989749 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 5875041730 ps |
| CPU time | 11.96 seconds |
| Started | Aug 23 02:25:09 PM UTC 24 |
| Finished | Aug 23 02:25:23 PM UTC 24 |
| Peak memory | 221740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789989749 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_escalation.2789989749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/29.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.2024710304 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 739472564 ps |
| CPU time | 23.69 seconds |
| Started | Aug 23 02:24:33 PM UTC 24 |
| Finished | Aug 23 02:24:58 PM UTC 24 |
| Peak memory | 302696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2024710304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ max_throughput.2024710304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/29.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.763559807 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 1158730496 ps |
| CPU time | 52.89 seconds |
| Started | Aug 23 02:26:28 PM UTC 24 |
| Finished | Aug 23 02:27:23 PM UTC 24 |
| Peak memory | 228880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763559807 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_mem_partial_access.763559807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/29.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.1175469137 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 5483819854 ps |
| CPU time | 132.02 seconds |
| Started | Aug 23 02:25:50 PM UTC 24 |
| Finished | Aug 23 02:28:04 PM UTC 24 |
| Peak memory | 221888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175469137 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_mem_walk.1175469137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/29.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.2787314153 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 52615130821 ps |
| CPU time | 902.34 seconds |
| Started | Aug 23 02:23:44 PM UTC 24 |
| Finished | Aug 23 02:38:55 PM UTC 24 |
| Peak memory | 388072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787314153 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multiple_keys.2787314153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/29.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access.2786254310 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 930665695 ps |
| CPU time | 14.03 seconds |
| Started | Aug 23 02:24:11 PM UTC 24 |
| Finished | Aug 23 02:24:26 PM UTC 24 |
| Peak memory | 255648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786254310 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_partial_access.2786254310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/29.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.3462592051 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 25308046398 ps |
| CPU time | 447.31 seconds |
| Started | Aug 23 02:24:27 PM UTC 24 |
| Finished | Aug 23 02:32:00 PM UTC 24 |
| Peak memory | 211552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462592051 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_partial_a ccess_b2b.3462592051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/29.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.3033810681 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 347025992 ps |
| CPU time | 3.27 seconds |
| Started | Aug 23 02:25:45 PM UTC 24 |
| Finished | Aug 23 02:25:49 PM UTC 24 |
| Peak memory | 211692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033810681 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.3033810681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/29.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_regwen.4273596255 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 3036099256 ps |
| CPU time | 354.63 seconds |
| Started | Aug 23 02:25:24 PM UTC 24 |
| Finished | Aug 23 02:31:23 PM UTC 24 |
| Peak memory | 384472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273596255 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.4273596255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/29.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_smoke.1732944139 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 2111311881 ps |
| CPU time | 13.94 seconds |
| Started | Aug 23 02:23:36 PM UTC 24 |
| Finished | Aug 23 02:23:51 PM UTC 24 |
| Peak memory | 211488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732944139 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.1732944139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/29.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all.486239622 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 118972059307 ps |
| CPU time | 426.41 seconds |
| Started | Aug 23 02:27:23 PM UTC 24 |
| Finished | Aug 23 02:34:34 PM UTC 24 |
| Peak memory | 392660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48623962 2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all.486239622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/29.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.734126845 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 1869285727 ps |
| CPU time | 58.24 seconds |
| Started | Aug 23 02:26:29 PM UTC 24 |
| Finished | Aug 23 02:27:29 PM UTC 24 |
| Peak memory | 319056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734126845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.734126845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/29.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.2887218235 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 8361276004 ps |
| CPU time | 284.07 seconds |
| Started | Aug 23 02:23:55 PM UTC 24 |
| Finished | Aug 23 02:28:43 PM UTC 24 |
| Peak memory | 211760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887218235 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_pipeline.2887218235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/29.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.3806294463 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 712694558 ps |
| CPU time | 7.92 seconds |
| Started | Aug 23 02:24:59 PM UTC 24 |
| Finished | Aug 23 02:25:09 PM UTC 24 |
| Peak memory | 233056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3806294463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl _throughput_w_partial_write.3806294463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/29.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.596181140 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 14348245149 ps |
| CPU time | 686.85 seconds |
| Started | Aug 23 12:56:11 PM UTC 24 |
| Finished | Aug 23 01:07:45 PM UTC 24 |
| Peak memory | 386532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596181140 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_access_during _key_req.596181140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/3.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_alert_test.1664422961 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 43491863 ps |
| CPU time | 0.57 seconds |
| Started | Aug 23 12:57:07 PM UTC 24 |
| Finished | Aug 23 12:57:09 PM UTC 24 |
| Peak memory | 210884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664422961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_alert_test.1664422961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/3.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_bijection.2904367673 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 16409083492 ps |
| CPU time | 495.78 seconds |
| Started | Aug 23 12:55:13 PM UTC 24 |
| Finished | Aug 23 01:03:34 PM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904367673 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.2904367673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/3.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_executable.807956843 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 30041905502 ps |
| CPU time | 492.67 seconds |
| Started | Aug 23 12:56:32 PM UTC 24 |
| Finished | Aug 23 01:04:50 PM UTC 24 |
| Peak memory | 388656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807956843 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executable.807956843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/3.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.2326398486 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 13086663130 ps |
| CPU time | 45.04 seconds |
| Started | Aug 23 12:55:52 PM UTC 24 |
| Finished | Aug 23 12:56:38 PM UTC 24 |
| Peak memory | 225968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326398486 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_escalation.2326398486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/3.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.2624427015 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 737030757 ps |
| CPU time | 19.78 seconds |
| Started | Aug 23 12:55:49 PM UTC 24 |
| Finished | Aug 23 12:56:10 PM UTC 24 |
| Peak memory | 300660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2624427015 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_m ax_throughput.2624427015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/3.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.3335341703 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 5236320429 ps |
| CPU time | 141.72 seconds |
| Started | Aug 23 12:56:44 PM UTC 24 |
| Finished | Aug 23 12:59:08 PM UTC 24 |
| Peak memory | 228820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335341703 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_mem_partial_access.3335341703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/3.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.3367023653 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 13827432651 ps |
| CPU time | 280.57 seconds |
| Started | Aug 23 12:56:40 PM UTC 24 |
| Finished | Aug 23 01:01:24 PM UTC 24 |
| Peak memory | 222072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367023653 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_mem_walk.3367023653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/3.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.514382712 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 3605234343 ps |
| CPU time | 24.63 seconds |
| Started | Aug 23 12:55:04 PM UTC 24 |
| Finished | Aug 23 12:55:30 PM UTC 24 |
| Peak memory | 259528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514382712 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multiple_keys.514382712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/3.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access.793385529 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 4426064908 ps |
| CPU time | 19.07 seconds |
| Started | Aug 23 12:55:28 PM UTC 24 |
| Finished | Aug 23 12:55:48 PM UTC 24 |
| Peak memory | 211500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793385529 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_partial_access.793385529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/3.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.3398428186 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 10454753840 ps |
| CPU time | 254.88 seconds |
| Started | Aug 23 12:55:31 PM UTC 24 |
| Finished | Aug 23 12:59:49 PM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398428186 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_partial_ac cess_b2b.3398428186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/3.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.574359996 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 1355179650 ps |
| CPU time | 3.17 seconds |
| Started | Aug 23 12:56:39 PM UTC 24 |
| Finished | Aug 23 12:56:43 PM UTC 24 |
| Peak memory | 211836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574359996 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.574359996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/3.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_regwen.2818573758 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 6272909503 ps |
| CPU time | 119.55 seconds |
| Started | Aug 23 12:56:39 PM UTC 24 |
| Finished | Aug 23 12:58:41 PM UTC 24 |
| Peak memory | 370140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818573758 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.2818573758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/3.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.797353126 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 493867294 ps |
| CPU time | 1.62 seconds |
| Started | Aug 23 12:57:04 PM UTC 24 |
| Finished | Aug 23 12:57:07 PM UTC 24 |
| Peak memory | 246932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797353126 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_sec_cm.797353126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/3.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_smoke.1922662202 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 2950481962 ps |
| CPU time | 7.2 seconds |
| Started | Aug 23 12:55:03 PM UTC 24 |
| Finished | Aug 23 12:55:12 PM UTC 24 |
| Peak memory | 213620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922662202 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.1922662202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/3.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all.67960539 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 204996069475 ps |
| CPU time | 2679.59 seconds |
| Started | Aug 23 12:56:58 PM UTC 24 |
| Finished | Aug 23 01:42:03 PM UTC 24 |
| Peak memory | 390248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67960539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all.67960539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/3.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.595856000 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 972096370 ps |
| CPU time | 8.73 seconds |
| Started | Aug 23 12:56:47 PM UTC 24 |
| Finished | Aug 23 12:56:57 PM UTC 24 |
| Peak memory | 221940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595856000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.595856000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/3.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.3663906688 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 17687298056 ps |
| CPU time | 277.94 seconds |
| Started | Aug 23 12:55:15 PM UTC 24 |
| Finished | Aug 23 12:59:56 PM UTC 24 |
| Peak memory | 211548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663906688 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_pipeline.3663906688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/3.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.1502725123 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 1578684099 ps |
| CPU time | 46.94 seconds |
| Started | Aug 23 12:55:50 PM UTC 24 |
| Finished | Aug 23 12:56:38 PM UTC 24 |
| Peak memory | 366176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1502725123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ throughput_w_partial_write.1502725123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/3.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.1457170503 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 18574528831 ps |
| CPU time | 996.21 seconds |
| Started | Aug 23 02:29:11 PM UTC 24 |
| Finished | Aug 23 02:45:57 PM UTC 24 |
| Peak memory | 392504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457170503 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_access_duri ng_key_req.1457170503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/30.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_alert_test.4031103252 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 27513793 ps |
| CPU time | 0.55 seconds |
| Started | Aug 23 02:31:24 PM UTC 24 |
| Finished | Aug 23 02:31:25 PM UTC 24 |
| Peak memory | 210932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031103252 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_alert_test.4031103252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/30.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_bijection.1501918919 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 90233664308 ps |
| CPU time | 1772.68 seconds |
| Started | Aug 23 02:28:05 PM UTC 24 |
| Finished | Aug 23 02:57:56 PM UTC 24 |
| Peak memory | 213152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501918919 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection.1501918919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/30.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_executable.488142189 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 13451608648 ps |
| CPU time | 546.8 seconds |
| Started | Aug 23 02:29:11 PM UTC 24 |
| Finished | Aug 23 02:38:23 PM UTC 24 |
| Peak memory | 384556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488142189 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executable.488142189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/30.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.2634197886 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 51545229314 ps |
| CPU time | 79.61 seconds |
| Started | Aug 23 02:29:05 PM UTC 24 |
| Finished | Aug 23 02:30:26 PM UTC 24 |
| Peak memory | 211824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634197886 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_escalation.2634197886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/30.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.883869693 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 678844234 ps |
| CPU time | 6.75 seconds |
| Started | Aug 23 02:28:55 PM UTC 24 |
| Finished | Aug 23 02:29:02 PM UTC 24 |
| Peak memory | 227872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 883869693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_m ax_throughput.883869693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/30.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.492201245 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 4018411002 ps |
| CPU time | 55.23 seconds |
| Started | Aug 23 02:30:23 PM UTC 24 |
| Finished | Aug 23 02:31:20 PM UTC 24 |
| Peak memory | 221876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492201245 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_mem_partial_access.492201245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/30.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.3320482921 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 4039820321 ps |
| CPU time | 106.49 seconds |
| Started | Aug 23 02:29:45 PM UTC 24 |
| Finished | Aug 23 02:31:34 PM UTC 24 |
| Peak memory | 221864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320482921 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_mem_walk.3320482921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/30.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.2986297558 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 19217630831 ps |
| CPU time | 613.67 seconds |
| Started | Aug 23 02:27:55 PM UTC 24 |
| Finished | Aug 23 02:38:15 PM UTC 24 |
| Peak memory | 384624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986297558 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multiple_keys.2986297558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/30.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access.4283026114 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 583476087 ps |
| CPU time | 7.49 seconds |
| Started | Aug 23 02:28:44 PM UTC 24 |
| Finished | Aug 23 02:28:52 PM UTC 24 |
| Peak memory | 211424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283026114 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_partial_access.4283026114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/30.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.283630911 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 54154639649 ps |
| CPU time | 301 seconds |
| Started | Aug 23 02:28:53 PM UTC 24 |
| Finished | Aug 23 02:33:57 PM UTC 24 |
| Peak memory | 211644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283630911 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_partial_ac cess_b2b.283630911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/30.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.3326507647 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 692381555 ps |
| CPU time | 3.33 seconds |
| Started | Aug 23 02:29:40 PM UTC 24 |
| Finished | Aug 23 02:29:44 PM UTC 24 |
| Peak memory | 211824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326507647 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.3326507647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/30.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_regwen.4035116169 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 38035051219 ps |
| CPU time | 309.11 seconds |
| Started | Aug 23 02:29:38 PM UTC 24 |
| Finished | Aug 23 02:34:51 PM UTC 24 |
| Peak memory | 388644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035116169 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.4035116169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/30.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_smoke.2856263589 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 2761970680 ps |
| CPU time | 52.16 seconds |
| Started | Aug 23 02:27:31 PM UTC 24 |
| Finished | Aug 23 02:28:25 PM UTC 24 |
| Peak memory | 378536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856263589 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.2856263589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/30.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_all.1737348372 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 103918758093 ps |
| CPU time | 1546.4 seconds |
| Started | Aug 23 02:31:20 PM UTC 24 |
| Finished | Aug 23 02:57:21 PM UTC 24 |
| Peak memory | 404592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17373483 72 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_a ll.1737348372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/30.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.1388077259 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 8608448542 ps |
| CPU time | 97.72 seconds |
| Started | Aug 23 02:30:26 PM UTC 24 |
| Finished | Aug 23 02:32:06 PM UTC 24 |
| Peak memory | 257704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388077259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.1388077259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/30.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.3709250329 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 11294585457 ps |
| CPU time | 265.79 seconds |
| Started | Aug 23 02:28:26 PM UTC 24 |
| Finished | Aug 23 02:32:56 PM UTC 24 |
| Peak memory | 211648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709250329 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_pipeline.3709250329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/30.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.3068239087 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 1390253163 ps |
| CPU time | 5.71 seconds |
| Started | Aug 23 02:29:04 PM UTC 24 |
| Finished | Aug 23 02:29:10 PM UTC 24 |
| Peak memory | 211564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3068239087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl _throughput_w_partial_write.3068239087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/30.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.2813330558 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 15560456661 ps |
| CPU time | 257.85 seconds |
| Started | Aug 23 02:33:07 PM UTC 24 |
| Finished | Aug 23 02:37:28 PM UTC 24 |
| Peak memory | 386696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813330558 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_access_duri ng_key_req.2813330558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/31.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_alert_test.2937760682 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 12258723 ps |
| CPU time | 0.56 seconds |
| Started | Aug 23 02:35:26 PM UTC 24 |
| Finished | Aug 23 02:35:28 PM UTC 24 |
| Peak memory | 210876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937760682 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_alert_test.2937760682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/31.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_bijection.1945907059 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 303287251372 ps |
| CPU time | 712.47 seconds |
| Started | Aug 23 02:31:36 PM UTC 24 |
| Finished | Aug 23 02:43:36 PM UTC 24 |
| Peak memory | 211540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945907059 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection.1945907059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/31.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_executable.2347944195 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 58802788316 ps |
| CPU time | 583.74 seconds |
| Started | Aug 23 02:33:22 PM UTC 24 |
| Finished | Aug 23 02:43:12 PM UTC 24 |
| Peak memory | 386572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347944195 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executable.2347944195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/31.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.2132293293 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 2360641856 ps |
| CPU time | 16.71 seconds |
| Started | Aug 23 02:33:03 PM UTC 24 |
| Finished | Aug 23 02:33:21 PM UTC 24 |
| Peak memory | 211480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132293293 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_escalation.2132293293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/31.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.1988982264 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 4158879615 ps |
| CPU time | 17.9 seconds |
| Started | Aug 23 02:32:43 PM UTC 24 |
| Finished | Aug 23 02:33:03 PM UTC 24 |
| Peak memory | 284196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1988982264 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ max_throughput.1988982264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/31.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.873719249 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 3359905651 ps |
| CPU time | 110.77 seconds |
| Started | Aug 23 02:33:59 PM UTC 24 |
| Finished | Aug 23 02:35:51 PM UTC 24 |
| Peak memory | 221932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873719249 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_mem_partial_access.873719249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/31.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.3182059719 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 28235493370 ps |
| CPU time | 276.55 seconds |
| Started | Aug 23 02:33:37 PM UTC 24 |
| Finished | Aug 23 02:38:17 PM UTC 24 |
| Peak memory | 221864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182059719 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_mem_walk.3182059719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/31.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.2452376739 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 22555174794 ps |
| CPU time | 861.57 seconds |
| Started | Aug 23 02:31:35 PM UTC 24 |
| Finished | Aug 23 02:46:05 PM UTC 24 |
| Peak memory | 388736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452376739 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multiple_keys.2452376739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/31.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access.2435935533 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 1801608846 ps |
| CPU time | 30.75 seconds |
| Started | Aug 23 02:32:07 PM UTC 24 |
| Finished | Aug 23 02:32:39 PM UTC 24 |
| Peak memory | 329184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435935533 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_partial_access.2435935533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/31.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.2037379625 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 9869162099 ps |
| CPU time | 213.37 seconds |
| Started | Aug 23 02:32:40 PM UTC 24 |
| Finished | Aug 23 02:36:16 PM UTC 24 |
| Peak memory | 211492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037379625 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_partial_a ccess_b2b.2037379625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/31.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.952507383 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 1197694845 ps |
| CPU time | 3.48 seconds |
| Started | Aug 23 02:33:32 PM UTC 24 |
| Finished | Aug 23 02:33:37 PM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952507383 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.952507383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/31.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_regwen.1751995975 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 61791771919 ps |
| CPU time | 595.36 seconds |
| Started | Aug 23 02:33:31 PM UTC 24 |
| Finished | Aug 23 02:43:33 PM UTC 24 |
| Peak memory | 388784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751995975 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.1751995975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/31.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_smoke.3024555522 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 845617694 ps |
| CPU time | 8.25 seconds |
| Started | Aug 23 02:31:26 PM UTC 24 |
| Finished | Aug 23 02:31:35 PM UTC 24 |
| Peak memory | 211488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024555522 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.3024555522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/31.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_all.3298823452 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 344622540302 ps |
| CPU time | 1397.47 seconds |
| Started | Aug 23 02:34:52 PM UTC 24 |
| Finished | Aug 23 02:58:23 PM UTC 24 |
| Peak memory | 386292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32988234 52 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_a ll.3298823452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/31.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.2041530272 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 1555629653 ps |
| CPU time | 65.77 seconds |
| Started | Aug 23 02:34:35 PM UTC 24 |
| Finished | Aug 23 02:35:42 PM UTC 24 |
| Peak memory | 349716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041530272 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.2041530272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/31.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.1652154653 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 6256951624 ps |
| CPU time | 202.88 seconds |
| Started | Aug 23 02:32:00 PM UTC 24 |
| Finished | Aug 23 02:35:26 PM UTC 24 |
| Peak memory | 211576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652154653 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_pipeline.1652154653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/31.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.2354628112 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 1388204085 ps |
| CPU time | 7.9 seconds |
| Started | Aug 23 02:32:57 PM UTC 24 |
| Finished | Aug 23 02:33:06 PM UTC 24 |
| Peak memory | 228952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2354628112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl _throughput_w_partial_write.2354628112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/31.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.3573124085 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 10776506355 ps |
| CPU time | 468.49 seconds |
| Started | Aug 23 02:37:29 PM UTC 24 |
| Finished | Aug 23 02:45:22 PM UTC 24 |
| Peak memory | 388900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573124085 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_access_duri ng_key_req.3573124085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/32.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_alert_test.69517734 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 39793782 ps |
| CPU time | 0.57 seconds |
| Started | Aug 23 02:40:01 PM UTC 24 |
| Finished | Aug 23 02:40:02 PM UTC 24 |
| Peak memory | 210876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69517734 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_alert_test.69517734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/32.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_bijection.1577000666 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 386779622545 ps |
| CPU time | 2035.08 seconds |
| Started | Aug 23 02:35:43 PM UTC 24 |
| Finished | Aug 23 03:09:58 PM UTC 24 |
| Peak memory | 213164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577000666 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection.1577000666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/32.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_executable.1475593849 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 47277709037 ps |
| CPU time | 313.61 seconds |
| Started | Aug 23 02:38:16 PM UTC 24 |
| Finished | Aug 23 02:43:33 PM UTC 24 |
| Peak memory | 382420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475593849 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executable.1475593849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/32.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.910133628 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 12788011584 ps |
| CPU time | 66.06 seconds |
| Started | Aug 23 02:37:24 PM UTC 24 |
| Finished | Aug 23 02:38:31 PM UTC 24 |
| Peak memory | 225976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910133628 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_escalation.910133628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/32.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.407721751 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 758528991 ps |
| CPU time | 21.11 seconds |
| Started | Aug 23 02:36:34 PM UTC 24 |
| Finished | Aug 23 02:36:56 PM UTC 24 |
| Peak memory | 302492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 407721751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_m ax_throughput.407721751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/32.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.983120165 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 5235103298 ps |
| CPU time | 147.26 seconds |
| Started | Aug 23 02:38:32 PM UTC 24 |
| Finished | Aug 23 02:41:02 PM UTC 24 |
| Peak memory | 229036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983120165 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_mem_partial_access.983120165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/32.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.3908273121 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 20272278758 ps |
| CPU time | 152.25 seconds |
| Started | Aug 23 02:38:29 PM UTC 24 |
| Finished | Aug 23 02:41:04 PM UTC 24 |
| Peak memory | 222020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908273121 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_mem_walk.3908273121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/32.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.700262372 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 25191550370 ps |
| CPU time | 421.22 seconds |
| Started | Aug 23 02:35:38 PM UTC 24 |
| Finished | Aug 23 02:42:44 PM UTC 24 |
| Peak memory | 388564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700262372 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multiple_keys.700262372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/32.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access.3744356078 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 5068177579 ps |
| CPU time | 13.82 seconds |
| Started | Aug 23 02:36:17 PM UTC 24 |
| Finished | Aug 23 02:36:32 PM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744356078 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_partial_access.3744356078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/32.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.4042316389 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 14304477502 ps |
| CPU time | 340.46 seconds |
| Started | Aug 23 02:36:19 PM UTC 24 |
| Finished | Aug 23 02:42:04 PM UTC 24 |
| Peak memory | 211572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042316389 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_partial_a ccess_b2b.4042316389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/32.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.2169778024 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 345872440 ps |
| CPU time | 3.28 seconds |
| Started | Aug 23 02:38:24 PM UTC 24 |
| Finished | Aug 23 02:38:28 PM UTC 24 |
| Peak memory | 211684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169778024 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.2169778024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/32.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_regwen.430427539 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 1129624349 ps |
| CPU time | 99.61 seconds |
| Started | Aug 23 02:38:18 PM UTC 24 |
| Finished | Aug 23 02:39:59 PM UTC 24 |
| Peak memory | 361888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430427539 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.430427539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/32.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_smoke.632790382 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 2412175925 ps |
| CPU time | 8.47 seconds |
| Started | Aug 23 02:35:28 PM UTC 24 |
| Finished | Aug 23 02:35:38 PM UTC 24 |
| Peak memory | 247336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632790382 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.632790382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/32.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all.1674591928 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 445982611325 ps |
| CPU time | 4069.9 seconds |
| Started | Aug 23 02:39:12 PM UTC 24 |
| Finished | Aug 23 03:47:40 PM UTC 24 |
| Peak memory | 390116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16745919 28 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_a ll.1674591928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/32.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.3189236515 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 1032835178 ps |
| CPU time | 14.09 seconds |
| Started | Aug 23 02:38:56 PM UTC 24 |
| Finished | Aug 23 02:39:12 PM UTC 24 |
| Peak memory | 229040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189236515 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.3189236515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/32.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.3396120548 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 5196210844 ps |
| CPU time | 319.75 seconds |
| Started | Aug 23 02:35:52 PM UTC 24 |
| Finished | Aug 23 02:41:16 PM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396120548 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_pipeline.3396120548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/32.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.1125631907 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 797598469 ps |
| CPU time | 25.24 seconds |
| Started | Aug 23 02:36:57 PM UTC 24 |
| Finished | Aug 23 02:37:23 PM UTC 24 |
| Peak memory | 310668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1125631907 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl _throughput_w_partial_write.1125631907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/32.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.3518913212 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 30114001789 ps |
| CPU time | 492.91 seconds |
| Started | Aug 23 02:41:55 PM UTC 24 |
| Finished | Aug 23 02:50:13 PM UTC 24 |
| Peak memory | 388844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518913212 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_access_duri ng_key_req.3518913212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/33.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_alert_test.3124306361 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 33615690 ps |
| CPU time | 0.55 seconds |
| Started | Aug 23 02:43:37 PM UTC 24 |
| Finished | Aug 23 02:43:39 PM UTC 24 |
| Peak memory | 210740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124306361 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_alert_test.3124306361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/33.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_bijection.1398727583 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 105501426321 ps |
| CPU time | 1998.57 seconds |
| Started | Aug 23 02:40:22 PM UTC 24 |
| Finished | Aug 23 03:14:00 PM UTC 24 |
| Peak memory | 213248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398727583 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection.1398727583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/33.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_executable.3486150593 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 46317545476 ps |
| CPU time | 445.83 seconds |
| Started | Aug 23 02:42:05 PM UTC 24 |
| Finished | Aug 23 02:49:35 PM UTC 24 |
| Peak memory | 388576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486150593 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executable.3486150593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/33.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.3980273423 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 35123848844 ps |
| CPU time | 52.59 seconds |
| Started | Aug 23 02:41:34 PM UTC 24 |
| Finished | Aug 23 02:42:29 PM UTC 24 |
| Peak memory | 221952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980273423 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_escalation.3980273423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/33.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.3034757283 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 756387442 ps |
| CPU time | 35.32 seconds |
| Started | Aug 23 02:41:16 PM UTC 24 |
| Finished | Aug 23 02:41:53 PM UTC 24 |
| Peak memory | 345652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3034757283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ max_throughput.3034757283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/33.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.2748993520 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 12583682700 ps |
| CPU time | 140.7 seconds |
| Started | Aug 23 02:43:13 PM UTC 24 |
| Finished | Aug 23 02:45:36 PM UTC 24 |
| Peak memory | 228880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748993520 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_mem_partial_access.2748993520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/33.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.2692822372 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 2062938199 ps |
| CPU time | 110.58 seconds |
| Started | Aug 23 02:42:50 PM UTC 24 |
| Finished | Aug 23 02:44:43 PM UTC 24 |
| Peak memory | 221888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692822372 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_mem_walk.2692822372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/33.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.3862207142 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 79885979819 ps |
| CPU time | 604.28 seconds |
| Started | Aug 23 02:40:19 PM UTC 24 |
| Finished | Aug 23 02:50:29 PM UTC 24 |
| Peak memory | 388564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862207142 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multiple_keys.3862207142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/33.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access.502567439 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 981651995 ps |
| CPU time | 13.25 seconds |
| Started | Aug 23 02:41:04 PM UTC 24 |
| Finished | Aug 23 02:41:19 PM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502567439 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_partial_access.502567439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/33.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.3181027070 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 15024500205 ps |
| CPU time | 244.79 seconds |
| Started | Aug 23 02:41:06 PM UTC 24 |
| Finished | Aug 23 02:45:14 PM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181027070 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_partial_a ccess_b2b.3181027070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/33.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.3951844161 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 548553808 ps |
| CPU time | 3 seconds |
| Started | Aug 23 02:42:45 PM UTC 24 |
| Finished | Aug 23 02:42:49 PM UTC 24 |
| Peak memory | 211692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951844161 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.3951844161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/33.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_regwen.1602014997 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 10876864475 ps |
| CPU time | 490.57 seconds |
| Started | Aug 23 02:42:30 PM UTC 24 |
| Finished | Aug 23 02:50:47 PM UTC 24 |
| Peak memory | 386732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602014997 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.1602014997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/33.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_smoke.85294979 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 1586065315 ps |
| CPU time | 13.98 seconds |
| Started | Aug 23 02:40:03 PM UTC 24 |
| Finished | Aug 23 02:40:18 PM UTC 24 |
| Peak memory | 211556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85294979 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.85294979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/33.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all.1813122118 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 286344705459 ps |
| CPU time | 4336.24 seconds |
| Started | Aug 23 02:43:34 PM UTC 24 |
| Finished | Aug 23 03:56:31 PM UTC 24 |
| Peak memory | 392296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18131221 18 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_a ll.1813122118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/33.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.436044845 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 291276460 ps |
| CPU time | 8.82 seconds |
| Started | Aug 23 02:43:34 PM UTC 24 |
| Finished | Aug 23 02:43:44 PM UTC 24 |
| Peak memory | 221804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436044845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.436044845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/33.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.916994838 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 15689067252 ps |
| CPU time | 202.76 seconds |
| Started | Aug 23 02:41:03 PM UTC 24 |
| Finished | Aug 23 02:44:29 PM UTC 24 |
| Peak memory | 211572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916994838 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_pipeline.916994838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/33.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.4014749793 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 2932498495 ps |
| CPU time | 12.74 seconds |
| Started | Aug 23 02:41:19 PM UTC 24 |
| Finished | Aug 23 02:41:34 PM UTC 24 |
| Peak memory | 261592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =4014749793 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl _throughput_w_partial_write.4014749793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/33.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.1804233027 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 94336001483 ps |
| CPU time | 408.58 seconds |
| Started | Aug 23 02:45:15 PM UTC 24 |
| Finished | Aug 23 02:52:09 PM UTC 24 |
| Peak memory | 386532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804233027 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_access_duri ng_key_req.1804233027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/34.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_alert_test.1295025813 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 14628106 ps |
| CPU time | 0.6 seconds |
| Started | Aug 23 02:48:03 PM UTC 24 |
| Finished | Aug 23 02:48:05 PM UTC 24 |
| Peak memory | 210740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295025813 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_alert_test.1295025813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/34.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_bijection.2847197573 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 86573308076 ps |
| CPU time | 1570.38 seconds |
| Started | Aug 23 02:43:54 PM UTC 24 |
| Finished | Aug 23 03:10:20 PM UTC 24 |
| Peak memory | 213308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847197573 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection.2847197573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/34.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_executable.2495510305 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 35254813062 ps |
| CPU time | 587.87 seconds |
| Started | Aug 23 02:45:23 PM UTC 24 |
| Finished | Aug 23 02:55:17 PM UTC 24 |
| Peak memory | 388564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495510305 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executable.2495510305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/34.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.320279480 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 38582343714 ps |
| CPU time | 57.39 seconds |
| Started | Aug 23 02:45:09 PM UTC 24 |
| Finished | Aug 23 02:46:08 PM UTC 24 |
| Peak memory | 221800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320279480 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_escalation.320279480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/34.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.668531195 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 687818780 ps |
| CPU time | 8.11 seconds |
| Started | Aug 23 02:44:50 PM UTC 24 |
| Finished | Aug 23 02:44:59 PM UTC 24 |
| Peak memory | 232928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 668531195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_m ax_throughput.668531195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/34.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.3784765062 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 2635177832 ps |
| CPU time | 118.89 seconds |
| Started | Aug 23 02:46:05 PM UTC 24 |
| Finished | Aug 23 02:48:06 PM UTC 24 |
| Peak memory | 221928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784765062 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_mem_partial_access.3784765062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/34.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.2012300636 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 7884932390 ps |
| CPU time | 218.94 seconds |
| Started | Aug 23 02:46:02 PM UTC 24 |
| Finished | Aug 23 02:49:44 PM UTC 24 |
| Peak memory | 222024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012300636 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_mem_walk.2012300636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/34.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.382902602 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 9400202442 ps |
| CPU time | 549.56 seconds |
| Started | Aug 23 02:43:45 PM UTC 24 |
| Finished | Aug 23 02:53:01 PM UTC 24 |
| Peak memory | 388564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382902602 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multiple_keys.382902602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/34.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access.4101344117 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 5450856846 ps |
| CPU time | 17.69 seconds |
| Started | Aug 23 02:44:30 PM UTC 24 |
| Finished | Aug 23 02:44:48 PM UTC 24 |
| Peak memory | 211576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101344117 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_partial_access.4101344117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/34.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.681146977 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 29692563291 ps |
| CPU time | 382.68 seconds |
| Started | Aug 23 02:44:44 PM UTC 24 |
| Finished | Aug 23 02:51:11 PM UTC 24 |
| Peak memory | 211488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681146977 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_partial_ac cess_b2b.681146977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/34.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.218383120 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 1876831773 ps |
| CPU time | 3.27 seconds |
| Started | Aug 23 02:45:57 PM UTC 24 |
| Finished | Aug 23 02:46:01 PM UTC 24 |
| Peak memory | 211708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218383120 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.218383120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/34.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_regwen.1856043838 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 3233301588 ps |
| CPU time | 447.03 seconds |
| Started | Aug 23 02:45:37 PM UTC 24 |
| Finished | Aug 23 02:53:09 PM UTC 24 |
| Peak memory | 386796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856043838 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.1856043838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/34.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_smoke.2904154655 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 7448953566 ps |
| CPU time | 13.17 seconds |
| Started | Aug 23 02:43:39 PM UTC 24 |
| Finished | Aug 23 02:43:53 PM UTC 24 |
| Peak memory | 211880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904154655 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.2904154655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/34.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all.2152578630 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 751114134806 ps |
| CPU time | 5168.51 seconds |
| Started | Aug 23 02:46:13 PM UTC 24 |
| Finished | Aug 23 04:13:10 PM UTC 24 |
| Peak memory | 390196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21525786 30 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_a ll.2152578630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/34.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.1770046352 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 14128749319 ps |
| CPU time | 111.21 seconds |
| Started | Aug 23 02:46:08 PM UTC 24 |
| Finished | Aug 23 02:48:02 PM UTC 24 |
| Peak memory | 392804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770046352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.1770046352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/34.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.4027772243 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 2344740620 ps |
| CPU time | 119.62 seconds |
| Started | Aug 23 02:44:10 PM UTC 24 |
| Finished | Aug 23 02:46:12 PM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027772243 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_pipeline.4027772243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/34.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.485685737 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 3392829004 ps |
| CPU time | 7.29 seconds |
| Started | Aug 23 02:45:00 PM UTC 24 |
| Finished | Aug 23 02:45:08 PM UTC 24 |
| Peak memory | 228760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =485685737 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ throughput_w_partial_write.485685737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/34.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.312796143 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 77584422413 ps |
| CPU time | 675.4 seconds |
| Started | Aug 23 02:50:30 PM UTC 24 |
| Finished | Aug 23 03:01:53 PM UTC 24 |
| Peak memory | 371820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312796143 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_access_durin g_key_req.312796143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/35.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_alert_test.3569374804 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 66439863 ps |
| CPU time | 0.54 seconds |
| Started | Aug 23 02:51:50 PM UTC 24 |
| Finished | Aug 23 02:51:52 PM UTC 24 |
| Peak memory | 210740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569374804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_alert_test.3569374804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/35.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_bijection.1748937487 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 441669294367 ps |
| CPU time | 2299.9 seconds |
| Started | Aug 23 02:48:16 PM UTC 24 |
| Finished | Aug 23 03:26:58 PM UTC 24 |
| Peak memory | 213320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748937487 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection.1748937487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/35.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_executable.1046759571 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 2054412023 ps |
| CPU time | 67.37 seconds |
| Started | Aug 23 02:50:38 PM UTC 24 |
| Finished | Aug 23 02:51:47 PM UTC 24 |
| Peak memory | 331224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046759571 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executable.1046759571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/35.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.2037612005 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 8274667893 ps |
| CPU time | 48.12 seconds |
| Started | Aug 23 02:50:28 PM UTC 24 |
| Finished | Aug 23 02:51:17 PM UTC 24 |
| Peak memory | 221816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037612005 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_escalation.2037612005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/35.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.2352141805 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 709679928 ps |
| CPU time | 12.41 seconds |
| Started | Aug 23 02:50:14 PM UTC 24 |
| Finished | Aug 23 02:50:27 PM UTC 24 |
| Peak memory | 261600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2352141805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ max_throughput.2352141805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/35.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.611494094 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 10922266091 ps |
| CPU time | 70.53 seconds |
| Started | Aug 23 02:51:12 PM UTC 24 |
| Finished | Aug 23 02:52:24 PM UTC 24 |
| Peak memory | 222004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611494094 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_mem_partial_access.611494094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/35.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.2714077812 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 345213500412 ps |
| CPU time | 404.59 seconds |
| Started | Aug 23 02:50:53 PM UTC 24 |
| Finished | Aug 23 02:57:43 PM UTC 24 |
| Peak memory | 221956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714077812 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_mem_walk.2714077812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/35.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.1181515938 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 71981969829 ps |
| CPU time | 564.98 seconds |
| Started | Aug 23 02:48:07 PM UTC 24 |
| Finished | Aug 23 02:57:38 PM UTC 24 |
| Peak memory | 388724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181515938 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multiple_keys.1181515938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/35.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access.2410374446 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 1176251494 ps |
| CPU time | 38.71 seconds |
| Started | Aug 23 02:49:36 PM UTC 24 |
| Finished | Aug 23 02:50:17 PM UTC 24 |
| Peak memory | 335260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410374446 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_partial_access.2410374446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/35.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.1391376837 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 86199437482 ps |
| CPU time | 479.97 seconds |
| Started | Aug 23 02:49:44 PM UTC 24 |
| Finished | Aug 23 02:57:50 PM UTC 24 |
| Peak memory | 211492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391376837 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_partial_a ccess_b2b.1391376837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/35.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.2482739088 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 363759635 ps |
| CPU time | 3.09 seconds |
| Started | Aug 23 02:50:48 PM UTC 24 |
| Finished | Aug 23 02:50:52 PM UTC 24 |
| Peak memory | 211696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482739088 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.2482739088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/35.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_regwen.105712824 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 33267835870 ps |
| CPU time | 577.55 seconds |
| Started | Aug 23 02:50:42 PM UTC 24 |
| Finished | Aug 23 03:00:26 PM UTC 24 |
| Peak memory | 388636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105712824 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.105712824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/35.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_smoke.4132919792 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 1590274806 ps |
| CPU time | 18.43 seconds |
| Started | Aug 23 02:48:05 PM UTC 24 |
| Finished | Aug 23 02:48:25 PM UTC 24 |
| Peak memory | 294504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132919792 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.4132919792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/35.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all.3729446117 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 264919648945 ps |
| CPU time | 2334.35 seconds |
| Started | Aug 23 02:51:48 PM UTC 24 |
| Finished | Aug 23 03:31:04 PM UTC 24 |
| Peak memory | 392304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37294461 17 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_a ll.3729446117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/35.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.3468493932 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 1930633818 ps |
| CPU time | 29.61 seconds |
| Started | Aug 23 02:51:18 PM UTC 24 |
| Finished | Aug 23 02:51:49 PM UTC 24 |
| Peak memory | 228972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468493932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.3468493932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/35.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.176234641 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 6268449173 ps |
| CPU time | 133.88 seconds |
| Started | Aug 23 02:48:25 PM UTC 24 |
| Finished | Aug 23 02:50:41 PM UTC 24 |
| Peak memory | 211624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176234641 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_pipeline.176234641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/35.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.3731342943 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 734683301 ps |
| CPU time | 18.42 seconds |
| Started | Aug 23 02:50:18 PM UTC 24 |
| Finished | Aug 23 02:50:37 PM UTC 24 |
| Peak memory | 294296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3731342943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl _throughput_w_partial_write.3731342943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/35.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.2385889666 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 10375449185 ps |
| CPU time | 550.12 seconds |
| Started | Aug 23 02:55:17 PM UTC 24 |
| Finished | Aug 23 03:04:33 PM UTC 24 |
| Peak memory | 388812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385889666 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_access_duri ng_key_req.2385889666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/36.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_alert_test.4285267881 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 25567382 ps |
| CPU time | 0.56 seconds |
| Started | Aug 23 02:57:43 PM UTC 24 |
| Finished | Aug 23 02:57:45 PM UTC 24 |
| Peak memory | 210816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285267881 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_alert_test.4285267881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/36.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_bijection.1195675827 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 22477057097 ps |
| CPU time | 1266.98 seconds |
| Started | Aug 23 02:52:23 PM UTC 24 |
| Finished | Aug 23 03:13:43 PM UTC 24 |
| Peak memory | 213500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195675827 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection.1195675827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/36.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_executable.1517341957 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 14925134941 ps |
| CPU time | 346.28 seconds |
| Started | Aug 23 02:55:34 PM UTC 24 |
| Finished | Aug 23 03:01:25 PM UTC 24 |
| Peak memory | 386600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517341957 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executable.1517341957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/36.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.1740000311 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 31501031807 ps |
| CPU time | 49.98 seconds |
| Started | Aug 23 02:54:51 PM UTC 24 |
| Finished | Aug 23 02:55:43 PM UTC 24 |
| Peak memory | 211572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740000311 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_escalation.1740000311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/36.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.124863335 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 3051092070 ps |
| CPU time | 51.6 seconds |
| Started | Aug 23 02:53:57 PM UTC 24 |
| Finished | Aug 23 02:54:50 PM UTC 24 |
| Peak memory | 378404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 124863335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_m ax_throughput.124863335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/36.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.1446748292 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 1430278133 ps |
| CPU time | 61.38 seconds |
| Started | Aug 23 02:57:13 PM UTC 24 |
| Finished | Aug 23 02:58:16 PM UTC 24 |
| Peak memory | 228812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446748292 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_mem_partial_access.1446748292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/36.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.1363767034 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 20737196316 ps |
| CPU time | 218.55 seconds |
| Started | Aug 23 02:56:15 PM UTC 24 |
| Finished | Aug 23 02:59:56 PM UTC 24 |
| Peak memory | 221820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363767034 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_mem_walk.1363767034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/36.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.3933986600 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 9898270840 ps |
| CPU time | 497.5 seconds |
| Started | Aug 23 02:52:09 PM UTC 24 |
| Finished | Aug 23 03:00:32 PM UTC 24 |
| Peak memory | 388772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933986600 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multiple_keys.3933986600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/36.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access.2341919857 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 2238068063 ps |
| CPU time | 52.39 seconds |
| Started | Aug 23 02:53:02 PM UTC 24 |
| Finished | Aug 23 02:53:56 PM UTC 24 |
| Peak memory | 376272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341919857 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_partial_access.2341919857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/36.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.720044888 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 67666154222 ps |
| CPU time | 352.47 seconds |
| Started | Aug 23 02:53:10 PM UTC 24 |
| Finished | Aug 23 02:59:07 PM UTC 24 |
| Peak memory | 211836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720044888 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_partial_ac cess_b2b.720044888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/36.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.11457753 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 1467029694 ps |
| CPU time | 3.3 seconds |
| Started | Aug 23 02:56:09 PM UTC 24 |
| Finished | Aug 23 02:56:14 PM UTC 24 |
| Peak memory | 211828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11457753 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.11457753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/36.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_regwen.593883665 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 36860672524 ps |
| CPU time | 361.25 seconds |
| Started | Aug 23 02:55:43 PM UTC 24 |
| Finished | Aug 23 03:01:49 PM UTC 24 |
| Peak memory | 380376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593883665 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.593883665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/36.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_smoke.2737980813 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 875061523 ps |
| CPU time | 29.54 seconds |
| Started | Aug 23 02:51:52 PM UTC 24 |
| Finished | Aug 23 02:52:23 PM UTC 24 |
| Peak memory | 331156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737980813 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.2737980813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/36.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all.1569624805 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 396785200235 ps |
| CPU time | 6623.03 seconds |
| Started | Aug 23 02:57:39 PM UTC 24 |
| Finished | Aug 23 04:49:04 PM UTC 24 |
| Peak memory | 379856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15696248 05 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_a ll.1569624805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/36.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.641107236 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 2434187807 ps |
| CPU time | 19.5 seconds |
| Started | Aug 23 02:57:22 PM UTC 24 |
| Finished | Aug 23 02:57:42 PM UTC 24 |
| Peak memory | 221852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641107236 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.641107236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/36.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.1753546550 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 9679294147 ps |
| CPU time | 282.8 seconds |
| Started | Aug 23 02:52:25 PM UTC 24 |
| Finished | Aug 23 02:57:12 PM UTC 24 |
| Peak memory | 211888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753546550 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_pipeline.1753546550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/36.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.88172359 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 3123266626 ps |
| CPU time | 54.74 seconds |
| Started | Aug 23 02:54:37 PM UTC 24 |
| Finished | Aug 23 02:55:34 PM UTC 24 |
| Peak memory | 382424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =88172359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_t hroughput_w_partial_write.88172359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/36.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.2805791242 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 22348108459 ps |
| CPU time | 437.02 seconds |
| Started | Aug 23 02:59:07 PM UTC 24 |
| Finished | Aug 23 03:06:29 PM UTC 24 |
| Peak memory | 378648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805791242 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_access_duri ng_key_req.2805791242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/37.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_alert_test.2453833419 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 10502469 ps |
| CPU time | 0.57 seconds |
| Started | Aug 23 03:01:26 PM UTC 24 |
| Finished | Aug 23 03:01:28 PM UTC 24 |
| Peak memory | 210932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453833419 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_alert_test.2453833419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/37.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_bijection.2872397328 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 204233860901 ps |
| CPU time | 1659.82 seconds |
| Started | Aug 23 02:57:51 PM UTC 24 |
| Finished | Aug 23 03:25:47 PM UTC 24 |
| Peak memory | 213220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872397328 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection.2872397328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/37.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_executable.2259847523 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 15912927902 ps |
| CPU time | 195.02 seconds |
| Started | Aug 23 02:59:35 PM UTC 24 |
| Finished | Aug 23 03:02:52 PM UTC 24 |
| Peak memory | 376368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259847523 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executable.2259847523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/37.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.2592358802 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 15670772982 ps |
| CPU time | 44.42 seconds |
| Started | Aug 23 02:59:04 PM UTC 24 |
| Finished | Aug 23 02:59:50 PM UTC 24 |
| Peak memory | 211904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592358802 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_escalation.2592358802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/37.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.2176197124 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 2802834201 ps |
| CPU time | 7.25 seconds |
| Started | Aug 23 02:58:47 PM UTC 24 |
| Finished | Aug 23 02:58:56 PM UTC 24 |
| Peak memory | 228008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2176197124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ max_throughput.2176197124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/37.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.4122853427 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 6367321450 ps |
| CPU time | 107.75 seconds |
| Started | Aug 23 03:00:10 PM UTC 24 |
| Finished | Aug 23 03:02:00 PM UTC 24 |
| Peak memory | 228808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122853427 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_mem_partial_access.4122853427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/37.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.1785580600 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 5315912971 ps |
| CPU time | 242.06 seconds |
| Started | Aug 23 02:59:58 PM UTC 24 |
| Finished | Aug 23 03:04:03 PM UTC 24 |
| Peak memory | 221888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785580600 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_mem_walk.1785580600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/37.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.3870541191 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 48013005467 ps |
| CPU time | 1015.84 seconds |
| Started | Aug 23 02:57:45 PM UTC 24 |
| Finished | Aug 23 03:14:50 PM UTC 24 |
| Peak memory | 388192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870541191 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multiple_keys.3870541191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/37.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access.2364678985 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 940139198 ps |
| CPU time | 45.65 seconds |
| Started | Aug 23 02:58:16 PM UTC 24 |
| Finished | Aug 23 02:59:04 PM UTC 24 |
| Peak memory | 362084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364678985 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_partial_access.2364678985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/37.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.2969254401 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 128673335497 ps |
| CPU time | 525.82 seconds |
| Started | Aug 23 02:58:24 PM UTC 24 |
| Finished | Aug 23 03:07:16 PM UTC 24 |
| Peak memory | 211500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969254401 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_partial_a ccess_b2b.2969254401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/37.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.1770466990 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 599896454 ps |
| CPU time | 3.31 seconds |
| Started | Aug 23 02:59:57 PM UTC 24 |
| Finished | Aug 23 03:00:01 PM UTC 24 |
| Peak memory | 211692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770466990 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.1770466990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/37.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_regwen.2502586147 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 8331662530 ps |
| CPU time | 294.61 seconds |
| Started | Aug 23 02:59:51 PM UTC 24 |
| Finished | Aug 23 03:04:49 PM UTC 24 |
| Peak memory | 386580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502586147 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.2502586147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/37.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_smoke.1258555939 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 962204004 ps |
| CPU time | 61.11 seconds |
| Started | Aug 23 02:57:44 PM UTC 24 |
| Finished | Aug 23 02:58:47 PM UTC 24 |
| Peak memory | 378340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258555939 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.1258555939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/37.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all.1211761050 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 613161624042 ps |
| CPU time | 5764.94 seconds |
| Started | Aug 23 03:00:33 PM UTC 24 |
| Finished | Aug 23 04:37:31 PM UTC 24 |
| Peak memory | 400480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12117610 50 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_a ll.1211761050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/37.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.3742719955 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 45933959597 ps |
| CPU time | 268.33 seconds |
| Started | Aug 23 02:57:56 PM UTC 24 |
| Finished | Aug 23 03:02:28 PM UTC 24 |
| Peak memory | 211588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742719955 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_pipeline.3742719955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/37.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.3803023507 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 3273683567 ps |
| CPU time | 58.96 seconds |
| Started | Aug 23 02:58:56 PM UTC 24 |
| Finished | Aug 23 02:59:57 PM UTC 24 |
| Peak memory | 382684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3803023507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl _throughput_w_partial_write.3803023507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/37.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.2340321453 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 12004533609 ps |
| CPU time | 126.19 seconds |
| Started | Aug 23 03:02:47 PM UTC 24 |
| Finished | Aug 23 03:04:55 PM UTC 24 |
| Peak memory | 368084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340321453 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_access_duri ng_key_req.2340321453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/38.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_alert_test.278967748 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 25964123 ps |
| CPU time | 0.61 seconds |
| Started | Aug 23 03:04:15 PM UTC 24 |
| Finished | Aug 23 03:04:17 PM UTC 24 |
| Peak memory | 210936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278967748 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_alert_test.278967748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/38.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_bijection.525218134 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 203155707722 ps |
| CPU time | 1086.9 seconds |
| Started | Aug 23 03:01:38 PM UTC 24 |
| Finished | Aug 23 03:19:56 PM UTC 24 |
| Peak memory | 213156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525218134 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection.525218134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/38.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_executable.2100772271 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 58018148088 ps |
| CPU time | 358.78 seconds |
| Started | Aug 23 03:02:53 PM UTC 24 |
| Finished | Aug 23 03:08:56 PM UTC 24 |
| Peak memory | 386736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100772271 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executable.2100772271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/38.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.2912887979 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 13628089163 ps |
| CPU time | 39.18 seconds |
| Started | Aug 23 03:02:32 PM UTC 24 |
| Finished | Aug 23 03:03:12 PM UTC 24 |
| Peak memory | 211760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912887979 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_escalation.2912887979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/38.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.1729726328 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 2702524046 ps |
| CPU time | 35.63 seconds |
| Started | Aug 23 03:02:09 PM UTC 24 |
| Finished | Aug 23 03:02:46 PM UTC 24 |
| Peak memory | 347680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1729726328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ max_throughput.1729726328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/38.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.3628650444 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 1448720921 ps |
| CPU time | 64.67 seconds |
| Started | Aug 23 03:03:35 PM UTC 24 |
| Finished | Aug 23 03:04:42 PM UTC 24 |
| Peak memory | 221852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628650444 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_mem_partial_access.3628650444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/38.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.1175942761 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 14400201778 ps |
| CPU time | 140.53 seconds |
| Started | Aug 23 03:03:31 PM UTC 24 |
| Finished | Aug 23 03:05:54 PM UTC 24 |
| Peak memory | 222144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175942761 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_mem_walk.1175942761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/38.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.3109091037 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 82102090278 ps |
| CPU time | 776.67 seconds |
| Started | Aug 23 03:01:29 PM UTC 24 |
| Finished | Aug 23 03:14:34 PM UTC 24 |
| Peak memory | 390020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109091037 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multiple_keys.3109091037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/38.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access.3300607026 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 1672006082 ps |
| CPU time | 13.26 seconds |
| Started | Aug 23 03:01:53 PM UTC 24 |
| Finished | Aug 23 03:02:08 PM UTC 24 |
| Peak memory | 211572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300607026 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_partial_access.3300607026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/38.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.4267072766 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 7363909386 ps |
| CPU time | 406.44 seconds |
| Started | Aug 23 03:02:01 PM UTC 24 |
| Finished | Aug 23 03:08:52 PM UTC 24 |
| Peak memory | 211624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267072766 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_partial_a ccess_b2b.4267072766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/38.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.455277003 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 1342836715 ps |
| CPU time | 3.56 seconds |
| Started | Aug 23 03:03:26 PM UTC 24 |
| Finished | Aug 23 03:03:31 PM UTC 24 |
| Peak memory | 211828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455277003 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.455277003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/38.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_regwen.3197208575 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 17504417733 ps |
| CPU time | 166.85 seconds |
| Started | Aug 23 03:03:13 PM UTC 24 |
| Finished | Aug 23 03:06:02 PM UTC 24 |
| Peak memory | 351768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197208575 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.3197208575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/38.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_smoke.3833544635 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 8664324008 ps |
| CPU time | 7.01 seconds |
| Started | Aug 23 03:01:29 PM UTC 24 |
| Finished | Aug 23 03:01:38 PM UTC 24 |
| Peak memory | 211216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833544635 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.3833544635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/38.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all.282659157 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 17999366482 ps |
| CPU time | 985.85 seconds |
| Started | Aug 23 03:04:13 PM UTC 24 |
| Finished | Aug 23 03:20:49 PM UTC 24 |
| Peak memory | 377964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28265915 7 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all.282659157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/38.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.1834552721 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 3057901553 ps |
| CPU time | 9.37 seconds |
| Started | Aug 23 03:04:04 PM UTC 24 |
| Finished | Aug 23 03:04:15 PM UTC 24 |
| Peak memory | 222136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834552721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.1834552721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/38.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.3070965830 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 10691348791 ps |
| CPU time | 140.6 seconds |
| Started | Aug 23 03:01:49 PM UTC 24 |
| Finished | Aug 23 03:04:12 PM UTC 24 |
| Peak memory | 211564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070965830 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_pipeline.3070965830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/38.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.2369087266 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 15580099563 ps |
| CPU time | 53.96 seconds |
| Started | Aug 23 03:02:30 PM UTC 24 |
| Finished | Aug 23 03:03:25 PM UTC 24 |
| Peak memory | 376408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2369087266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl _throughput_w_partial_write.2369087266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/38.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.3020911220 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 30310508603 ps |
| CPU time | 386.43 seconds |
| Started | Aug 23 03:06:14 PM UTC 24 |
| Finished | Aug 23 03:12:45 PM UTC 24 |
| Peak memory | 386716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020911220 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_access_duri ng_key_req.3020911220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/39.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_alert_test.2101602895 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 33790833 ps |
| CPU time | 0.53 seconds |
| Started | Aug 23 03:08:35 PM UTC 24 |
| Finished | Aug 23 03:08:37 PM UTC 24 |
| Peak memory | 210932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101602895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_alert_test.2101602895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/39.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_bijection.752323693 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 34497872228 ps |
| CPU time | 1967.09 seconds |
| Started | Aug 23 03:04:34 PM UTC 24 |
| Finished | Aug 23 03:37:40 PM UTC 24 |
| Peak memory | 213236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752323693 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection.752323693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/39.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_executable.2196146730 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 3286882444 ps |
| CPU time | 249.82 seconds |
| Started | Aug 23 03:06:27 PM UTC 24 |
| Finished | Aug 23 03:10:40 PM UTC 24 |
| Peak memory | 378324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196146730 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executable.2196146730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/39.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.2286526414 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 36921578566 ps |
| CPU time | 63.59 seconds |
| Started | Aug 23 03:06:03 PM UTC 24 |
| Finished | Aug 23 03:07:09 PM UTC 24 |
| Peak memory | 226228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286526414 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_escalation.2286526414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/39.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.1571792055 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 2920388898 ps |
| CPU time | 27.04 seconds |
| Started | Aug 23 03:05:45 PM UTC 24 |
| Finished | Aug 23 03:06:14 PM UTC 24 |
| Peak memory | 314920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1571792055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ max_throughput.1571792055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/39.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.2368344322 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 11681462480 ps |
| CPU time | 75.49 seconds |
| Started | Aug 23 03:07:17 PM UTC 24 |
| Finished | Aug 23 03:08:34 PM UTC 24 |
| Peak memory | 228936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368344322 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_mem_partial_access.2368344322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/39.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.3778852850 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 9076394686 ps |
| CPU time | 147.84 seconds |
| Started | Aug 23 03:07:15 PM UTC 24 |
| Finished | Aug 23 03:09:45 PM UTC 24 |
| Peak memory | 221936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778852850 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_mem_walk.3778852850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/39.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.1436810931 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 10805603600 ps |
| CPU time | 297.55 seconds |
| Started | Aug 23 03:04:31 PM UTC 24 |
| Finished | Aug 23 03:09:32 PM UTC 24 |
| Peak memory | 384488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436810931 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multiple_keys.1436810931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/39.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access.1878210669 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 16421583257 ps |
| CPU time | 53.08 seconds |
| Started | Aug 23 03:04:50 PM UTC 24 |
| Finished | Aug 23 03:05:44 PM UTC 24 |
| Peak memory | 363984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878210669 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_partial_access.1878210669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/39.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.2535756234 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 19298247382 ps |
| CPU time | 205.68 seconds |
| Started | Aug 23 03:04:56 PM UTC 24 |
| Finished | Aug 23 03:08:24 PM UTC 24 |
| Peak memory | 211584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535756234 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_partial_a ccess_b2b.2535756234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/39.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.2484920664 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 349195843 ps |
| CPU time | 3.21 seconds |
| Started | Aug 23 03:07:10 PM UTC 24 |
| Finished | Aug 23 03:07:14 PM UTC 24 |
| Peak memory | 211692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484920664 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.2484920664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/39.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_regwen.4214361359 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 12481685720 ps |
| CPU time | 185.01 seconds |
| Started | Aug 23 03:06:30 PM UTC 24 |
| Finished | Aug 23 03:09:38 PM UTC 24 |
| Peak memory | 364048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214361359 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.4214361359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/39.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_smoke.3496633294 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 3025154844 ps |
| CPU time | 11.49 seconds |
| Started | Aug 23 03:04:17 PM UTC 24 |
| Finished | Aug 23 03:04:30 PM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496633294 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.3496633294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/39.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all.802460953 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 61204245322 ps |
| CPU time | 1693.79 seconds |
| Started | Aug 23 03:08:26 PM UTC 24 |
| Finished | Aug 23 03:36:56 PM UTC 24 |
| Peak memory | 390328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80246095 3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all.802460953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/39.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.3669697713 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 6713040986 ps |
| CPU time | 39.47 seconds |
| Started | Aug 23 03:08:25 PM UTC 24 |
| Finished | Aug 23 03:09:06 PM UTC 24 |
| Peak memory | 221872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669697713 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.3669697713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/39.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.3566999637 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 4437750677 ps |
| CPU time | 264.36 seconds |
| Started | Aug 23 03:04:43 PM UTC 24 |
| Finished | Aug 23 03:09:11 PM UTC 24 |
| Peak memory | 211576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566999637 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_pipeline.3566999637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/39.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.3746081578 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 767807413 ps |
| CPU time | 30.1 seconds |
| Started | Aug 23 03:05:55 PM UTC 24 |
| Finished | Aug 23 03:06:27 PM UTC 24 |
| Peak memory | 327068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3746081578 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl _throughput_w_partial_write.3746081578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/39.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.4049079420 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 278709538048 ps |
| CPU time | 616.82 seconds |
| Started | Aug 23 12:58:28 PM UTC 24 |
| Finished | Aug 23 01:08:52 PM UTC 24 |
| Peak memory | 374236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049079420 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_access_durin g_key_req.4049079420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/4.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_alert_test.3446160874 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 12619534 ps |
| CPU time | 0.54 seconds |
| Started | Aug 23 12:59:13 PM UTC 24 |
| Finished | Aug 23 12:59:15 PM UTC 24 |
| Peak memory | 210824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446160874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_alert_test.3446160874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/4.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_bijection.2321904780 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 107665239553 ps |
| CPU time | 1190.86 seconds |
| Started | Aug 23 12:57:22 PM UTC 24 |
| Finished | Aug 23 01:17:25 PM UTC 24 |
| Peak memory | 213216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321904780 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection.2321904780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/4.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_executable.3103112323 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 7483301634 ps |
| CPU time | 231.23 seconds |
| Started | Aug 23 12:58:31 PM UTC 24 |
| Finished | Aug 23 01:02:26 PM UTC 24 |
| Peak memory | 380588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103112323 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executable.3103112323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/4.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.2995709662 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 2649942114 ps |
| CPU time | 8.52 seconds |
| Started | Aug 23 12:58:21 PM UTC 24 |
| Finished | Aug 23 12:58:31 PM UTC 24 |
| Peak memory | 221612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995709662 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_escalation.2995709662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/4.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.4067190568 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 761585354 ps |
| CPU time | 21.24 seconds |
| Started | Aug 23 12:58:08 PM UTC 24 |
| Finished | Aug 23 12:58:30 PM UTC 24 |
| Peak memory | 300656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4067190568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_m ax_throughput.4067190568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/4.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.6774441 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 4391208200 ps |
| CPU time | 128.74 seconds |
| Started | Aug 23 12:58:43 PM UTC 24 |
| Finished | Aug 23 01:00:54 PM UTC 24 |
| Peak memory | 221796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6774441 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_mem_partial_access.6774441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/4.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.735174312 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 20655468173 ps |
| CPU time | 305.39 seconds |
| Started | Aug 23 12:58:42 PM UTC 24 |
| Finished | Aug 23 01:03:51 PM UTC 24 |
| Peak memory | 221800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735174312 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_mem_walk.735174312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/4.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.2577821789 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 137183102391 ps |
| CPU time | 742.87 seconds |
| Started | Aug 23 12:57:20 PM UTC 24 |
| Finished | Aug 23 01:09:50 PM UTC 24 |
| Peak memory | 388632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577821789 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multiple_keys.2577821789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/4.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access.772546648 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 3779167759 ps |
| CPU time | 22.23 seconds |
| Started | Aug 23 12:57:47 PM UTC 24 |
| Finished | Aug 23 12:58:10 PM UTC 24 |
| Peak memory | 211620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772546648 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_partial_access.772546648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/4.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.3467247307 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 19738848043 ps |
| CPU time | 211.39 seconds |
| Started | Aug 23 12:58:08 PM UTC 24 |
| Finished | Aug 23 01:01:42 PM UTC 24 |
| Peak memory | 211548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467247307 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_partial_ac cess_b2b.3467247307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/4.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.1524755773 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 1612952663 ps |
| CPU time | 3.56 seconds |
| Started | Aug 23 12:58:41 PM UTC 24 |
| Finished | Aug 23 12:58:46 PM UTC 24 |
| Peak memory | 211836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524755773 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.1524755773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/4.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_regwen.864799721 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 2871710109 ps |
| CPU time | 474.36 seconds |
| Started | Aug 23 12:58:31 PM UTC 24 |
| Finished | Aug 23 01:06:31 PM UTC 24 |
| Peak memory | 388788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864799721 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.864799721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/4.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.3457436218 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 852359512 ps |
| CPU time | 1.84 seconds |
| Started | Aug 23 12:59:09 PM UTC 24 |
| Finished | Aug 23 12:59:12 PM UTC 24 |
| Peak memory | 246948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457436218 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_sec_cm.3457436218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/4.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_smoke.1416037777 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 13307303772 ps |
| CPU time | 9.95 seconds |
| Started | Aug 23 12:57:09 PM UTC 24 |
| Finished | Aug 23 12:57:21 PM UTC 24 |
| Peak memory | 211488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416037777 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.1416037777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/4.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all.2147145847 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 466066650070 ps |
| CPU time | 5383.44 seconds |
| Started | Aug 23 12:59:03 PM UTC 24 |
| Finished | Aug 23 02:29:38 PM UTC 24 |
| Peak memory | 388164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21471458 47 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all.2147145847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/4.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.759894289 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 2893567799 ps |
| CPU time | 127.47 seconds |
| Started | Aug 23 12:58:46 PM UTC 24 |
| Finished | Aug 23 01:00:56 PM UTC 24 |
| Peak memory | 349848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759894289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.759894289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/4.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.1781634250 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 5601322941 ps |
| CPU time | 259.96 seconds |
| Started | Aug 23 12:57:28 PM UTC 24 |
| Finished | Aug 23 01:01:51 PM UTC 24 |
| Peak memory | 211572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781634250 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_pipeline.1781634250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/4.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.1162007149 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 3136347689 ps |
| CPU time | 30.73 seconds |
| Started | Aug 23 12:58:11 PM UTC 24 |
| Finished | Aug 23 12:58:43 PM UTC 24 |
| Peak memory | 333484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1162007149 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ throughput_w_partial_write.1162007149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/4.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.2166097545 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 4251756873 ps |
| CPU time | 42.75 seconds |
| Started | Aug 23 03:09:46 PM UTC 24 |
| Finished | Aug 23 03:10:30 PM UTC 24 |
| Peak memory | 215640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166097545 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_access_duri ng_key_req.2166097545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/40.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_alert_test.3795872899 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 24002617 ps |
| CPU time | 0.57 seconds |
| Started | Aug 23 03:10:41 PM UTC 24 |
| Finished | Aug 23 03:10:43 PM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795872899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_alert_test.3795872899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/40.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_bijection.3743682977 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 270215108728 ps |
| CPU time | 1631.33 seconds |
| Started | Aug 23 03:08:56 PM UTC 24 |
| Finished | Aug 23 03:36:24 PM UTC 24 |
| Peak memory | 213236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743682977 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection.3743682977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/40.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_executable.1341722469 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 25460730629 ps |
| CPU time | 944.31 seconds |
| Started | Aug 23 03:09:59 PM UTC 24 |
| Finished | Aug 23 03:25:52 PM UTC 24 |
| Peak memory | 390124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341722469 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executable.1341722469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/40.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.597848962 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 11623894299 ps |
| CPU time | 58.11 seconds |
| Started | Aug 23 03:09:40 PM UTC 24 |
| Finished | Aug 23 03:10:39 PM UTC 24 |
| Peak memory | 211640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597848962 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_escalation.597848962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/40.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.837853357 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 764324054 ps |
| CPU time | 27.61 seconds |
| Started | Aug 23 03:09:35 PM UTC 24 |
| Finished | Aug 23 03:10:04 PM UTC 24 |
| Peak memory | 310692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 837853357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_m ax_throughput.837853357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/40.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.1937819394 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 17334516139 ps |
| CPU time | 72.57 seconds |
| Started | Aug 23 03:10:31 PM UTC 24 |
| Finished | Aug 23 03:11:45 PM UTC 24 |
| Peak memory | 222116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937819394 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_mem_partial_access.1937819394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/40.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.2921693741 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 13973509637 ps |
| CPU time | 275.28 seconds |
| Started | Aug 23 03:10:26 PM UTC 24 |
| Finished | Aug 23 03:15:05 PM UTC 24 |
| Peak memory | 221876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921693741 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_mem_walk.2921693741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/40.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.1014543179 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 43139292031 ps |
| CPU time | 683.34 seconds |
| Started | Aug 23 03:08:52 PM UTC 24 |
| Finished | Aug 23 03:20:23 PM UTC 24 |
| Peak memory | 384724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014543179 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multiple_keys.1014543179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/40.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access.3278615348 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 1477007188 ps |
| CPU time | 20.59 seconds |
| Started | Aug 23 03:09:11 PM UTC 24 |
| Finished | Aug 23 03:09:33 PM UTC 24 |
| Peak memory | 211556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278615348 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_partial_access.3278615348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/40.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.4217631185 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 4896640750 ps |
| CPU time | 209.54 seconds |
| Started | Aug 23 03:09:32 PM UTC 24 |
| Finished | Aug 23 03:13:05 PM UTC 24 |
| Peak memory | 211624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217631185 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_partial_a ccess_b2b.4217631185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/40.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.4058557252 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 1040348525 ps |
| CPU time | 3.06 seconds |
| Started | Aug 23 03:10:21 PM UTC 24 |
| Finished | Aug 23 03:10:25 PM UTC 24 |
| Peak memory | 211952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058557252 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.4058557252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/40.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_regwen.3607645758 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 53004264087 ps |
| CPU time | 463.72 seconds |
| Started | Aug 23 03:10:04 PM UTC 24 |
| Finished | Aug 23 03:17:53 PM UTC 24 |
| Peak memory | 376296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607645758 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.3607645758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/40.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_smoke.1392051760 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 14543356157 ps |
| CPU time | 60.06 seconds |
| Started | Aug 23 03:08:37 PM UTC 24 |
| Finished | Aug 23 03:09:39 PM UTC 24 |
| Peak memory | 370212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392051760 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.1392051760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/40.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all.2326890936 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 488033860175 ps |
| CPU time | 3013.02 seconds |
| Started | Aug 23 03:10:40 PM UTC 24 |
| Finished | Aug 23 04:01:21 PM UTC 24 |
| Peak memory | 392292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23268909 36 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_a ll.2326890936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/40.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.245703104 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 2397498437 ps |
| CPU time | 71.49 seconds |
| Started | Aug 23 03:10:39 PM UTC 24 |
| Finished | Aug 23 03:11:52 PM UTC 24 |
| Peak memory | 339748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245703104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.245703104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/40.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.2477962594 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 5049503253 ps |
| CPU time | 154.21 seconds |
| Started | Aug 23 03:09:06 PM UTC 24 |
| Finished | Aug 23 03:11:43 PM UTC 24 |
| Peak memory | 211512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477962594 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_pipeline.2477962594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/40.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.3667887076 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 2301819862 ps |
| CPU time | 58.07 seconds |
| Started | Aug 23 03:09:39 PM UTC 24 |
| Finished | Aug 23 03:10:38 PM UTC 24 |
| Peak memory | 382500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3667887076 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl _throughput_w_partial_write.3667887076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/40.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.3302297579 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 24100311876 ps |
| CPU time | 738.87 seconds |
| Started | Aug 23 03:13:27 PM UTC 24 |
| Finished | Aug 23 03:25:54 PM UTC 24 |
| Peak memory | 388776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302297579 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_access_duri ng_key_req.3302297579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/41.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_alert_test.2921206944 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 21559128 ps |
| CPU time | 0.56 seconds |
| Started | Aug 23 03:15:06 PM UTC 24 |
| Finished | Aug 23 03:15:08 PM UTC 24 |
| Peak memory | 210880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921206944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_alert_test.2921206944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/41.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_bijection.1835371883 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 171258449845 ps |
| CPU time | 1375.82 seconds |
| Started | Aug 23 03:11:44 PM UTC 24 |
| Finished | Aug 23 03:34:54 PM UTC 24 |
| Peak memory | 213252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835371883 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection.1835371883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/41.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_executable.539183479 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 22169075845 ps |
| CPU time | 968.78 seconds |
| Started | Aug 23 03:13:44 PM UTC 24 |
| Finished | Aug 23 03:30:02 PM UTC 24 |
| Peak memory | 390248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539183479 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executable.539183479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/41.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.1231039427 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 93900750335 ps |
| CPU time | 90.09 seconds |
| Started | Aug 23 03:13:20 PM UTC 24 |
| Finished | Aug 23 03:14:52 PM UTC 24 |
| Peak memory | 226112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231039427 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_escalation.1231039427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/41.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.2996630222 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 1502679566 ps |
| CPU time | 31.56 seconds |
| Started | Aug 23 03:12:46 PM UTC 24 |
| Finished | Aug 23 03:13:19 PM UTC 24 |
| Peak memory | 327140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2996630222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ max_throughput.2996630222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/41.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.3882470442 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 4959213044 ps |
| CPU time | 122.51 seconds |
| Started | Aug 23 03:14:40 PM UTC 24 |
| Finished | Aug 23 03:16:44 PM UTC 24 |
| Peak memory | 221916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882470442 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_mem_partial_access.3882470442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/41.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.1431281294 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 15693657438 ps |
| CPU time | 139.84 seconds |
| Started | Aug 23 03:14:37 PM UTC 24 |
| Finished | Aug 23 03:16:59 PM UTC 24 |
| Peak memory | 222076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431281294 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_mem_walk.1431281294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/41.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.1874703512 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 7207718034 ps |
| CPU time | 381.01 seconds |
| Started | Aug 23 03:10:53 PM UTC 24 |
| Finished | Aug 23 03:17:19 PM UTC 24 |
| Peak memory | 384688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874703512 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multiple_keys.1874703512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/41.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access.3715650605 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 15499188126 ps |
| CPU time | 21.49 seconds |
| Started | Aug 23 03:11:53 PM UTC 24 |
| Finished | Aug 23 03:12:16 PM UTC 24 |
| Peak memory | 211632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715650605 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_partial_access.3715650605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/41.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.912129065 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 141444243191 ps |
| CPU time | 514.65 seconds |
| Started | Aug 23 03:12:17 PM UTC 24 |
| Finished | Aug 23 03:20:57 PM UTC 24 |
| Peak memory | 211572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912129065 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_partial_ac cess_b2b.912129065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/41.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.1706306428 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 1403356664 ps |
| CPU time | 3.22 seconds |
| Started | Aug 23 03:14:35 PM UTC 24 |
| Finished | Aug 23 03:14:39 PM UTC 24 |
| Peak memory | 211824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706306428 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.1706306428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/41.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_regwen.1853628683 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 11017645075 ps |
| CPU time | 310.63 seconds |
| Started | Aug 23 03:14:00 PM UTC 24 |
| Finished | Aug 23 03:19:15 PM UTC 24 |
| Peak memory | 372196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853628683 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.1853628683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/41.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_smoke.4118498906 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 873067021 ps |
| CPU time | 8.35 seconds |
| Started | Aug 23 03:10:43 PM UTC 24 |
| Finished | Aug 23 03:10:53 PM UTC 24 |
| Peak memory | 224592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118498906 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.4118498906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/41.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all.618648674 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 146866703209 ps |
| CPU time | 3279.63 seconds |
| Started | Aug 23 03:14:53 PM UTC 24 |
| Finished | Aug 23 04:10:02 PM UTC 24 |
| Peak memory | 394332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61864867 4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all.618648674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/41.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.96921376 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 2494221096 ps |
| CPU time | 35.26 seconds |
| Started | Aug 23 03:14:51 PM UTC 24 |
| Finished | Aug 23 03:15:27 PM UTC 24 |
| Peak memory | 222200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96921376 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.96921376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/41.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.1255443712 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 35628656662 ps |
| CPU time | 167.42 seconds |
| Started | Aug 23 03:11:46 PM UTC 24 |
| Finished | Aug 23 03:14:36 PM UTC 24 |
| Peak memory | 211652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255443712 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_pipeline.1255443712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/41.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.1621809583 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 760407929 ps |
| CPU time | 18.96 seconds |
| Started | Aug 23 03:13:06 PM UTC 24 |
| Finished | Aug 23 03:13:27 PM UTC 24 |
| Peak memory | 294500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1621809583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl _throughput_w_partial_write.1621809583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/41.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.4007097761 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 18939133111 ps |
| CPU time | 392.6 seconds |
| Started | Aug 23 03:18:19 PM UTC 24 |
| Finished | Aug 23 03:24:56 PM UTC 24 |
| Peak memory | 378416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007097761 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_access_duri ng_key_req.4007097761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/42.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_alert_test.3364006771 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 41295739 ps |
| CPU time | 0.58 seconds |
| Started | Aug 23 03:21:00 PM UTC 24 |
| Finished | Aug 23 03:21:01 PM UTC 24 |
| Peak memory | 210740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364006771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_alert_test.3364006771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/42.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_bijection.2561785171 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 311498070950 ps |
| CPU time | 893.55 seconds |
| Started | Aug 23 03:15:38 PM UTC 24 |
| Finished | Aug 23 03:30:41 PM UTC 24 |
| Peak memory | 211632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561785171 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection.2561785171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/42.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_executable.455897466 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 7841239908 ps |
| CPU time | 215.46 seconds |
| Started | Aug 23 03:19:14 PM UTC 24 |
| Finished | Aug 23 03:22:53 PM UTC 24 |
| Peak memory | 384480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455897466 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executable.455897466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/42.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.524131191 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 36011578236 ps |
| CPU time | 64.19 seconds |
| Started | Aug 23 03:18:08 PM UTC 24 |
| Finished | Aug 23 03:19:14 PM UTC 24 |
| Peak memory | 221792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524131191 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_escalation.524131191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/42.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.852628713 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 3058653249 ps |
| CPU time | 56.27 seconds |
| Started | Aug 23 03:17:20 PM UTC 24 |
| Finished | Aug 23 03:18:18 PM UTC 24 |
| Peak memory | 382500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 852628713 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_m ax_throughput.852628713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/42.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.2485650019 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 11244356871 ps |
| CPU time | 147.2 seconds |
| Started | Aug 23 03:20:24 PM UTC 24 |
| Finished | Aug 23 03:22:53 PM UTC 24 |
| Peak memory | 228972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485650019 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_mem_partial_access.2485650019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/42.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.301298018 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 57614942366 ps |
| CPU time | 297.78 seconds |
| Started | Aug 23 03:20:02 PM UTC 24 |
| Finished | Aug 23 03:25:04 PM UTC 24 |
| Peak memory | 221948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301298018 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_mem_walk.301298018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/42.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.2932357075 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 35061155773 ps |
| CPU time | 637.33 seconds |
| Started | Aug 23 03:15:28 PM UTC 24 |
| Finished | Aug 23 03:26:12 PM UTC 24 |
| Peak memory | 388640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932357075 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multiple_keys.2932357075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/42.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access.2480617450 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 4990184473 ps |
| CPU time | 15.61 seconds |
| Started | Aug 23 03:16:59 PM UTC 24 |
| Finished | Aug 23 03:17:16 PM UTC 24 |
| Peak memory | 211692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480617450 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_partial_access.2480617450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/42.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.621265271 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 31422523364 ps |
| CPU time | 299.97 seconds |
| Started | Aug 23 03:17:18 PM UTC 24 |
| Finished | Aug 23 03:22:21 PM UTC 24 |
| Peak memory | 211880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621265271 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_partial_ac cess_b2b.621265271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/42.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.3338294299 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 1163676500 ps |
| CPU time | 3.65 seconds |
| Started | Aug 23 03:19:57 PM UTC 24 |
| Finished | Aug 23 03:20:02 PM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338294299 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.3338294299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/42.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_regwen.3485052247 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 70495000497 ps |
| CPU time | 684.18 seconds |
| Started | Aug 23 03:19:15 PM UTC 24 |
| Finished | Aug 23 03:30:46 PM UTC 24 |
| Peak memory | 384544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485052247 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.3485052247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/42.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_smoke.754957979 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 4234173118 ps |
| CPU time | 26.52 seconds |
| Started | Aug 23 03:15:09 PM UTC 24 |
| Finished | Aug 23 03:15:37 PM UTC 24 |
| Peak memory | 298512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754957979 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.754957979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/42.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all.548529887 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 449387805570 ps |
| CPU time | 1032.82 seconds |
| Started | Aug 23 03:20:58 PM UTC 24 |
| Finished | Aug 23 03:38:21 PM UTC 24 |
| Peak memory | 375900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54852988 7 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all.548529887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/42.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.2634155202 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 25109299759 ps |
| CPU time | 250.54 seconds |
| Started | Aug 23 03:16:45 PM UTC 24 |
| Finished | Aug 23 03:20:59 PM UTC 24 |
| Peak memory | 211652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634155202 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_pipeline.2634155202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/42.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.95012621 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 723295955 ps |
| CPU time | 12.56 seconds |
| Started | Aug 23 03:17:54 PM UTC 24 |
| Finished | Aug 23 03:18:07 PM UTC 24 |
| Peak memory | 263580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =95012621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_t hroughput_w_partial_write.95012621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/42.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.1330349431 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 1636519808 ps |
| CPU time | 46.9 seconds |
| Started | Aug 23 03:23:57 PM UTC 24 |
| Finished | Aug 23 03:24:45 PM UTC 24 |
| Peak memory | 320932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330349431 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_access_duri ng_key_req.1330349431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/43.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_alert_test.35121261 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 37813826 ps |
| CPU time | 0.6 seconds |
| Started | Aug 23 03:25:54 PM UTC 24 |
| Finished | Aug 23 03:25:56 PM UTC 24 |
| Peak memory | 210736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35121261 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_alert_test.35121261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/43.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_bijection.550584059 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 148492564592 ps |
| CPU time | 1525.97 seconds |
| Started | Aug 23 03:21:57 PM UTC 24 |
| Finished | Aug 23 03:47:38 PM UTC 24 |
| Peak memory | 213108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550584059 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection.550584059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/43.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_executable.1008167950 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 14521484046 ps |
| CPU time | 486.26 seconds |
| Started | Aug 23 03:24:01 PM UTC 24 |
| Finished | Aug 23 03:32:12 PM UTC 24 |
| Peak memory | 388656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008167950 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executable.1008167950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/43.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.3178590543 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 6561196341 ps |
| CPU time | 16.17 seconds |
| Started | Aug 23 03:23:39 PM UTC 24 |
| Finished | Aug 23 03:23:56 PM UTC 24 |
| Peak memory | 211640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178590543 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_escalation.3178590543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/43.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.4134122295 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 1138573384 ps |
| CPU time | 18.64 seconds |
| Started | Aug 23 03:23:16 PM UTC 24 |
| Finished | Aug 23 03:23:36 PM UTC 24 |
| Peak memory | 294304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4134122295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ max_throughput.4134122295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/43.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.352242746 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 15646620742 ps |
| CPU time | 133.8 seconds |
| Started | Aug 23 03:25:05 PM UTC 24 |
| Finished | Aug 23 03:27:22 PM UTC 24 |
| Peak memory | 221880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352242746 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_mem_partial_access.352242746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/43.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.3000124863 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 258782661161 ps |
| CPU time | 325.64 seconds |
| Started | Aug 23 03:25:03 PM UTC 24 |
| Finished | Aug 23 03:30:33 PM UTC 24 |
| Peak memory | 221940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000124863 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_mem_walk.3000124863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/43.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.3525575789 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 3708555776 ps |
| CPU time | 133.78 seconds |
| Started | Aug 23 03:21:21 PM UTC 24 |
| Finished | Aug 23 03:23:37 PM UTC 24 |
| Peak memory | 384468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525575789 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multiple_keys.3525575789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/43.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access.376681350 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 6360499412 ps |
| CPU time | 21.6 seconds |
| Started | Aug 23 03:22:53 PM UTC 24 |
| Finished | Aug 23 03:23:16 PM UTC 24 |
| Peak memory | 211556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376681350 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_partial_access.376681350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/43.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.3382946215 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 32835330857 ps |
| CPU time | 409.91 seconds |
| Started | Aug 23 03:22:54 PM UTC 24 |
| Finished | Aug 23 03:29:49 PM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382946215 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_partial_a ccess_b2b.3382946215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/43.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.2618392342 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 3734043535 ps |
| CPU time | 3.77 seconds |
| Started | Aug 23 03:24:57 PM UTC 24 |
| Finished | Aug 23 03:25:02 PM UTC 24 |
| Peak memory | 211888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618392342 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.2618392342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/43.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_regwen.967575934 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 3820745216 ps |
| CPU time | 385.42 seconds |
| Started | Aug 23 03:24:46 PM UTC 24 |
| Finished | Aug 23 03:31:16 PM UTC 24 |
| Peak memory | 386516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967575934 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.967575934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/43.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_smoke.554821945 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 5388097521 ps |
| CPU time | 17.01 seconds |
| Started | Aug 23 03:21:02 PM UTC 24 |
| Finished | Aug 23 03:21:20 PM UTC 24 |
| Peak memory | 211692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554821945 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.554821945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/43.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all.1131797550 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 18308359295 ps |
| CPU time | 1302.75 seconds |
| Started | Aug 23 03:25:53 PM UTC 24 |
| Finished | Aug 23 03:47:48 PM UTC 24 |
| Peak memory | 390248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11317975 50 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_a ll.1131797550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/43.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3749429518 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 1825424477 ps |
| CPU time | 9.18 seconds |
| Started | Aug 23 03:25:48 PM UTC 24 |
| Finished | Aug 23 03:25:59 PM UTC 24 |
| Peak memory | 222072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749429518 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.3749429518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/43.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.2107844677 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 5198578013 ps |
| CPU time | 270.64 seconds |
| Started | Aug 23 03:22:22 PM UTC 24 |
| Finished | Aug 23 03:26:56 PM UTC 24 |
| Peak memory | 211760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107844677 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_pipeline.2107844677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/43.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.1019286027 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 2904019267 ps |
| CPU time | 20.85 seconds |
| Started | Aug 23 03:23:37 PM UTC 24 |
| Finished | Aug 23 03:24:00 PM UTC 24 |
| Peak memory | 296408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1019286027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl _throughput_w_partial_write.1019286027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/43.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.358436378 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 13555574359 ps |
| CPU time | 575.75 seconds |
| Started | Aug 23 03:28:01 PM UTC 24 |
| Finished | Aug 23 03:37:43 PM UTC 24 |
| Peak memory | 384736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358436378 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_access_durin g_key_req.358436378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/44.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_alert_test.1140038737 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 47941952 ps |
| CPU time | 0.58 seconds |
| Started | Aug 23 03:30:42 PM UTC 24 |
| Finished | Aug 23 03:30:44 PM UTC 24 |
| Peak memory | 210936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140038737 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_alert_test.1140038737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/44.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_bijection.2756245834 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 341867343218 ps |
| CPU time | 1552.79 seconds |
| Started | Aug 23 03:26:14 PM UTC 24 |
| Finished | Aug 23 03:52:22 PM UTC 24 |
| Peak memory | 213236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756245834 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection.2756245834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/44.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_executable.1107973520 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 3683516009 ps |
| CPU time | 134.64 seconds |
| Started | Aug 23 03:29:01 PM UTC 24 |
| Finished | Aug 23 03:31:17 PM UTC 24 |
| Peak memory | 353764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107973520 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executable.1107973520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/44.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.2248530962 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 12951377472 ps |
| CPU time | 71.39 seconds |
| Started | Aug 23 03:28:01 PM UTC 24 |
| Finished | Aug 23 03:29:14 PM UTC 24 |
| Peak memory | 221948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248530962 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_escalation.2248530962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/44.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.986176123 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 2680193337 ps |
| CPU time | 6.7 seconds |
| Started | Aug 23 03:27:23 PM UTC 24 |
| Finished | Aug 23 03:27:31 PM UTC 24 |
| Peak memory | 221860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 986176123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_m ax_throughput.986176123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/44.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.1918332429 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 10752613987 ps |
| CPU time | 68.22 seconds |
| Started | Aug 23 03:29:50 PM UTC 24 |
| Finished | Aug 23 03:31:00 PM UTC 24 |
| Peak memory | 221808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918332429 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_mem_partial_access.1918332429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/44.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.1093948825 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 60136084524 ps |
| CPU time | 273.29 seconds |
| Started | Aug 23 03:29:41 PM UTC 24 |
| Finished | Aug 23 03:34:18 PM UTC 24 |
| Peak memory | 221860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093948825 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_mem_walk.1093948825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/44.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.1930199732 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 43431357542 ps |
| CPU time | 212.84 seconds |
| Started | Aug 23 03:25:59 PM UTC 24 |
| Finished | Aug 23 03:29:35 PM UTC 24 |
| Peak memory | 341464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930199732 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multiple_keys.1930199732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/44.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access.2247073778 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 6836759664 ps |
| CPU time | 60.82 seconds |
| Started | Aug 23 03:26:58 PM UTC 24 |
| Finished | Aug 23 03:28:01 PM UTC 24 |
| Peak memory | 370336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247073778 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_partial_access.2247073778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/44.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.669355529 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 22647249024 ps |
| CPU time | 249.46 seconds |
| Started | Aug 23 03:26:59 PM UTC 24 |
| Finished | Aug 23 03:31:12 PM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669355529 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_partial_ac cess_b2b.669355529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/44.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.4250955483 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 6714724551 ps |
| CPU time | 3.61 seconds |
| Started | Aug 23 03:29:36 PM UTC 24 |
| Finished | Aug 23 03:29:40 PM UTC 24 |
| Peak memory | 211756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250955483 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.4250955483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/44.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_regwen.3149922066 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 11473093150 ps |
| CPU time | 361.93 seconds |
| Started | Aug 23 03:29:15 PM UTC 24 |
| Finished | Aug 23 03:35:21 PM UTC 24 |
| Peak memory | 382428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149922066 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.3149922066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/44.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_smoke.2217829343 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 940884966 ps |
| CPU time | 15.36 seconds |
| Started | Aug 23 03:25:56 PM UTC 24 |
| Finished | Aug 23 03:26:13 PM UTC 24 |
| Peak memory | 211484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217829343 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.2217829343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/44.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all.2257502352 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 86681472293 ps |
| CPU time | 1347.08 seconds |
| Started | Aug 23 03:30:34 PM UTC 24 |
| Finished | Aug 23 03:53:14 PM UTC 24 |
| Peak memory | 400496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22575023 52 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_a ll.2257502352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/44.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.716591144 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 4316927971 ps |
| CPU time | 67.6 seconds |
| Started | Aug 23 03:30:03 PM UTC 24 |
| Finished | Aug 23 03:31:12 PM UTC 24 |
| Peak memory | 386968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716591144 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.716591144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/44.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.1270642347 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 11794002048 ps |
| CPU time | 163.26 seconds |
| Started | Aug 23 03:26:14 PM UTC 24 |
| Finished | Aug 23 03:28:59 PM UTC 24 |
| Peak memory | 211664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270642347 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_pipeline.1270642347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/44.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.2524927477 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 3140236122 ps |
| CPU time | 27.15 seconds |
| Started | Aug 23 03:27:32 PM UTC 24 |
| Finished | Aug 23 03:28:01 PM UTC 24 |
| Peak memory | 327204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2524927477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl _throughput_w_partial_write.2524927477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/44.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.1725812168 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 32007248353 ps |
| CPU time | 391.12 seconds |
| Started | Aug 23 03:31:24 PM UTC 24 |
| Finished | Aug 23 03:37:59 PM UTC 24 |
| Peak memory | 382428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725812168 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_access_duri ng_key_req.1725812168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/45.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_alert_test.2495965681 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 23036509 ps |
| CPU time | 0.55 seconds |
| Started | Aug 23 03:34:00 PM UTC 24 |
| Finished | Aug 23 03:34:01 PM UTC 24 |
| Peak memory | 210816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495965681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_alert_test.2495965681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/45.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_bijection.2260113331 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 72409068621 ps |
| CPU time | 1061.92 seconds |
| Started | Aug 23 03:31:00 PM UTC 24 |
| Finished | Aug 23 03:48:53 PM UTC 24 |
| Peak memory | 213056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260113331 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection.2260113331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/45.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_executable.3346332326 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 18632089725 ps |
| CPU time | 529.84 seconds |
| Started | Aug 23 03:31:26 PM UTC 24 |
| Finished | Aug 23 03:40:21 PM UTC 24 |
| Peak memory | 384480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346332326 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executable.3346332326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/45.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.3137906021 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 25853030760 ps |
| CPU time | 44.43 seconds |
| Started | Aug 23 03:31:19 PM UTC 24 |
| Finished | Aug 23 03:32:04 PM UTC 24 |
| Peak memory | 211576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137906021 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_escalation.3137906021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/45.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.3768018335 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 2794265532 ps |
| CPU time | 7.57 seconds |
| Started | Aug 23 03:31:13 PM UTC 24 |
| Finished | Aug 23 03:31:22 PM UTC 24 |
| Peak memory | 228008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3768018335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ max_throughput.3768018335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/45.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.4072405745 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 5063391309 ps |
| CPU time | 139.39 seconds |
| Started | Aug 23 03:32:13 PM UTC 24 |
| Finished | Aug 23 03:34:35 PM UTC 24 |
| Peak memory | 221996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072405745 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_mem_partial_access.4072405745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/45.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.1025515899 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 3953669296 ps |
| CPU time | 106.79 seconds |
| Started | Aug 23 03:32:10 PM UTC 24 |
| Finished | Aug 23 03:33:59 PM UTC 24 |
| Peak memory | 221836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025515899 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_mem_walk.1025515899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/45.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.5554838 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 18672842685 ps |
| CPU time | 152.61 seconds |
| Started | Aug 23 03:30:47 PM UTC 24 |
| Finished | Aug 23 03:33:23 PM UTC 24 |
| Peak memory | 273852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5554838 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multiple_keys.5554838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/45.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.1687235333 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 4317818667 ps |
| CPU time | 209.38 seconds |
| Started | Aug 23 03:31:12 PM UTC 24 |
| Finished | Aug 23 03:34:45 PM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687235333 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_partial_a ccess_b2b.1687235333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/45.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.3815755252 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 356646094 ps |
| CPU time | 3.13 seconds |
| Started | Aug 23 03:32:05 PM UTC 24 |
| Finished | Aug 23 03:32:09 PM UTC 24 |
| Peak memory | 211696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815755252 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.3815755252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/45.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_regwen.780620358 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 20418354505 ps |
| CPU time | 836.4 seconds |
| Started | Aug 23 03:31:41 PM UTC 24 |
| Finished | Aug 23 03:45:46 PM UTC 24 |
| Peak memory | 386016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780620358 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.780620358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/45.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_smoke.3981982903 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 11718652490 ps |
| CPU time | 12.5 seconds |
| Started | Aug 23 03:30:45 PM UTC 24 |
| Finished | Aug 23 03:30:59 PM UTC 24 |
| Peak memory | 247332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981982903 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.3981982903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/45.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all.1604859650 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 52088565143 ps |
| CPU time | 3244.04 seconds |
| Started | Aug 23 03:33:52 PM UTC 24 |
| Finished | Aug 23 04:28:27 PM UTC 24 |
| Peak memory | 388452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16048596 50 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_a ll.1604859650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/45.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2623872359 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1179311636 ps |
| CPU time | 27.08 seconds |
| Started | Aug 23 03:33:23 PM UTC 24 |
| Finished | Aug 23 03:33:52 PM UTC 24 |
| Peak memory | 236144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623872359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.2623872359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/45.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.3956751088 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 12397928837 ps |
| CPU time | 197.39 seconds |
| Started | Aug 23 03:31:00 PM UTC 24 |
| Finished | Aug 23 03:34:21 PM UTC 24 |
| Peak memory | 211652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956751088 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_pipeline.3956751088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/45.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.2526368052 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 2693459497 ps |
| CPU time | 7.1 seconds |
| Started | Aug 23 03:31:17 PM UTC 24 |
| Finished | Aug 23 03:31:25 PM UTC 24 |
| Peak memory | 221992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2526368052 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl _throughput_w_partial_write.2526368052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/45.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.1849329098 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 31270734967 ps |
| CPU time | 792.81 seconds |
| Started | Aug 23 03:35:27 PM UTC 24 |
| Finished | Aug 23 03:48:48 PM UTC 24 |
| Peak memory | 386712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849329098 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_access_duri ng_key_req.1849329098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/46.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_alert_test.1037584278 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 49367269 ps |
| CPU time | 0.58 seconds |
| Started | Aug 23 03:37:28 PM UTC 24 |
| Finished | Aug 23 03:37:30 PM UTC 24 |
| Peak memory | 210816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037584278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_alert_test.1037584278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/46.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_bijection.3790175829 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 460596191788 ps |
| CPU time | 1978.34 seconds |
| Started | Aug 23 03:34:19 PM UTC 24 |
| Finished | Aug 23 04:07:38 PM UTC 24 |
| Peak memory | 213172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790175829 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection.3790175829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/46.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_executable.1049736282 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 6284998533 ps |
| CPU time | 282.53 seconds |
| Started | Aug 23 03:35:38 PM UTC 24 |
| Finished | Aug 23 03:40:24 PM UTC 24 |
| Peak memory | 362160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049736282 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executable.1049736282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/46.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.1939882530 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 13376646181 ps |
| CPU time | 77.85 seconds |
| Started | Aug 23 03:35:22 PM UTC 24 |
| Finished | Aug 23 03:36:42 PM UTC 24 |
| Peak memory | 225984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939882530 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_escalation.1939882530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/46.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.2698047092 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 792204870 ps |
| CPU time | 46.06 seconds |
| Started | Aug 23 03:34:50 PM UTC 24 |
| Finished | Aug 23 03:35:37 PM UTC 24 |
| Peak memory | 353708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2698047092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ max_throughput.2698047092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/46.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.3976087703 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 2482167330 ps |
| CPU time | 125.36 seconds |
| Started | Aug 23 03:36:43 PM UTC 24 |
| Finished | Aug 23 03:38:50 PM UTC 24 |
| Peak memory | 228868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976087703 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_mem_partial_access.3976087703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/46.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.2916261934 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 5718559517 ps |
| CPU time | 125.57 seconds |
| Started | Aug 23 03:36:31 PM UTC 24 |
| Finished | Aug 23 03:38:39 PM UTC 24 |
| Peak memory | 222024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916261934 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_mem_walk.2916261934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/46.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.3284468813 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 8338926082 ps |
| CPU time | 108.32 seconds |
| Started | Aug 23 03:34:07 PM UTC 24 |
| Finished | Aug 23 03:35:57 PM UTC 24 |
| Peak memory | 366116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284468813 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multiple_keys.3284468813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/46.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access.273352711 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 3705804972 ps |
| CPU time | 11.31 seconds |
| Started | Aug 23 03:34:36 PM UTC 24 |
| Finished | Aug 23 03:34:49 PM UTC 24 |
| Peak memory | 211620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273352711 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_partial_access.273352711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/46.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.3881207856 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 36743584501 ps |
| CPU time | 369.77 seconds |
| Started | Aug 23 03:34:46 PM UTC 24 |
| Finished | Aug 23 03:41:00 PM UTC 24 |
| Peak memory | 211552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881207856 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_partial_a ccess_b2b.3881207856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/46.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.2620661203 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 1407780766 ps |
| CPU time | 3.59 seconds |
| Started | Aug 23 03:36:24 PM UTC 24 |
| Finished | Aug 23 03:36:29 PM UTC 24 |
| Peak memory | 211624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620661203 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.2620661203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/46.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_regwen.286928973 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 1743697339 ps |
| CPU time | 94.29 seconds |
| Started | Aug 23 03:35:58 PM UTC 24 |
| Finished | Aug 23 03:37:35 PM UTC 24 |
| Peak memory | 380300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286928973 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.286928973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/46.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_smoke.2958063002 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 390307544 ps |
| CPU time | 3.37 seconds |
| Started | Aug 23 03:34:02 PM UTC 24 |
| Finished | Aug 23 03:34:06 PM UTC 24 |
| Peak memory | 211240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958063002 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.2958063002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/46.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all.569511339 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 42300423269 ps |
| CPU time | 2487.24 seconds |
| Started | Aug 23 03:36:57 PM UTC 24 |
| Finished | Aug 23 04:18:48 PM UTC 24 |
| Peak memory | 390324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56951133 9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all.569511339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/46.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.352915006 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 3530994676 ps |
| CPU time | 39.12 seconds |
| Started | Aug 23 03:36:47 PM UTC 24 |
| Finished | Aug 23 03:37:27 PM UTC 24 |
| Peak memory | 228988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352915006 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.352915006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/46.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.2805633045 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 20512654310 ps |
| CPU time | 222.02 seconds |
| Started | Aug 23 03:34:22 PM UTC 24 |
| Finished | Aug 23 03:38:07 PM UTC 24 |
| Peak memory | 211556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805633045 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_pipeline.2805633045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/46.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.603824158 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 1499062124 ps |
| CPU time | 31.13 seconds |
| Started | Aug 23 03:34:54 PM UTC 24 |
| Finished | Aug 23 03:35:26 PM UTC 24 |
| Peak memory | 329184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =603824158 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ throughput_w_partial_write.603824158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/46.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.280043274 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 15722213789 ps |
| CPU time | 459.37 seconds |
| Started | Aug 23 03:38:35 PM UTC 24 |
| Finished | Aug 23 03:46:19 PM UTC 24 |
| Peak memory | 382512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280043274 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_access_durin g_key_req.280043274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/47.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_alert_test.3277445605 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 10499028 ps |
| CPU time | 0.55 seconds |
| Started | Aug 23 03:41:00 PM UTC 24 |
| Finished | Aug 23 03:41:02 PM UTC 24 |
| Peak memory | 210740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277445605 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_alert_test.3277445605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/47.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_bijection.382128627 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 80300562768 ps |
| CPU time | 1115.3 seconds |
| Started | Aug 23 03:37:40 PM UTC 24 |
| Finished | Aug 23 03:56:27 PM UTC 24 |
| Peak memory | 213252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382128627 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection.382128627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/47.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_executable.2820663676 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 20776108676 ps |
| CPU time | 217.13 seconds |
| Started | Aug 23 03:38:40 PM UTC 24 |
| Finished | Aug 23 03:42:20 PM UTC 24 |
| Peak memory | 386604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820663676 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executable.2820663676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/47.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.2759454016 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 10679326624 ps |
| CPU time | 36.48 seconds |
| Started | Aug 23 03:38:25 PM UTC 24 |
| Finished | Aug 23 03:39:03 PM UTC 24 |
| Peak memory | 221880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759454016 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_escalation.2759454016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/47.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.210870320 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 1404909219 ps |
| CPU time | 14.47 seconds |
| Started | Aug 23 03:38:08 PM UTC 24 |
| Finished | Aug 23 03:38:24 PM UTC 24 |
| Peak memory | 267744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 210870320 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_m ax_throughput.210870320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/47.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.1843180137 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 17573697577 ps |
| CPU time | 135.17 seconds |
| Started | Aug 23 03:39:09 PM UTC 24 |
| Finished | Aug 23 03:41:26 PM UTC 24 |
| Peak memory | 228888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843180137 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_mem_partial_access.1843180137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/47.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.301973885 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 10530537147 ps |
| CPU time | 132.34 seconds |
| Started | Aug 23 03:39:09 PM UTC 24 |
| Finished | Aug 23 03:41:24 PM UTC 24 |
| Peak memory | 221860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301973885 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_mem_walk.301973885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/47.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_multiple_keys.2400900779 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 10558295954 ps |
| CPU time | 210.86 seconds |
| Started | Aug 23 03:37:35 PM UTC 24 |
| Finished | Aug 23 03:41:09 PM UTC 24 |
| Peak memory | 370120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400900779 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multiple_keys.2400900779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/47.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access.119552854 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 1209852686 ps |
| CPU time | 32.42 seconds |
| Started | Aug 23 03:38:00 PM UTC 24 |
| Finished | Aug 23 03:38:34 PM UTC 24 |
| Peak memory | 329088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119552854 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_partial_access.119552854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/47.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.310656774 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 15109023778 ps |
| CPU time | 333.29 seconds |
| Started | Aug 23 03:38:01 PM UTC 24 |
| Finished | Aug 23 03:43:39 PM UTC 24 |
| Peak memory | 211568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310656774 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_partial_ac cess_b2b.310656774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/47.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.401919708 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 1412498695 ps |
| CPU time | 3.03 seconds |
| Started | Aug 23 03:39:04 PM UTC 24 |
| Finished | Aug 23 03:39:08 PM UTC 24 |
| Peak memory | 211704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401919708 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.401919708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/47.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_regwen.215748679 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 4372731455 ps |
| CPU time | 678.51 seconds |
| Started | Aug 23 03:38:51 PM UTC 24 |
| Finished | Aug 23 03:50:16 PM UTC 24 |
| Peak memory | 390880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215748679 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.215748679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/47.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_smoke.1504089339 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 782720663 ps |
| CPU time | 29.47 seconds |
| Started | Aug 23 03:37:30 PM UTC 24 |
| Finished | Aug 23 03:38:01 PM UTC 24 |
| Peak memory | 331180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504089339 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.1504089339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/47.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all.3324321050 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 121027031640 ps |
| CPU time | 2343.55 seconds |
| Started | Aug 23 03:40:25 PM UTC 24 |
| Finished | Aug 23 04:19:51 PM UTC 24 |
| Peak memory | 392228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33243210 50 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_a ll.3324321050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/47.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3122670281 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 9409250051 ps |
| CPU time | 82.77 seconds |
| Started | Aug 23 03:40:22 PM UTC 24 |
| Finished | Aug 23 03:41:47 PM UTC 24 |
| Peak memory | 364332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122670281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.3122670281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/47.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.2533084726 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 4214150887 ps |
| CPU time | 244.2 seconds |
| Started | Aug 23 03:37:44 PM UTC 24 |
| Finished | Aug 23 03:41:52 PM UTC 24 |
| Peak memory | 211632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533084726 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_pipeline.2533084726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/47.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.2729081965 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 798873514 ps |
| CPU time | 45.29 seconds |
| Started | Aug 23 03:38:21 PM UTC 24 |
| Finished | Aug 23 03:39:08 PM UTC 24 |
| Peak memory | 368016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2729081965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl _throughput_w_partial_write.2729081965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/47.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.3329014529 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 14300684047 ps |
| CPU time | 251.73 seconds |
| Started | Aug 23 03:42:20 PM UTC 24 |
| Finished | Aug 23 03:46:35 PM UTC 24 |
| Peak memory | 388568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329014529 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_access_duri ng_key_req.3329014529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/48.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_alert_test.4037841624 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 23801532 ps |
| CPU time | 0.55 seconds |
| Started | Aug 23 03:45:54 PM UTC 24 |
| Finished | Aug 23 03:45:56 PM UTC 24 |
| Peak memory | 210876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037841624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_alert_test.4037841624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/48.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_bijection.3337685652 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 137814884470 ps |
| CPU time | 414.34 seconds |
| Started | Aug 23 03:41:25 PM UTC 24 |
| Finished | Aug 23 03:48:24 PM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337685652 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection.3337685652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/48.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_executable.4288921066 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 18452478171 ps |
| CPU time | 390.43 seconds |
| Started | Aug 23 03:42:36 PM UTC 24 |
| Finished | Aug 23 03:49:11 PM UTC 24 |
| Peak memory | 355816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288921066 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executable.4288921066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/48.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.2135967747 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 7302464561 ps |
| CPU time | 25.77 seconds |
| Started | Aug 23 03:42:09 PM UTC 24 |
| Finished | Aug 23 03:42:36 PM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135967747 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_escalation.2135967747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/48.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.900270705 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 2966297015 ps |
| CPU time | 15.15 seconds |
| Started | Aug 23 03:41:52 PM UTC 24 |
| Finished | Aug 23 03:42:08 PM UTC 24 |
| Peak memory | 280100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 900270705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_m ax_throughput.900270705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/48.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.4179985511 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 1579740492 ps |
| CPU time | 106.73 seconds |
| Started | Aug 23 03:44:05 PM UTC 24 |
| Finished | Aug 23 03:45:53 PM UTC 24 |
| Peak memory | 221740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179985511 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_mem_partial_access.4179985511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/48.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.1037014007 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 64656449629 ps |
| CPU time | 323.1 seconds |
| Started | Aug 23 03:43:45 PM UTC 24 |
| Finished | Aug 23 03:49:12 PM UTC 24 |
| Peak memory | 222076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037014007 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_mem_walk.1037014007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/48.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.3839278128 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 25370242764 ps |
| CPU time | 888.42 seconds |
| Started | Aug 23 03:41:10 PM UTC 24 |
| Finished | Aug 23 03:56:07 PM UTC 24 |
| Peak memory | 390484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839278128 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multiple_keys.3839278128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/48.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access.2412775329 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 1886377136 ps |
| CPU time | 18.53 seconds |
| Started | Aug 23 03:41:48 PM UTC 24 |
| Finished | Aug 23 03:42:08 PM UTC 24 |
| Peak memory | 211716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412775329 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_partial_access.2412775329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/48.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.2006655751 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 46988210619 ps |
| CPU time | 555.12 seconds |
| Started | Aug 23 03:41:51 PM UTC 24 |
| Finished | Aug 23 03:51:13 PM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006655751 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_partial_a ccess_b2b.2006655751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/48.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.1487651062 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 352709894 ps |
| CPU time | 3.15 seconds |
| Started | Aug 23 03:43:40 PM UTC 24 |
| Finished | Aug 23 03:43:44 PM UTC 24 |
| Peak memory | 211692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487651062 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.1487651062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/48.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_regwen.697698719 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 2670614909 ps |
| CPU time | 85.01 seconds |
| Started | Aug 23 03:42:37 PM UTC 24 |
| Finished | Aug 23 03:44:04 PM UTC 24 |
| Peak memory | 362136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697698719 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.697698719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/48.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_smoke.3911992046 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 923332416 ps |
| CPU time | 45.7 seconds |
| Started | Aug 23 03:41:02 PM UTC 24 |
| Finished | Aug 23 03:41:50 PM UTC 24 |
| Peak memory | 361876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911992046 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.3911992046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/48.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all.2257280885 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 143341203064 ps |
| CPU time | 3051.87 seconds |
| Started | Aug 23 03:45:46 PM UTC 24 |
| Finished | Aug 23 04:37:07 PM UTC 24 |
| Peak memory | 377960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22572808 85 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_a ll.2257280885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/48.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1794348239 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 17491835063 ps |
| CPU time | 36.3 seconds |
| Started | Aug 23 03:45:29 PM UTC 24 |
| Finished | Aug 23 03:46:07 PM UTC 24 |
| Peak memory | 222128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794348239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.1794348239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/48.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.1047857682 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 6382937993 ps |
| CPU time | 327.35 seconds |
| Started | Aug 23 03:41:28 PM UTC 24 |
| Finished | Aug 23 03:46:59 PM UTC 24 |
| Peak memory | 211644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047857682 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_pipeline.1047857682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/48.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.3572848521 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 779629517 ps |
| CPU time | 25.28 seconds |
| Started | Aug 23 03:42:09 PM UTC 24 |
| Finished | Aug 23 03:42:36 PM UTC 24 |
| Peak memory | 312728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3572848521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl _throughput_w_partial_write.3572848521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/48.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.3401689624 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 3571512451 ps |
| CPU time | 141.75 seconds |
| Started | Aug 23 03:47:18 PM UTC 24 |
| Finished | Aug 23 03:49:42 PM UTC 24 |
| Peak memory | 386536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401689624 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_access_duri ng_key_req.3401689624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/49.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_alert_test.2748657225 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 158990897 ps |
| CPU time | 0.59 seconds |
| Started | Aug 23 03:48:53 PM UTC 24 |
| Finished | Aug 23 03:48:55 PM UTC 24 |
| Peak memory | 210936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748657225 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_alert_test.2748657225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/49.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_bijection.2074281141 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 99098585774 ps |
| CPU time | 685.7 seconds |
| Started | Aug 23 03:46:07 PM UTC 24 |
| Finished | Aug 23 03:57:41 PM UTC 24 |
| Peak memory | 213172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074281141 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection.2074281141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/49.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_executable.659686821 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 37743122757 ps |
| CPU time | 613.35 seconds |
| Started | Aug 23 03:47:39 PM UTC 24 |
| Finished | Aug 23 03:57:59 PM UTC 24 |
| Peak memory | 384636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659686821 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executable.659686821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/49.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.3221438317 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 21180259479 ps |
| CPU time | 37.7 seconds |
| Started | Aug 23 03:47:14 PM UTC 24 |
| Finished | Aug 23 03:47:53 PM UTC 24 |
| Peak memory | 221868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221438317 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_escalation.3221438317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/49.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.3572230458 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 1432699082 ps |
| CPU time | 13.46 seconds |
| Started | Aug 23 03:46:59 PM UTC 24 |
| Finished | Aug 23 03:47:13 PM UTC 24 |
| Peak memory | 267748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3572230458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ max_throughput.3572230458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/49.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.2837934770 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 5565287458 ps |
| CPU time | 66.73 seconds |
| Started | Aug 23 03:47:54 PM UTC 24 |
| Finished | Aug 23 03:49:03 PM UTC 24 |
| Peak memory | 229064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837934770 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_mem_partial_access.2837934770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/49.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.1507602607 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 2993466841 ps |
| CPU time | 124.25 seconds |
| Started | Aug 23 03:47:54 PM UTC 24 |
| Finished | Aug 23 03:50:01 PM UTC 24 |
| Peak memory | 211816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507602607 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_mem_walk.1507602607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/49.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.302393712 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 16509579565 ps |
| CPU time | 568.76 seconds |
| Started | Aug 23 03:46:07 PM UTC 24 |
| Finished | Aug 23 03:55:42 PM UTC 24 |
| Peak memory | 386516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302393712 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multiple_keys.302393712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/49.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access.3566187558 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 1420971081 ps |
| CPU time | 5.09 seconds |
| Started | Aug 23 03:46:35 PM UTC 24 |
| Finished | Aug 23 03:46:42 PM UTC 24 |
| Peak memory | 220636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566187558 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_partial_access.3566187558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/49.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.4094748846 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 4642885815 ps |
| CPU time | 264.49 seconds |
| Started | Aug 23 03:46:43 PM UTC 24 |
| Finished | Aug 23 03:51:11 PM UTC 24 |
| Peak memory | 211752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094748846 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_partial_a ccess_b2b.4094748846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/49.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.1449755334 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 1397819058 ps |
| CPU time | 3.54 seconds |
| Started | Aug 23 03:47:49 PM UTC 24 |
| Finished | Aug 23 03:47:54 PM UTC 24 |
| Peak memory | 211692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449755334 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.1449755334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/49.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_regwen.370446376 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 1597676004 ps |
| CPU time | 134.15 seconds |
| Started | Aug 23 03:47:41 PM UTC 24 |
| Finished | Aug 23 03:49:57 PM UTC 24 |
| Peak memory | 378272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370446376 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.370446376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/49.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_smoke.3084128320 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 803863596 ps |
| CPU time | 8.95 seconds |
| Started | Aug 23 03:45:56 PM UTC 24 |
| Finished | Aug 23 03:46:06 PM UTC 24 |
| Peak memory | 231004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084128320 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.3084128320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/49.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all.959121801 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 101504104159 ps |
| CPU time | 877.72 seconds |
| Started | Aug 23 03:48:48 PM UTC 24 |
| Finished | Aug 23 04:03:35 PM UTC 24 |
| Peak memory | 390248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95912180 1 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all.959121801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/49.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.4210790722 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 3198515508 ps |
| CPU time | 40.49 seconds |
| Started | Aug 23 03:48:25 PM UTC 24 |
| Finished | Aug 23 03:49:07 PM UTC 24 |
| Peak memory | 236472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210790722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.4210790722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/49.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.2842979186 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 19891940594 ps |
| CPU time | 296.34 seconds |
| Started | Aug 23 03:46:19 PM UTC 24 |
| Finished | Aug 23 03:51:20 PM UTC 24 |
| Peak memory | 211576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842979186 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_pipeline.2842979186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/49.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.3645276734 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 1481967185 ps |
| CPU time | 15.81 seconds |
| Started | Aug 23 03:47:00 PM UTC 24 |
| Finished | Aug 23 03:47:17 PM UTC 24 |
| Peak memory | 277980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3645276734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl _throughput_w_partial_write.3645276734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/49.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.2641421107 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 8050850874 ps |
| CPU time | 209.85 seconds |
| Started | Aug 23 01:00:55 PM UTC 24 |
| Finished | Aug 23 01:04:28 PM UTC 24 |
| Peak memory | 359992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641421107 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_access_durin g_key_req.2641421107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/5.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_alert_test.836037177 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 43151123 ps |
| CPU time | 0.54 seconds |
| Started | Aug 23 01:01:51 PM UTC 24 |
| Finished | Aug 23 01:01:52 PM UTC 24 |
| Peak memory | 210816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836037177 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_alert_test.836037177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/5.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_bijection.1061792478 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 150995357998 ps |
| CPU time | 2183.02 seconds |
| Started | Aug 23 12:59:37 PM UTC 24 |
| Finished | Aug 23 01:36:21 PM UTC 24 |
| Peak memory | 213168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061792478 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.1061792478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/5.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_executable.1009873968 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 39035256274 ps |
| CPU time | 72.27 seconds |
| Started | Aug 23 01:00:56 PM UTC 24 |
| Finished | Aug 23 01:02:10 PM UTC 24 |
| Peak memory | 320992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009873968 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executable.1009873968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/5.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.1656436305 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 12509163271 ps |
| CPU time | 70.81 seconds |
| Started | Aug 23 01:00:16 PM UTC 24 |
| Finished | Aug 23 01:01:28 PM UTC 24 |
| Peak memory | 211564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656436305 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_escalation.1656436305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/5.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.1060530686 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 3150750557 ps |
| CPU time | 11.89 seconds |
| Started | Aug 23 12:59:57 PM UTC 24 |
| Finished | Aug 23 01:00:10 PM UTC 24 |
| Peak memory | 261684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1060530686 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_m ax_throughput.1060530686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/5.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.1445251310 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 13981617512 ps |
| CPU time | 142.26 seconds |
| Started | Aug 23 01:01:31 PM UTC 24 |
| Finished | Aug 23 01:03:56 PM UTC 24 |
| Peak memory | 228800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445251310 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_mem_partial_access.1445251310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/5.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.3701888145 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 3100979455 ps |
| CPU time | 194.86 seconds |
| Started | Aug 23 12:59:17 PM UTC 24 |
| Finished | Aug 23 01:02:34 PM UTC 24 |
| Peak memory | 358044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701888145 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multiple_keys.3701888145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/5.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access.1790611219 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 4533874331 ps |
| CPU time | 17.3 seconds |
| Started | Aug 23 12:59:57 PM UTC 24 |
| Finished | Aug 23 01:00:15 PM UTC 24 |
| Peak memory | 211872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790611219 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_partial_access.1790611219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/5.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.2320400491 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 6953130117 ps |
| CPU time | 336.97 seconds |
| Started | Aug 23 12:59:57 PM UTC 24 |
| Finished | Aug 23 01:05:38 PM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320400491 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_partial_ac cess_b2b.2320400491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/5.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.4095263162 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 709621008 ps |
| CPU time | 3.22 seconds |
| Started | Aug 23 01:01:26 PM UTC 24 |
| Finished | Aug 23 01:01:30 PM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095263162 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.4095263162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/5.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_regwen.3928609994 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 35003639804 ps |
| CPU time | 666.08 seconds |
| Started | Aug 23 01:01:01 PM UTC 24 |
| Finished | Aug 23 01:12:15 PM UTC 24 |
| Peak memory | 386704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928609994 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.3928609994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/5.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_smoke.514680568 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 9205622040 ps |
| CPU time | 18.89 seconds |
| Started | Aug 23 12:59:16 PM UTC 24 |
| Finished | Aug 23 12:59:36 PM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514680568 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.514680568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/5.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3272259886 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 1575885567 ps |
| CPU time | 4.06 seconds |
| Started | Aug 23 01:01:43 PM UTC 24 |
| Finished | Aug 23 01:01:48 PM UTC 24 |
| Peak memory | 222064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272259886 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.3272259886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/5.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.2713428604 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 20143179592 ps |
| CPU time | 123.39 seconds |
| Started | Aug 23 12:59:50 PM UTC 24 |
| Finished | Aug 23 01:01:55 PM UTC 24 |
| Peak memory | 211628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713428604 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_pipeline.2713428604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/5.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.1484497649 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 830415194 ps |
| CPU time | 47.84 seconds |
| Started | Aug 23 01:00:11 PM UTC 24 |
| Finished | Aug 23 01:01:00 PM UTC 24 |
| Peak memory | 361892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1484497649 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ throughput_w_partial_write.1484497649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/5.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.2768406601 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 23222118905 ps |
| CPU time | 477.62 seconds |
| Started | Aug 23 01:02:47 PM UTC 24 |
| Finished | Aug 23 01:10:50 PM UTC 24 |
| Peak memory | 380380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768406601 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_access_durin g_key_req.2768406601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/6.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_alert_test.3054870169 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 77992746 ps |
| CPU time | 0.56 seconds |
| Started | Aug 23 01:04:03 PM UTC 24 |
| Finished | Aug 23 01:04:04 PM UTC 24 |
| Peak memory | 210736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054870169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_alert_test.3054870169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/6.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_bijection.418586393 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 60081299724 ps |
| CPU time | 1151.41 seconds |
| Started | Aug 23 01:01:56 PM UTC 24 |
| Finished | Aug 23 01:21:19 PM UTC 24 |
| Peak memory | 213156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418586393 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.418586393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/6.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_executable.2898329589 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 3236065362 ps |
| CPU time | 115.65 seconds |
| Started | Aug 23 01:02:52 PM UTC 24 |
| Finished | Aug 23 01:04:50 PM UTC 24 |
| Peak memory | 370144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898329589 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executable.2898329589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/6.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.1731814794 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 19295738992 ps |
| CPU time | 62.48 seconds |
| Started | Aug 23 01:02:37 PM UTC 24 |
| Finished | Aug 23 01:03:41 PM UTC 24 |
| Peak memory | 211704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731814794 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_escalation.1731814794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/6.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.3924785761 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 717456185 ps |
| CPU time | 8.94 seconds |
| Started | Aug 23 01:02:26 PM UTC 24 |
| Finished | Aug 23 01:02:36 PM UTC 24 |
| Peak memory | 245220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3924785761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_m ax_throughput.3924785761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/6.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.2607855397 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 11015874801 ps |
| CPU time | 151.51 seconds |
| Started | Aug 23 01:03:42 PM UTC 24 |
| Finished | Aug 23 01:06:15 PM UTC 24 |
| Peak memory | 222180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607855397 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_mem_partial_access.2607855397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/6.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.487501554 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 57548887737 ps |
| CPU time | 289.49 seconds |
| Started | Aug 23 01:03:41 PM UTC 24 |
| Finished | Aug 23 01:08:34 PM UTC 24 |
| Peak memory | 221860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487501554 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_mem_walk.487501554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/6.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.3544244621 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 58414510269 ps |
| CPU time | 394.09 seconds |
| Started | Aug 23 01:01:53 PM UTC 24 |
| Finished | Aug 23 01:08:31 PM UTC 24 |
| Peak memory | 382496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544244621 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multiple_keys.3544244621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/6.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access.1882253831 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 820292967 ps |
| CPU time | 6.12 seconds |
| Started | Aug 23 01:02:11 PM UTC 24 |
| Finished | Aug 23 01:02:18 PM UTC 24 |
| Peak memory | 211696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882253831 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_partial_access.1882253831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/6.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.234526020 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 174334292572 ps |
| CPU time | 417.52 seconds |
| Started | Aug 23 01:02:19 PM UTC 24 |
| Finished | Aug 23 01:09:22 PM UTC 24 |
| Peak memory | 211568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234526020 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_partial_acc ess_b2b.234526020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/6.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.2970572224 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 2814464304 ps |
| CPU time | 3.6 seconds |
| Started | Aug 23 01:03:35 PM UTC 24 |
| Finished | Aug 23 01:03:39 PM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970572224 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.2970572224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/6.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_regwen.210068195 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 19367502076 ps |
| CPU time | 487.09 seconds |
| Started | Aug 23 01:03:15 PM UTC 24 |
| Finished | Aug 23 01:11:28 PM UTC 24 |
| Peak memory | 388920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210068195 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.210068195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/6.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_smoke.458947673 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 1957641626 ps |
| CPU time | 16.47 seconds |
| Started | Aug 23 01:01:52 PM UTC 24 |
| Finished | Aug 23 01:02:09 PM UTC 24 |
| Peak memory | 277984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458947673 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.458947673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/6.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all.1545495700 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 2059675673774 ps |
| CPU time | 7048.94 seconds |
| Started | Aug 23 01:03:57 PM UTC 24 |
| Finished | Aug 23 03:02:31 PM UTC 24 |
| Peak memory | 390248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15454957 00 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all.1545495700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/6.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3361644989 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 1072298468 ps |
| CPU time | 18.85 seconds |
| Started | Aug 23 01:03:52 PM UTC 24 |
| Finished | Aug 23 01:04:12 PM UTC 24 |
| Peak memory | 221864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361644989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.3361644989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/6.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.1433651499 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 38136988872 ps |
| CPU time | 309.65 seconds |
| Started | Aug 23 01:02:10 PM UTC 24 |
| Finished | Aug 23 01:07:24 PM UTC 24 |
| Peak memory | 211556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433651499 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_pipeline.1433651499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/6.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.4055603600 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 2881655038 ps |
| CPU time | 10.69 seconds |
| Started | Aug 23 01:02:35 PM UTC 24 |
| Finished | Aug 23 01:02:47 PM UTC 24 |
| Peak memory | 247332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =4055603600 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ throughput_w_partial_write.4055603600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/6.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.3150509053 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 97182364128 ps |
| CPU time | 523.38 seconds |
| Started | Aug 23 01:06:07 PM UTC 24 |
| Finished | Aug 23 01:14:56 PM UTC 24 |
| Peak memory | 382420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150509053 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_access_durin g_key_req.3150509053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/7.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_alert_test.1862066486 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 36035337 ps |
| CPU time | 0.56 seconds |
| Started | Aug 23 01:08:07 PM UTC 24 |
| Finished | Aug 23 01:08:09 PM UTC 24 |
| Peak memory | 210736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862066486 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_alert_test.1862066486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/7.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_bijection.1127623934 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 26406514424 ps |
| CPU time | 716.3 seconds |
| Started | Aug 23 01:04:25 PM UTC 24 |
| Finished | Aug 23 01:16:29 PM UTC 24 |
| Peak memory | 211740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127623934 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.1127623934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/7.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_executable.3871991889 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 7160288200 ps |
| CPU time | 438.2 seconds |
| Started | Aug 23 01:06:16 PM UTC 24 |
| Finished | Aug 23 01:13:39 PM UTC 24 |
| Peak memory | 362028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871991889 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executable.3871991889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/7.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.3772609208 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 43908808785 ps |
| CPU time | 72.72 seconds |
| Started | Aug 23 01:05:51 PM UTC 24 |
| Finished | Aug 23 01:07:05 PM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772609208 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_escalation.3772609208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/7.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.1983999319 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 898743762 ps |
| CPU time | 47.02 seconds |
| Started | Aug 23 01:05:01 PM UTC 24 |
| Finished | Aug 23 01:05:50 PM UTC 24 |
| Peak memory | 374168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1983999319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_m ax_throughput.1983999319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/7.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.3181056712 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 12867971997 ps |
| CPU time | 128.53 seconds |
| Started | Aug 23 01:07:24 PM UTC 24 |
| Finished | Aug 23 01:09:35 PM UTC 24 |
| Peak memory | 228884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181056712 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_mem_partial_access.3181056712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/7.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.542298793 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 68969851446 ps |
| CPU time | 146.99 seconds |
| Started | Aug 23 01:07:11 PM UTC 24 |
| Finished | Aug 23 01:09:40 PM UTC 24 |
| Peak memory | 221844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542298793 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_mem_walk.542298793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/7.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.3588336660 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 38670083428 ps |
| CPU time | 400.66 seconds |
| Started | Aug 23 01:04:13 PM UTC 24 |
| Finished | Aug 23 01:10:58 PM UTC 24 |
| Peak memory | 372384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588336660 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multiple_keys.3588336660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/7.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access.4000785047 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 457622346 ps |
| CPU time | 8.2 seconds |
| Started | Aug 23 01:04:51 PM UTC 24 |
| Finished | Aug 23 01:05:01 PM UTC 24 |
| Peak memory | 211568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000785047 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_partial_access.4000785047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/7.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.118535330 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 19234258633 ps |
| CPU time | 361.41 seconds |
| Started | Aug 23 01:04:51 PM UTC 24 |
| Finished | Aug 23 01:10:57 PM UTC 24 |
| Peak memory | 211752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118535330 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_partial_acc ess_b2b.118535330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/7.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.261618021 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 1407500699 ps |
| CPU time | 3.57 seconds |
| Started | Aug 23 01:07:06 PM UTC 24 |
| Finished | Aug 23 01:07:11 PM UTC 24 |
| Peak memory | 211632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261618021 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.261618021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/7.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_regwen.4236373022 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 8034850206 ps |
| CPU time | 601.48 seconds |
| Started | Aug 23 01:06:32 PM UTC 24 |
| Finished | Aug 23 01:16:40 PM UTC 24 |
| Peak memory | 388732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236373022 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.4236373022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/7.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_smoke.1559807477 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 3948978423 ps |
| CPU time | 18.51 seconds |
| Started | Aug 23 01:04:05 PM UTC 24 |
| Finished | Aug 23 01:04:25 PM UTC 24 |
| Peak memory | 276124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559807477 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.1559807477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/7.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all.3426073383 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 78528263920 ps |
| CPU time | 1790.04 seconds |
| Started | Aug 23 01:07:58 PM UTC 24 |
| Finished | Aug 23 01:38:06 PM UTC 24 |
| Peak memory | 396464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34260733 83 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all.3426073383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/7.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2694591827 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 661334068 ps |
| CPU time | 11.42 seconds |
| Started | Aug 23 01:07:45 PM UTC 24 |
| Finished | Aug 23 01:07:58 PM UTC 24 |
| Peak memory | 221936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694591827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.2694591827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/7.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.2261122493 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 15085388814 ps |
| CPU time | 222.78 seconds |
| Started | Aug 23 01:04:29 PM UTC 24 |
| Finished | Aug 23 01:08:15 PM UTC 24 |
| Peak memory | 211624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261122493 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_pipeline.2261122493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/7.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.1959725099 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 6095215708 ps |
| CPU time | 26.11 seconds |
| Started | Aug 23 01:05:39 PM UTC 24 |
| Finished | Aug 23 01:06:06 PM UTC 24 |
| Peak memory | 306728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1959725099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ throughput_w_partial_write.1959725099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/7.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.232194596 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 21207502145 ps |
| CPU time | 154.52 seconds |
| Started | Aug 23 01:09:36 PM UTC 24 |
| Finished | Aug 23 01:12:13 PM UTC 24 |
| Peak memory | 384532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232194596 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_access_during _key_req.232194596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/8.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_alert_test.2493299544 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 36275757 ps |
| CPU time | 0.55 seconds |
| Started | Aug 23 01:10:50 PM UTC 24 |
| Finished | Aug 23 01:10:52 PM UTC 24 |
| Peak memory | 210824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493299544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_alert_test.2493299544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/8.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_bijection.3262364546 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 155753552322 ps |
| CPU time | 1274.35 seconds |
| Started | Aug 23 01:08:25 PM UTC 24 |
| Finished | Aug 23 01:29:52 PM UTC 24 |
| Peak memory | 213296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262364546 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection.3262364546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/8.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_executable.3781899311 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 120640879224 ps |
| CPU time | 1078.98 seconds |
| Started | Aug 23 01:09:36 PM UTC 24 |
| Finished | Aug 23 01:27:45 PM UTC 24 |
| Peak memory | 392296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781899311 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executable.3781899311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/8.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.3299851408 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 37240089064 ps |
| CPU time | 72.58 seconds |
| Started | Aug 23 01:09:23 PM UTC 24 |
| Finished | Aug 23 01:10:37 PM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299851408 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_escalation.3299851408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/8.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.1002944477 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 1501944879 ps |
| CPU time | 9.98 seconds |
| Started | Aug 23 01:09:01 PM UTC 24 |
| Finished | Aug 23 01:09:12 PM UTC 24 |
| Peak memory | 247396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1002944477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_m ax_throughput.1002944477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/8.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.3075237352 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 11472856117 ps |
| CPU time | 74.29 seconds |
| Started | Aug 23 01:09:52 PM UTC 24 |
| Finished | Aug 23 01:11:08 PM UTC 24 |
| Peak memory | 221804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075237352 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_mem_partial_access.3075237352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/8.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.2010129983 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 5335742512 ps |
| CPU time | 104.76 seconds |
| Started | Aug 23 01:09:51 PM UTC 24 |
| Finished | Aug 23 01:11:38 PM UTC 24 |
| Peak memory | 222076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010129983 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_mem_walk.2010129983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/8.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.3636023211 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 32314708780 ps |
| CPU time | 367.55 seconds |
| Started | Aug 23 01:08:15 PM UTC 24 |
| Finished | Aug 23 01:14:27 PM UTC 24 |
| Peak memory | 386508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636023211 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multiple_keys.3636023211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/8.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access.2969383586 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 3203967198 ps |
| CPU time | 23.69 seconds |
| Started | Aug 23 01:08:35 PM UTC 24 |
| Finished | Aug 23 01:09:00 PM UTC 24 |
| Peak memory | 211752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969383586 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_partial_access.2969383586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/8.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.1466891868 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 14282010125 ps |
| CPU time | 325.96 seconds |
| Started | Aug 23 01:08:53 PM UTC 24 |
| Finished | Aug 23 01:14:23 PM UTC 24 |
| Peak memory | 211584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466891868 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_partial_ac cess_b2b.1466891868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/8.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.610927942 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 720020113 ps |
| CPU time | 3.28 seconds |
| Started | Aug 23 01:09:47 PM UTC 24 |
| Finished | Aug 23 01:09:51 PM UTC 24 |
| Peak memory | 211624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610927942 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.610927942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/8.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_smoke.1064948068 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 1561892317 ps |
| CPU time | 14.2 seconds |
| Started | Aug 23 01:08:09 PM UTC 24 |
| Finished | Aug 23 01:08:25 PM UTC 24 |
| Peak memory | 211548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064948068 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.1064948068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/8.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all.295965877 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 28724687083 ps |
| CPU time | 1800.35 seconds |
| Started | Aug 23 01:10:38 PM UTC 24 |
| Finished | Aug 23 01:40:54 PM UTC 24 |
| Peak memory | 390248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29596587 7 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all.295965877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/8.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2246955240 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 3588247880 ps |
| CPU time | 26.46 seconds |
| Started | Aug 23 01:10:29 PM UTC 24 |
| Finished | Aug 23 01:10:57 PM UTC 24 |
| Peak memory | 274204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246955240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.2246955240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/8.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.1013685700 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 4464717691 ps |
| CPU time | 295.49 seconds |
| Started | Aug 23 01:08:33 PM UTC 24 |
| Finished | Aug 23 01:13:32 PM UTC 24 |
| Peak memory | 211564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013685700 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_pipeline.1013685700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/8.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.2363184389 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 764638328 ps |
| CPU time | 31.84 seconds |
| Started | Aug 23 01:09:13 PM UTC 24 |
| Finished | Aug 23 01:09:46 PM UTC 24 |
| Peak memory | 341616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2363184389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ throughput_w_partial_write.2363184389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/8.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.2187728126 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 27259894204 ps |
| CPU time | 660.8 seconds |
| Started | Aug 23 01:12:06 PM UTC 24 |
| Finished | Aug 23 01:23:13 PM UTC 24 |
| Peak memory | 388652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187728126 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_access_durin g_key_req.2187728126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/9.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_alert_test.831635932 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 40044266 ps |
| CPU time | 0.56 seconds |
| Started | Aug 23 01:13:40 PM UTC 24 |
| Finished | Aug 23 01:13:41 PM UTC 24 |
| Peak memory | 210736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831635932 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_alert_test.831635932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/9.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_bijection.2892125115 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 31760827220 ps |
| CPU time | 1883.21 seconds |
| Started | Aug 23 01:10:58 PM UTC 24 |
| Finished | Aug 23 01:42:39 PM UTC 24 |
| Peak memory | 213224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892125115 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.2892125115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/9.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_executable.4099715562 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 5513458900 ps |
| CPU time | 326.42 seconds |
| Started | Aug 23 01:12:13 PM UTC 24 |
| Finished | Aug 23 01:17:44 PM UTC 24 |
| Peak memory | 386744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099715562 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executable.4099715562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/9.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.1251699936 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 3458647368 ps |
| CPU time | 25.5 seconds |
| Started | Aug 23 01:11:39 PM UTC 24 |
| Finished | Aug 23 01:12:06 PM UTC 24 |
| Peak memory | 222020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251699936 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_escalation.1251699936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/9.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.3988064652 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 1526740769 ps |
| CPU time | 47.06 seconds |
| Started | Aug 23 01:11:27 PM UTC 24 |
| Finished | Aug 23 01:12:15 PM UTC 24 |
| Peak memory | 376212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3988064652 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_m ax_throughput.3988064652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/9.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.3181087614 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 1041830434 ps |
| CPU time | 56.59 seconds |
| Started | Aug 23 01:12:28 PM UTC 24 |
| Finished | Aug 23 01:13:27 PM UTC 24 |
| Peak memory | 228984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181087614 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_mem_partial_access.3181087614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/9.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.1169653841 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 15715700488 ps |
| CPU time | 266.68 seconds |
| Started | Aug 23 01:12:21 PM UTC 24 |
| Finished | Aug 23 01:16:51 PM UTC 24 |
| Peak memory | 221872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169653841 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_mem_walk.1169653841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/9.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.3622075877 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 7273853556 ps |
| CPU time | 206.95 seconds |
| Started | Aug 23 01:10:58 PM UTC 24 |
| Finished | Aug 23 01:14:27 PM UTC 24 |
| Peak memory | 384596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622075877 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multiple_keys.3622075877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/9.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access.1174923709 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 4743268588 ps |
| CPU time | 17.85 seconds |
| Started | Aug 23 01:11:07 PM UTC 24 |
| Finished | Aug 23 01:11:26 PM UTC 24 |
| Peak memory | 211556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174923709 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_partial_access.1174923709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/9.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.1168015463 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 179605124785 ps |
| CPU time | 416.78 seconds |
| Started | Aug 23 01:11:09 PM UTC 24 |
| Finished | Aug 23 01:18:11 PM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168015463 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_partial_ac cess_b2b.1168015463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/9.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.2153376085 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 393583682 ps |
| CPU time | 3.1 seconds |
| Started | Aug 23 01:12:16 PM UTC 24 |
| Finished | Aug 23 01:12:21 PM UTC 24 |
| Peak memory | 211644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153376085 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.2153376085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/9.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_regwen.967144218 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 9379259552 ps |
| CPU time | 312.23 seconds |
| Started | Aug 23 01:12:15 PM UTC 24 |
| Finished | Aug 23 01:17:32 PM UTC 24 |
| Peak memory | 374312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967144218 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.967144218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/9.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_smoke.1221073947 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 492876399 ps |
| CPU time | 12.03 seconds |
| Started | Aug 23 01:10:52 PM UTC 24 |
| Finished | Aug 23 01:11:06 PM UTC 24 |
| Peak memory | 211564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221073947 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.1221073947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/9.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all.2125750268 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 163828240889 ps |
| CPU time | 2799.84 seconds |
| Started | Aug 23 01:13:33 PM UTC 24 |
| Finished | Aug 23 02:00:39 PM UTC 24 |
| Peak memory | 390308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21257502 68 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all.2125750268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/9.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3772297132 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 2009832112 ps |
| CPU time | 36.43 seconds |
| Started | Aug 23 01:13:28 PM UTC 24 |
| Finished | Aug 23 01:14:05 PM UTC 24 |
| Peak memory | 221924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772297132 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.3772297132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/9.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.3474561260 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 4173167070 ps |
| CPU time | 251.3 seconds |
| Started | Aug 23 01:10:59 PM UTC 24 |
| Finished | Aug 23 01:15:13 PM UTC 24 |
| Peak memory | 211556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474561260 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_pipeline.3474561260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/9.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.3408295099 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 1632022317 ps |
| CPU time | 57.72 seconds |
| Started | Aug 23 01:11:29 PM UTC 24 |
| Finished | Aug 23 01:12:28 PM UTC 24 |
| Peak memory | 380392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3408295099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ throughput_w_partial_write.3408295099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/sram_ctrl_main-sim-vcs/9.sram_ctrl_throughput_w_partial_write/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |