| T307 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.2128238625 |
|
|
Aug 27 09:58:23 AM UTC 24 |
Aug 27 10:04:09 AM UTC 24 |
15139555104 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.1500715546 |
|
|
Aug 27 10:03:29 AM UTC 24 |
Aug 27 10:04:19 AM UTC 24 |
1152453124 ps |
| T308 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.2372381569 |
|
|
Aug 27 09:57:56 AM UTC 24 |
Aug 27 10:04:21 AM UTC 24 |
20710721504 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_smoke.861128080 |
|
|
Aug 27 10:04:04 AM UTC 24 |
Aug 27 10:04:25 AM UTC 24 |
1545031002 ps |
| T310 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.3568536757 |
|
|
Aug 27 09:56:21 AM UTC 24 |
Aug 27 10:04:34 AM UTC 24 |
15337821803 ps |
| T311 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.3444210641 |
|
|
Aug 27 09:53:50 AM UTC 24 |
Aug 27 10:04:38 AM UTC 24 |
31766797459 ps |
| T312 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access.1755648039 |
|
|
Aug 27 10:04:26 AM UTC 24 |
Aug 27 10:05:07 AM UTC 24 |
7713238635 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.2040204882 |
|
|
Aug 27 09:47:45 AM UTC 24 |
Aug 27 10:05:28 AM UTC 24 |
67983438703 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.2824258927 |
|
|
Aug 27 10:04:39 AM UTC 24 |
Aug 27 10:05:29 AM UTC 24 |
5143561238 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_bijection.1520566936 |
|
|
Aug 27 09:42:35 AM UTC 24 |
Aug 27 10:05:41 AM UTC 24 |
694073990872 ps |
| T91 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.4010752576 |
|
|
Aug 27 10:03:15 AM UTC 24 |
Aug 27 10:05:54 AM UTC 24 |
17866804214 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.2178675779 |
|
|
Aug 27 10:05:08 AM UTC 24 |
Aug 27 10:06:27 AM UTC 24 |
774232962 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.1619106006 |
|
|
Aug 27 10:01:14 AM UTC 24 |
Aug 27 10:06:28 AM UTC 24 |
14221810900 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.3561994559 |
|
|
Aug 27 10:05:29 AM UTC 24 |
Aug 27 10:06:34 AM UTC 24 |
20487439455 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.3960170510 |
|
|
Aug 27 10:06:27 AM UTC 24 |
Aug 27 10:06:35 AM UTC 24 |
1620905482 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.3174036317 |
|
|
Aug 27 10:06:36 AM UTC 24 |
Aug 27 10:06:52 AM UTC 24 |
1160321187 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.3818722965 |
|
|
Aug 27 10:05:30 AM UTC 24 |
Aug 27 10:07:00 AM UTC 24 |
19238853287 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_alert_test.4190054451 |
|
|
Aug 27 10:07:01 AM UTC 24 |
Aug 27 10:07:03 AM UTC 24 |
21004737 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_bijection.2704806186 |
|
|
Aug 27 09:54:52 AM UTC 24 |
Aug 27 10:07:32 AM UTC 24 |
83239912922 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all.401520384 |
|
|
Aug 27 09:35:31 AM UTC 24 |
Aug 27 10:07:34 AM UTC 24 |
49070225519 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.1318923363 |
|
|
Aug 27 09:58:43 AM UTC 24 |
Aug 27 10:08:07 AM UTC 24 |
85538074295 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.2557405412 |
|
|
Aug 27 10:01:30 AM UTC 24 |
Aug 27 10:08:09 AM UTC 24 |
15606730805 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.1864707296 |
|
|
Aug 27 09:49:29 AM UTC 24 |
Aug 27 10:08:11 AM UTC 24 |
90974813206 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access.1480868703 |
|
|
Aug 27 10:08:09 AM UTC 24 |
Aug 27 10:08:40 AM UTC 24 |
5337274342 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.2819894688 |
|
|
Aug 27 10:03:10 AM UTC 24 |
Aug 27 10:08:43 AM UTC 24 |
106385881126 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_smoke.50461280 |
|
|
Aug 27 10:07:04 AM UTC 24 |
Aug 27 10:08:44 AM UTC 24 |
1274517305 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.3004074525 |
|
|
Aug 27 10:01:10 AM UTC 24 |
Aug 27 10:08:57 AM UTC 24 |
57664539958 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.1715542223 |
|
|
Aug 27 10:06:28 AM UTC 24 |
Aug 27 10:08:59 AM UTC 24 |
13167794406 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_bijection.2695516120 |
|
|
Aug 27 09:45:02 AM UTC 24 |
Aug 27 10:09:18 AM UTC 24 |
16740669735 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.1136434001 |
|
|
Aug 27 10:08:44 AM UTC 24 |
Aug 27 10:09:52 AM UTC 24 |
1559076470 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.852254637 |
|
|
Aug 27 10:08:41 AM UTC 24 |
Aug 27 10:09:52 AM UTC 24 |
1505280800 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.266819064 |
|
|
Aug 27 10:06:35 AM UTC 24 |
Aug 27 10:09:54 AM UTC 24 |
9695770368 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.2122164484 |
|
|
Aug 27 10:09:53 AM UTC 24 |
Aug 27 10:10:00 AM UTC 24 |
364997601 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.2779509725 |
|
|
Aug 27 10:08:45 AM UTC 24 |
Aug 27 10:10:18 AM UTC 24 |
42675607227 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.1558698783 |
|
|
Aug 27 10:04:35 AM UTC 24 |
Aug 27 10:10:30 AM UTC 24 |
18520281974 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_alert_test.782297620 |
|
|
Aug 27 10:10:31 AM UTC 24 |
Aug 27 10:10:33 AM UTC 24 |
14565490 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.1870281651 |
|
|
Aug 27 10:04:10 AM UTC 24 |
Aug 27 10:10:37 AM UTC 24 |
9976315545 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.3758672926 |
|
|
Aug 27 10:09:55 AM UTC 24 |
Aug 27 10:11:08 AM UTC 24 |
1647628001 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.4192735468 |
|
|
Aug 27 10:01:59 AM UTC 24 |
Aug 27 10:11:14 AM UTC 24 |
7865818072 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.3435193805 |
|
|
Aug 27 10:04:22 AM UTC 24 |
Aug 27 10:11:21 AM UTC 24 |
11231381410 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.4292094376 |
|
|
Aug 27 09:50:57 AM UTC 24 |
Aug 27 10:11:27 AM UTC 24 |
47387397825 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_executable.3771055293 |
|
|
Aug 27 10:02:27 AM UTC 24 |
Aug 27 10:11:31 AM UTC 24 |
24336558043 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access.1885854544 |
|
|
Aug 27 10:11:22 AM UTC 24 |
Aug 27 10:11:52 AM UTC 24 |
3416861511 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.443806122 |
|
|
Aug 27 10:11:32 AM UTC 24 |
Aug 27 10:11:52 AM UTC 24 |
2870520650 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.2042500638 |
|
|
Aug 27 10:07:33 AM UTC 24 |
Aug 27 10:12:00 AM UTC 24 |
3929846326 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.1275592594 |
|
|
Aug 27 10:10:01 AM UTC 24 |
Aug 27 10:12:07 AM UTC 24 |
1540732190 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_smoke.1535739054 |
|
|
Aug 27 10:10:34 AM UTC 24 |
Aug 27 10:12:17 AM UTC 24 |
5266423901 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_bijection.1866748807 |
|
|
Aug 27 10:01:12 AM UTC 24 |
Aug 27 10:12:34 AM UTC 24 |
6965734161 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.1040035953 |
|
|
Aug 27 10:12:36 AM UTC 24 |
Aug 27 10:12:43 AM UTC 24 |
1402324595 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.4248240983 |
|
|
Aug 27 09:59:14 AM UTC 24 |
Aug 27 10:12:52 AM UTC 24 |
16408098546 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_executable.2445448963 |
|
|
Aug 27 10:08:59 AM UTC 24 |
Aug 27 10:12:55 AM UTC 24 |
37781597832 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.2109008788 |
|
|
Aug 27 10:11:53 AM UTC 24 |
Aug 27 10:13:08 AM UTC 24 |
904041962 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.2375122256 |
|
|
Aug 27 10:09:53 AM UTC 24 |
Aug 27 10:13:13 AM UTC 24 |
64139223576 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_bijection.3257002048 |
|
|
Aug 27 09:47:55 AM UTC 24 |
Aug 27 10:13:14 AM UTC 24 |
189121975172 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_alert_test.3293433141 |
|
|
Aug 27 10:13:14 AM UTC 24 |
Aug 27 10:13:16 AM UTC 24 |
25160649 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_smoke.463186625 |
|
|
Aug 27 10:13:15 AM UTC 24 |
Aug 27 10:13:30 AM UTC 24 |
1734487113 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.1431913424 |
|
|
Aug 27 10:08:12 AM UTC 24 |
Aug 27 10:13:33 AM UTC 24 |
45013401976 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_regwen.1599997804 |
|
|
Aug 27 10:02:54 AM UTC 24 |
Aug 27 10:14:05 AM UTC 24 |
15391114703 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access.3392374982 |
|
|
Aug 27 10:14:07 AM UTC 24 |
Aug 27 10:14:21 AM UTC 24 |
913341560 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.1196513918 |
|
|
Aug 27 10:12:53 AM UTC 24 |
Aug 27 10:14:31 AM UTC 24 |
2708300847 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.1752985214 |
|
|
Aug 27 10:12:56 AM UTC 24 |
Aug 27 10:14:32 AM UTC 24 |
4912942951 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.2972436033 |
|
|
Aug 27 10:11:53 AM UTC 24 |
Aug 27 10:14:32 AM UTC 24 |
57090213693 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.2099156027 |
|
|
Aug 27 10:08:07 AM UTC 24 |
Aug 27 10:14:44 AM UTC 24 |
5184167622 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.2873961406 |
|
|
Aug 27 10:14:32 AM UTC 24 |
Aug 27 10:14:56 AM UTC 24 |
3028192145 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.3939013103 |
|
|
Aug 27 10:12:44 AM UTC 24 |
Aug 27 10:15:19 AM UTC 24 |
28827407977 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_bijection.2980119020 |
|
|
Aug 27 09:50:59 AM UTC 24 |
Aug 27 10:15:23 AM UTC 24 |
90578667721 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.643303121 |
|
|
Aug 27 10:15:24 AM UTC 24 |
Aug 27 10:15:31 AM UTC 24 |
1039589843 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.757764808 |
|
|
Aug 27 10:14:33 AM UTC 24 |
Aug 27 10:16:00 AM UTC 24 |
7899867264 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.4239046749 |
|
|
Aug 27 10:11:15 AM UTC 24 |
Aug 27 10:16:05 AM UTC 24 |
13696272839 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.3329321508 |
|
|
Aug 27 10:14:33 AM UTC 24 |
Aug 27 10:16:28 AM UTC 24 |
825364133 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.1531551641 |
|
|
Aug 27 10:16:06 AM UTC 24 |
Aug 27 10:16:51 AM UTC 24 |
977917175 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_alert_test.1090291653 |
|
|
Aug 27 10:16:51 AM UTC 24 |
Aug 27 10:16:53 AM UTC 24 |
19200203 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_executable.434113339 |
|
|
Aug 27 09:57:09 AM UTC 24 |
Aug 27 10:17:28 AM UTC 24 |
12388903666 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_smoke.3949931374 |
|
|
Aug 27 10:16:54 AM UTC 24 |
Aug 27 10:17:34 AM UTC 24 |
2037185008 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_bijection.2389649620 |
|
|
Aug 27 09:39:23 AM UTC 24 |
Aug 27 10:17:44 AM UTC 24 |
122301583620 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.3719325294 |
|
|
Aug 27 10:11:28 AM UTC 24 |
Aug 27 10:17:49 AM UTC 24 |
18405328774 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_executable.3745578204 |
|
|
Aug 27 10:05:42 AM UTC 24 |
Aug 27 10:18:02 AM UTC 24 |
102333727605 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_regwen.449704202 |
|
|
Aug 27 09:59:25 AM UTC 24 |
Aug 27 10:18:05 AM UTC 24 |
20244963894 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.2790780110 |
|
|
Aug 27 10:16:01 AM UTC 24 |
Aug 27 10:18:14 AM UTC 24 |
3188652511 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.2642408119 |
|
|
Aug 27 10:13:34 AM UTC 24 |
Aug 27 10:18:41 AM UTC 24 |
7973348709 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_regwen.1069271886 |
|
|
Aug 27 10:09:18 AM UTC 24 |
Aug 27 10:18:54 AM UTC 24 |
9941369541 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.568486913 |
|
|
Aug 27 10:15:32 AM UTC 24 |
Aug 27 10:19:01 AM UTC 24 |
13851925722 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.4148975366 |
|
|
Aug 27 10:18:05 AM UTC 24 |
Aug 27 10:19:15 AM UTC 24 |
1823595586 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access.173735420 |
|
|
Aug 27 10:17:49 AM UTC 24 |
Aug 27 10:19:31 AM UTC 24 |
1372764429 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.3588682875 |
|
|
Aug 27 10:19:31 AM UTC 24 |
Aug 27 10:19:38 AM UTC 24 |
356820696 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.1395524407 |
|
|
Aug 27 10:18:15 AM UTC 24 |
Aug 27 10:19:51 AM UTC 24 |
3145088212 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_regwen.3732495839 |
|
|
Aug 27 10:05:54 AM UTC 24 |
Aug 27 10:20:19 AM UTC 24 |
18290632766 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.2738758985 |
|
|
Aug 27 10:20:20 AM UTC 24 |
Aug 27 10:20:35 AM UTC 24 |
749558272 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.3947265369 |
|
|
Aug 27 10:18:42 AM UTC 24 |
Aug 27 10:20:43 AM UTC 24 |
33226832303 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_alert_test.1788173660 |
|
|
Aug 27 10:20:44 AM UTC 24 |
Aug 27 10:20:46 AM UTC 24 |
67026026 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.844661649 |
|
|
Aug 27 09:57:03 AM UTC 24 |
Aug 27 10:21:08 AM UTC 24 |
23276282602 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_smoke.283197429 |
|
|
Aug 27 10:20:48 AM UTC 24 |
Aug 27 10:21:09 AM UTC 24 |
779791064 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_regwen.3525873748 |
|
|
Aug 27 10:15:21 AM UTC 24 |
Aug 27 10:21:39 AM UTC 24 |
41977313738 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all.2729861241 |
|
|
Aug 27 09:41:53 AM UTC 24 |
Aug 27 10:21:44 AM UTC 24 |
39228556131 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.2339957969 |
|
|
Aug 27 10:17:45 AM UTC 24 |
Aug 27 10:21:45 AM UTC 24 |
3370115794 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all.2113686689 |
|
|
Aug 27 10:16:28 AM UTC 24 |
Aug 27 10:21:59 AM UTC 24 |
100651553833 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.3045278119 |
|
|
Aug 27 10:14:22 AM UTC 24 |
Aug 27 10:22:33 AM UTC 24 |
204380256631 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.721934884 |
|
|
Aug 27 10:08:58 AM UTC 24 |
Aug 27 10:22:33 AM UTC 24 |
51898373397 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access.1941446675 |
|
|
Aug 27 10:21:45 AM UTC 24 |
Aug 27 10:23:23 AM UTC 24 |
2519140606 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.3186825209 |
|
|
Aug 27 10:19:51 AM UTC 24 |
Aug 27 10:23:25 AM UTC 24 |
8992183176 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.2562871415 |
|
|
Aug 27 10:21:59 AM UTC 24 |
Aug 27 10:23:28 AM UTC 24 |
756650524 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.3887405545 |
|
|
Aug 27 10:21:39 AM UTC 24 |
Aug 27 10:23:30 AM UTC 24 |
1305759144 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.1824209328 |
|
|
Aug 27 10:23:31 AM UTC 24 |
Aug 27 10:23:39 AM UTC 24 |
1523403371 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.4004823502 |
|
|
Aug 27 10:12:00 AM UTC 24 |
Aug 27 10:23:40 AM UTC 24 |
38463264528 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_bijection.2207049258 |
|
|
Aug 27 09:58:17 AM UTC 24 |
Aug 27 10:23:52 AM UTC 24 |
69460821671 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.3680984723 |
|
|
Aug 27 10:22:34 AM UTC 24 |
Aug 27 10:24:03 AM UTC 24 |
36101936283 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.1192013677 |
|
|
Aug 27 10:22:34 AM UTC 24 |
Aug 27 10:24:11 AM UTC 24 |
810562253 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_alert_test.2567096974 |
|
|
Aug 27 10:24:12 AM UTC 24 |
Aug 27 10:24:14 AM UTC 24 |
48210905 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_smoke.815025006 |
|
|
Aug 27 10:24:15 AM UTC 24 |
Aug 27 10:24:30 AM UTC 24 |
1711891728 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.573271776 |
|
|
Aug 27 10:19:39 AM UTC 24 |
Aug 27 10:24:46 AM UTC 24 |
5474306403 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.3771718324 |
|
|
Aug 27 10:23:52 AM UTC 24 |
Aug 27 10:25:29 AM UTC 24 |
3508100091 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.2468966444 |
|
|
Aug 27 10:23:40 AM UTC 24 |
Aug 27 10:25:36 AM UTC 24 |
12810209539 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all.2741866115 |
|
|
Aug 27 09:58:01 AM UTC 24 |
Aug 27 10:26:08 AM UTC 24 |
209576224495 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_regwen.1210909408 |
|
|
Aug 27 10:12:17 AM UTC 24 |
Aug 27 10:26:43 AM UTC 24 |
6106371229 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access.1315620206 |
|
|
Aug 27 10:25:36 AM UTC 24 |
Aug 27 10:26:45 AM UTC 24 |
3738577276 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all.4047692460 |
|
|
Aug 27 09:44:31 AM UTC 24 |
Aug 27 10:26:52 AM UTC 24 |
67020332039 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.318486417 |
|
|
Aug 27 10:26:46 AM UTC 24 |
Aug 27 10:27:04 AM UTC 24 |
704114834 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.1929446496 |
|
|
Aug 27 10:18:03 AM UTC 24 |
Aug 27 10:27:11 AM UTC 24 |
15552017839 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.204261007 |
|
|
Aug 27 10:13:17 AM UTC 24 |
Aug 27 10:27:45 AM UTC 24 |
22278518912 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_regwen.2385926833 |
|
|
Aug 27 10:19:16 AM UTC 24 |
Aug 27 10:28:02 AM UTC 24 |
10167530537 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.4144164580 |
|
|
Aug 27 10:26:44 AM UTC 24 |
Aug 27 10:28:03 AM UTC 24 |
2830658142 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.1240308770 |
|
|
Aug 27 10:28:03 AM UTC 24 |
Aug 27 10:28:09 AM UTC 24 |
1673679876 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_executable.264419830 |
|
|
Aug 27 10:12:08 AM UTC 24 |
Aug 27 10:29:01 AM UTC 24 |
19260465375 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.694814315 |
|
|
Aug 27 10:14:45 AM UTC 24 |
Aug 27 10:29:01 AM UTC 24 |
15376552262 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.300788913 |
|
|
Aug 27 10:26:53 AM UTC 24 |
Aug 27 10:29:05 AM UTC 24 |
116052745194 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_alert_test.1604279447 |
|
|
Aug 27 10:29:06 AM UTC 24 |
Aug 27 10:29:08 AM UTC 24 |
14796980 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.4257025282 |
|
|
Aug 27 10:23:40 AM UTC 24 |
Aug 27 10:29:11 AM UTC 24 |
23178328343 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.2490992272 |
|
|
Aug 27 10:10:37 AM UTC 24 |
Aug 27 10:29:21 AM UTC 24 |
32975405257 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.2138966487 |
|
|
Aug 27 10:29:01 AM UTC 24 |
Aug 27 10:29:21 AM UTC 24 |
1329557146 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_executable.1913992241 |
|
|
Aug 27 10:19:03 AM UTC 24 |
Aug 27 10:29:27 AM UTC 24 |
15753166228 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all.1654112458 |
|
|
Aug 27 09:26:09 AM UTC 24 |
Aug 27 10:29:27 AM UTC 24 |
161447238767 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.3360704807 |
|
|
Aug 27 10:21:09 AM UTC 24 |
Aug 27 10:29:28 AM UTC 24 |
29667691407 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_executable.3061420695 |
|
|
Aug 27 10:14:56 AM UTC 24 |
Aug 27 10:29:39 AM UTC 24 |
19487045953 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.3626796101 |
|
|
Aug 27 10:23:24 AM UTC 24 |
Aug 27 10:30:10 AM UTC 24 |
6695859813 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_smoke.671123025 |
|
|
Aug 27 10:29:09 AM UTC 24 |
Aug 27 10:30:22 AM UTC 24 |
866114467 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.2389850570 |
|
|
Aug 27 10:25:30 AM UTC 24 |
Aug 27 10:30:24 AM UTC 24 |
14507338766 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.1388236294 |
|
|
Aug 27 10:29:29 AM UTC 24 |
Aug 27 10:30:31 AM UTC 24 |
1013688438 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access.2448596418 |
|
|
Aug 27 10:29:28 AM UTC 24 |
Aug 27 10:30:33 AM UTC 24 |
4325342284 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.139362069 |
|
|
Aug 27 10:30:35 AM UTC 24 |
Aug 27 10:30:40 AM UTC 24 |
694111874 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.3770365757 |
|
|
Aug 27 10:29:40 AM UTC 24 |
Aug 27 10:30:52 AM UTC 24 |
792448721 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.3085283955 |
|
|
Aug 27 10:28:10 AM UTC 24 |
Aug 27 10:30:53 AM UTC 24 |
16867302064 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.2734950002 |
|
|
Aug 27 10:18:56 AM UTC 24 |
Aug 27 10:30:55 AM UTC 24 |
14702224724 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.3283408731 |
|
|
Aug 27 10:17:29 AM UTC 24 |
Aug 27 10:31:11 AM UTC 24 |
65436291106 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all.1908149066 |
|
|
Aug 27 10:13:09 AM UTC 24 |
Aug 27 10:31:13 AM UTC 24 |
19435064987 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_alert_test.2924772558 |
|
|
Aug 27 10:31:12 AM UTC 24 |
Aug 27 10:31:14 AM UTC 24 |
11831503 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.1309305492 |
|
|
Aug 27 10:30:10 AM UTC 24 |
Aug 27 10:31:26 AM UTC 24 |
12297356338 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.1422882026 |
|
|
Aug 27 10:28:04 AM UTC 24 |
Aug 27 10:31:33 AM UTC 24 |
62859181513 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.513632822 |
|
|
Aug 27 10:30:53 AM UTC 24 |
Aug 27 10:32:07 AM UTC 24 |
1336688304 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_bijection.1560814231 |
|
|
Aug 27 10:13:30 AM UTC 24 |
Aug 27 10:32:10 AM UTC 24 |
17388958694 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access.1949805273 |
|
|
Aug 27 10:32:08 AM UTC 24 |
Aug 27 10:32:23 AM UTC 24 |
699784220 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.3673540494 |
|
|
Aug 27 10:32:23 AM UTC 24 |
Aug 27 10:32:35 AM UTC 24 |
702480667 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.2811976690 |
|
|
Aug 27 10:21:46 AM UTC 24 |
Aug 27 10:32:43 AM UTC 24 |
48481351074 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_smoke.4268120315 |
|
|
Aug 27 10:31:14 AM UTC 24 |
Aug 27 10:33:03 AM UTC 24 |
783408576 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.2307621066 |
|
|
Aug 27 10:32:35 AM UTC 24 |
Aug 27 10:33:16 AM UTC 24 |
1493318254 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.1547229306 |
|
|
Aug 27 10:29:22 AM UTC 24 |
Aug 27 10:33:29 AM UTC 24 |
14369063163 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.2167938747 |
|
|
Aug 27 10:30:53 AM UTC 24 |
Aug 27 10:33:30 AM UTC 24 |
1703051236 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.3432150205 |
|
|
Aug 27 10:33:31 AM UTC 24 |
Aug 27 10:33:39 AM UTC 24 |
1343052221 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.659910708 |
|
|
Aug 27 10:32:43 AM UTC 24 |
Aug 27 10:34:00 AM UTC 24 |
26257946093 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_bijection.962415412 |
|
|
Aug 27 10:04:19 AM UTC 24 |
Aug 27 10:34:32 AM UTC 24 |
398085574317 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.2271481207 |
|
|
Aug 27 10:30:41 AM UTC 24 |
Aug 27 10:34:36 AM UTC 24 |
17125852085 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.2339599802 |
|
|
Aug 27 10:34:33 AM UTC 24 |
Aug 27 10:35:12 AM UTC 24 |
3159875081 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_alert_test.1631663350 |
|
|
Aug 27 10:35:13 AM UTC 24 |
Aug 27 10:35:15 AM UTC 24 |
56460296 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_regwen.1519802521 |
|
|
Aug 27 10:23:28 AM UTC 24 |
Aug 27 10:35:25 AM UTC 24 |
70951323238 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_smoke.195980347 |
|
|
Aug 27 10:35:16 AM UTC 24 |
Aug 27 10:36:13 AM UTC 24 |
5441007640 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.1947921508 |
|
|
Aug 27 10:31:34 AM UTC 24 |
Aug 27 10:36:31 AM UTC 24 |
13868090972 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.1050593212 |
|
|
Aug 27 10:34:01 AM UTC 24 |
Aug 27 10:36:38 AM UTC 24 |
6640266402 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.2189610920 |
|
|
Aug 27 10:29:12 AM UTC 24 |
Aug 27 10:37:12 AM UTC 24 |
4842784220 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.107479707 |
|
|
Aug 27 10:26:10 AM UTC 24 |
Aug 27 10:37:17 AM UTC 24 |
111472945261 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.24214134 |
|
|
Aug 27 10:24:30 AM UTC 24 |
Aug 27 10:37:23 AM UTC 24 |
21980149211 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access.3357520519 |
|
|
Aug 27 10:36:39 AM UTC 24 |
Aug 27 10:37:29 AM UTC 24 |
2151844807 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.3282418868 |
|
|
Aug 27 10:37:25 AM UTC 24 |
Aug 27 10:37:38 AM UTC 24 |
1466647351 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.3459087248 |
|
|
Aug 27 10:37:18 AM UTC 24 |
Aug 27 10:37:39 AM UTC 24 |
724469011 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.2572870012 |
|
|
Aug 27 10:27:05 AM UTC 24 |
Aug 27 10:38:09 AM UTC 24 |
206760616885 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_executable.1723047714 |
|
|
Aug 27 10:27:12 AM UTC 24 |
Aug 27 10:38:18 AM UTC 24 |
130789205906 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.822538680 |
|
|
Aug 27 10:29:28 AM UTC 24 |
Aug 27 10:38:20 AM UTC 24 |
15116851383 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.1774751128 |
|
|
Aug 27 10:38:18 AM UTC 24 |
Aug 27 10:38:26 AM UTC 24 |
705155941 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.775016313 |
|
|
Aug 27 10:31:16 AM UTC 24 |
Aug 27 10:38:28 AM UTC 24 |
52834753827 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_bijection.1279854909 |
|
|
Aug 27 10:29:22 AM UTC 24 |
Aug 27 10:39:06 AM UTC 24 |
144836406001 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.1664336121 |
|
|
Aug 27 10:37:30 AM UTC 24 |
Aug 27 10:39:15 AM UTC 24 |
13646627035 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_alert_test.2380531424 |
|
|
Aug 27 10:39:16 AM UTC 24 |
Aug 27 10:39:18 AM UTC 24 |
34873960 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_regwen.1180274085 |
|
|
Aug 27 10:30:32 AM UTC 24 |
Aug 27 10:39:27 AM UTC 24 |
67852342749 ps |
| T46 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.509842511 |
|
|
Aug 27 10:38:29 AM UTC 24 |
Aug 27 10:40:05 AM UTC 24 |
5289122971 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_regwen.3530566167 |
|
|
Aug 27 10:33:30 AM UTC 24 |
Aug 27 10:40:10 AM UTC 24 |
2179022784 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.2398970578 |
|
|
Aug 27 10:36:32 AM UTC 24 |
Aug 27 10:40:11 AM UTC 24 |
3079458031 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.583406706 |
|
|
Aug 27 10:35:26 AM UTC 24 |
Aug 27 10:40:41 AM UTC 24 |
5663597644 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_smoke.760822622 |
|
|
Aug 27 10:39:19 AM UTC 24 |
Aug 27 10:40:50 AM UTC 24 |
5300448483 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access.45569652 |
|
|
Aug 27 10:40:11 AM UTC 24 |
Aug 27 10:40:54 AM UTC 24 |
19201488901 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_executable.2493612925 |
|
|
Aug 27 10:23:26 AM UTC 24 |
Aug 27 10:41:12 AM UTC 24 |
125972453620 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.1656312038 |
|
|
Aug 27 10:40:51 AM UTC 24 |
Aug 27 10:41:13 AM UTC 24 |
2861548457 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.2955168983 |
|
|
Aug 27 10:33:40 AM UTC 24 |
Aug 27 10:41:16 AM UTC 24 |
93839153449 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.3180409943 |
|
|
Aug 27 10:40:55 AM UTC 24 |
Aug 27 10:41:35 AM UTC 24 |
3100080201 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.2323101888 |
|
|
Aug 27 10:37:39 AM UTC 24 |
Aug 27 10:41:49 AM UTC 24 |
11820080188 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.3382343372 |
|
|
Aug 27 10:38:27 AM UTC 24 |
Aug 27 10:41:51 AM UTC 24 |
9776586554 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.2427930550 |
|
|
Aug 27 10:41:51 AM UTC 24 |
Aug 27 10:41:58 AM UTC 24 |
1359595635 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.3039804818 |
|
|
Aug 27 10:41:12 AM UTC 24 |
Aug 27 10:42:10 AM UTC 24 |
35470958233 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_regwen.1398848347 |
|
|
Aug 27 10:27:46 AM UTC 24 |
Aug 27 10:42:42 AM UTC 24 |
25920292997 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.383845592 |
|
|
Aug 27 10:42:11 AM UTC 24 |
Aug 27 10:42:59 AM UTC 24 |
5045292741 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_alert_test.415472102 |
|
|
Aug 27 10:43:00 AM UTC 24 |
Aug 27 10:43:02 AM UTC 24 |
30262046 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_smoke.2048092398 |
|
|
Aug 27 10:43:03 AM UTC 24 |
Aug 27 10:43:24 AM UTC 24 |
2787968155 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_executable.3333099337 |
|
|
Aug 27 10:30:24 AM UTC 24 |
Aug 27 10:43:26 AM UTC 24 |
201861501478 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.508960458 |
|
|
Aug 27 10:38:20 AM UTC 24 |
Aug 27 10:43:28 AM UTC 24 |
5712132030 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.3440615131 |
|
|
Aug 27 10:33:04 AM UTC 24 |
Aug 27 10:44:00 AM UTC 24 |
11166816947 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access.921527309 |
|
|
Aug 27 10:44:02 AM UTC 24 |
Aug 27 10:44:27 AM UTC 24 |
3660223955 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.704716741 |
|
|
Aug 27 10:42:00 AM UTC 24 |
Aug 27 10:45:31 AM UTC 24 |
6044883207 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.2062579327 |
|
|
Aug 27 10:30:22 AM UTC 24 |
Aug 27 10:45:48 AM UTC 24 |
12891271545 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.2282187553 |
|
|
Aug 27 10:32:10 AM UTC 24 |
Aug 27 10:46:05 AM UTC 24 |
41203290482 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.3384101967 |
|
|
Aug 27 10:37:14 AM UTC 24 |
Aug 27 10:46:06 AM UTC 24 |
70756625055 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_bijection.844436542 |
|
|
Aug 27 10:07:34 AM UTC 24 |
Aug 27 10:46:11 AM UTC 24 |
135076683181 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_bijection.2102028439 |
|
|
Aug 27 10:24:47 AM UTC 24 |
Aug 27 10:46:16 AM UTC 24 |
17562339235 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.4128100186 |
|
|
Aug 27 10:45:32 AM UTC 24 |
Aug 27 10:46:22 AM UTC 24 |
1485407121 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.3395259820 |
|
|
Aug 27 10:46:23 AM UTC 24 |
Aug 27 10:46:31 AM UTC 24 |
1469150029 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_executable.2619593461 |
|
|
Aug 27 10:41:17 AM UTC 24 |
Aug 27 10:46:40 AM UTC 24 |
8056047143 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.1186825696 |
|
|
Aug 27 10:45:48 AM UTC 24 |
Aug 27 10:46:53 AM UTC 24 |
2807930180 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_executable.389903977 |
|
|
Aug 27 10:33:18 AM UTC 24 |
Aug 27 10:47:07 AM UTC 24 |
50874195366 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.3829761147 |
|
|
Aug 27 10:46:05 AM UTC 24 |
Aug 27 10:47:44 AM UTC 24 |
13717687025 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_alert_test.2867034080 |
|
|
Aug 27 10:47:45 AM UTC 24 |
Aug 27 10:47:47 AM UTC 24 |
42605728 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_executable.1349382744 |
|
|
Aug 27 10:46:12 AM UTC 24 |
Aug 27 10:47:53 AM UTC 24 |
2339731593 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_smoke.1039217970 |
|
|
Aug 27 10:47:48 AM UTC 24 |
Aug 27 10:47:56 AM UTC 24 |
768846049 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.646175379 |
|
|
Aug 27 10:40:10 AM UTC 24 |
Aug 27 10:47:59 AM UTC 24 |
21834614350 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.1562417897 |
|
|
Aug 27 10:46:41 AM UTC 24 |
Aug 27 10:48:10 AM UTC 24 |
1575926864 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.1173579504 |
|
|
Aug 27 10:46:54 AM UTC 24 |
Aug 27 10:48:12 AM UTC 24 |
2124684928 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access.1313669545 |
|
|
Aug 27 10:48:10 AM UTC 24 |
Aug 27 10:48:40 AM UTC 24 |
3360257570 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.3144566690 |
|
|
Aug 27 10:41:52 AM UTC 24 |
Aug 27 10:49:05 AM UTC 24 |
76810083071 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.1689946669 |
|
|
Aug 27 10:48:41 AM UTC 24 |
Aug 27 10:49:09 AM UTC 24 |
731570549 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.1140967406 |
|
|
Aug 27 10:49:06 AM UTC 24 |
Aug 27 10:49:29 AM UTC 24 |
2916621501 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all.3305565403 |
|
|
Aug 27 10:06:53 AM UTC 24 |
Aug 27 10:50:02 AM UTC 24 |
34640588016 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.2282554366 |
|
|
Aug 27 10:46:32 AM UTC 24 |
Aug 27 10:50:07 AM UTC 24 |
6902953361 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.3834471237 |
|
|
Aug 27 10:49:10 AM UTC 24 |
Aug 27 10:50:28 AM UTC 24 |
11755962482 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.3430488775 |
|
|
Aug 27 10:43:29 AM UTC 24 |
Aug 27 10:50:30 AM UTC 24 |
5461265199 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.3413000928 |
|
|
Aug 27 10:50:29 AM UTC 24 |
Aug 27 10:50:35 AM UTC 24 |
1350730966 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_regwen.3935880002 |
|
|
Aug 27 10:38:09 AM UTC 24 |
Aug 27 10:50:54 AM UTC 24 |
19130178518 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_regwen.2828763307 |
|
|
Aug 27 10:41:36 AM UTC 24 |
Aug 27 10:50:55 AM UTC 24 |
2445390142 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.3060080360 |
|
|
Aug 27 10:39:27 AM UTC 24 |
Aug 27 10:50:56 AM UTC 24 |
137454646720 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_alert_test.2712671639 |
|
|
Aug 27 10:50:57 AM UTC 24 |
Aug 27 10:50:59 AM UTC 24 |
89826313 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.576304949 |
|
|
Aug 27 10:40:42 AM UTC 24 |
Aug 27 10:51:07 AM UTC 24 |
16291614756 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_smoke.2099653348 |
|
|
Aug 27 10:51:00 AM UTC 24 |
Aug 27 10:51:13 AM UTC 24 |
1902393262 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_bijection.3180729537 |
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|
Aug 27 10:36:14 AM UTC 24 |
Aug 27 10:51:48 AM UTC 24 |
53784460005 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.1830266693 |
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|
Aug 27 10:50:55 AM UTC 24 |
Aug 27 10:52:00 AM UTC 24 |
3373866156 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.605729102 |
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|
Aug 27 10:48:00 AM UTC 24 |
Aug 27 10:52:32 AM UTC 24 |
3971642323 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access.3817699534 |
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|
Aug 27 10:52:00 AM UTC 24 |
Aug 27 10:52:32 AM UTC 24 |
6321471258 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.2801264107 |
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|
Aug 27 10:41:14 AM UTC 24 |
Aug 27 10:52:49 AM UTC 24 |
16773298397 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.976208833 |
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|
Aug 27 10:52:50 AM UTC 24 |
Aug 27 10:53:06 AM UTC 24 |
5551399916 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_executable.2685948146 |
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|
Aug 27 10:50:03 AM UTC 24 |
Aug 27 10:53:25 AM UTC 24 |
32721141951 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all.1749707075 |
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|
Aug 27 09:23:18 AM UTC 24 |
Aug 27 10:53:55 AM UTC 24 |
544392317847 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.1553387797 |
|
|
Aug 27 10:50:35 AM UTC 24 |
Aug 27 10:53:57 AM UTC 24 |
10174558261 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all.1294686368 |
|
|
Aug 27 09:50:47 AM UTC 24 |
Aug 27 10:54:08 AM UTC 24 |
141332841269 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.1017000205 |
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Aug 27 10:52:34 AM UTC 24 |
Aug 27 10:54:14 AM UTC 24 |
3294974810 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.573876146 |
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|
Aug 27 10:54:09 AM UTC 24 |
Aug 27 10:54:16 AM UTC 24 |
1367288690 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.2924940346 |
|
|
Aug 27 10:44:28 AM UTC 24 |
Aug 27 10:54:24 AM UTC 24 |
69248224796 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_regwen.2982906726 |
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Aug 27 10:53:58 AM UTC 24 |
Aug 27 10:54:45 AM UTC 24 |
7018814949 ps |