| T552 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.2220471877 |
|
|
Aug 27 10:53:07 AM UTC 24 |
Aug 27 10:54:45 AM UTC 24 |
15442242952 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_alert_test.1707645606 |
|
|
Aug 27 10:54:46 AM UTC 24 |
Aug 27 10:54:48 AM UTC 24 |
21626806 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_regwen.4047689827 |
|
|
Aug 27 10:46:17 AM UTC 24 |
Aug 27 10:54:58 AM UTC 24 |
7124225840 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all.695143065 |
|
|
Aug 27 10:10:19 AM UTC 24 |
Aug 27 10:55:03 AM UTC 24 |
60152821452 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.1756780664 |
|
|
Aug 27 10:49:30 AM UTC 24 |
Aug 27 10:55:15 AM UTC 24 |
31349557104 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_smoke.1850846938 |
|
|
Aug 27 10:54:49 AM UTC 24 |
Aug 27 10:55:15 AM UTC 24 |
1250242112 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.588136791 |
|
|
Aug 27 10:54:24 AM UTC 24 |
Aug 27 10:55:26 AM UTC 24 |
5145739944 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access.996498199 |
|
|
Aug 27 10:55:16 AM UTC 24 |
Aug 27 10:55:53 AM UTC 24 |
1569205088 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.3751913963 |
|
|
Aug 27 10:43:25 AM UTC 24 |
Aug 27 10:56:04 AM UTC 24 |
25047852394 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.88373779 |
|
|
Aug 27 10:54:58 AM UTC 24 |
Aug 27 10:56:13 AM UTC 24 |
10321779686 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.221272915 |
|
|
Aug 27 10:56:05 AM UTC 24 |
Aug 27 10:56:23 AM UTC 24 |
1807947708 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.1346207859 |
|
|
Aug 27 10:55:54 AM UTC 24 |
Aug 27 10:56:35 AM UTC 24 |
3038264492 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.3060515060 |
|
|
Aug 27 10:48:12 AM UTC 24 |
Aug 27 10:56:36 AM UTC 24 |
19036429782 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.13458817 |
|
|
Aug 27 10:50:31 AM UTC 24 |
Aug 27 10:57:01 AM UTC 24 |
55269851136 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.982951595 |
|
|
Aug 27 10:57:03 AM UTC 24 |
Aug 27 10:57:10 AM UTC 24 |
1408176359 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.1702839771 |
|
|
Aug 27 10:54:17 AM UTC 24 |
Aug 27 10:57:23 AM UTC 24 |
4746901752 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.958616375 |
|
|
Aug 27 10:52:33 AM UTC 24 |
Aug 27 10:57:41 AM UTC 24 |
22163414974 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.3172779086 |
|
|
Aug 27 10:51:48 AM UTC 24 |
Aug 27 10:57:44 AM UTC 24 |
3394363516 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.3465094594 |
|
|
Aug 27 10:57:42 AM UTC 24 |
Aug 27 10:58:16 AM UTC 24 |
1790392260 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_alert_test.2254245102 |
|
|
Aug 27 10:58:17 AM UTC 24 |
Aug 27 10:58:20 AM UTC 24 |
11777194 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.2751219543 |
|
|
Aug 27 10:56:14 AM UTC 24 |
Aug 27 10:58:25 AM UTC 24 |
21646798047 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all.1574864966 |
|
|
Aug 27 10:24:05 AM UTC 24 |
Aug 27 11:00:05 AM UTC 24 |
19559723409 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_smoke.878754134 |
|
|
Aug 27 10:58:20 AM UTC 24 |
Aug 27 11:00:12 AM UTC 24 |
5425403487 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.1312955166 |
|
|
Aug 27 10:57:24 AM UTC 24 |
Aug 27 11:00:18 AM UTC 24 |
2444328277 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.1264811326 |
|
|
Aug 27 10:55:16 AM UTC 24 |
Aug 27 11:00:18 AM UTC 24 |
15660379696 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.13701097 |
|
|
Aug 27 10:53:25 AM UTC 24 |
Aug 27 11:00:24 AM UTC 24 |
8509460478 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.2816241417 |
|
|
Aug 27 10:54:15 AM UTC 24 |
Aug 27 11:00:30 AM UTC 24 |
13815500764 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_bijection.345486382 |
|
|
Aug 27 10:11:08 AM UTC 24 |
Aug 27 11:00:41 AM UTC 24 |
849271019860 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access.2347468842 |
|
|
Aug 27 11:00:19 AM UTC 24 |
Aug 27 11:00:55 AM UTC 24 |
29209192867 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all.312419992 |
|
|
Aug 27 09:19:16 AM UTC 24 |
Aug 27 11:01:15 AM UTC 24 |
990500026364 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_bijection.2589482748 |
|
|
Aug 27 10:47:57 AM UTC 24 |
Aug 27 11:01:18 AM UTC 24 |
36140227450 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.3461525469 |
|
|
Aug 27 10:57:11 AM UTC 24 |
Aug 27 11:01:19 AM UTC 24 |
14460378028 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all.4238687122 |
|
|
Aug 27 09:29:04 AM UTC 24 |
Aug 27 11:01:25 AM UTC 24 |
94049192678 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.4266532874 |
|
|
Aug 27 11:01:20 AM UTC 24 |
Aug 27 11:01:26 AM UTC 24 |
367798952 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_regwen.1498664392 |
|
|
Aug 27 10:56:38 AM UTC 24 |
Aug 27 11:01:31 AM UTC 24 |
24003895743 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.96986715 |
|
|
Aug 27 10:51:08 AM UTC 24 |
Aug 27 11:01:37 AM UTC 24 |
65344772328 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.2438308503 |
|
|
Aug 27 11:00:31 AM UTC 24 |
Aug 27 11:01:41 AM UTC 24 |
772503306 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_alert_test.385871698 |
|
|
Aug 27 11:01:42 AM UTC 24 |
Aug 27 11:01:44 AM UTC 24 |
25642407 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.2416663780 |
|
|
Aug 27 11:00:42 AM UTC 24 |
Aug 27 11:01:51 AM UTC 24 |
25008181670 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.1219757216 |
|
|
Aug 27 11:00:25 AM UTC 24 |
Aug 27 11:02:08 AM UTC 24 |
8403058907 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.3244578142 |
|
|
Aug 27 10:58:26 AM UTC 24 |
Aug 27 11:02:20 AM UTC 24 |
8361629010 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_smoke.3601718037 |
|
|
Aug 27 11:01:45 AM UTC 24 |
Aug 27 11:02:22 AM UTC 24 |
1342080131 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.626379362 |
|
|
Aug 27 10:55:27 AM UTC 24 |
Aug 27 11:02:36 AM UTC 24 |
16135044756 ps |
| T48 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.2805689603 |
|
|
Aug 27 11:01:32 AM UTC 24 |
Aug 27 11:02:38 AM UTC 24 |
2213713614 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.1876352577 |
|
|
Aug 27 11:01:27 AM UTC 24 |
Aug 27 11:02:43 AM UTC 24 |
7375941590 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access.1587567554 |
|
|
Aug 27 11:02:22 AM UTC 24 |
Aug 27 11:02:43 AM UTC 24 |
3091372582 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.677456233 |
|
|
Aug 27 10:47:54 AM UTC 24 |
Aug 27 11:02:45 AM UTC 24 |
54166060947 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_bijection.1840088859 |
|
|
Aug 27 10:17:35 AM UTC 24 |
Aug 27 11:03:09 AM UTC 24 |
105902587889 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all.2337868370 |
|
|
Aug 27 09:31:56 AM UTC 24 |
Aug 27 11:03:17 AM UTC 24 |
603293794317 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.2464267963 |
|
|
Aug 27 11:02:44 AM UTC 24 |
Aug 27 11:03:24 AM UTC 24 |
1271842444 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.3539362439 |
|
|
Aug 27 11:03:25 AM UTC 24 |
Aug 27 11:03:32 AM UTC 24 |
1406688746 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.1229995409 |
|
|
Aug 27 11:02:45 AM UTC 24 |
Aug 27 11:04:05 AM UTC 24 |
7948281044 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.921715552 |
|
|
Aug 27 11:02:38 AM UTC 24 |
Aug 27 11:04:06 AM UTC 24 |
769983909 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.1895141301 |
|
|
Aug 27 11:01:26 AM UTC 24 |
Aug 27 11:04:27 AM UTC 24 |
9550101208 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_bijection.409232822 |
|
|
Aug 27 10:43:27 AM UTC 24 |
Aug 27 11:04:56 AM UTC 24 |
66952413402 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.1195573897 |
|
|
Aug 27 10:46:06 AM UTC 24 |
Aug 27 11:04:59 AM UTC 24 |
80877745915 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_alert_test.171961283 |
|
|
Aug 27 11:04:57 AM UTC 24 |
Aug 27 11:04:59 AM UTC 24 |
12019042 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.2398121567 |
|
|
Aug 27 11:00:13 AM UTC 24 |
Aug 27 11:05:09 AM UTC 24 |
4897467676 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_smoke.1252336955 |
|
|
Aug 27 11:05:00 AM UTC 24 |
Aug 27 11:05:09 AM UTC 24 |
1049438849 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all.588452835 |
|
|
Aug 27 10:34:37 AM UTC 24 |
Aug 27 11:05:53 AM UTC 24 |
178152970994 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access.160327726 |
|
|
Aug 27 11:05:55 AM UTC 24 |
Aug 27 11:06:13 AM UTC 24 |
1998604953 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.3566885754 |
|
|
Aug 27 11:02:36 AM UTC 24 |
Aug 27 11:06:28 AM UTC 24 |
2668212842 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_bijection.1925267581 |
|
|
Aug 27 10:21:10 AM UTC 24 |
Aug 27 11:06:36 AM UTC 24 |
105557110406 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.2458851507 |
|
|
Aug 27 11:02:46 AM UTC 24 |
Aug 27 11:06:37 AM UTC 24 |
4030167750 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.825424053 |
|
|
Aug 27 11:03:33 AM UTC 24 |
Aug 27 11:06:39 AM UTC 24 |
9361946011 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.574984186 |
|
|
Aug 27 11:00:19 AM UTC 24 |
Aug 27 11:06:41 AM UTC 24 |
11204937390 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.3639248816 |
|
|
Aug 27 11:04:05 AM UTC 24 |
Aug 27 11:06:55 AM UTC 24 |
23489838040 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.851819995 |
|
|
Aug 27 11:06:38 AM UTC 24 |
Aug 27 11:06:56 AM UTC 24 |
5306680668 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.3550560347 |
|
|
Aug 27 10:56:24 AM UTC 24 |
Aug 27 11:07:01 AM UTC 24 |
17802287333 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.2529391386 |
|
|
Aug 27 11:06:57 AM UTC 24 |
Aug 27 11:07:03 AM UTC 24 |
368573764 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.2714907940 |
|
|
Aug 27 11:06:36 AM UTC 24 |
Aug 27 11:07:08 AM UTC 24 |
2892969222 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.3791638740 |
|
|
Aug 27 11:06:29 AM UTC 24 |
Aug 27 11:07:13 AM UTC 24 |
9073497685 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.2823511879 |
|
|
Aug 27 11:07:09 AM UTC 24 |
Aug 27 11:07:22 AM UTC 24 |
935337388 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_alert_test.707374212 |
|
|
Aug 27 11:07:22 AM UTC 24 |
Aug 27 11:07:25 AM UTC 24 |
15531456 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.3318323946 |
|
|
Aug 27 11:04:07 AM UTC 24 |
Aug 27 11:07:28 AM UTC 24 |
2545409947 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_bijection.3594928977 |
|
|
Aug 27 10:31:27 AM UTC 24 |
Aug 27 11:07:31 AM UTC 24 |
27396342242 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.1659001558 |
|
|
Aug 27 11:07:28 AM UTC 24 |
Aug 27 11:08:02 AM UTC 24 |
1575709728 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all.1294730260 |
|
|
Aug 27 10:03:47 AM UTC 24 |
Aug 27 11:08:30 AM UTC 24 |
144218714309 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access.2371723825 |
|
|
Aug 27 11:08:31 AM UTC 24 |
Aug 27 11:08:57 AM UTC 24 |
3293407950 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.2433254668 |
|
|
Aug 27 11:02:21 AM UTC 24 |
Aug 27 11:09:10 AM UTC 24 |
5306591334 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_smoke.1763151387 |
|
|
Aug 27 11:07:25 AM UTC 24 |
Aug 27 11:09:10 AM UTC 24 |
998151494 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_executable.2015858940 |
|
|
Aug 27 10:37:40 AM UTC 24 |
Aug 27 11:09:20 AM UTC 24 |
294286274229 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_regwen.3820560140 |
|
|
Aug 27 10:50:08 AM UTC 24 |
Aug 27 11:09:22 AM UTC 24 |
19785082436 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.2691654176 |
|
|
Aug 27 11:09:11 AM UTC 24 |
Aug 27 11:09:23 AM UTC 24 |
712312651 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.4160970948 |
|
|
Aug 27 11:09:11 AM UTC 24 |
Aug 27 11:09:24 AM UTC 24 |
2686942796 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.3910722222 |
|
|
Aug 27 11:07:04 AM UTC 24 |
Aug 27 11:09:36 AM UTC 24 |
5026013367 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.3362393282 |
|
|
Aug 27 11:09:37 AM UTC 24 |
Aug 27 11:09:43 AM UTC 24 |
682807792 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_regwen.3751644724 |
|
|
Aug 27 11:09:25 AM UTC 24 |
Aug 27 11:09:55 AM UTC 24 |
2523094959 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_executable.513121474 |
|
|
Aug 27 11:03:10 AM UTC 24 |
Aug 27 11:09:57 AM UTC 24 |
16023563611 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.1984239564 |
|
|
Aug 27 11:05:10 AM UTC 24 |
Aug 27 11:10:08 AM UTC 24 |
20361506985 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all.2070098958 |
|
|
Aug 27 10:20:35 AM UTC 24 |
Aug 27 11:10:39 AM UTC 24 |
23033500504 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_alert_test.3090119237 |
|
|
Aug 27 11:10:40 AM UTC 24 |
Aug 27 11:10:42 AM UTC 24 |
24768423 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.4052729832 |
|
|
Aug 27 11:08:03 AM UTC 24 |
Aug 27 11:10:51 AM UTC 24 |
2861175734 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.649681437 |
|
|
Aug 27 11:09:20 AM UTC 24 |
Aug 27 11:11:10 AM UTC 24 |
10747299649 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.275028556 |
|
|
Aug 27 11:06:14 AM UTC 24 |
Aug 27 11:11:21 AM UTC 24 |
12143943419 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.503268411 |
|
|
Aug 27 11:09:56 AM UTC 24 |
Aug 27 11:11:51 AM UTC 24 |
46979248191 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_smoke.810550175 |
|
|
Aug 27 11:10:43 AM UTC 24 |
Aug 27 11:11:58 AM UTC 24 |
1727386333 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.3061712187 |
|
|
Aug 27 11:07:02 AM UTC 24 |
Aug 27 11:12:12 AM UTC 24 |
43791952687 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.2027501334 |
|
|
Aug 27 11:09:57 AM UTC 24 |
Aug 27 11:12:25 AM UTC 24 |
2593924231 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.482413868 |
|
|
Aug 27 11:12:13 AM UTC 24 |
Aug 27 11:12:51 AM UTC 24 |
752227255 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.3929235624 |
|
|
Aug 27 11:12:27 AM UTC 24 |
Aug 27 11:13:15 AM UTC 24 |
764579534 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access.2881928166 |
|
|
Aug 27 11:11:52 AM UTC 24 |
Aug 27 11:13:42 AM UTC 24 |
1279410215 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_regwen.1741730853 |
|
|
Aug 27 11:06:56 AM UTC 24 |
Aug 27 11:13:43 AM UTC 24 |
7711063443 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.398654936 |
|
|
Aug 27 11:13:44 AM UTC 24 |
Aug 27 11:13:52 AM UTC 24 |
1876787971 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.3991708480 |
|
|
Aug 27 11:05:00 AM UTC 24 |
Aug 27 11:14:14 AM UTC 24 |
7380144979 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.245988214 |
|
|
Aug 27 11:12:52 AM UTC 24 |
Aug 27 11:14:30 AM UTC 24 |
27751112674 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.987511456 |
|
|
Aug 27 11:09:44 AM UTC 24 |
Aug 27 11:14:39 AM UTC 24 |
30881171378 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.381356136 |
|
|
Aug 27 11:08:57 AM UTC 24 |
Aug 27 11:14:40 AM UTC 24 |
23301437644 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_regwen.3408756927 |
|
|
Aug 27 11:13:42 AM UTC 24 |
Aug 27 11:14:41 AM UTC 24 |
2808507210 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_alert_test.4218074138 |
|
|
Aug 27 11:14:40 AM UTC 24 |
Aug 27 11:14:42 AM UTC 24 |
18373860 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_smoke.1940544083 |
|
|
Aug 27 11:14:41 AM UTC 24 |
Aug 27 11:15:04 AM UTC 24 |
1636986192 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.398240580 |
|
|
Aug 27 11:14:08 AM UTC 24 |
Aug 27 11:15:28 AM UTC 24 |
13163310247 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_executable.2735970192 |
|
|
Aug 27 11:01:16 AM UTC 24 |
Aug 27 11:15:30 AM UTC 24 |
83506537636 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access.3840934894 |
|
|
Aug 27 11:15:29 AM UTC 24 |
Aug 27 11:15:51 AM UTC 24 |
2190764042 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all.3075738851 |
|
|
Aug 27 09:53:17 AM UTC 24 |
Aug 27 11:15:58 AM UTC 24 |
486381971706 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.3000476032 |
|
|
Aug 27 11:15:59 AM UTC 24 |
Aug 27 11:16:15 AM UTC 24 |
732279026 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_regwen.1249280426 |
|
|
Aug 27 11:01:19 AM UTC 24 |
Aug 27 11:16:17 AM UTC 24 |
12978662494 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_executable.2141528139 |
|
|
Aug 27 11:06:41 AM UTC 24 |
Aug 27 11:16:21 AM UTC 24 |
12839927019 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.3172011144 |
|
|
Aug 27 11:11:21 AM UTC 24 |
Aug 27 11:16:35 AM UTC 24 |
3704904182 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.3273041514 |
|
|
Aug 27 11:00:57 AM UTC 24 |
Aug 27 11:16:49 AM UTC 24 |
32047346940 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.4237788653 |
|
|
Aug 27 11:16:50 AM UTC 24 |
Aug 27 11:16:56 AM UTC 24 |
365093584 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all.2302978077 |
|
|
Aug 27 09:47:31 AM UTC 24 |
Aug 27 11:17:09 AM UTC 24 |
258335418080 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.2494481653 |
|
|
Aug 27 11:16:16 AM UTC 24 |
Aug 27 11:17:10 AM UTC 24 |
36390560740 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.819952770 |
|
|
Aug 27 11:13:52 AM UTC 24 |
Aug 27 11:17:30 AM UTC 24 |
10475167041 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.290111341 |
|
|
Aug 27 11:15:52 AM UTC 24 |
Aug 27 11:17:30 AM UTC 24 |
3450576645 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_alert_test.1543797441 |
|
|
Aug 27 11:17:31 AM UTC 24 |
Aug 27 11:17:33 AM UTC 24 |
40980570 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.308168642 |
|
|
Aug 27 11:17:11 AM UTC 24 |
Aug 27 11:17:54 AM UTC 24 |
1009789597 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_smoke.2068597037 |
|
|
Aug 27 11:17:34 AM UTC 24 |
Aug 27 11:18:02 AM UTC 24 |
2035298679 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_executable.4246879301 |
|
|
Aug 27 10:56:36 AM UTC 24 |
Aug 27 11:18:33 AM UTC 24 |
110296733551 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_executable.829755034 |
|
|
Aug 27 10:53:56 AM UTC 24 |
Aug 27 11:19:11 AM UTC 24 |
75271213091 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.60289573 |
|
|
Aug 27 11:10:52 AM UTC 24 |
Aug 27 11:19:14 AM UTC 24 |
82154893830 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.3579724306 |
|
|
Aug 27 11:14:15 AM UTC 24 |
Aug 27 11:19:19 AM UTC 24 |
2040477349 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.3106393412 |
|
|
Aug 27 11:09:22 AM UTC 24 |
Aug 27 11:19:35 AM UTC 24 |
26861383631 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.528887870 |
|
|
Aug 27 11:11:59 AM UTC 24 |
Aug 27 11:19:42 AM UTC 24 |
14825458425 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.512904184 |
|
|
Aug 27 11:17:10 AM UTC 24 |
Aug 27 11:19:53 AM UTC 24 |
3932156179 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access.942976407 |
|
|
Aug 27 11:19:12 AM UTC 24 |
Aug 27 11:19:54 AM UTC 24 |
4736720882 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.4200363067 |
|
|
Aug 27 11:19:35 AM UTC 24 |
Aug 27 11:19:56 AM UTC 24 |
1479370981 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.1425637886 |
|
|
Aug 27 11:19:43 AM UTC 24 |
Aug 27 11:20:29 AM UTC 24 |
4587383045 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.3020510342 |
|
|
Aug 27 11:01:52 AM UTC 24 |
Aug 27 11:20:32 AM UTC 24 |
101222670257 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.372499801 |
|
|
Aug 27 11:20:30 AM UTC 24 |
Aug 27 11:20:38 AM UTC 24 |
6714054138 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.3131542637 |
|
|
Aug 27 11:19:20 AM UTC 24 |
Aug 27 11:21:12 AM UTC 24 |
1561974731 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.1910103786 |
|
|
Aug 27 11:15:05 AM UTC 24 |
Aug 27 11:21:23 AM UTC 24 |
5405308138 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all.4127791406 |
|
|
Aug 27 10:39:07 AM UTC 24 |
Aug 27 11:21:24 AM UTC 24 |
58640040607 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.542131524 |
|
|
Aug 27 11:06:39 AM UTC 24 |
Aug 27 11:21:26 AM UTC 24 |
38155831025 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_alert_test.2190014715 |
|
|
Aug 27 11:21:24 AM UTC 24 |
Aug 27 11:21:26 AM UTC 24 |
37640246 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.206493423 |
|
|
Aug 27 11:16:57 AM UTC 24 |
Aug 27 11:21:27 AM UTC 24 |
43178136889 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_smoke.719882519 |
|
|
Aug 27 11:21:26 AM UTC 24 |
Aug 27 11:21:48 AM UTC 24 |
1352419593 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.1964302348 |
|
|
Aug 27 11:13:09 AM UTC 24 |
Aug 27 11:21:51 AM UTC 24 |
10257736333 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.3974429291 |
|
|
Aug 27 11:15:31 AM UTC 24 |
Aug 27 11:22:03 AM UTC 24 |
117380648448 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access.1318141202 |
|
|
Aug 27 11:21:52 AM UTC 24 |
Aug 27 11:22:04 AM UTC 24 |
2841526271 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.2373210317 |
|
|
Aug 27 11:20:39 AM UTC 24 |
Aug 27 11:22:12 AM UTC 24 |
5764861295 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.1994500712 |
|
|
Aug 27 11:22:05 AM UTC 24 |
Aug 27 11:22:23 AM UTC 24 |
729383616 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.1830643834 |
|
|
Aug 27 11:21:13 AM UTC 24 |
Aug 27 11:22:32 AM UTC 24 |
1997574362 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.1751998293 |
|
|
Aug 27 11:22:24 AM UTC 24 |
Aug 27 11:22:55 AM UTC 24 |
17774070230 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_bijection.2651520982 |
|
|
Aug 27 11:02:09 AM UTC 24 |
Aug 27 11:23:23 AM UTC 24 |
98357436877 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.2660910159 |
|
|
Aug 27 11:18:34 AM UTC 24 |
Aug 27 11:23:33 AM UTC 24 |
7604404017 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.1101327265 |
|
|
Aug 27 11:22:12 AM UTC 24 |
Aug 27 11:23:34 AM UTC 24 |
1663050413 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.1086498812 |
|
|
Aug 27 11:23:34 AM UTC 24 |
Aug 27 11:23:41 AM UTC 24 |
352769520 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_regwen.3528650626 |
|
|
Aug 27 11:03:18 AM UTC 24 |
Aug 27 11:23:58 AM UTC 24 |
15310613949 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_all.183796814 |
|
|
Aug 27 10:00:40 AM UTC 24 |
Aug 27 11:24:11 AM UTC 24 |
175513098151 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_regwen.4159520019 |
|
|
Aug 27 11:16:36 AM UTC 24 |
Aug 27 11:24:29 AM UTC 24 |
8605086126 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_alert_test.1019548477 |
|
|
Aug 27 11:24:30 AM UTC 24 |
Aug 27 11:24:33 AM UTC 24 |
29802378 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_smoke.3595835276 |
|
|
Aug 27 11:24:34 AM UTC 24 |
Aug 27 11:24:55 AM UTC 24 |
987001497 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.2118006632 |
|
|
Aug 27 11:23:42 AM UTC 24 |
Aug 27 11:25:04 AM UTC 24 |
2386064448 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_executable.3311173670 |
|
|
Aug 27 11:16:21 AM UTC 24 |
Aug 27 11:25:21 AM UTC 24 |
15609941661 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.1614890991 |
|
|
Aug 27 11:14:42 AM UTC 24 |
Aug 27 11:25:22 AM UTC 24 |
34533181523 ps |
| T47 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.2272105976 |
|
|
Aug 27 11:23:59 AM UTC 24 |
Aug 27 11:25:24 AM UTC 24 |
1645339541 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access.336847662 |
|
|
Aug 27 11:25:23 AM UTC 24 |
Aug 27 11:25:38 AM UTC 24 |
1491972365 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.2582380208 |
|
|
Aug 27 11:25:39 AM UTC 24 |
Aug 27 11:25:51 AM UTC 24 |
3731534503 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_bijection.3692898099 |
|
|
Aug 27 11:05:10 AM UTC 24 |
Aug 27 11:25:57 AM UTC 24 |
21120032512 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.1929378960 |
|
|
Aug 27 11:23:35 AM UTC 24 |
Aug 27 11:26:00 AM UTC 24 |
2059616114 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.1417600184 |
|
|
Aug 27 11:20:33 AM UTC 24 |
Aug 27 11:26:48 AM UTC 24 |
13796915310 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.313249447 |
|
|
Aug 27 11:24:57 AM UTC 24 |
Aug 27 11:26:52 AM UTC 24 |
5849628012 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.3511379094 |
|
|
Aug 27 11:19:14 AM UTC 24 |
Aug 27 11:27:02 AM UTC 24 |
17479292433 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.3947173020 |
|
|
Aug 27 11:27:02 AM UTC 24 |
Aug 27 11:27:09 AM UTC 24 |
1527769852 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_regwen.3528764990 |
|
|
Aug 27 11:19:57 AM UTC 24 |
Aug 27 11:27:23 AM UTC 24 |
25556409630 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.1781849066 |
|
|
Aug 27 11:25:51 AM UTC 24 |
Aug 27 11:27:24 AM UTC 24 |
790137490 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.1018822892 |
|
|
Aug 27 11:22:04 AM UTC 24 |
Aug 27 11:27:28 AM UTC 24 |
12343550801 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.1619991586 |
|
|
Aug 27 11:25:21 AM UTC 24 |
Aug 27 11:28:06 AM UTC 24 |
3444648157 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_alert_test.3469520333 |
|
|
Aug 27 11:28:07 AM UTC 24 |
Aug 27 11:28:09 AM UTC 24 |
15192991 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.3620496796 |
|
|
Aug 27 11:21:49 AM UTC 24 |
Aug 27 11:28:38 AM UTC 24 |
5146711463 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.442861443 |
|
|
Aug 27 11:25:57 AM UTC 24 |
Aug 27 11:28:42 AM UTC 24 |
62823717049 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_smoke.517164647 |
|
|
Aug 27 11:28:10 AM UTC 24 |
Aug 27 11:28:48 AM UTC 24 |
1998571452 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all.3257298027 |
|
|
Aug 27 10:30:55 AM UTC 24 |
Aug 27 11:28:52 AM UTC 24 |
144769738725 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.4239018701 |
|
|
Aug 27 11:27:23 AM UTC 24 |
Aug 27 11:29:07 AM UTC 24 |
2650658657 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access.1895180293 |
|
|
Aug 27 11:28:53 AM UTC 24 |
Aug 27 11:29:13 AM UTC 24 |
565505623 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_bijection.1626384447 |
|
|
Aug 27 11:07:32 AM UTC 24 |
Aug 27 11:29:29 AM UTC 24 |
52558717703 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_bijection.1640189786 |
|
|
Aug 27 11:11:11 AM UTC 24 |
Aug 27 11:29:49 AM UTC 24 |
230978265042 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.282629653 |
|
|
Aug 27 11:27:26 AM UTC 24 |
Aug 27 11:29:54 AM UTC 24 |
30098747426 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.3120094687 |
|
|
Aug 27 11:29:50 AM UTC 24 |
Aug 27 11:30:34 AM UTC 24 |
7171617610 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.4165755264 |
|
|
Aug 27 11:29:30 AM UTC 24 |
Aug 27 11:30:47 AM UTC 24 |
898273580 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.1203748395 |
|
|
Aug 27 11:29:14 AM UTC 24 |
Aug 27 11:30:53 AM UTC 24 |
3048480871 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.3780601702 |
|
|
Aug 27 11:30:54 AM UTC 24 |
Aug 27 11:31:01 AM UTC 24 |
352319133 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all.1573850316 |
|
|
Aug 27 10:29:01 AM UTC 24 |
Aug 27 11:32:11 AM UTC 24 |
45680068303 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.2348399861 |
|
|
Aug 27 11:22:32 AM UTC 24 |
Aug 27 11:33:14 AM UTC 24 |
12288583055 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.908586550 |
|
|
Aug 27 11:25:25 AM UTC 24 |
Aug 27 11:33:19 AM UTC 24 |
36235912167 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_regwen.2310137060 |
|
|
Aug 27 11:26:53 AM UTC 24 |
Aug 27 11:33:31 AM UTC 24 |
19987466268 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_alert_test.323949384 |
|
|
Aug 27 11:33:32 AM UTC 24 |
Aug 27 11:33:34 AM UTC 24 |
19973899 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_smoke.494076198 |
|
|
Aug 27 11:33:35 AM UTC 24 |
Aug 27 11:33:49 AM UTC 24 |
1461054657 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_regwen.2970910332 |
|
|
Aug 27 11:23:24 AM UTC 24 |
Aug 27 11:33:57 AM UTC 24 |
47995232479 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_executable.1822662612 |
|
|
Aug 27 11:13:16 AM UTC 24 |
Aug 27 11:34:02 AM UTC 24 |
22005988676 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.1292298469 |
|
|
Aug 27 11:27:10 AM UTC 24 |
Aug 27 11:34:05 AM UTC 24 |
28786926180 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_regwen.2160303212 |
|
|
Aug 27 11:30:49 AM UTC 24 |
Aug 27 11:34:33 AM UTC 24 |
18651400894 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_bijection.2992277515 |
|
|
Aug 27 10:51:14 AM UTC 24 |
Aug 27 11:34:36 AM UTC 24 |
64891406811 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access.3771480696 |
|
|
Aug 27 11:34:06 AM UTC 24 |
Aug 27 11:34:53 AM UTC 24 |
4301766631 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.738622144 |
|
|
Aug 27 11:31:02 AM UTC 24 |
Aug 27 11:35:01 AM UTC 24 |
33047434746 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_bijection.2055071683 |
|
|
Aug 27 10:40:06 AM UTC 24 |
Aug 27 11:35:09 AM UTC 24 |
690532254875 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.562951619 |
|
|
Aug 27 11:19:53 AM UTC 24 |
Aug 27 11:35:09 AM UTC 24 |
30845778783 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.3998789114 |
|
|
Aug 27 11:34:44 AM UTC 24 |
Aug 27 11:35:14 AM UTC 24 |
769419710 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.3433808604 |
|
|
Aug 27 11:35:14 AM UTC 24 |
Aug 27 11:35:21 AM UTC 24 |
367187592 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_executable.858165433 |
|
|
Aug 27 11:30:34 AM UTC 24 |
Aug 27 11:35:27 AM UTC 24 |
7424112249 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.1335155754 |
|
|
Aug 27 11:34:37 AM UTC 24 |
Aug 27 11:35:52 AM UTC 24 |
3216404401 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.20467815 |
|
|
Aug 27 11:32:12 AM UTC 24 |
Aug 27 11:35:55 AM UTC 24 |
5341807831 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_executable.505910325 |
|
|
Aug 27 11:19:54 AM UTC 24 |
Aug 27 11:36:53 AM UTC 24 |
11700771409 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_alert_test.3495328653 |
|
|
Aug 27 11:36:53 AM UTC 24 |
Aug 27 11:36:55 AM UTC 24 |
42211796 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_smoke.916015496 |
|
|
Aug 27 11:36:56 AM UTC 24 |
Aug 27 11:37:14 AM UTC 24 |
455308701 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_executable.3413642014 |
|
|
Aug 27 11:26:49 AM UTC 24 |
Aug 27 11:37:31 AM UTC 24 |
29541295635 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.2623648940 |
|
|
Aug 27 11:35:22 AM UTC 24 |
Aug 27 11:38:09 AM UTC 24 |
15473168797 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.3529617983 |
|
|
Aug 27 11:35:53 AM UTC 24 |
Aug 27 11:38:16 AM UTC 24 |
2376008897 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.1401887541 |
|
|
Aug 27 11:34:54 AM UTC 24 |
Aug 27 11:38:17 AM UTC 24 |
140743348916 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.2247464725 |
|
|
Aug 27 11:28:48 AM UTC 24 |
Aug 27 11:38:19 AM UTC 24 |
5569676181 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.2844215240 |
|
|
Aug 27 11:35:29 AM UTC 24 |
Aug 27 11:38:26 AM UTC 24 |
6382180431 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access.4215242217 |
|
|
Aug 27 11:38:17 AM UTC 24 |
Aug 27 11:38:30 AM UTC 24 |
2100979540 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_executable.996407777 |
|
|
Aug 27 11:22:56 AM UTC 24 |
Aug 27 11:38:32 AM UTC 24 |
18150536602 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.2106167204 |
|
|
Aug 27 11:38:19 AM UTC 24 |
Aug 27 11:38:43 AM UTC 24 |
3266949476 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.3894960925 |
|
|
Aug 27 11:29:08 AM UTC 24 |
Aug 27 11:39:13 AM UTC 24 |
76620964652 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.3897941961 |
|
|
Aug 27 11:38:31 AM UTC 24 |
Aug 27 11:39:16 AM UTC 24 |
4718105070 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.275054669 |
|
|
Aug 27 11:39:17 AM UTC 24 |
Aug 27 11:39:24 AM UTC 24 |
347092334 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.3998091704 |
|
|
Aug 27 11:38:27 AM UTC 24 |
Aug 27 11:39:29 AM UTC 24 |
3113297373 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all.714765928 |
|
|
Aug 27 10:47:07 AM UTC 24 |
Aug 27 11:39:33 AM UTC 24 |
168632510328 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.2808094478 |
|
|
Aug 27 11:34:34 AM UTC 24 |
Aug 27 11:39:45 AM UTC 24 |
41824667764 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.2376837005 |
|
|
Aug 27 11:39:34 AM UTC 24 |
Aug 27 11:40:18 AM UTC 24 |
2105643153 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_alert_test.3671474452 |
|
|
Aug 27 11:40:19 AM UTC 24 |
Aug 27 11:40:21 AM UTC 24 |
29256781 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.3106631752 |
|
|
Aug 27 11:34:03 AM UTC 24 |
Aug 27 11:40:40 AM UTC 24 |
16043993064 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_smoke.3318061021 |
|
|
Aug 27 11:40:22 AM UTC 24 |
Aug 27 11:40:46 AM UTC 24 |
535062862 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_executable.548321045 |
|
|
Aug 27 11:35:10 AM UTC 24 |
Aug 27 11:41:14 AM UTC 24 |
14701741311 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.3556587212 |
|
|
Aug 27 11:39:29 AM UTC 24 |
Aug 27 11:42:20 AM UTC 24 |
5810965307 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.2847032193 |
|
|
Aug 27 11:33:50 AM UTC 24 |
Aug 27 11:42:48 AM UTC 24 |
30885883314 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access.1035417314 |
|
|
Aug 27 11:42:22 AM UTC 24 |
Aug 27 11:42:51 AM UTC 24 |
762307910 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_bijection.2693150374 |
|
|
Aug 27 11:00:07 AM UTC 24 |
Aug 27 11:42:59 AM UTC 24 |
517800605972 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.3492132667 |
|
|
Aug 27 11:21:27 AM UTC 24 |
Aug 27 11:43:04 AM UTC 24 |
23265426042 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.657478120 |
|
|
Aug 27 11:42:52 AM UTC 24 |
Aug 27 11:43:52 AM UTC 24 |
2957411350 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.2659749815 |
|
|
Aug 27 11:37:15 AM UTC 24 |
Aug 27 11:43:53 AM UTC 24 |
17503546902 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.1955688676 |
|
|
Aug 27 11:43:05 AM UTC 24 |
Aug 27 11:44:07 AM UTC 24 |
24395906741 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.2874004978 |
|
|
Aug 27 11:43:00 AM UTC 24 |
Aug 27 11:44:35 AM UTC 24 |
804004459 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.4283082240 |
|
|
Aug 27 11:17:54 AM UTC 24 |
Aug 27 11:44:35 AM UTC 24 |
69544997701 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.567778642 |
|
|
Aug 27 11:44:36 AM UTC 24 |
Aug 27 11:44:42 AM UTC 24 |
373271925 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.2513501212 |
|
|
Aug 27 11:38:10 AM UTC 24 |
Aug 27 11:44:44 AM UTC 24 |
15751553241 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.2832849558 |
|
|
Aug 27 11:39:25 AM UTC 24 |
Aug 27 11:45:26 AM UTC 24 |
5255449289 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all.3264862808 |
|
|
Aug 27 10:42:43 AM UTC 24 |
Aug 27 11:45:30 AM UTC 24 |
184140321352 ps |