| T800 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_alert_test.932466849 |
|
|
Aug 27 11:45:32 AM UTC 24 |
Aug 27 11:45:33 AM UTC 24 |
15098356 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_bijection.2560344229 |
|
|
Aug 27 11:25:05 AM UTC 24 |
Aug 27 11:45:36 AM UTC 24 |
61484662270 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.3992332899 |
|
|
Aug 27 11:29:54 AM UTC 24 |
Aug 27 11:45:44 AM UTC 24 |
81936844380 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.2142487243 |
|
|
Aug 27 11:44:44 AM UTC 24 |
Aug 27 11:45:46 AM UTC 24 |
9571448590 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_smoke.798033931 |
|
|
Aug 27 11:45:35 AM UTC 24 |
Aug 27 11:45:48 AM UTC 24 |
2706115338 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all.569775502 |
|
|
Aug 27 10:54:46 AM UTC 24 |
Aug 27 11:45:48 AM UTC 24 |
48711066989 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.2071060765 |
|
|
Aug 27 11:26:02 AM UTC 24 |
Aug 27 11:46:05 AM UTC 24 |
17488984059 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_regwen.278563846 |
|
|
Aug 27 11:44:08 AM UTC 24 |
Aug 27 11:46:19 AM UTC 24 |
4681115330 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access.3409726073 |
|
|
Aug 27 11:45:49 AM UTC 24 |
Aug 27 11:46:20 AM UTC 24 |
607388068 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.910471400 |
|
|
Aug 27 11:28:38 AM UTC 24 |
Aug 27 11:46:27 AM UTC 24 |
96415369211 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.3660811153 |
|
|
Aug 27 11:46:20 AM UTC 24 |
Aug 27 11:46:36 AM UTC 24 |
4590192500 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.1904195102 |
|
|
Aug 27 11:46:20 AM UTC 24 |
Aug 27 11:47:04 AM UTC 24 |
3400020462 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.247844356 |
|
|
Aug 27 11:44:42 AM UTC 24 |
Aug 27 11:47:06 AM UTC 24 |
17510940848 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.3126419984 |
|
|
Aug 27 11:46:05 AM UTC 24 |
Aug 27 11:47:12 AM UTC 24 |
749106975 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.1830999783 |
|
|
Aug 27 11:47:07 AM UTC 24 |
Aug 27 11:47:12 AM UTC 24 |
351043784 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.2212791006 |
|
|
Aug 27 11:38:18 AM UTC 24 |
Aug 27 11:47:13 AM UTC 24 |
6539617645 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2156010444 |
|
|
Aug 27 11:47:14 AM UTC 24 |
Aug 27 11:47:29 AM UTC 24 |
173845011 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_executable.1206384646 |
|
|
Aug 27 11:43:54 AM UTC 24 |
Aug 27 11:47:33 AM UTC 24 |
17401179284 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_alert_test.556057447 |
|
|
Aug 27 11:47:34 AM UTC 24 |
Aug 27 11:47:37 AM UTC 24 |
78314715 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.221659802 |
|
|
Aug 27 11:44:36 AM UTC 24 |
Aug 27 11:47:38 AM UTC 24 |
24675629698 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.1310205202 |
|
|
Aug 27 11:16:17 AM UTC 24 |
Aug 27 11:47:47 AM UTC 24 |
44500849125 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_smoke.110393667 |
|
|
Aug 27 11:47:38 AM UTC 24 |
Aug 27 11:48:02 AM UTC 24 |
3511848296 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.2651503531 |
|
|
Aug 27 11:47:13 AM UTC 24 |
Aug 27 11:49:04 AM UTC 24 |
5219499723 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.489353225 |
|
|
Aug 27 11:41:14 AM UTC 24 |
Aug 27 11:49:11 AM UTC 24 |
6403767563 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access.1213628253 |
|
|
Aug 27 11:49:05 AM UTC 24 |
Aug 27 11:49:29 AM UTC 24 |
6182899883 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_bijection.907801440 |
|
|
Aug 27 11:14:43 AM UTC 24 |
Aug 27 11:50:20 AM UTC 24 |
100962441655 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_bijection.1210923212 |
|
|
Aug 27 11:18:03 AM UTC 24 |
Aug 27 11:50:22 AM UTC 24 |
112744221873 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.3745767431 |
|
|
Aug 27 11:49:30 AM UTC 24 |
Aug 27 11:50:30 AM UTC 24 |
3144961462 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.3485755050 |
|
|
Aug 27 11:40:41 AM UTC 24 |
Aug 27 11:51:00 AM UTC 24 |
38152746875 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.3575927246 |
|
|
Aug 27 11:47:12 AM UTC 24 |
Aug 27 11:51:17 AM UTC 24 |
37428510713 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.270805359 |
|
|
Aug 27 11:45:47 AM UTC 24 |
Aug 27 11:51:22 AM UTC 24 |
10685581386 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.3394757840 |
|
|
Aug 27 11:51:23 AM UTC 24 |
Aug 27 11:51:31 AM UTC 24 |
1400503091 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.3248537828 |
|
|
Aug 27 11:42:49 AM UTC 24 |
Aug 27 11:51:49 AM UTC 24 |
12564772707 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.2933996080 |
|
|
Aug 27 11:50:21 AM UTC 24 |
Aug 27 11:51:55 AM UTC 24 |
3528388509 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.1628053047 |
|
|
Aug 27 11:50:23 AM UTC 24 |
Aug 27 11:52:00 AM UTC 24 |
43075822206 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_bijection.1166092329 |
|
|
Aug 27 11:37:32 AM UTC 24 |
Aug 27 11:52:09 AM UTC 24 |
41652369492 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_alert_test.3618338930 |
|
|
Aug 27 11:52:10 AM UTC 24 |
Aug 27 11:52:12 AM UTC 24 |
62293626 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1834947038 |
|
|
Aug 27 11:51:56 AM UTC 24 |
Aug 27 11:52:17 AM UTC 24 |
940513636 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.4075078033 |
|
|
Aug 27 11:35:01 AM UTC 24 |
Aug 27 11:52:24 AM UTC 24 |
97764297624 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_smoke.1286722857 |
|
|
Aug 27 11:52:13 AM UTC 24 |
Aug 27 11:52:37 AM UTC 24 |
2273824059 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.1079094745 |
|
|
Aug 27 11:46:29 AM UTC 24 |
Aug 27 11:52:57 AM UTC 24 |
7828481337 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_bijection.671417459 |
|
|
Aug 27 11:28:42 AM UTC 24 |
Aug 27 11:53:05 AM UTC 24 |
311466674023 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.3637920875 |
|
|
Aug 27 11:48:03 AM UTC 24 |
Aug 27 11:53:07 AM UTC 24 |
4351348324 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.1178566305 |
|
|
Aug 27 11:43:53 AM UTC 24 |
Aug 27 11:53:19 AM UTC 24 |
20301283463 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access.1818609027 |
|
|
Aug 27 11:52:58 AM UTC 24 |
Aug 27 11:53:31 AM UTC 24 |
5693215443 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_regwen.903942439 |
|
|
Aug 27 11:47:05 AM UTC 24 |
Aug 27 11:53:54 AM UTC 24 |
20003016923 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.4194904727 |
|
|
Aug 27 11:51:50 AM UTC 24 |
Aug 27 11:53:59 AM UTC 24 |
10660208055 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.1265082973 |
|
|
Aug 27 11:53:19 AM UTC 24 |
Aug 27 11:53:59 AM UTC 24 |
1328841163 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.1538929054 |
|
|
Aug 27 11:38:33 AM UTC 24 |
Aug 27 11:54:03 AM UTC 24 |
15208109398 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.2921683411 |
|
|
Aug 27 11:54:04 AM UTC 24 |
Aug 27 11:54:10 AM UTC 24 |
1364481774 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.3927650633 |
|
|
Aug 27 11:53:55 AM UTC 24 |
Aug 27 11:54:10 AM UTC 24 |
1100083591 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.1139661146 |
|
|
Aug 27 11:47:39 AM UTC 24 |
Aug 27 11:54:12 AM UTC 24 |
9078618540 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2749987152 |
|
|
Aug 27 11:54:12 AM UTC 24 |
Aug 27 11:54:27 AM UTC 24 |
2535118016 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.3099059646 |
|
|
Aug 27 11:53:08 AM UTC 24 |
Aug 27 11:54:29 AM UTC 24 |
1123142595 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_regwen.2241198482 |
|
|
Aug 27 11:39:14 AM UTC 24 |
Aug 27 11:54:30 AM UTC 24 |
19938816751 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_alert_test.287401694 |
|
|
Aug 27 11:54:29 AM UTC 24 |
Aug 27 11:54:31 AM UTC 24 |
13858720 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.728564702 |
|
|
Aug 27 11:53:33 AM UTC 24 |
Aug 27 11:54:37 AM UTC 24 |
5084305896 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.2265337308 |
|
|
Aug 27 11:51:32 AM UTC 24 |
Aug 27 11:54:51 AM UTC 24 |
69165174580 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access.326357215 |
|
|
Aug 27 11:54:52 AM UTC 24 |
Aug 27 11:55:42 AM UTC 24 |
4810548617 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_smoke.319673816 |
|
|
Aug 27 11:54:30 AM UTC 24 |
Aug 27 11:55:43 AM UTC 24 |
900562478 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.805288759 |
|
|
Aug 27 11:55:44 AM UTC 24 |
Aug 27 11:56:04 AM UTC 24 |
2684852733 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.26060752 |
|
|
Aug 27 11:56:05 AM UTC 24 |
Aug 27 11:56:19 AM UTC 24 |
2982444255 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.3982964238 |
|
|
Aug 27 11:52:38 AM UTC 24 |
Aug 27 11:57:07 AM UTC 24 |
2681347403 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.1854349472 |
|
|
Aug 27 11:54:11 AM UTC 24 |
Aug 27 11:57:21 AM UTC 24 |
7131401990 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all.3057503844 |
|
|
Aug 27 11:39:45 AM UTC 24 |
Aug 27 11:57:26 AM UTC 24 |
20817049610 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_all.3321740576 |
|
|
Aug 27 11:01:38 AM UTC 24 |
Aug 27 11:57:30 AM UTC 24 |
123236928778 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_bijection.2664249978 |
|
|
Aug 27 11:45:45 AM UTC 24 |
Aug 27 11:57:34 AM UTC 24 |
125733399976 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.3705157658 |
|
|
Aug 27 11:57:31 AM UTC 24 |
Aug 27 11:57:36 AM UTC 24 |
354205181 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.3839420247 |
|
|
Aug 27 11:45:37 AM UTC 24 |
Aug 27 11:58:03 AM UTC 24 |
32016378093 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_bijection.3796979580 |
|
|
Aug 27 11:21:29 AM UTC 24 |
Aug 27 11:58:04 AM UTC 24 |
127039068051 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.1621478140 |
|
|
Aug 27 11:54:11 AM UTC 24 |
Aug 27 11:58:09 AM UTC 24 |
48560452309 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.1773745469 |
|
|
Aug 27 11:49:12 AM UTC 24 |
Aug 27 11:58:11 AM UTC 24 |
8042264999 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_alert_test.3605281597 |
|
|
Aug 27 11:58:10 AM UTC 24 |
Aug 27 11:58:12 AM UTC 24 |
15116749 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_smoke.1429771370 |
|
|
Aug 27 11:58:12 AM UTC 24 |
Aug 27 11:58:19 AM UTC 24 |
1411186991 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.3930436534 |
|
|
Aug 27 11:45:49 AM UTC 24 |
Aug 27 11:58:23 AM UTC 24 |
196915880850 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.21436148 |
|
|
Aug 27 11:58:03 AM UTC 24 |
Aug 27 11:58:26 AM UTC 24 |
1936259146 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all.2100055953 |
|
|
Aug 27 11:45:27 AM UTC 24 |
Aug 27 11:58:34 AM UTC 24 |
7418972501 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access.2460373298 |
|
|
Aug 27 11:58:27 AM UTC 24 |
Aug 27 11:58:38 AM UTC 24 |
536421352 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_regwen.1661748978 |
|
|
Aug 27 11:35:10 AM UTC 24 |
Aug 27 11:58:45 AM UTC 24 |
32796319437 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.3885659404 |
|
|
Aug 27 11:58:39 AM UTC 24 |
Aug 27 11:59:07 AM UTC 24 |
747095704 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.493324921 |
|
|
Aug 27 11:58:46 AM UTC 24 |
Aug 27 11:59:13 AM UTC 24 |
2956317554 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_regwen.3349847017 |
|
|
Aug 27 11:57:28 AM UTC 24 |
Aug 27 11:59:15 AM UTC 24 |
1475767482 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.1401407639 |
|
|
Aug 27 11:56:20 AM UTC 24 |
Aug 27 11:59:16 AM UTC 24 |
34873457720 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.2695334524 |
|
|
Aug 27 11:59:08 AM UTC 24 |
Aug 27 11:59:24 AM UTC 24 |
1300527038 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.2923196187 |
|
|
Aug 27 11:59:26 AM UTC 24 |
Aug 27 11:59:32 AM UTC 24 |
360681151 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.4146338731 |
|
|
Aug 27 11:57:37 AM UTC 24 |
Aug 27 11:59:57 AM UTC 24 |
6303435566 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.2462247280 |
|
|
Aug 27 11:57:35 AM UTC 24 |
Aug 27 12:00:02 PM UTC 24 |
5975219683 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.3226259698 |
|
|
Aug 27 11:50:31 AM UTC 24 |
Aug 27 12:00:07 PM UTC 24 |
38667550485 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.1802736508 |
|
|
Aug 27 11:54:38 AM UTC 24 |
Aug 27 12:01:09 PM UTC 24 |
4942848727 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_executable.1957352804 |
|
|
Aug 27 11:38:44 AM UTC 24 |
Aug 27 12:01:11 PM UTC 24 |
20052687752 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_alert_test.4010286002 |
|
|
Aug 27 12:01:11 PM UTC 24 |
Aug 27 12:01:13 PM UTC 24 |
16366015 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_all.2267501254 |
|
|
Aug 27 10:57:45 AM UTC 24 |
Aug 27 12:01:15 PM UTC 24 |
78405838109 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.2838868308 |
|
|
Aug 27 11:59:58 AM UTC 24 |
Aug 27 12:01:30 PM UTC 24 |
1471695653 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_smoke.1099804362 |
|
|
Aug 27 12:01:12 PM UTC 24 |
Aug 27 12:01:34 PM UTC 24 |
488920395 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.2268057606 |
|
|
Aug 27 12:00:02 PM UTC 24 |
Aug 27 12:01:34 PM UTC 24 |
15196694146 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_executable.2964337203 |
|
|
Aug 27 11:51:00 AM UTC 24 |
Aug 27 12:01:36 PM UTC 24 |
15887070285 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access.4233574253 |
|
|
Aug 27 12:01:35 PM UTC 24 |
Aug 27 12:01:47 PM UTC 24 |
3992533498 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_executable.2120962705 |
|
|
Aug 27 11:54:00 AM UTC 24 |
Aug 27 12:02:20 PM UTC 24 |
7997171706 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.3898309938 |
|
|
Aug 27 12:01:47 PM UTC 24 |
Aug 27 12:02:21 PM UTC 24 |
740233088 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all.788520119 |
|
|
Aug 27 11:10:08 AM UTC 24 |
Aug 27 12:02:22 PM UTC 24 |
81275870208 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.675693482 |
|
|
Aug 27 12:01:37 PM UTC 24 |
Aug 27 12:02:30 PM UTC 24 |
761491249 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.3808341915 |
|
|
Aug 27 12:02:21 PM UTC 24 |
Aug 27 12:02:34 PM UTC 24 |
3633021475 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.4011036116 |
|
|
Aug 27 12:02:34 PM UTC 24 |
Aug 27 12:02:41 PM UTC 24 |
345716959 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.2256329133 |
|
|
Aug 27 11:58:24 AM UTC 24 |
Aug 27 12:03:29 PM UTC 24 |
9385689742 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_regwen.1519588383 |
|
|
Aug 27 11:51:18 AM UTC 24 |
Aug 27 12:03:52 PM UTC 24 |
18673663146 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.3467690163 |
|
|
Aug 27 11:59:33 AM UTC 24 |
Aug 27 12:03:55 PM UTC 24 |
24700783224 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.3076803766 |
|
|
Aug 27 11:58:35 AM UTC 24 |
Aug 27 12:04:16 PM UTC 24 |
10068653329 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_alert_test.2794506139 |
|
|
Aug 27 12:04:17 PM UTC 24 |
Aug 27 12:04:19 PM UTC 24 |
39666986 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3021802523 |
|
|
Aug 27 12:03:52 PM UTC 24 |
Aug 27 12:04:26 PM UTC 24 |
1038314454 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.337879622 |
|
|
Aug 27 11:55:43 AM UTC 24 |
Aug 27 12:04:46 PM UTC 24 |
81322755066 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.3282694915 |
|
|
Aug 27 12:03:30 PM UTC 24 |
Aug 27 12:04:58 PM UTC 24 |
29139729554 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.1990502335 |
|
|
Aug 27 12:02:41 PM UTC 24 |
Aug 27 12:05:04 PM UTC 24 |
9399059501 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_executable.2803432783 |
|
|
Aug 27 11:46:37 AM UTC 24 |
Aug 27 12:05:53 PM UTC 24 |
81129925650 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.3545811685 |
|
|
Aug 27 12:01:35 PM UTC 24 |
Aug 27 12:06:01 PM UTC 24 |
31828837596 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_executable.2249418214 |
|
|
Aug 27 11:59:15 AM UTC 24 |
Aug 27 12:06:20 PM UTC 24 |
58237487723 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_regwen.3379593806 |
|
|
Aug 27 11:54:00 AM UTC 24 |
Aug 27 12:06:33 PM UTC 24 |
3954477841 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.2057591937 |
|
|
Aug 27 11:53:06 AM UTC 24 |
Aug 27 12:06:33 PM UTC 24 |
35256126229 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.3890918557 |
|
|
Aug 27 11:57:08 AM UTC 24 |
Aug 27 12:06:46 PM UTC 24 |
26907292057 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.4199837785 |
|
|
Aug 27 11:59:13 AM UTC 24 |
Aug 27 12:07:14 PM UTC 24 |
12643210505 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_bijection.325639595 |
|
|
Aug 27 11:33:57 AM UTC 24 |
Aug 27 12:07:22 PM UTC 24 |
27378086193 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_regwen.259481538 |
|
|
Aug 27 11:59:17 AM UTC 24 |
Aug 27 12:07:24 PM UTC 24 |
14552689118 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_multiple_keys.1423941226 |
|
|
Aug 27 11:54:31 AM UTC 24 |
Aug 27 12:07:53 PM UTC 24 |
67978050730 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.2791240164 |
|
|
Aug 27 11:58:13 AM UTC 24 |
Aug 27 12:08:08 PM UTC 24 |
18662368158 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.4086271413 |
|
|
Aug 27 12:01:31 PM UTC 24 |
Aug 27 12:08:08 PM UTC 24 |
5089427707 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all.1160349482 |
|
|
Aug 27 11:21:24 AM UTC 24 |
Aug 27 12:08:21 PM UTC 24 |
90987179612 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_executable.3081662374 |
|
|
Aug 27 11:57:21 AM UTC 24 |
Aug 27 12:08:55 PM UTC 24 |
52678981311 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_bijection.261990237 |
|
|
Aug 27 11:47:48 AM UTC 24 |
Aug 27 12:10:18 PM UTC 24 |
17381348447 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.2639676706 |
|
|
Aug 27 12:02:22 PM UTC 24 |
Aug 27 12:10:55 PM UTC 24 |
31847847647 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_regwen.351554019 |
|
|
Aug 27 12:02:31 PM UTC 24 |
Aug 27 12:11:58 PM UTC 24 |
74030412344 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_bijection.1371004618 |
|
|
Aug 27 11:40:47 AM UTC 24 |
Aug 27 12:12:02 PM UTC 24 |
65227761822 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all.1682616305 |
|
|
Aug 27 10:50:56 AM UTC 24 |
Aug 27 12:16:48 PM UTC 24 |
509021660633 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_executable.3954088863 |
|
|
Aug 27 12:02:23 PM UTC 24 |
Aug 27 12:19:34 PM UTC 24 |
36925705066 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.3542909275 |
|
|
Aug 27 12:01:14 PM UTC 24 |
Aug 27 12:23:12 PM UTC 24 |
24561081152 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_bijection.1416452950 |
|
|
Aug 27 11:58:19 AM UTC 24 |
Aug 27 12:23:33 PM UTC 24 |
60001593178 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all.2509020799 |
|
|
Aug 27 11:52:00 AM UTC 24 |
Aug 27 12:25:03 PM UTC 24 |
83853412549 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_bijection.2973716082 |
|
|
Aug 27 11:52:25 AM UTC 24 |
Aug 27 12:28:23 PM UTC 24 |
201393745900 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all.172434207 |
|
|
Aug 27 11:04:29 AM UTC 24 |
Aug 27 12:37:03 PM UTC 24 |
485516867562 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all.3732793675 |
|
|
Aug 27 12:03:56 PM UTC 24 |
Aug 27 12:37:13 PM UTC 24 |
152360147389 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_bijection.1302068708 |
|
|
Aug 27 11:54:32 AM UTC 24 |
Aug 27 12:37:44 PM UTC 24 |
30491319456 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all.1417551260 |
|
|
Aug 27 11:54:13 AM UTC 24 |
Aug 27 12:39:37 PM UTC 24 |
37160766638 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_bijection.28290647 |
|
|
Aug 27 12:01:16 PM UTC 24 |
Aug 27 12:39:48 PM UTC 24 |
99956153473 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all.2519989465 |
|
|
Aug 27 11:07:14 AM UTC 24 |
Aug 27 12:40:13 PM UTC 24 |
161149664989 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all.4185230610 |
|
|
Aug 27 11:14:31 AM UTC 24 |
Aug 27 12:40:40 PM UTC 24 |
266142130899 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all.2419979696 |
|
|
Aug 27 11:33:20 AM UTC 24 |
Aug 27 12:41:19 PM UTC 24 |
645620844020 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all.2794896168 |
|
|
Aug 27 11:35:56 AM UTC 24 |
Aug 27 12:44:09 PM UTC 24 |
724966224124 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all.2276370499 |
|
|
Aug 27 11:27:29 AM UTC 24 |
Aug 27 12:57:39 PM UTC 24 |
267684431701 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all.210868277 |
|
|
Aug 27 11:17:31 AM UTC 24 |
Aug 27 01:00:47 PM UTC 24 |
828720243957 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all.829525311 |
|
|
Aug 27 11:24:12 AM UTC 24 |
Aug 27 01:04:24 PM UTC 24 |
190002000576 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all.2558516383 |
|
|
Aug 27 11:47:29 AM UTC 24 |
Aug 27 01:16:15 PM UTC 24 |
261784302583 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all.1011293867 |
|
|
Aug 27 11:58:04 AM UTC 24 |
Aug 27 01:38:59 PM UTC 24 |
449172341824 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all.3988317457 |
|
|
Aug 27 12:00:07 PM UTC 24 |
Aug 27 02:20:52 PM UTC 24 |
1690857934626 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3031291771 |
|
|
Aug 27 12:04:27 PM UTC 24 |
Aug 27 12:04:35 PM UTC 24 |
134841987 ps |
| T62 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.34894016 |
|
|
Aug 27 12:04:36 PM UTC 24 |
Aug 27 12:04:41 PM UTC 24 |
351201121 ps |
| T65 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1226283345 |
|
|
Aug 27 12:04:42 PM UTC 24 |
Aug 27 12:04:44 PM UTC 24 |
38179803 ps |
| T66 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.892124477 |
|
|
Aug 27 12:04:45 PM UTC 24 |
Aug 27 12:04:47 PM UTC 24 |
108320244 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3716361470 |
|
|
Aug 27 12:04:48 PM UTC 24 |
Aug 27 12:04:51 PM UTC 24 |
21435682 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.702638983 |
|
|
Aug 27 12:04:47 PM UTC 24 |
Aug 27 12:04:51 PM UTC 24 |
193279392 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.172406157 |
|
|
Aug 27 12:04:51 PM UTC 24 |
Aug 27 12:04:54 PM UTC 24 |
29461064 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3752227975 |
|
|
Aug 27 12:04:51 PM UTC 24 |
Aug 27 12:05:00 PM UTC 24 |
371923579 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2659653469 |
|
|
Aug 27 12:04:59 PM UTC 24 |
Aug 27 12:05:04 PM UTC 24 |
160426566 ps |
| T63 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.654096026 |
|
|
Aug 27 12:05:01 PM UTC 24 |
Aug 27 12:05:05 PM UTC 24 |
497398298 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.977873247 |
|
|
Aug 27 12:05:05 PM UTC 24 |
Aug 27 12:05:07 PM UTC 24 |
82792469 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2981476784 |
|
|
Aug 27 12:05:05 PM UTC 24 |
Aug 27 12:05:07 PM UTC 24 |
38227552 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.4049189694 |
|
|
Aug 27 12:05:05 PM UTC 24 |
Aug 27 12:05:10 PM UTC 24 |
613711542 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1343950765 |
|
|
Aug 27 12:05:08 PM UTC 24 |
Aug 27 12:05:10 PM UTC 24 |
27932634 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1504774727 |
|
|
Aug 27 12:05:08 PM UTC 24 |
Aug 27 12:05:10 PM UTC 24 |
23277035 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1776813077 |
|
|
Aug 27 12:05:10 PM UTC 24 |
Aug 27 12:05:18 PM UTC 24 |
786614358 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3299412675 |
|
|
Aug 27 12:05:11 PM UTC 24 |
Aug 27 12:05:18 PM UTC 24 |
259329035 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.530682585 |
|
|
Aug 27 12:05:20 PM UTC 24 |
Aug 27 12:05:22 PM UTC 24 |
13883063 ps |
| T64 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1966666389 |
|
|
Aug 27 12:05:19 PM UTC 24 |
Aug 27 12:05:24 PM UTC 24 |
1354200615 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1885950402 |
|
|
Aug 27 12:05:23 PM UTC 24 |
Aug 27 12:05:25 PM UTC 24 |
14800918 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.890562792 |
|
|
Aug 27 12:05:26 PM UTC 24 |
Aug 27 12:05:28 PM UTC 24 |
47347951 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.713399068 |
|
|
Aug 27 12:05:25 PM UTC 24 |
Aug 27 12:05:28 PM UTC 24 |
90812090 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3514024191 |
|
|
Aug 27 12:05:29 PM UTC 24 |
Aug 27 12:05:31 PM UTC 24 |
17265998 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3123284475 |
|
|
Aug 27 12:05:29 PM UTC 24 |
Aug 27 12:05:36 PM UTC 24 |
374206636 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.743636129 |
|
|
Aug 27 12:05:36 PM UTC 24 |
Aug 27 12:05:40 PM UTC 24 |
63129158 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3360647702 |
|
|
Aug 27 12:05:42 PM UTC 24 |
Aug 27 12:05:46 PM UTC 24 |
154299333 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1351018520 |
|
|
Aug 27 12:05:47 PM UTC 24 |
Aug 27 12:05:49 PM UTC 24 |
36692091 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.4016925184 |
|
|
Aug 27 12:05:50 PM UTC 24 |
Aug 27 12:05:52 PM UTC 24 |
53170474 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2923191555 |
|
|
Aug 27 12:05:53 PM UTC 24 |
Aug 27 12:05:56 PM UTC 24 |
29177342 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.713662752 |
|
|
Aug 27 12:05:54 PM UTC 24 |
Aug 27 12:05:56 PM UTC 24 |
16583012 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3585153715 |
|
|
Aug 27 12:05:57 PM UTC 24 |
Aug 27 12:05:59 PM UTC 24 |
14497111 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.4068693441 |
|
|
Aug 27 12:04:20 PM UTC 24 |
Aug 27 12:06:03 PM UTC 24 |
70545953333 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1726200731 |
|
|
Aug 27 12:05:57 PM UTC 24 |
Aug 27 12:06:05 PM UTC 24 |
368117459 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3802823001 |
|
|
Aug 27 12:06:01 PM UTC 24 |
Aug 27 12:06:07 PM UTC 24 |
407009070 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2709618781 |
|
|
Aug 27 12:06:03 PM UTC 24 |
Aug 27 12:06:07 PM UTC 24 |
172597378 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2901838141 |
|
|
Aug 27 12:06:06 PM UTC 24 |
Aug 27 12:06:08 PM UTC 24 |
15443645 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2957403721 |
|
|
Aug 27 12:06:08 PM UTC 24 |
Aug 27 12:06:10 PM UTC 24 |
140972297 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3494113378 |
|
|
Aug 27 12:06:09 PM UTC 24 |
Aug 27 12:06:11 PM UTC 24 |
17776990 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1039396757 |
|
|
Aug 27 12:06:08 PM UTC 24 |
Aug 27 12:06:13 PM UTC 24 |
1467524447 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1362143840 |
|
|
Aug 27 12:06:11 PM UTC 24 |
Aug 27 12:06:13 PM UTC 24 |
16979994 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.654905950 |
|
|
Aug 27 12:06:14 PM UTC 24 |
Aug 27 12:06:19 PM UTC 24 |
78636376 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2624617646 |
|
|
Aug 27 12:06:12 PM UTC 24 |
Aug 27 12:06:20 PM UTC 24 |
364497104 ps |
| T104 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2473544364 |
|
|
Aug 27 12:06:21 PM UTC 24 |
Aug 27 12:06:23 PM UTC 24 |
81403212 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.4233454068 |
|
|
Aug 27 12:06:20 PM UTC 24 |
Aug 27 12:06:23 PM UTC 24 |
203201284 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2230296213 |
|
|
Aug 27 12:06:22 PM UTC 24 |
Aug 27 12:06:24 PM UTC 24 |
31017522 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.201021723 |
|
|
Aug 27 12:05:32 PM UTC 24 |
Aug 27 12:06:25 PM UTC 24 |
3887075443 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2598535894 |
|
|
Aug 27 12:06:26 PM UTC 24 |
Aug 27 12:06:30 PM UTC 24 |
121065388 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.737920520 |
|
|
Aug 27 12:06:25 PM UTC 24 |
Aug 27 12:06:31 PM UTC 24 |
29281379 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2986351215 |
|
|
Aug 27 12:06:30 PM UTC 24 |
Aug 27 12:06:33 PM UTC 24 |
190982687 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2087688975 |
|
|
Aug 27 12:06:24 PM UTC 24 |
Aug 27 12:06:33 PM UTC 24 |
364248934 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3098285900 |
|
|
Aug 27 12:06:32 PM UTC 24 |
Aug 27 12:06:34 PM UTC 24 |
97575253 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2226220078 |
|
|
Aug 27 12:06:35 PM UTC 24 |
Aug 27 12:06:37 PM UTC 24 |
42538943 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3237783055 |
|
|
Aug 27 12:06:34 PM UTC 24 |
Aug 27 12:06:38 PM UTC 24 |
354612286 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1349428784 |
|
|
Aug 27 12:06:34 PM UTC 24 |
Aug 27 12:06:38 PM UTC 24 |
102656828 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.567355183 |
|
|
Aug 27 12:06:38 PM UTC 24 |
Aug 27 12:06:41 PM UTC 24 |
38576400 ps |
| T86 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.141893467 |
|
|
Aug 27 12:05:11 PM UTC 24 |
Aug 27 12:06:42 PM UTC 24 |
28195715376 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3565118188 |
|
|
Aug 27 12:06:34 PM UTC 24 |
Aug 27 12:06:42 PM UTC 24 |
355509495 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1493471026 |
|
|
Aug 27 12:06:39 PM UTC 24 |
Aug 27 12:06:44 PM UTC 24 |
719185518 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.779619823 |
|
|
Aug 27 12:06:43 PM UTC 24 |
Aug 27 12:06:45 PM UTC 24 |
24545957 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.762996303 |
|
|
Aug 27 12:06:45 PM UTC 24 |
Aug 27 12:06:47 PM UTC 24 |
19443602 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1550607098 |
|
|
Aug 27 12:06:42 PM UTC 24 |
Aug 27 12:06:47 PM UTC 24 |
90517020 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1422315874 |
|
|
Aug 27 12:06:43 PM UTC 24 |
Aug 27 12:06:47 PM UTC 24 |
457977539 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3198386311 |
|
|
Aug 27 12:06:49 PM UTC 24 |
Aug 27 12:06:51 PM UTC 24 |
18315193 ps |
| T87 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.169449794 |
|
|
Aug 27 12:04:55 PM UTC 24 |
Aug 27 12:06:51 PM UTC 24 |
29430450948 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3949100883 |
|
|
Aug 27 12:06:49 PM UTC 24 |
Aug 27 12:06:52 PM UTC 24 |
93319311 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2119052522 |
|
|
Aug 27 12:07:05 PM UTC 24 |
Aug 27 12:07:07 PM UTC 24 |
35958579 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.601260352 |
|
|
Aug 27 12:06:46 PM UTC 24 |
Aug 27 12:06:54 PM UTC 24 |
372815322 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.259902947 |
|
|
Aug 27 12:06:49 PM UTC 24 |
Aug 27 12:06:54 PM UTC 24 |
787656437 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2581791390 |
|
|
Aug 27 12:06:52 PM UTC 24 |
Aug 27 12:06:54 PM UTC 24 |
251420270 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2062031042 |
|
|
Aug 27 12:06:55 PM UTC 24 |
Aug 27 12:06:57 PM UTC 24 |
14272411 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.981480895 |
|
|
Aug 27 12:06:55 PM UTC 24 |
Aug 27 12:06:58 PM UTC 24 |
510705980 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2666927588 |
|
|
Aug 27 12:06:52 PM UTC 24 |
Aug 27 12:06:59 PM UTC 24 |
349999431 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3752155631 |
|
|
Aug 27 12:06:58 PM UTC 24 |
Aug 27 12:07:00 PM UTC 24 |
63957132 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1809292892 |
|
|
Aug 27 12:06:55 PM UTC 24 |
Aug 27 12:07:01 PM UTC 24 |
42912596 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3816851481 |
|
|
Aug 27 12:07:01 PM UTC 24 |
Aug 27 12:07:05 PM UTC 24 |
26777028 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3300632684 |
|
|
Aug 27 12:07:02 PM UTC 24 |
Aug 27 12:07:05 PM UTC 24 |
126771045 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2239128285 |
|
|
Aug 27 12:07:09 PM UTC 24 |
Aug 27 12:07:17 PM UTC 24 |
410718458 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.976463127 |
|
|
Aug 27 12:07:00 PM UTC 24 |
Aug 27 12:07:07 PM UTC 24 |
706506529 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3187837628 |
|
|
Aug 27 12:07:07 PM UTC 24 |
Aug 27 12:07:09 PM UTC 24 |
43534359 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1054699198 |
|
|
Aug 27 12:07:08 PM UTC 24 |
Aug 27 12:07:14 PM UTC 24 |
708309628 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1593781621 |
|
|
Aug 27 12:07:16 PM UTC 24 |
Aug 27 12:07:18 PM UTC 24 |
21746584 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.72588142 |
|
|
Aug 27 12:07:16 PM UTC 24 |
Aug 27 12:07:21 PM UTC 24 |
610258795 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1902567185 |
|
|
Aug 27 12:07:18 PM UTC 24 |
Aug 27 12:07:21 PM UTC 24 |
19276246 ps |
| T92 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1263853343 |
|
|
Aug 27 12:06:47 PM UTC 24 |
Aug 27 12:07:21 PM UTC 24 |
7727366033 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.576722772 |
|
|
Aug 27 12:07:19 PM UTC 24 |
Aug 27 12:07:25 PM UTC 24 |
361756197 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1826570987 |
|
|
Aug 27 12:07:23 PM UTC 24 |
Aug 27 12:07:25 PM UTC 24 |
22178376 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3828572357 |
|
|
Aug 27 12:07:22 PM UTC 24 |
Aug 27 12:07:27 PM UTC 24 |
328308190 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.568322927 |
|
|
Aug 27 12:07:25 PM UTC 24 |
Aug 27 12:07:27 PM UTC 24 |
21533294 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2178564129 |
|
|
Aug 27 12:07:23 PM UTC 24 |
Aug 27 12:07:30 PM UTC 24 |
2218739500 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3145757636 |
|
|
Aug 27 12:07:28 PM UTC 24 |
Aug 27 12:07:32 PM UTC 24 |
485761586 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1788006234 |
|
|
Aug 27 12:07:28 PM UTC 24 |
Aug 27 12:07:32 PM UTC 24 |
68278742 ps |
| T98 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1244503306 |
|
|
Aug 27 12:06:00 PM UTC 24 |
Aug 27 12:07:33 PM UTC 24 |
63965905645 ps |
| T93 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1990679409 |
|
|
Aug 27 12:07:31 PM UTC 24 |
Aug 27 12:07:33 PM UTC 24 |
17857229 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3903200354 |
|
|
Aug 27 12:07:26 PM UTC 24 |
Aug 27 12:07:34 PM UTC 24 |
1935981637 ps |
| T94 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.475762166 |
|
|
Aug 27 12:06:14 PM UTC 24 |
Aug 27 12:07:36 PM UTC 24 |
7798707651 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1738840872 |
|
|
Aug 27 12:07:33 PM UTC 24 |
Aug 27 12:07:36 PM UTC 24 |
18468614 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1826711260 |
|
|
Aug 27 12:07:37 PM UTC 24 |
Aug 27 12:07:39 PM UTC 24 |
32607741 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1907500762 |
|
|
Aug 27 12:07:35 PM UTC 24 |
Aug 27 12:07:39 PM UTC 24 |
142125002 ps |
| T95 |
/workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3657207394 |
|
|
Aug 27 12:06:34 PM UTC 24 |
Aug 27 12:07:39 PM UTC 24 |
7441927842 ps |