| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.97 | 99.19 | 94.27 | 99.72 | 100.00 | 96.03 | 99.12 | 97.44 |
| T99 | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.113850220 | Aug 27 12:07:37 PM UTC 24 | Aug 27 12:07:39 PM UTC 24 | 12364763 ps | ||
| T1008 | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.736921295 | Aug 27 12:07:35 PM UTC 24 | Aug 27 12:07:41 PM UTC 24 | 91872270 ps | ||
| T1009 | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2441681637 | Aug 27 12:07:33 PM UTC 24 | Aug 27 12:07:41 PM UTC 24 | 1417083397 ps | ||
| T128 | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1524564288 | Aug 27 12:07:41 PM UTC 24 | Aug 27 12:07:44 PM UTC 24 | 74541177 ps | ||
| T1010 | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1715750608 | Aug 27 12:07:42 PM UTC 24 | Aug 27 12:07:45 PM UTC 24 | 103551537 ps | ||
| T1011 | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1883226515 | Aug 27 12:07:42 PM UTC 24 | Aug 27 12:07:45 PM UTC 24 | 20292092 ps | ||
| T1012 | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1917912130 | Aug 27 12:07:41 PM UTC 24 | Aug 27 12:07:49 PM UTC 24 | 1970132064 ps | ||
| T1013 | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1533899808 | Aug 27 12:07:41 PM UTC 24 | Aug 27 12:07:50 PM UTC 24 | 2631686124 ps | ||
| T1014 | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2941366143 | Aug 27 12:07:46 PM UTC 24 | Aug 27 12:07:51 PM UTC 24 | 228063464 ps | ||
| T1015 | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.4157372442 | Aug 27 12:07:51 PM UTC 24 | Aug 27 12:07:53 PM UTC 24 | 15835702 ps | ||
| T129 | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.44317683 | Aug 27 12:07:50 PM UTC 24 | Aug 27 12:07:53 PM UTC 24 | 231682295 ps | ||
| T1016 | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.233048986 | Aug 27 12:07:46 PM UTC 24 | Aug 27 12:07:54 PM UTC 24 | 347842478 ps | ||
| T1017 | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.167869489 | Aug 27 12:07:52 PM UTC 24 | Aug 27 12:07:54 PM UTC 24 | 26646871 ps | ||
| T1018 | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1320820185 | Aug 27 12:07:56 PM UTC 24 | Aug 27 12:07:58 PM UTC 24 | 58839974 ps | ||
| T96 | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3719687100 | Aug 27 12:06:39 PM UTC 24 | Aug 27 12:07:58 PM UTC 24 | 11747306856 ps | ||
| T100 | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.678668061 | Aug 27 12:06:24 PM UTC 24 | Aug 27 12:08:00 PM UTC 24 | 61466732348 ps | ||
| T1019 | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1520029682 | Aug 27 12:07:53 PM UTC 24 | Aug 27 12:08:00 PM UTC 24 | 1239097163 ps | ||
| T131 | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.132736413 | Aug 27 12:07:56 PM UTC 24 | Aug 27 12:08:01 PM UTC 24 | 929120812 ps | ||
| T1020 | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3866804630 | Aug 27 12:07:59 PM UTC 24 | Aug 27 12:08:01 PM UTC 24 | 17208538 ps | ||
| T97 | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2193362628 | Aug 27 12:06:53 PM UTC 24 | Aug 27 12:08:02 PM UTC 24 | 14196041227 ps | ||
| T1021 | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2114376464 | Aug 27 12:07:56 PM UTC 24 | Aug 27 12:08:04 PM UTC 24 | 152723753 ps | ||
| T1022 | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1881724213 | Aug 27 12:07:59 PM UTC 24 | Aug 27 12:08:04 PM UTC 24 | 359852712 ps | ||
| T1023 | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.926030965 | Aug 27 12:08:02 PM UTC 24 | Aug 27 12:08:05 PM UTC 24 | 174950116 ps | ||
| T1024 | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2367585365 | Aug 27 12:08:04 PM UTC 24 | Aug 27 12:08:06 PM UTC 24 | 17569705 ps | ||
| T1025 | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2177622371 | Aug 27 12:08:04 PM UTC 24 | Aug 27 12:08:06 PM UTC 24 | 55399628 ps | ||
| T1026 | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2012627842 | Aug 27 12:08:01 PM UTC 24 | Aug 27 12:08:08 PM UTC 24 | 44841426 ps | ||
| T1027 | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2850362126 | Aug 27 12:07:08 PM UTC 24 | Aug 27 12:08:15 PM UTC 24 | 7439742572 ps | ||
| T1028 | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3681454282 | Aug 27 12:08:06 PM UTC 24 | Aug 27 12:08:16 PM UTC 24 | 2368605121 ps | ||
| T1029 | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.4056400112 | Aug 27 12:07:41 PM UTC 24 | Aug 27 12:08:22 PM UTC 24 | 3847265325 ps | ||
| T1030 | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3335165318 | Aug 27 12:07:56 PM UTC 24 | Aug 27 12:08:25 PM UTC 24 | 15444124592 ps | ||
| T1031 | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.903628793 | Aug 27 12:07:01 PM UTC 24 | Aug 27 12:08:32 PM UTC 24 | 15046699955 ps | ||
| T1032 | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2625886888 | Aug 27 12:07:35 PM UTC 24 | Aug 27 12:08:42 PM UTC 24 | 50372924826 ps | ||
| T1033 | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.229369782 | Aug 27 12:07:22 PM UTC 24 | Aug 27 12:08:48 PM UTC 24 | 29416424494 ps | ||
| T1034 | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.342818615 | Aug 27 12:07:26 PM UTC 24 | Aug 27 12:08:53 PM UTC 24 | 7259778518 ps | ||
| T1035 | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.984396136 | Aug 27 12:07:46 PM UTC 24 | Aug 27 12:08:55 PM UTC 24 | 7262441175 ps | ||
| T1036 | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3471049895 | Aug 27 12:08:01 PM UTC 24 | Aug 27 12:09:53 PM UTC 24 | 28214740579 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.809541380 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 373726364 ps |
| CPU time | 11.8 seconds |
| Started | Aug 27 09:19:16 AM UTC 24 |
| Finished | Aug 27 09:19:29 AM UTC 24 |
| Peak memory | 221744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809541380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.809541380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/0.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3453944806 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 2423069051 ps |
| CPU time | 26.85 seconds |
| Started | Aug 27 09:31:55 AM UTC 24 |
| Finished | Aug 27 09:32:23 AM UTC 24 |
| Peak memory | 222004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453944806 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.3453944806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/5.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.3060649528 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 6683004241 ps |
| CPU time | 30.95 seconds |
| Started | Aug 27 09:19:33 AM UTC 24 |
| Finished | Aug 27 09:20:06 AM UTC 24 |
| Peak memory | 211556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060649528 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_escalation.3060649528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/1.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_regwen.3850478350 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 41830303414 ps |
| CPU time | 577.84 seconds |
| Started | Aug 27 09:20:01 AM UTC 24 |
| Finished | Aug 27 09:29:45 AM UTC 24 |
| Peak memory | 388580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850478350 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.3850478350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/1.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.2976232735 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 488461073 ps |
| CPU time | 5.52 seconds |
| Started | Aug 27 09:20:42 AM UTC 24 |
| Finished | Aug 27 09:20:48 AM UTC 24 |
| Peak memory | 247772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976232735 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_sec_cm.2976232735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.348749038 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 69029665598 ps |
| CPU time | 545.33 seconds |
| Started | Aug 27 09:19:14 AM UTC 24 |
| Finished | Aug 27 09:28:27 AM UTC 24 |
| Peak memory | 211744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348749038 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_partial_acc ess_b2b.348749038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/0.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.34894016 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 351201121 ps |
| CPU time | 3.81 seconds |
| Started | Aug 27 12:04:36 PM UTC 24 |
| Finished | Aug 27 12:04:41 PM UTC 24 |
| Peak memory | 223836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489 4016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_tl_in tg_err.34894016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/0.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3651800691 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 12114919031 ps |
| CPU time | 158.13 seconds |
| Started | Aug 27 09:20:15 AM UTC 24 |
| Finished | Aug 27 09:22:56 AM UTC 24 |
| Peak memory | 228916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651800691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.3651800691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/1.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_executable.99522684 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 56832698365 ps |
| CPU time | 700.54 seconds |
| Started | Aug 27 09:24:51 AM UTC 24 |
| Finished | Aug 27 09:36:40 AM UTC 24 |
| Peak memory | 380584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99522684 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executable.99522684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/3.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.60364901 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 3428915240 ps |
| CPU time | 142.51 seconds |
| Started | Aug 27 09:19:16 AM UTC 24 |
| Finished | Aug 27 09:21:41 AM UTC 24 |
| Peak memory | 221796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60364901 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_mem_partial_access.60364901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/0.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.4246921372 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 11046289926 ps |
| CPU time | 112.49 seconds |
| Started | Aug 27 09:27:26 AM UTC 24 |
| Finished | Aug 27 09:29:21 AM UTC 24 |
| Peak memory | 211548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246921372 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_escalation.4246921372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/4.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.4068693441 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 70545953333 ps |
| CPU time | 100.75 seconds |
| Started | Aug 27 12:04:20 PM UTC 24 |
| Finished | Aug 27 12:06:03 PM UTC 24 |
| Peak memory | 213516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 068693441 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ passthru_mem_tl_intg_err.4068693441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/0.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.4020235310 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 1537151530 ps |
| CPU time | 6.9 seconds |
| Started | Aug 27 09:19:16 AM UTC 24 |
| Finished | Aug 27 09:19:24 AM UTC 24 |
| Peak memory | 211632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020235310 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.4020235310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/0.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_regwen.4253126571 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 59605818190 ps |
| CPU time | 742.65 seconds |
| Started | Aug 27 09:25:10 AM UTC 24 |
| Finished | Aug 27 09:37:41 AM UTC 24 |
| Peak memory | 386592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253126571 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.4253126571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/3.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.981480895 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 510705980 ps |
| CPU time | 2.34 seconds |
| Started | Aug 27 12:06:55 PM UTC 24 |
| Finished | Aug 27 12:06:58 PM UTC 24 |
| Peak memory | 223664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9814 80895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl_ intg_err.981480895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/10.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.44317683 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 231682295 ps |
| CPU time | 2.55 seconds |
| Started | Aug 27 12:07:50 PM UTC 24 |
| Finished | Aug 27 12:07:53 PM UTC 24 |
| Peak memory | 223712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4431 7683 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_i ntg_err.44317683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/17.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2981476784 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 38227552 ps |
| CPU time | 1.04 seconds |
| Started | Aug 27 12:05:05 PM UTC 24 |
| Finished | Aug 27 12:05:07 PM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981476784 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_rw.2981476784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/1.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_alert_test.4020757151 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 14375125 ps |
| CPU time | 1.06 seconds |
| Started | Aug 27 09:19:20 AM UTC 24 |
| Finished | Aug 27 09:19:22 AM UTC 24 |
| Peak memory | 210732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020757151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_alert_test.4020757151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/0.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.132736413 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 929120812 ps |
| CPU time | 4.08 seconds |
| Started | Aug 27 12:07:56 PM UTC 24 |
| Finished | Aug 27 12:08:01 PM UTC 24 |
| Peak memory | 223780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327 36413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_tl_ intg_err.132736413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/18.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_executable.3104391943 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 11057456941 ps |
| CPU time | 386.01 seconds |
| Started | Aug 27 09:51:40 AM UTC 24 |
| Finished | Aug 27 09:58:11 AM UTC 24 |
| Peak memory | 366048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104391943 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executable.3104391943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/12.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3716361470 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 21435682 ps |
| CPU time | 1.05 seconds |
| Started | Aug 27 12:04:48 PM UTC 24 |
| Finished | Aug 27 12:04:51 PM UTC 24 |
| Peak memory | 212468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716361 470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_al iasing.3716361470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.702638983 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 193279392 ps |
| CPU time | 2.33 seconds |
| Started | Aug 27 12:04:47 PM UTC 24 |
| Finished | Aug 27 12:04:51 PM UTC 24 |
| Peak memory | 213620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7026389 83 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_bit _bash.702638983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1226283345 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 38179803 ps |
| CPU time | 0.99 seconds |
| Started | Aug 27 12:04:42 PM UTC 24 |
| Finished | Aug 27 12:04:44 PM UTC 24 |
| Peak memory | 212988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226283 345 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_hw _reset.1226283345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3752227975 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 371923579 ps |
| CPU time | 7.67 seconds |
| Started | Aug 27 12:04:51 PM UTC 24 |
| Finished | Aug 27 12:05:00 PM UTC 24 |
| Peak memory | 223944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=3752227975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.3752227975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.892124477 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 108320244 ps |
| CPU time | 1.04 seconds |
| Started | Aug 27 12:04:45 PM UTC 24 |
| Finished | Aug 27 12:04:47 PM UTC 24 |
| Peak memory | 212812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892124477 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_rw.892124477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.172406157 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 29461064 ps |
| CPU time | 1.25 seconds |
| Started | Aug 27 12:04:51 PM UTC 24 |
| Finished | Aug 27 12:04:54 PM UTC 24 |
| Peak memory | 212772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=172406157 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ ctrl_same_csr_outstanding.172406157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/0.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3031291771 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 134841987 ps |
| CPU time | 7.24 seconds |
| Started | Aug 27 12:04:27 PM UTC 24 |
| Finished | Aug 27 12:04:35 PM UTC 24 |
| Peak memory | 223764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031291771 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_tl_errors.3031291771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/0.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1343950765 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 27932634 ps |
| CPU time | 1.13 seconds |
| Started | Aug 27 12:05:08 PM UTC 24 |
| Finished | Aug 27 12:05:10 PM UTC 24 |
| Peak memory | 212812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343950 765 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_al iasing.1343950765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/1.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.4049189694 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 613711542 ps |
| CPU time | 3.57 seconds |
| Started | Aug 27 12:05:05 PM UTC 24 |
| Finished | Aug 27 12:05:10 PM UTC 24 |
| Peak memory | 213568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049189 694 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_bi t_bash.4049189694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/1.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.977873247 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 82792469 ps |
| CPU time | 1.03 seconds |
| Started | Aug 27 12:05:05 PM UTC 24 |
| Finished | Aug 27 12:05:07 PM UTC 24 |
| Peak memory | 212380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9778732 47 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_hw_ reset.977873247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/1.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1776813077 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 786614358 ps |
| CPU time | 6.37 seconds |
| Started | Aug 27 12:05:10 PM UTC 24 |
| Finished | Aug 27 12:05:18 PM UTC 24 |
| Peak memory | 225864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=1776813077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.1776813077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.169449794 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 29430450948 ps |
| CPU time | 114.4 seconds |
| Started | Aug 27 12:04:55 PM UTC 24 |
| Finished | Aug 27 12:06:51 PM UTC 24 |
| Peak memory | 213860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 69449794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_p assthru_mem_tl_intg_err.169449794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/1.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1504774727 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 23277035 ps |
| CPU time | 1.17 seconds |
| Started | Aug 27 12:05:08 PM UTC 24 |
| Finished | Aug 27 12:05:10 PM UTC 24 |
| Peak memory | 212808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1504774727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram _ctrl_same_csr_outstanding.1504774727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/1.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2659653469 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 160426566 ps |
| CPU time | 3.8 seconds |
| Started | Aug 27 12:04:59 PM UTC 24 |
| Finished | Aug 27 12:05:04 PM UTC 24 |
| Peak memory | 223696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659653469 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_errors.2659653469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/1.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.654096026 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 497398298 ps |
| CPU time | 2.88 seconds |
| Started | Aug 27 12:05:01 PM UTC 24 |
| Finished | Aug 27 12:05:05 PM UTC 24 |
| Peak memory | 223708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6540 96026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_i ntg_err.654096026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/1.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.976463127 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 706506529 ps |
| CPU time | 6.03 seconds |
| Started | Aug 27 12:07:00 PM UTC 24 |
| Finished | Aug 27 12:07:07 PM UTC 24 |
| Peak memory | 213324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=976463127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.976463127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2062031042 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 14272411 ps |
| CPU time | 1.05 seconds |
| Started | Aug 27 12:06:55 PM UTC 24 |
| Finished | Aug 27 12:06:57 PM UTC 24 |
| Peak memory | 212808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062031042 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_rw.2062031042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/10.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2193362628 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 14196041227 ps |
| CPU time | 67.12 seconds |
| Started | Aug 27 12:06:53 PM UTC 24 |
| Finished | Aug 27 12:08:02 PM UTC 24 |
| Peak memory | 213468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 193362628 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl _passthru_mem_tl_intg_err.2193362628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/10.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3752155631 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 63957132 ps |
| CPU time | 1.1 seconds |
| Started | Aug 27 12:06:58 PM UTC 24 |
| Finished | Aug 27 12:07:00 PM UTC 24 |
| Peak memory | 212528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3752155631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sra m_ctrl_same_csr_outstanding.3752155631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/10.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1809292892 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 42912596 ps |
| CPU time | 5.09 seconds |
| Started | Aug 27 12:06:55 PM UTC 24 |
| Finished | Aug 27 12:07:01 PM UTC 24 |
| Peak memory | 223716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809292892 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl_errors.1809292892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/10.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1054699198 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 708309628 ps |
| CPU time | 5.33 seconds |
| Started | Aug 27 12:07:08 PM UTC 24 |
| Finished | Aug 27 12:07:14 PM UTC 24 |
| Peak memory | 223636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=1054699198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.1054699198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2119052522 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 35958579 ps |
| CPU time | 0.98 seconds |
| Started | Aug 27 12:07:05 PM UTC 24 |
| Finished | Aug 27 12:07:07 PM UTC 24 |
| Peak memory | 212464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119052522 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_rw.2119052522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/11.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.903628793 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 15046699955 ps |
| CPU time | 89.25 seconds |
| Started | Aug 27 12:07:01 PM UTC 24 |
| Finished | Aug 27 12:08:32 PM UTC 24 |
| Peak memory | 213728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9 03628793 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ passthru_mem_tl_intg_err.903628793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/11.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3187837628 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 43534359 ps |
| CPU time | 1.02 seconds |
| Started | Aug 27 12:07:07 PM UTC 24 |
| Finished | Aug 27 12:07:09 PM UTC 24 |
| Peak memory | 212528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3187837628 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sra m_ctrl_same_csr_outstanding.3187837628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/11.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3816851481 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 26777028 ps |
| CPU time | 2.65 seconds |
| Started | Aug 27 12:07:01 PM UTC 24 |
| Finished | Aug 27 12:07:05 PM UTC 24 |
| Peak memory | 223984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816851481 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl_errors.3816851481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/11.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3300632684 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 126771045 ps |
| CPU time | 2.18 seconds |
| Started | Aug 27 12:07:02 PM UTC 24 |
| Finished | Aug 27 12:07:05 PM UTC 24 |
| Peak memory | 223728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300 632684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl _intg_err.3300632684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/11.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.576722772 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 361756197 ps |
| CPU time | 4.99 seconds |
| Started | Aug 27 12:07:19 PM UTC 24 |
| Finished | Aug 27 12:07:25 PM UTC 24 |
| Peak memory | 223768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=576722772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.576722772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1593781621 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 21746584 ps |
| CPU time | 1.01 seconds |
| Started | Aug 27 12:07:16 PM UTC 24 |
| Finished | Aug 27 12:07:18 PM UTC 24 |
| Peak memory | 213164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593781621 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_rw.1593781621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/12.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2850362126 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 7439742572 ps |
| CPU time | 64.9 seconds |
| Started | Aug 27 12:07:08 PM UTC 24 |
| Finished | Aug 27 12:08:15 PM UTC 24 |
| Peak memory | 213724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 850362126 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl _passthru_mem_tl_intg_err.2850362126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/12.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1902567185 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 19276246 ps |
| CPU time | 1.15 seconds |
| Started | Aug 27 12:07:18 PM UTC 24 |
| Finished | Aug 27 12:07:21 PM UTC 24 |
| Peak memory | 212588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1902567185 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sra m_ctrl_same_csr_outstanding.1902567185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/12.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2239128285 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 410718458 ps |
| CPU time | 6.52 seconds |
| Started | Aug 27 12:07:09 PM UTC 24 |
| Finished | Aug 27 12:07:17 PM UTC 24 |
| Peak memory | 213468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239128285 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl_errors.2239128285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/12.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.72588142 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 610258795 ps |
| CPU time | 3.47 seconds |
| Started | Aug 27 12:07:16 PM UTC 24 |
| Finished | Aug 27 12:07:21 PM UTC 24 |
| Peak memory | 213392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7258 8142 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl_i ntg_err.72588142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/12.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3903200354 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 1935981637 ps |
| CPU time | 6.63 seconds |
| Started | Aug 27 12:07:26 PM UTC 24 |
| Finished | Aug 27 12:07:34 PM UTC 24 |
| Peak memory | 223564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=3903200354 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.3903200354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1826570987 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 22178376 ps |
| CPU time | 0.88 seconds |
| Started | Aug 27 12:07:23 PM UTC 24 |
| Finished | Aug 27 12:07:25 PM UTC 24 |
| Peak memory | 212464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826570987 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_rw.1826570987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/13.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.229369782 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 29416424494 ps |
| CPU time | 84.6 seconds |
| Started | Aug 27 12:07:22 PM UTC 24 |
| Finished | Aug 27 12:08:48 PM UTC 24 |
| Peak memory | 213528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 29369782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ passthru_mem_tl_intg_err.229369782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/13.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.568322927 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 21533294 ps |
| CPU time | 0.95 seconds |
| Started | Aug 27 12:07:25 PM UTC 24 |
| Finished | Aug 27 12:07:27 PM UTC 24 |
| Peak memory | 212808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=568322927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram _ctrl_same_csr_outstanding.568322927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/13.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3828572357 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 328308190 ps |
| CPU time | 3.76 seconds |
| Started | Aug 27 12:07:22 PM UTC 24 |
| Finished | Aug 27 12:07:27 PM UTC 24 |
| Peak memory | 213540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828572357 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl_errors.3828572357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/13.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2178564129 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 2218739500 ps |
| CPU time | 5.52 seconds |
| Started | Aug 27 12:07:23 PM UTC 24 |
| Finished | Aug 27 12:07:30 PM UTC 24 |
| Peak memory | 223908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178 564129 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl _intg_err.2178564129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/13.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2441681637 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 1417083397 ps |
| CPU time | 6.49 seconds |
| Started | Aug 27 12:07:33 PM UTC 24 |
| Finished | Aug 27 12:07:41 PM UTC 24 |
| Peak memory | 223556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=2441681637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.2441681637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1990679409 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 17857229 ps |
| CPU time | 0.92 seconds |
| Started | Aug 27 12:07:31 PM UTC 24 |
| Finished | Aug 27 12:07:33 PM UTC 24 |
| Peak memory | 212464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990679409 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_rw.1990679409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/14.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.342818615 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 7259778518 ps |
| CPU time | 84.49 seconds |
| Started | Aug 27 12:07:26 PM UTC 24 |
| Finished | Aug 27 12:08:53 PM UTC 24 |
| Peak memory | 213656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 42818615 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ passthru_mem_tl_intg_err.342818615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/14.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1738840872 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 18468614 ps |
| CPU time | 1.18 seconds |
| Started | Aug 27 12:07:33 PM UTC 24 |
| Finished | Aug 27 12:07:36 PM UTC 24 |
| Peak memory | 212528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1738840872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sra m_ctrl_same_csr_outstanding.1738840872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/14.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1788006234 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 68278742 ps |
| CPU time | 3.53 seconds |
| Started | Aug 27 12:07:28 PM UTC 24 |
| Finished | Aug 27 12:07:32 PM UTC 24 |
| Peak memory | 223708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788006234 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_tl_errors.1788006234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/14.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3145757636 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 485761586 ps |
| CPU time | 2.86 seconds |
| Started | Aug 27 12:07:28 PM UTC 24 |
| Finished | Aug 27 12:07:32 PM UTC 24 |
| Peak memory | 223580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145 757636 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_tl _intg_err.3145757636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/14.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1533899808 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 2631686124 ps |
| CPU time | 8.02 seconds |
| Started | Aug 27 12:07:41 PM UTC 24 |
| Finished | Aug 27 12:07:50 PM UTC 24 |
| Peak memory | 223760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=1533899808 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.1533899808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.113850220 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 12364763 ps |
| CPU time | 0.97 seconds |
| Started | Aug 27 12:07:37 PM UTC 24 |
| Finished | Aug 27 12:07:39 PM UTC 24 |
| Peak memory | 212808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113850220 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_rw.113850220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/15.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2625886888 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 50372924826 ps |
| CPU time | 64.71 seconds |
| Started | Aug 27 12:07:35 PM UTC 24 |
| Finished | Aug 27 12:08:42 PM UTC 24 |
| Peak memory | 213528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 625886888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl _passthru_mem_tl_intg_err.2625886888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/15.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1826711260 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 32607741 ps |
| CPU time | 1.01 seconds |
| Started | Aug 27 12:07:37 PM UTC 24 |
| Finished | Aug 27 12:07:39 PM UTC 24 |
| Peak memory | 212528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1826711260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sra m_ctrl_same_csr_outstanding.1826711260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/15.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.736921295 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 91872270 ps |
| CPU time | 4.43 seconds |
| Started | Aug 27 12:07:35 PM UTC 24 |
| Finished | Aug 27 12:07:41 PM UTC 24 |
| Peak memory | 223740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736921295 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl_errors.736921295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/15.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1907500762 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 142125002 ps |
| CPU time | 2.16 seconds |
| Started | Aug 27 12:07:35 PM UTC 24 |
| Finished | Aug 27 12:07:39 PM UTC 24 |
| Peak memory | 223644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907 500762 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl _intg_err.1907500762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/15.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.233048986 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 347842478 ps |
| CPU time | 6.29 seconds |
| Started | Aug 27 12:07:46 PM UTC 24 |
| Finished | Aug 27 12:07:54 PM UTC 24 |
| Peak memory | 230828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=233048986 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.233048986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1715750608 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 103551537 ps |
| CPU time | 1.03 seconds |
| Started | Aug 27 12:07:42 PM UTC 24 |
| Finished | Aug 27 12:07:45 PM UTC 24 |
| Peak memory | 212808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715750608 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_rw.1715750608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/16.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.4056400112 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 3847265325 ps |
| CPU time | 40.19 seconds |
| Started | Aug 27 12:07:41 PM UTC 24 |
| Finished | Aug 27 12:08:22 PM UTC 24 |
| Peak memory | 213456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 056400112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl _passthru_mem_tl_intg_err.4056400112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/16.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1883226515 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 20292092 ps |
| CPU time | 1.02 seconds |
| Started | Aug 27 12:07:42 PM UTC 24 |
| Finished | Aug 27 12:07:45 PM UTC 24 |
| Peak memory | 212528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1883226515 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sra m_ctrl_same_csr_outstanding.1883226515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/16.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1917912130 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 1970132064 ps |
| CPU time | 6.62 seconds |
| Started | Aug 27 12:07:41 PM UTC 24 |
| Finished | Aug 27 12:07:49 PM UTC 24 |
| Peak memory | 223644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917912130 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl_errors.1917912130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/16.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1524564288 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 74541177 ps |
| CPU time | 2.3 seconds |
| Started | Aug 27 12:07:41 PM UTC 24 |
| Finished | Aug 27 12:07:44 PM UTC 24 |
| Peak memory | 223908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524 564288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl _intg_err.1524564288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/16.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1520029682 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 1239097163 ps |
| CPU time | 5.5 seconds |
| Started | Aug 27 12:07:53 PM UTC 24 |
| Finished | Aug 27 12:08:00 PM UTC 24 |
| Peak memory | 223640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=1520029682 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.1520029682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.4157372442 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 15835702 ps |
| CPU time | 1.05 seconds |
| Started | Aug 27 12:07:51 PM UTC 24 |
| Finished | Aug 27 12:07:53 PM UTC 24 |
| Peak memory | 212748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157372442 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_rw.4157372442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/17.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.984396136 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 7262441175 ps |
| CPU time | 67.35 seconds |
| Started | Aug 27 12:07:46 PM UTC 24 |
| Finished | Aug 27 12:08:55 PM UTC 24 |
| Peak memory | 213476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9 84396136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ passthru_mem_tl_intg_err.984396136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/17.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.167869489 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 26646871 ps |
| CPU time | 1.08 seconds |
| Started | Aug 27 12:07:52 PM UTC 24 |
| Finished | Aug 27 12:07:54 PM UTC 24 |
| Peak memory | 212692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=167869489 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram _ctrl_same_csr_outstanding.167869489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/17.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2941366143 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 228063464 ps |
| CPU time | 3.57 seconds |
| Started | Aug 27 12:07:46 PM UTC 24 |
| Finished | Aug 27 12:07:51 PM UTC 24 |
| Peak memory | 223964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941366143 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_errors.2941366143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/17.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1881724213 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 359852712 ps |
| CPU time | 3.99 seconds |
| Started | Aug 27 12:07:59 PM UTC 24 |
| Finished | Aug 27 12:08:04 PM UTC 24 |
| Peak memory | 213580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=1881724213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.1881724213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1320820185 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 58839974 ps |
| CPU time | 1.01 seconds |
| Started | Aug 27 12:07:56 PM UTC 24 |
| Finished | Aug 27 12:07:58 PM UTC 24 |
| Peak memory | 213164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320820185 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_rw.1320820185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/18.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3335165318 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 15444124592 ps |
| CPU time | 28.02 seconds |
| Started | Aug 27 12:07:56 PM UTC 24 |
| Finished | Aug 27 12:08:25 PM UTC 24 |
| Peak memory | 213388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 335165318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl _passthru_mem_tl_intg_err.3335165318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/18.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3866804630 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 17208538 ps |
| CPU time | 1.08 seconds |
| Started | Aug 27 12:07:59 PM UTC 24 |
| Finished | Aug 27 12:08:01 PM UTC 24 |
| Peak memory | 212700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3866804630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sra m_ctrl_same_csr_outstanding.3866804630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/18.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2114376464 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 152723753 ps |
| CPU time | 6.94 seconds |
| Started | Aug 27 12:07:56 PM UTC 24 |
| Finished | Aug 27 12:08:04 PM UTC 24 |
| Peak memory | 223708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114376464 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_tl_errors.2114376464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/18.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3681454282 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 2368605121 ps |
| CPU time | 9.24 seconds |
| Started | Aug 27 12:08:06 PM UTC 24 |
| Finished | Aug 27 12:08:16 PM UTC 24 |
| Peak memory | 223764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=3681454282 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.3681454282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2367585365 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 17569705 ps |
| CPU time | 1.01 seconds |
| Started | Aug 27 12:08:04 PM UTC 24 |
| Finished | Aug 27 12:08:06 PM UTC 24 |
| Peak memory | 212324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367585365 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_rw.2367585365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/19.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3471049895 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 28214740579 ps |
| CPU time | 109.27 seconds |
| Started | Aug 27 12:08:01 PM UTC 24 |
| Finished | Aug 27 12:09:53 PM UTC 24 |
| Peak memory | 213716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 471049895 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl _passthru_mem_tl_intg_err.3471049895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/19.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2177622371 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 55399628 ps |
| CPU time | 1.09 seconds |
| Started | Aug 27 12:08:04 PM UTC 24 |
| Finished | Aug 27 12:08:06 PM UTC 24 |
| Peak memory | 212304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2177622371 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sra m_ctrl_same_csr_outstanding.2177622371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/19.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2012627842 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 44841426 ps |
| CPU time | 5.34 seconds |
| Started | Aug 27 12:08:01 PM UTC 24 |
| Finished | Aug 27 12:08:08 PM UTC 24 |
| Peak memory | 213732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012627842 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl_errors.2012627842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/19.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.926030965 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 174950116 ps |
| CPU time | 2.51 seconds |
| Started | Aug 27 12:08:02 PM UTC 24 |
| Finished | Aug 27 12:08:05 PM UTC 24 |
| Peak memory | 223852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9260 30965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl_ intg_err.926030965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/19.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.890562792 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 47347951 ps |
| CPU time | 1.06 seconds |
| Started | Aug 27 12:05:26 PM UTC 24 |
| Finished | Aug 27 12:05:28 PM UTC 24 |
| Peak memory | 212468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8905627 92 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_ali asing.890562792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/2.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.713399068 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 90812090 ps |
| CPU time | 2.47 seconds |
| Started | Aug 27 12:05:25 PM UTC 24 |
| Finished | Aug 27 12:05:28 PM UTC 24 |
| Peak memory | 213608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7133990 68 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_bit _bash.713399068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/2.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.530682585 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 13883063 ps |
| CPU time | 0.99 seconds |
| Started | Aug 27 12:05:20 PM UTC 24 |
| Finished | Aug 27 12:05:22 PM UTC 24 |
| Peak memory | 212468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5306825 85 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_hw_ reset.530682585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/2.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3123284475 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 374206636 ps |
| CPU time | 5.52 seconds |
| Started | Aug 27 12:05:29 PM UTC 24 |
| Finished | Aug 27 12:05:36 PM UTC 24 |
| Peak memory | 223700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=3123284475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.3123284475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1885950402 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 14800918 ps |
| CPU time | 1 seconds |
| Started | Aug 27 12:05:23 PM UTC 24 |
| Finished | Aug 27 12:05:25 PM UTC 24 |
| Peak memory | 212460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885950402 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_rw.1885950402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/2.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.141893467 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 28195715376 ps |
| CPU time | 88.18 seconds |
| Started | Aug 27 12:05:11 PM UTC 24 |
| Finished | Aug 27 12:06:42 PM UTC 24 |
| Peak memory | 213540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 41893467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_p assthru_mem_tl_intg_err.141893467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/2.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3514024191 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 17265998 ps |
| CPU time | 1.12 seconds |
| Started | Aug 27 12:05:29 PM UTC 24 |
| Finished | Aug 27 12:05:31 PM UTC 24 |
| Peak memory | 212524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3514024191 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram _ctrl_same_csr_outstanding.3514024191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/2.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3299412675 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 259329035 ps |
| CPU time | 5.99 seconds |
| Started | Aug 27 12:05:11 PM UTC 24 |
| Finished | Aug 27 12:05:18 PM UTC 24 |
| Peak memory | 223844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299412675 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_errors.3299412675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/2.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1966666389 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 1354200615 ps |
| CPU time | 4.35 seconds |
| Started | Aug 27 12:05:19 PM UTC 24 |
| Finished | Aug 27 12:05:24 PM UTC 24 |
| Peak memory | 223584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966 666389 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_ intg_err.1966666389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/2.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.713662752 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 16583012 ps |
| CPU time | 1.06 seconds |
| Started | Aug 27 12:05:54 PM UTC 24 |
| Finished | Aug 27 12:05:56 PM UTC 24 |
| Peak memory | 212700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7136627 52 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_ali asing.713662752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/3.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2923191555 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 29177342 ps |
| CPU time | 1.82 seconds |
| Started | Aug 27 12:05:53 PM UTC 24 |
| Finished | Aug 27 12:05:56 PM UTC 24 |
| Peak memory | 212468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923191 555 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_bi t_bash.2923191555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/3.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1351018520 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 36692091 ps |
| CPU time | 0.89 seconds |
| Started | Aug 27 12:05:47 PM UTC 24 |
| Finished | Aug 27 12:05:49 PM UTC 24 |
| Peak memory | 212468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351018 520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_hw _reset.1351018520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/3.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1726200731 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 368117459 ps |
| CPU time | 6.41 seconds |
| Started | Aug 27 12:05:57 PM UTC 24 |
| Finished | Aug 27 12:06:05 PM UTC 24 |
| Peak memory | 223576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=1726200731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.1726200731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.4016925184 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 53170474 ps |
| CPU time | 0.94 seconds |
| Started | Aug 27 12:05:50 PM UTC 24 |
| Finished | Aug 27 12:05:52 PM UTC 24 |
| Peak memory | 212460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016925184 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_rw.4016925184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/3.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.201021723 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 3887075443 ps |
| CPU time | 51.38 seconds |
| Started | Aug 27 12:05:32 PM UTC 24 |
| Finished | Aug 27 12:06:25 PM UTC 24 |
| Peak memory | 213376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 01021723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_p assthru_mem_tl_intg_err.201021723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/3.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3585153715 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 14497111 ps |
| CPU time | 1.05 seconds |
| Started | Aug 27 12:05:57 PM UTC 24 |
| Finished | Aug 27 12:05:59 PM UTC 24 |
| Peak memory | 212380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3585153715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram _ctrl_same_csr_outstanding.3585153715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/3.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.743636129 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 63129158 ps |
| CPU time | 2.99 seconds |
| Started | Aug 27 12:05:36 PM UTC 24 |
| Finished | Aug 27 12:05:40 PM UTC 24 |
| Peak memory | 223920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743636129 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_errors.743636129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/3.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3360647702 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 154299333 ps |
| CPU time | 3.56 seconds |
| Started | Aug 27 12:05:42 PM UTC 24 |
| Finished | Aug 27 12:05:46 PM UTC 24 |
| Peak memory | 223904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360 647702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_ intg_err.3360647702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/3.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3494113378 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 17776990 ps |
| CPU time | 1.14 seconds |
| Started | Aug 27 12:06:09 PM UTC 24 |
| Finished | Aug 27 12:06:11 PM UTC 24 |
| Peak memory | 212812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494113 378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_al iasing.3494113378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/4.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1039396757 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 1467524447 ps |
| CPU time | 3.87 seconds |
| Started | Aug 27 12:06:08 PM UTC 24 |
| Finished | Aug 27 12:06:13 PM UTC 24 |
| Peak memory | 213204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039396 757 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_bi t_bash.1039396757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/4.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2901838141 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 15443645 ps |
| CPU time | 1.09 seconds |
| Started | Aug 27 12:06:06 PM UTC 24 |
| Finished | Aug 27 12:06:08 PM UTC 24 |
| Peak memory | 212472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901838 141 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_hw _reset.2901838141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/4.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2624617646 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 364497104 ps |
| CPU time | 6.53 seconds |
| Started | Aug 27 12:06:12 PM UTC 24 |
| Finished | Aug 27 12:06:20 PM UTC 24 |
| Peak memory | 223816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=2624617646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.2624617646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2957403721 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 140972297 ps |
| CPU time | 1.04 seconds |
| Started | Aug 27 12:06:08 PM UTC 24 |
| Finished | Aug 27 12:06:10 PM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957403721 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_rw.2957403721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/4.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1244503306 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 63965905645 ps |
| CPU time | 90.75 seconds |
| Started | Aug 27 12:06:00 PM UTC 24 |
| Finished | Aug 27 12:07:33 PM UTC 24 |
| Peak memory | 213592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 244503306 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ passthru_mem_tl_intg_err.1244503306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/4.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1362143840 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 16979994 ps |
| CPU time | 1.08 seconds |
| Started | Aug 27 12:06:11 PM UTC 24 |
| Finished | Aug 27 12:06:13 PM UTC 24 |
| Peak memory | 212524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1362143840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram _ctrl_same_csr_outstanding.1362143840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/4.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3802823001 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 407009070 ps |
| CPU time | 4.92 seconds |
| Started | Aug 27 12:06:01 PM UTC 24 |
| Finished | Aug 27 12:06:07 PM UTC 24 |
| Peak memory | 223676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802823001 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_errors.3802823001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/4.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2709618781 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 172597378 ps |
| CPU time | 2.77 seconds |
| Started | Aug 27 12:06:03 PM UTC 24 |
| Finished | Aug 27 12:06:07 PM UTC 24 |
| Peak memory | 223732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709 618781 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_ intg_err.2709618781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/4.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2087688975 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 364248934 ps |
| CPU time | 7.83 seconds |
| Started | Aug 27 12:06:24 PM UTC 24 |
| Finished | Aug 27 12:06:33 PM UTC 24 |
| Peak memory | 223764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=2087688975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.2087688975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2473544364 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 81403212 ps |
| CPU time | 1.04 seconds |
| Started | Aug 27 12:06:21 PM UTC 24 |
| Finished | Aug 27 12:06:23 PM UTC 24 |
| Peak memory | 212460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473544364 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_rw.2473544364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/5.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.475762166 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 7798707651 ps |
| CPU time | 79.16 seconds |
| Started | Aug 27 12:06:14 PM UTC 24 |
| Finished | Aug 27 12:07:36 PM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 75762166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_p assthru_mem_tl_intg_err.475762166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/5.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2230296213 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 31017522 ps |
| CPU time | 0.97 seconds |
| Started | Aug 27 12:06:22 PM UTC 24 |
| Finished | Aug 27 12:06:24 PM UTC 24 |
| Peak memory | 212984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2230296213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram _ctrl_same_csr_outstanding.2230296213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/5.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.654905950 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 78636376 ps |
| CPU time | 3.47 seconds |
| Started | Aug 27 12:06:14 PM UTC 24 |
| Finished | Aug 27 12:06:19 PM UTC 24 |
| Peak memory | 223720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654905950 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_errors.654905950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/5.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.4233454068 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 203201284 ps |
| CPU time | 2.58 seconds |
| Started | Aug 27 12:06:20 PM UTC 24 |
| Finished | Aug 27 12:06:23 PM UTC 24 |
| Peak memory | 213416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233 454068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_ intg_err.4233454068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/5.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3565118188 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 355509495 ps |
| CPU time | 6.78 seconds |
| Started | Aug 27 12:06:34 PM UTC 24 |
| Finished | Aug 27 12:06:42 PM UTC 24 |
| Peak memory | 223384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=3565118188 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.3565118188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2986351215 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 190982687 ps |
| CPU time | 1.06 seconds |
| Started | Aug 27 12:06:30 PM UTC 24 |
| Finished | Aug 27 12:06:33 PM UTC 24 |
| Peak memory | 213100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986351215 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_rw.2986351215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/6.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.678668061 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 61466732348 ps |
| CPU time | 93.64 seconds |
| Started | Aug 27 12:06:24 PM UTC 24 |
| Finished | Aug 27 12:08:00 PM UTC 24 |
| Peak memory | 223776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6 78668061 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_p assthru_mem_tl_intg_err.678668061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/6.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3098285900 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 97575253 ps |
| CPU time | 1.01 seconds |
| Started | Aug 27 12:06:32 PM UTC 24 |
| Finished | Aug 27 12:06:34 PM UTC 24 |
| Peak memory | 212524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3098285900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram _ctrl_same_csr_outstanding.3098285900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/6.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.737920520 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 29281379 ps |
| CPU time | 4.88 seconds |
| Started | Aug 27 12:06:25 PM UTC 24 |
| Finished | Aug 27 12:06:31 PM UTC 24 |
| Peak memory | 213464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737920520 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_errors.737920520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/6.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2598535894 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 121065388 ps |
| CPU time | 2.34 seconds |
| Started | Aug 27 12:06:26 PM UTC 24 |
| Finished | Aug 27 12:06:30 PM UTC 24 |
| Peak memory | 223856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598 535894 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_ intg_err.2598535894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/6.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1493471026 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 719185518 ps |
| CPU time | 4.72 seconds |
| Started | Aug 27 12:06:39 PM UTC 24 |
| Finished | Aug 27 12:06:44 PM UTC 24 |
| Peak memory | 223772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=1493471026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.1493471026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2226220078 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 42538943 ps |
| CPU time | 1.03 seconds |
| Started | Aug 27 12:06:35 PM UTC 24 |
| Finished | Aug 27 12:06:37 PM UTC 24 |
| Peak memory | 212460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226220078 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_rw.2226220078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/7.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3657207394 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 7441927842 ps |
| CPU time | 63.1 seconds |
| Started | Aug 27 12:06:34 PM UTC 24 |
| Finished | Aug 27 12:07:39 PM UTC 24 |
| Peak memory | 213600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 657207394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ passthru_mem_tl_intg_err.3657207394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/7.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.567355183 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 38576400 ps |
| CPU time | 1.09 seconds |
| Started | Aug 27 12:06:38 PM UTC 24 |
| Finished | Aug 27 12:06:41 PM UTC 24 |
| Peak memory | 212532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=567355183 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ ctrl_same_csr_outstanding.567355183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/7.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1349428784 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 102656828 ps |
| CPU time | 2.75 seconds |
| Started | Aug 27 12:06:34 PM UTC 24 |
| Finished | Aug 27 12:06:38 PM UTC 24 |
| Peak memory | 213464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349428784 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_tl_errors.1349428784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/7.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3237783055 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 354612286 ps |
| CPU time | 2.39 seconds |
| Started | Aug 27 12:06:34 PM UTC 24 |
| Finished | Aug 27 12:06:38 PM UTC 24 |
| Peak memory | 213480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237 783055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_tl_ intg_err.3237783055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/7.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.601260352 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 372815322 ps |
| CPU time | 6.53 seconds |
| Started | Aug 27 12:06:46 PM UTC 24 |
| Finished | Aug 27 12:06:54 PM UTC 24 |
| Peak memory | 223572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=601260352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.601260352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.779619823 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 24545957 ps |
| CPU time | 1.01 seconds |
| Started | Aug 27 12:06:43 PM UTC 24 |
| Finished | Aug 27 12:06:45 PM UTC 24 |
| Peak memory | 212468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779619823 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_rw.779619823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/8.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3719687100 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 11747306856 ps |
| CPU time | 77.48 seconds |
| Started | Aug 27 12:06:39 PM UTC 24 |
| Finished | Aug 27 12:07:58 PM UTC 24 |
| Peak memory | 213604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 719687100 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ passthru_mem_tl_intg_err.3719687100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/8.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.762996303 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 19443602 ps |
| CPU time | 1.13 seconds |
| Started | Aug 27 12:06:45 PM UTC 24 |
| Finished | Aug 27 12:06:47 PM UTC 24 |
| Peak memory | 212532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=762996303 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ ctrl_same_csr_outstanding.762996303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/8.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1550607098 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 90517020 ps |
| CPU time | 4.55 seconds |
| Started | Aug 27 12:06:42 PM UTC 24 |
| Finished | Aug 27 12:06:47 PM UTC 24 |
| Peak memory | 223904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550607098 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_errors.1550607098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/8.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1422315874 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 457977539 ps |
| CPU time | 3.59 seconds |
| Started | Aug 27 12:06:43 PM UTC 24 |
| Finished | Aug 27 12:06:47 PM UTC 24 |
| Peak memory | 223648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422 315874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_ intg_err.1422315874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/8.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.2666927588 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 349999431 ps |
| CPU time | 6.19 seconds |
| Started | Aug 27 12:06:52 PM UTC 24 |
| Finished | Aug 27 12:06:59 PM UTC 24 |
| Peak memory | 213324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=2666927588 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.2666927588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3198386311 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 18315193 ps |
| CPU time | 0.85 seconds |
| Started | Aug 27 12:06:49 PM UTC 24 |
| Finished | Aug 27 12:06:51 PM UTC 24 |
| Peak memory | 212864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198386311 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_rw.3198386311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/9.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1263853343 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 7727366033 ps |
| CPU time | 32.92 seconds |
| Started | Aug 27 12:06:47 PM UTC 24 |
| Finished | Aug 27 12:07:21 PM UTC 24 |
| Peak memory | 213388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 263853343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ passthru_mem_tl_intg_err.1263853343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/9.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2581791390 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 251420270 ps |
| CPU time | 1.28 seconds |
| Started | Aug 27 12:06:52 PM UTC 24 |
| Finished | Aug 27 12:06:54 PM UTC 24 |
| Peak memory | 212524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2581791390 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram _ctrl_same_csr_outstanding.2581791390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/9.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3949100883 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 93319311 ps |
| CPU time | 2.44 seconds |
| Started | Aug 27 12:06:49 PM UTC 24 |
| Finished | Aug 27 12:06:52 PM UTC 24 |
| Peak memory | 223700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949100883 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_errors.3949100883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/9.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.259902947 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 787656437 ps |
| CPU time | 4.39 seconds |
| Started | Aug 27 12:06:49 PM UTC 24 |
| Finished | Aug 27 12:06:54 PM UTC 24 |
| Peak memory | 223924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599 02947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_i ntg_err.259902947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/9.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.2842177779 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 11327782401 ps |
| CPU time | 159.6 seconds |
| Started | Aug 27 09:19:14 AM UTC 24 |
| Finished | Aug 27 09:21:57 AM UTC 24 |
| Peak memory | 378344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842177779 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_access_durin g_key_req.2842177779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/0.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_bijection.4026657894 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 86433982950 ps |
| CPU time | 1433.29 seconds |
| Started | Aug 27 09:19:14 AM UTC 24 |
| Finished | Aug 27 09:43:23 AM UTC 24 |
| Peak memory | 211828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026657894 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.4026657894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/0.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_executable.3186858413 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 12492954905 ps |
| CPU time | 457.26 seconds |
| Started | Aug 27 09:19:14 AM UTC 24 |
| Finished | Aug 27 09:26:57 AM UTC 24 |
| Peak memory | 378532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186858413 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executable.3186858413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/0.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.1626901457 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 21026154259 ps |
| CPU time | 107.3 seconds |
| Started | Aug 27 09:19:14 AM UTC 24 |
| Finished | Aug 27 09:21:04 AM UTC 24 |
| Peak memory | 211572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626901457 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_escalation.1626901457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/0.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.2941677850 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 9585365649 ps |
| CPU time | 9.93 seconds |
| Started | Aug 27 09:19:14 AM UTC 24 |
| Finished | Aug 27 09:19:25 AM UTC 24 |
| Peak memory | 221784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2941677850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_m ax_throughput.2941677850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/0.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.1492522244 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 4535715989 ps |
| CPU time | 235.37 seconds |
| Started | Aug 27 09:19:16 AM UTC 24 |
| Finished | Aug 27 09:23:14 AM UTC 24 |
| Peak memory | 211596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492522244 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_mem_walk.1492522244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/0.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.3975567874 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 7573400242 ps |
| CPU time | 699 seconds |
| Started | Aug 27 09:19:14 AM UTC 24 |
| Finished | Aug 27 09:31:01 AM UTC 24 |
| Peak memory | 388696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975567874 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multiple_keys.3975567874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/0.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access.636632588 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 808027472 ps |
| CPU time | 11.66 seconds |
| Started | Aug 27 09:19:14 AM UTC 24 |
| Finished | Aug 27 09:19:27 AM UTC 24 |
| Peak memory | 211512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636632588 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_partial_access.636632588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/0.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_regwen.4064882265 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 7488402930 ps |
| CPU time | 521.57 seconds |
| Started | Aug 27 09:19:16 AM UTC 24 |
| Finished | Aug 27 09:28:03 AM UTC 24 |
| Peak memory | 386716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064882265 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.4064882265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/0.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.2811791043 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 969721984 ps |
| CPU time | 4.35 seconds |
| Started | Aug 27 09:19:16 AM UTC 24 |
| Finished | Aug 27 09:19:21 AM UTC 24 |
| Peak memory | 247888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811791043 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_sec_cm.2811791043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_smoke.2262525827 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4662233765 ps |
| CPU time | 9.73 seconds |
| Started | Aug 27 09:19:14 AM UTC 24 |
| Finished | Aug 27 09:19:25 AM UTC 24 |
| Peak memory | 211556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262525827 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.2262525827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/0.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all.312419992 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 990500026364 ps |
| CPU time | 6056.9 seconds |
| Started | Aug 27 09:19:16 AM UTC 24 |
| Finished | Aug 27 11:01:15 AM UTC 24 |
| Peak memory | 392304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31241999 2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all.312419992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/0.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.127801419 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 3530229729 ps |
| CPU time | 239.75 seconds |
| Started | Aug 27 09:19:14 AM UTC 24 |
| Finished | Aug 27 09:23:17 AM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127801419 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_pipeline.127801419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/0.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.4227460620 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 798659155 ps |
| CPU time | 84.87 seconds |
| Started | Aug 27 09:19:14 AM UTC 24 |
| Finished | Aug 27 09:20:41 AM UTC 24 |
| Peak memory | 359836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =4227460620 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ throughput_w_partial_write.4227460620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/0.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.1466713011 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 19014507450 ps |
| CPU time | 1164.97 seconds |
| Started | Aug 27 09:19:48 AM UTC 24 |
| Finished | Aug 27 09:39:25 AM UTC 24 |
| Peak memory | 388576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466713011 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_access_durin g_key_req.1466713011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/1.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_alert_test.2442055819 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 74362128 ps |
| CPU time | 0.96 seconds |
| Started | Aug 27 09:20:48 AM UTC 24 |
| Finished | Aug 27 09:20:50 AM UTC 24 |
| Peak memory | 210812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442055819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_alert_test.2442055819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/1.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_bijection.2893000686 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 276705442801 ps |
| CPU time | 1675.92 seconds |
| Started | Aug 27 09:19:24 AM UTC 24 |
| Finished | Aug 27 09:47:40 AM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893000686 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection.2893000686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/1.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_executable.1179477453 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 20345604805 ps |
| CPU time | 1150.05 seconds |
| Started | Aug 27 09:19:58 AM UTC 24 |
| Finished | Aug 27 09:39:22 AM UTC 24 |
| Peak memory | 386728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179477453 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executable.1179477453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/1.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.2783928521 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 739229164 ps |
| CPU time | 30.51 seconds |
| Started | Aug 27 09:19:28 AM UTC 24 |
| Finished | Aug 27 09:20:00 AM UTC 24 |
| Peak memory | 288368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2783928521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_m ax_throughput.2783928521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/1.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.1022628815 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 5056894267 ps |
| CPU time | 181.53 seconds |
| Started | Aug 27 09:20:09 AM UTC 24 |
| Finished | Aug 27 09:23:14 AM UTC 24 |
| Peak memory | 221936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022628815 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_mem_partial_access.1022628815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/1.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.3533527247 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 2634388762 ps |
| CPU time | 213.7 seconds |
| Started | Aug 27 09:20:09 AM UTC 24 |
| Finished | Aug 27 09:23:46 AM UTC 24 |
| Peak memory | 222020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533527247 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_mem_walk.3533527247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/1.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.2356797515 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 70620027287 ps |
| CPU time | 1057.94 seconds |
| Started | Aug 27 09:19:23 AM UTC 24 |
| Finished | Aug 27 09:37:13 AM UTC 24 |
| Peak memory | 388636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356797515 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multiple_keys.2356797515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/1.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access.1105889502 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 4635032490 ps |
| CPU time | 40.54 seconds |
| Started | Aug 27 09:19:26 AM UTC 24 |
| Finished | Aug 27 09:20:08 AM UTC 24 |
| Peak memory | 282072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105889502 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_partial_access.1105889502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/1.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.779374832 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 24890548474 ps |
| CPU time | 356.91 seconds |
| Started | Aug 27 09:19:27 AM UTC 24 |
| Finished | Aug 27 09:25:29 AM UTC 24 |
| Peak memory | 211548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779374832 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_partial_acc ess_b2b.779374832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/1.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.979265955 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1531772934 ps |
| CPU time | 6.35 seconds |
| Started | Aug 27 09:20:07 AM UTC 24 |
| Finished | Aug 27 09:20:14 AM UTC 24 |
| Peak memory | 211632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979265955 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.979265955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/1.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_smoke.125076536 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 995441679 ps |
| CPU time | 23.81 seconds |
| Started | Aug 27 09:19:22 AM UTC 24 |
| Finished | Aug 27 09:19:47 AM UTC 24 |
| Peak memory | 211432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125076536 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.125076536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/1.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all.3350353788 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 16787108246 ps |
| CPU time | 1811.49 seconds |
| Started | Aug 27 09:20:39 AM UTC 24 |
| Finished | Aug 27 09:51:10 AM UTC 24 |
| Peak memory | 388564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33503537 88 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all.3350353788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/1.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.1759458441 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 20719879587 ps |
| CPU time | 311.35 seconds |
| Started | Aug 27 09:19:26 AM UTC 24 |
| Finished | Aug 27 09:24:41 AM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759458441 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_pipeline.1759458441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/1.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.2401288894 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 716783271 ps |
| CPU time | 25.48 seconds |
| Started | Aug 27 09:19:30 AM UTC 24 |
| Finished | Aug 27 09:19:57 AM UTC 24 |
| Peak memory | 273888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2401288894 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ throughput_w_partial_write.2401288894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/1.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.2600304329 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 123690052475 ps |
| CPU time | 574.59 seconds |
| Started | Aug 27 09:46:03 AM UTC 24 |
| Finished | Aug 27 09:55:44 AM UTC 24 |
| Peak memory | 363996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600304329 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_access_duri ng_key_req.2600304329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/10.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_alert_test.3203114928 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 77596162 ps |
| CPU time | 1.02 seconds |
| Started | Aug 27 09:47:41 AM UTC 24 |
| Finished | Aug 27 09:47:43 AM UTC 24 |
| Peak memory | 210736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203114928 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_alert_test.3203114928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/10.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_bijection.2695516120 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 16740669735 ps |
| CPU time | 1438.44 seconds |
| Started | Aug 27 09:45:02 AM UTC 24 |
| Finished | Aug 27 10:09:18 AM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695516120 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection.2695516120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/10.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_executable.1287728683 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 3783944080 ps |
| CPU time | 47.38 seconds |
| Started | Aug 27 09:46:12 AM UTC 24 |
| Finished | Aug 27 09:47:01 AM UTC 24 |
| Peak memory | 277976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287728683 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executable.1287728683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/10.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.2408316181 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 6527589102 ps |
| CPU time | 45.04 seconds |
| Started | Aug 27 09:45:58 AM UTC 24 |
| Finished | Aug 27 09:46:44 AM UTC 24 |
| Peak memory | 211588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408316181 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_escalation.2408316181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/10.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.2579133632 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 1395541158 ps |
| CPU time | 20.09 seconds |
| Started | Aug 27 09:45:40 AM UTC 24 |
| Finished | Aug 27 09:46:02 AM UTC 24 |
| Peak memory | 261608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2579133632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ max_throughput.2579133632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/10.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.4109264379 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 9423783377 ps |
| CPU time | 174.87 seconds |
| Started | Aug 27 09:47:01 AM UTC 24 |
| Finished | Aug 27 09:49:59 AM UTC 24 |
| Peak memory | 221816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109264379 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_mem_partial_access.4109264379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/10.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.3998018991 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 15759615504 ps |
| CPU time | 241.47 seconds |
| Started | Aug 27 09:46:53 AM UTC 24 |
| Finished | Aug 27 09:50:58 AM UTC 24 |
| Peak memory | 221888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998018991 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_mem_walk.3998018991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/10.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.2154298163 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 57811863527 ps |
| CPU time | 838.83 seconds |
| Started | Aug 27 09:45:01 AM UTC 24 |
| Finished | Aug 27 09:59:09 AM UTC 24 |
| Peak memory | 382484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154298163 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multiple_keys.2154298163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/10.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access.528703931 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 6785108218 ps |
| CPU time | 17.73 seconds |
| Started | Aug 27 09:45:27 AM UTC 24 |
| Finished | Aug 27 09:45:47 AM UTC 24 |
| Peak memory | 211876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528703931 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_partial_access.528703931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/10.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.4248431628 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 42965780618 ps |
| CPU time | 217.25 seconds |
| Started | Aug 27 09:45:31 AM UTC 24 |
| Finished | Aug 27 09:49:13 AM UTC 24 |
| Peak memory | 211780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248431628 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_partial_a ccess_b2b.4248431628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/10.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.3295445299 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 1400753918 ps |
| CPU time | 6.45 seconds |
| Started | Aug 27 09:46:45 AM UTC 24 |
| Finished | Aug 27 09:46:53 AM UTC 24 |
| Peak memory | 211644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295445299 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.3295445299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/10.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_regwen.158237261 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 61455396990 ps |
| CPU time | 656.46 seconds |
| Started | Aug 27 09:46:44 AM UTC 24 |
| Finished | Aug 27 09:57:49 AM UTC 24 |
| Peak memory | 370408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158237261 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.158237261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/10.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_smoke.1247526416 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 887501682 ps |
| CPU time | 26.32 seconds |
| Started | Aug 27 09:44:34 AM UTC 24 |
| Finished | Aug 27 09:45:01 AM UTC 24 |
| Peak memory | 211556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247526416 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.1247526416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/10.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all.2302978077 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 258335418080 ps |
| CPU time | 5321.7 seconds |
| Started | Aug 27 09:47:31 AM UTC 24 |
| Finished | Aug 27 11:17:09 AM UTC 24 |
| Peak memory | 390316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23029780 77 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_a ll.2302978077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/10.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.4001449479 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 1015145109 ps |
| CPU time | 113.25 seconds |
| Started | Aug 27 09:47:17 AM UTC 24 |
| Finished | Aug 27 09:49:13 AM UTC 24 |
| Peak memory | 364336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001449479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.4001449479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/10.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.682697261 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 8022438623 ps |
| CPU time | 360.07 seconds |
| Started | Aug 27 09:45:19 AM UTC 24 |
| Finished | Aug 27 09:51:24 AM UTC 24 |
| Peak memory | 211620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682697261 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_pipeline.682697261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/10.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.429024353 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 801351892 ps |
| CPU time | 53.86 seconds |
| Started | Aug 27 09:45:48 AM UTC 24 |
| Finished | Aug 27 09:46:43 AM UTC 24 |
| Peak memory | 333208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =429024353 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ throughput_w_partial_write.429024353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/10.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.1864707296 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 90974813206 ps |
| CPU time | 1109.11 seconds |
| Started | Aug 27 09:49:29 AM UTC 24 |
| Finished | Aug 27 10:08:11 AM UTC 24 |
| Peak memory | 388584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864707296 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_access_duri ng_key_req.1864707296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/11.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_alert_test.3110811672 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 34060761 ps |
| CPU time | 0.93 seconds |
| Started | Aug 27 09:50:53 AM UTC 24 |
| Finished | Aug 27 09:50:55 AM UTC 24 |
| Peak memory | 210936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110811672 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_alert_test.3110811672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/11.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_bijection.3257002048 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 189121975172 ps |
| CPU time | 1502.46 seconds |
| Started | Aug 27 09:47:55 AM UTC 24 |
| Finished | Aug 27 10:13:14 AM UTC 24 |
| Peak memory | 211556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257002048 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection.3257002048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/11.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_executable.4153472555 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 6672458784 ps |
| CPU time | 470.4 seconds |
| Started | Aug 27 09:49:30 AM UTC 24 |
| Finished | Aug 27 09:57:27 AM UTC 24 |
| Peak memory | 386728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153472555 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executable.4153472555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/11.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.2656590625 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 38333622224 ps |
| CPU time | 93.68 seconds |
| Started | Aug 27 09:49:17 AM UTC 24 |
| Finished | Aug 27 09:50:53 AM UTC 24 |
| Peak memory | 221876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656590625 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_escalation.2656590625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/11.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.1303372054 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 769691474 ps |
| CPU time | 13.47 seconds |
| Started | Aug 27 09:49:14 AM UTC 24 |
| Finished | Aug 27 09:49:28 AM UTC 24 |
| Peak memory | 228344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1303372054 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ max_throughput.1303372054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/11.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.2233429577 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 10932634446 ps |
| CPU time | 80.84 seconds |
| Started | Aug 27 09:50:01 AM UTC 24 |
| Finished | Aug 27 09:51:23 AM UTC 24 |
| Peak memory | 221996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233429577 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_mem_partial_access.2233429577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/11.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.2916493578 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 41438825250 ps |
| CPU time | 177.29 seconds |
| Started | Aug 27 09:49:42 AM UTC 24 |
| Finished | Aug 27 09:52:43 AM UTC 24 |
| Peak memory | 222016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916493578 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_mem_walk.2916493578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/11.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.2040204882 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 67983438703 ps |
| CPU time | 1052.21 seconds |
| Started | Aug 27 09:47:45 AM UTC 24 |
| Finished | Aug 27 10:05:28 AM UTC 24 |
| Peak memory | 388628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040204882 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multiple_keys.2040204882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/11.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access.1222682969 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 2150507273 ps |
| CPU time | 17.86 seconds |
| Started | Aug 27 09:48:58 AM UTC 24 |
| Finished | Aug 27 09:49:17 AM UTC 24 |
| Peak memory | 211552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222682969 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_partial_access.1222682969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/11.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.92849459 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 53990738234 ps |
| CPU time | 367.85 seconds |
| Started | Aug 27 09:49:14 AM UTC 24 |
| Finished | Aug 27 09:55:27 AM UTC 24 |
| Peak memory | 211880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92849459 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_partial_acc ess_b2b.92849459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/11.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.3978526612 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 357173702 ps |
| CPU time | 5.97 seconds |
| Started | Aug 27 09:49:34 AM UTC 24 |
| Finished | Aug 27 09:49:42 AM UTC 24 |
| Peak memory | 211648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978526612 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.3978526612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/11.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_regwen.4173010844 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 12000123398 ps |
| CPU time | 503.6 seconds |
| Started | Aug 27 09:49:30 AM UTC 24 |
| Finished | Aug 27 09:58:00 AM UTC 24 |
| Peak memory | 388784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173010844 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.4173010844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/11.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_smoke.2666543605 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 2848513570 ps |
| CPU time | 18.98 seconds |
| Started | Aug 27 09:47:44 AM UTC 24 |
| Finished | Aug 27 09:48:04 AM UTC 24 |
| Peak memory | 211548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666543605 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.2666543605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/11.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all.1294686368 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 141332841269 ps |
| CPU time | 3763.78 seconds |
| Started | Aug 27 09:50:47 AM UTC 24 |
| Finished | Aug 27 10:54:08 AM UTC 24 |
| Peak memory | 394328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12946863 68 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_a ll.1294686368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/11.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.2974076818 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 7716938247 ps |
| CPU time | 39.32 seconds |
| Started | Aug 27 09:50:15 AM UTC 24 |
| Finished | Aug 27 09:50:56 AM UTC 24 |
| Peak memory | 317220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974076818 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.2974076818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/11.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.2174090120 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 6495479276 ps |
| CPU time | 603.46 seconds |
| Started | Aug 27 09:48:05 AM UTC 24 |
| Finished | Aug 27 09:58:16 AM UTC 24 |
| Peak memory | 211628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174090120 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_pipeline.2174090120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/11.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.1236759688 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 708186785 ps |
| CPU time | 13 seconds |
| Started | Aug 27 09:49:15 AM UTC 24 |
| Finished | Aug 27 09:49:29 AM UTC 24 |
| Peak memory | 228772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1236759688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl _throughput_w_partial_write.1236759688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/11.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.1676799136 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 26637372697 ps |
| CPU time | 448.98 seconds |
| Started | Aug 27 09:51:39 AM UTC 24 |
| Finished | Aug 27 09:59:13 AM UTC 24 |
| Peak memory | 380628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676799136 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_access_duri ng_key_req.1676799136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/12.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_alert_test.1328301723 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 11821623 ps |
| CPU time | 1.03 seconds |
| Started | Aug 27 09:53:23 AM UTC 24 |
| Finished | Aug 27 09:53:25 AM UTC 24 |
| Peak memory | 210876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328301723 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_alert_test.1328301723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/12.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_bijection.2980119020 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 90578667721 ps |
| CPU time | 1448.44 seconds |
| Started | Aug 27 09:50:59 AM UTC 24 |
| Finished | Aug 27 10:15:23 AM UTC 24 |
| Peak memory | 211684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980119020 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection.2980119020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/12.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.3363247359 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 1737836335 ps |
| CPU time | 24.87 seconds |
| Started | Aug 27 09:51:38 AM UTC 24 |
| Finished | Aug 27 09:52:04 AM UTC 24 |
| Peak memory | 221732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363247359 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_escalation.3363247359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/12.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.1608665914 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 2233728939 ps |
| CPU time | 13.27 seconds |
| Started | Aug 27 09:51:24 AM UTC 24 |
| Finished | Aug 27 09:51:38 AM UTC 24 |
| Peak memory | 221796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1608665914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ max_throughput.1608665914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/12.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.2292907954 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 50253350475 ps |
| CPU time | 222.61 seconds |
| Started | Aug 27 09:52:44 AM UTC 24 |
| Finished | Aug 27 09:56:30 AM UTC 24 |
| Peak memory | 221944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292907954 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_mem_partial_access.2292907954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/12.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.1361788042 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 6928156701 ps |
| CPU time | 155.85 seconds |
| Started | Aug 27 09:52:12 AM UTC 24 |
| Finished | Aug 27 09:54:51 AM UTC 24 |
| Peak memory | 221936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361788042 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_mem_walk.1361788042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/12.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.4292094376 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 47387397825 ps |
| CPU time | 1215.63 seconds |
| Started | Aug 27 09:50:57 AM UTC 24 |
| Finished | Aug 27 10:11:27 AM UTC 24 |
| Peak memory | 388632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292094376 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multiple_keys.4292094376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/12.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access.562576707 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 6859475614 ps |
| CPU time | 24.45 seconds |
| Started | Aug 27 09:51:12 AM UTC 24 |
| Finished | Aug 27 09:51:37 AM UTC 24 |
| Peak memory | 211540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562576707 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_partial_access.562576707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/12.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.1933961856 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 17233416811 ps |
| CPU time | 415.82 seconds |
| Started | Aug 27 09:51:21 AM UTC 24 |
| Finished | Aug 27 09:58:22 AM UTC 24 |
| Peak memory | 211632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933961856 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_partial_a ccess_b2b.1933961856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/12.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.2357568761 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 1349317755 ps |
| CPU time | 6.16 seconds |
| Started | Aug 27 09:52:04 AM UTC 24 |
| Finished | Aug 27 09:52:12 AM UTC 24 |
| Peak memory | 211644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357568761 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.2357568761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/12.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_regwen.731484994 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 13645642177 ps |
| CPU time | 567.11 seconds |
| Started | Aug 27 09:51:45 AM UTC 24 |
| Finished | Aug 27 10:01:18 AM UTC 24 |
| Peak memory | 386516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731484994 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.731484994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/12.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_smoke.2004428459 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 1582009921 ps |
| CPU time | 9.13 seconds |
| Started | Aug 27 09:50:56 AM UTC 24 |
| Finished | Aug 27 09:51:07 AM UTC 24 |
| Peak memory | 217704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004428459 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.2004428459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/12.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all.3075738851 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 486381971706 ps |
| CPU time | 4912.12 seconds |
| Started | Aug 27 09:53:17 AM UTC 24 |
| Finished | Aug 27 11:15:58 AM UTC 24 |
| Peak memory | 392284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30757388 51 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_a ll.3075738851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/12.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.2975400108 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 400575847 ps |
| CPU time | 23.36 seconds |
| Started | Aug 27 09:52:52 AM UTC 24 |
| Finished | Aug 27 09:53:16 AM UTC 24 |
| Peak memory | 221876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975400108 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.2975400108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/12.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.390744317 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 26499450253 ps |
| CPU time | 484.27 seconds |
| Started | Aug 27 09:51:07 AM UTC 24 |
| Finished | Aug 27 09:59:18 AM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390744317 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_pipeline.390744317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/12.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.552779319 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 690262240 ps |
| CPU time | 13.42 seconds |
| Started | Aug 27 09:51:25 AM UTC 24 |
| Finished | Aug 27 09:51:39 AM UTC 24 |
| Peak memory | 228756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =552779319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ throughput_w_partial_write.552779319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/12.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.844661649 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 23276282602 ps |
| CPU time | 1429.82 seconds |
| Started | Aug 27 09:57:03 AM UTC 24 |
| Finished | Aug 27 10:21:08 AM UTC 24 |
| Peak memory | 388740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844661649 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_access_durin g_key_req.844661649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/13.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_alert_test.3838680410 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 32664870 ps |
| CPU time | 0.86 seconds |
| Started | Aug 27 09:58:09 AM UTC 24 |
| Finished | Aug 27 09:58:11 AM UTC 24 |
| Peak memory | 210816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838680410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_alert_test.3838680410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/13.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_bijection.2704806186 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 83239912922 ps |
| CPU time | 751.76 seconds |
| Started | Aug 27 09:54:52 AM UTC 24 |
| Finished | Aug 27 10:07:32 AM UTC 24 |
| Peak memory | 211632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704806186 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection.2704806186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/13.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_executable.434113339 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 12388903666 ps |
| CPU time | 1207.31 seconds |
| Started | Aug 27 09:57:09 AM UTC 24 |
| Finished | Aug 27 10:17:28 AM UTC 24 |
| Peak memory | 386508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434113339 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executable.434113339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/13.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.1501650705 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 17959680145 ps |
| CPU time | 81.02 seconds |
| Started | Aug 27 09:56:36 AM UTC 24 |
| Finished | Aug 27 09:57:58 AM UTC 24 |
| Peak memory | 221992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501650705 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_escalation.1501650705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/13.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.460035132 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 668430522 ps |
| CPU time | 11.33 seconds |
| Started | Aug 27 09:56:22 AM UTC 24 |
| Finished | Aug 27 09:56:35 AM UTC 24 |
| Peak memory | 211308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 460035132 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_m ax_throughput.460035132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/13.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.3290790402 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 2562074389 ps |
| CPU time | 192.43 seconds |
| Started | Aug 27 09:57:57 AM UTC 24 |
| Finished | Aug 27 10:01:13 AM UTC 24 |
| Peak memory | 222056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290790402 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_mem_partial_access.3290790402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/13.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.2372381569 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 20710721504 ps |
| CPU time | 380.48 seconds |
| Started | Aug 27 09:57:56 AM UTC 24 |
| Finished | Aug 27 10:04:21 AM UTC 24 |
| Peak memory | 221940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372381569 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_mem_walk.2372381569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/13.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.3444210641 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 31766797459 ps |
| CPU time | 640.41 seconds |
| Started | Aug 27 09:53:50 AM UTC 24 |
| Finished | Aug 27 10:04:38 AM UTC 24 |
| Peak memory | 382628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444210641 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multiple_keys.3444210641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/13.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access.621378687 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 1738475621 ps |
| CPU time | 35.39 seconds |
| Started | Aug 27 09:55:45 AM UTC 24 |
| Finished | Aug 27 09:56:22 AM UTC 24 |
| Peak memory | 282224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621378687 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_partial_access.621378687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/13.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.3568536757 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 15337821803 ps |
| CPU time | 486.94 seconds |
| Started | Aug 27 09:56:21 AM UTC 24 |
| Finished | Aug 27 10:04:34 AM UTC 24 |
| Peak memory | 211632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568536757 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_partial_a ccess_b2b.3568536757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/13.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.3948391710 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 359070543 ps |
| CPU time | 5.36 seconds |
| Started | Aug 27 09:57:49 AM UTC 24 |
| Finished | Aug 27 09:57:56 AM UTC 24 |
| Peak memory | 211644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948391710 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.3948391710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/13.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_regwen.3737001917 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 2292601713 ps |
| CPU time | 59.12 seconds |
| Started | Aug 27 09:57:28 AM UTC 24 |
| Finished | Aug 27 09:58:29 AM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737001917 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.3737001917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/13.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_smoke.1305941692 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 8646566025 ps |
| CPU time | 21.61 seconds |
| Started | Aug 27 09:53:26 AM UTC 24 |
| Finished | Aug 27 09:53:49 AM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305941692 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.1305941692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/13.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all.2741866115 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 209576224495 ps |
| CPU time | 1670.24 seconds |
| Started | Aug 27 09:58:01 AM UTC 24 |
| Finished | Aug 27 10:26:08 AM UTC 24 |
| Peak memory | 384108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27418661 15 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_a ll.2741866115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/13.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.2428584273 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 326094102 ps |
| CPU time | 8.43 seconds |
| Started | Aug 27 09:57:59 AM UTC 24 |
| Finished | Aug 27 09:58:08 AM UTC 24 |
| Peak memory | 222204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428584273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.2428584273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/13.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.4009339047 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 4268761172 ps |
| CPU time | 385.32 seconds |
| Started | Aug 27 09:55:27 AM UTC 24 |
| Finished | Aug 27 10:01:58 AM UTC 24 |
| Peak memory | 211628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009339047 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_pipeline.4009339047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/13.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.3009999320 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 3172646358 ps |
| CPU time | 29.91 seconds |
| Started | Aug 27 09:56:31 AM UTC 24 |
| Finished | Aug 27 09:57:02 AM UTC 24 |
| Peak memory | 298672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3009999320 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl _throughput_w_partial_write.3009999320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/13.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.4248240983 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 16408098546 ps |
| CPU time | 809.33 seconds |
| Started | Aug 27 09:59:14 AM UTC 24 |
| Finished | Aug 27 10:12:52 AM UTC 24 |
| Peak memory | 386592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248240983 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_access_duri ng_key_req.4248240983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/14.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_alert_test.1674217616 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 36136053 ps |
| CPU time | 1 seconds |
| Started | Aug 27 10:00:50 AM UTC 24 |
| Finished | Aug 27 10:00:53 AM UTC 24 |
| Peak memory | 210876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674217616 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_alert_test.1674217616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/14.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_bijection.2207049258 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 69460821671 ps |
| CPU time | 1517.6 seconds |
| Started | Aug 27 09:58:17 AM UTC 24 |
| Finished | Aug 27 10:23:52 AM UTC 24 |
| Peak memory | 211728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207049258 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection.2207049258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/14.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_executable.2914838666 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 21438320583 ps |
| CPU time | 131.26 seconds |
| Started | Aug 27 09:59:18 AM UTC 24 |
| Finished | Aug 27 10:01:32 AM UTC 24 |
| Peak memory | 370136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914838666 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executable.2914838666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/14.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.1897369246 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 20912823620 ps |
| CPU time | 88.26 seconds |
| Started | Aug 27 09:59:09 AM UTC 24 |
| Finished | Aug 27 10:00:39 AM UTC 24 |
| Peak memory | 221728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897369246 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_escalation.1897369246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/14.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.3976025464 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 5977509705 ps |
| CPU time | 49.62 seconds |
| Started | Aug 27 09:58:51 AM UTC 24 |
| Finished | Aug 27 09:59:42 AM UTC 24 |
| Peak memory | 300584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3976025464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ max_throughput.3976025464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/14.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.2091563612 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 17660925704 ps |
| CPU time | 153.19 seconds |
| Started | Aug 27 09:59:51 AM UTC 24 |
| Finished | Aug 27 10:02:27 AM UTC 24 |
| Peak memory | 222052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091563612 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_mem_partial_access.2091563612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/14.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.2934604792 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 7458424074 ps |
| CPU time | 180.21 seconds |
| Started | Aug 27 09:59:50 AM UTC 24 |
| Finished | Aug 27 10:02:53 AM UTC 24 |
| Peak memory | 221888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934604792 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_mem_walk.2934604792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/14.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.1264103581 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 5178040593 ps |
| CPU time | 153.91 seconds |
| Started | Aug 27 09:58:12 AM UTC 24 |
| Finished | Aug 27 10:00:49 AM UTC 24 |
| Peak memory | 333348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264103581 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multiple_keys.1264103581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/14.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access.1403350818 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 873361240 ps |
| CPU time | 19.61 seconds |
| Started | Aug 27 09:58:30 AM UTC 24 |
| Finished | Aug 27 09:58:51 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403350818 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_partial_access.1403350818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/14.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.1318923363 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 85538074295 ps |
| CPU time | 556.76 seconds |
| Started | Aug 27 09:58:43 AM UTC 24 |
| Finished | Aug 27 10:08:07 AM UTC 24 |
| Peak memory | 211564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318923363 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_partial_a ccess_b2b.1318923363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/14.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.3298020030 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 344418046 ps |
| CPU time | 5.27 seconds |
| Started | Aug 27 09:59:43 AM UTC 24 |
| Finished | Aug 27 09:59:49 AM UTC 24 |
| Peak memory | 211912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298020030 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.3298020030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/14.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_regwen.449704202 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 20244963894 ps |
| CPU time | 1108.11 seconds |
| Started | Aug 27 09:59:25 AM UTC 24 |
| Finished | Aug 27 10:18:05 AM UTC 24 |
| Peak memory | 384468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449704202 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.449704202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/14.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_smoke.1296827339 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 896949209 ps |
| CPU time | 29.26 seconds |
| Started | Aug 27 09:58:11 AM UTC 24 |
| Finished | Aug 27 09:58:42 AM UTC 24 |
| Peak memory | 211504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296827339 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.1296827339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/14.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_all.183796814 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 175513098151 ps |
| CPU time | 4954.95 seconds |
| Started | Aug 27 10:00:40 AM UTC 24 |
| Finished | Aug 27 11:24:11 AM UTC 24 |
| Peak memory | 392360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18379681 4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all.183796814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/14.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.3334979159 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 3708207064 ps |
| CPU time | 165.65 seconds |
| Started | Aug 27 10:00:21 AM UTC 24 |
| Finished | Aug 27 10:03:09 AM UTC 24 |
| Peak memory | 335452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334979159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.3334979159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/14.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.2128238625 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 15139555104 ps |
| CPU time | 341.38 seconds |
| Started | Aug 27 09:58:23 AM UTC 24 |
| Finished | Aug 27 10:04:09 AM UTC 24 |
| Peak memory | 211588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128238625 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_pipeline.2128238625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/14.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.110918981 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 1471080566 ps |
| CPU time | 22.87 seconds |
| Started | Aug 27 09:58:59 AM UTC 24 |
| Finished | Aug 27 09:59:24 AM UTC 24 |
| Peak memory | 286252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =110918981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ throughput_w_partial_write.110918981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/14.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.4192735468 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 7865818072 ps |
| CPU time | 548.13 seconds |
| Started | Aug 27 10:01:59 AM UTC 24 |
| Finished | Aug 27 10:11:14 AM UTC 24 |
| Peak memory | 368164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192735468 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_access_duri ng_key_req.4192735468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/15.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_alert_test.3570601650 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 22308569 ps |
| CPU time | 1 seconds |
| Started | Aug 27 10:04:01 AM UTC 24 |
| Finished | Aug 27 10:04:03 AM UTC 24 |
| Peak memory | 210736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570601650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_alert_test.3570601650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/15.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_bijection.1866748807 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 6965734161 ps |
| CPU time | 672.88 seconds |
| Started | Aug 27 10:01:12 AM UTC 24 |
| Finished | Aug 27 10:12:34 AM UTC 24 |
| Peak memory | 211612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866748807 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection.1866748807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/15.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_executable.3771055293 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 24336558043 ps |
| CPU time | 537.74 seconds |
| Started | Aug 27 10:02:27 AM UTC 24 |
| Finished | Aug 27 10:11:31 AM UTC 24 |
| Peak memory | 384552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771055293 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executable.3771055293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/15.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.3844030938 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 11139223265 ps |
| CPU time | 104.67 seconds |
| Started | Aug 27 10:01:59 AM UTC 24 |
| Finished | Aug 27 10:03:46 AM UTC 24 |
| Peak memory | 211612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844030938 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_escalation.3844030938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/15.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.3762970645 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 6264189958 ps |
| CPU time | 24.12 seconds |
| Started | Aug 27 10:01:33 AM UTC 24 |
| Finished | Aug 27 10:01:58 AM UTC 24 |
| Peak memory | 251560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3762970645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ max_throughput.3762970645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/15.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.4010752576 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 17866804214 ps |
| CPU time | 156.17 seconds |
| Started | Aug 27 10:03:15 AM UTC 24 |
| Finished | Aug 27 10:05:54 AM UTC 24 |
| Peak memory | 229076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010752576 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_mem_partial_access.4010752576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/15.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.2819894688 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 106385881126 ps |
| CPU time | 329.17 seconds |
| Started | Aug 27 10:03:10 AM UTC 24 |
| Finished | Aug 27 10:08:43 AM UTC 24 |
| Peak memory | 211696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819894688 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_mem_walk.2819894688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/15.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.3004074525 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 57664539958 ps |
| CPU time | 461.14 seconds |
| Started | Aug 27 10:01:10 AM UTC 24 |
| Finished | Aug 27 10:08:57 AM UTC 24 |
| Peak memory | 360072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004074525 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multiple_keys.3004074525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/15.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access.44808678 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 413082289 ps |
| CPU time | 20.36 seconds |
| Started | Aug 27 10:01:20 AM UTC 24 |
| Finished | Aug 27 10:01:41 AM UTC 24 |
| Peak memory | 263640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44808678 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_partial_access.44808678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/15.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.2557405412 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 15606730805 ps |
| CPU time | 394.07 seconds |
| Started | Aug 27 10:01:30 AM UTC 24 |
| Finished | Aug 27 10:08:09 AM UTC 24 |
| Peak memory | 211760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557405412 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_partial_a ccess_b2b.2557405412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/15.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.2115057829 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 1306805256 ps |
| CPU time | 6.48 seconds |
| Started | Aug 27 10:03:07 AM UTC 24 |
| Finished | Aug 27 10:03:14 AM UTC 24 |
| Peak memory | 211912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115057829 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.2115057829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/15.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_regwen.1599997804 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 15391114703 ps |
| CPU time | 663.24 seconds |
| Started | Aug 27 10:02:54 AM UTC 24 |
| Finished | Aug 27 10:14:05 AM UTC 24 |
| Peak memory | 388588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599997804 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.1599997804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/15.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_smoke.2041396713 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 805581238 ps |
| CPU time | 15.51 seconds |
| Started | Aug 27 10:00:53 AM UTC 24 |
| Finished | Aug 27 10:01:10 AM UTC 24 |
| Peak memory | 251332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041396713 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.2041396713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/15.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all.1294730260 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 144218714309 ps |
| CPU time | 3842.66 seconds |
| Started | Aug 27 10:03:47 AM UTC 24 |
| Finished | Aug 27 11:08:30 AM UTC 24 |
| Peak memory | 392300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12947302 60 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_a ll.1294730260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/15.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.1500715546 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 1152453124 ps |
| CPU time | 47.59 seconds |
| Started | Aug 27 10:03:29 AM UTC 24 |
| Finished | Aug 27 10:04:19 AM UTC 24 |
| Peak memory | 228960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500715546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.1500715546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/15.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.1619106006 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 14221810900 ps |
| CPU time | 310.29 seconds |
| Started | Aug 27 10:01:14 AM UTC 24 |
| Finished | Aug 27 10:06:28 AM UTC 24 |
| Peak memory | 211628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619106006 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_pipeline.1619106006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/15.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.2225142606 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 828947178 ps |
| CPU time | 103.59 seconds |
| Started | Aug 27 10:01:42 AM UTC 24 |
| Finished | Aug 27 10:03:28 AM UTC 24 |
| Peak memory | 380580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2225142606 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl _throughput_w_partial_write.2225142606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/15.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.3818722965 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 19238853287 ps |
| CPU time | 88.12 seconds |
| Started | Aug 27 10:05:30 AM UTC 24 |
| Finished | Aug 27 10:07:00 AM UTC 24 |
| Peak memory | 306740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818722965 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_access_duri ng_key_req.3818722965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/16.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_alert_test.4190054451 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 21004737 ps |
| CPU time | 0.95 seconds |
| Started | Aug 27 10:07:01 AM UTC 24 |
| Finished | Aug 27 10:07:03 AM UTC 24 |
| Peak memory | 210736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190054451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_alert_test.4190054451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/16.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_bijection.962415412 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 398085574317 ps |
| CPU time | 1794.56 seconds |
| Started | Aug 27 10:04:19 AM UTC 24 |
| Finished | Aug 27 10:34:32 AM UTC 24 |
| Peak memory | 213248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962415412 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection.962415412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/16.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_executable.3745578204 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 102333727605 ps |
| CPU time | 731.92 seconds |
| Started | Aug 27 10:05:42 AM UTC 24 |
| Finished | Aug 27 10:18:02 AM UTC 24 |
| Peak memory | 386720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745578204 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executable.3745578204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/16.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.3561994559 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 20487439455 ps |
| CPU time | 63.08 seconds |
| Started | Aug 27 10:05:29 AM UTC 24 |
| Finished | Aug 27 10:06:34 AM UTC 24 |
| Peak memory | 211572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561994559 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_escalation.3561994559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/16.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.2824258927 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 5143561238 ps |
| CPU time | 48.15 seconds |
| Started | Aug 27 10:04:39 AM UTC 24 |
| Finished | Aug 27 10:05:29 AM UTC 24 |
| Peak memory | 306920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2824258927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ max_throughput.2824258927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/16.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.266819064 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 9695770368 ps |
| CPU time | 195.92 seconds |
| Started | Aug 27 10:06:35 AM UTC 24 |
| Finished | Aug 27 10:09:54 AM UTC 24 |
| Peak memory | 228860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266819064 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_mem_partial_access.266819064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/16.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.1715542223 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 13167794406 ps |
| CPU time | 147.42 seconds |
| Started | Aug 27 10:06:28 AM UTC 24 |
| Finished | Aug 27 10:08:59 AM UTC 24 |
| Peak memory | 221888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715542223 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_mem_walk.1715542223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/16.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.1870281651 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 9976315545 ps |
| CPU time | 381.87 seconds |
| Started | Aug 27 10:04:10 AM UTC 24 |
| Finished | Aug 27 10:10:37 AM UTC 24 |
| Peak memory | 386528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870281651 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multiple_keys.1870281651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/16.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access.1755648039 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 7713238635 ps |
| CPU time | 38.54 seconds |
| Started | Aug 27 10:04:26 AM UTC 24 |
| Finished | Aug 27 10:05:07 AM UTC 24 |
| Peak memory | 211572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755648039 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_partial_access.1755648039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/16.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.1558698783 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 18520281974 ps |
| CPU time | 350.04 seconds |
| Started | Aug 27 10:04:35 AM UTC 24 |
| Finished | Aug 27 10:10:30 AM UTC 24 |
| Peak memory | 211888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558698783 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_partial_a ccess_b2b.1558698783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/16.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.3960170510 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 1620905482 ps |
| CPU time | 6.49 seconds |
| Started | Aug 27 10:06:27 AM UTC 24 |
| Finished | Aug 27 10:06:35 AM UTC 24 |
| Peak memory | 211912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960170510 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.3960170510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/16.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_regwen.3732495839 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 18290632766 ps |
| CPU time | 856.3 seconds |
| Started | Aug 27 10:05:54 AM UTC 24 |
| Finished | Aug 27 10:20:19 AM UTC 24 |
| Peak memory | 380452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732495839 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.3732495839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/16.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_smoke.861128080 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 1545031002 ps |
| CPU time | 20.09 seconds |
| Started | Aug 27 10:04:04 AM UTC 24 |
| Finished | Aug 27 10:04:25 AM UTC 24 |
| Peak memory | 211556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861128080 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.861128080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/16.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all.3305565403 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 34640588016 ps |
| CPU time | 2563.26 seconds |
| Started | Aug 27 10:06:53 AM UTC 24 |
| Finished | Aug 27 10:50:02 AM UTC 24 |
| Peak memory | 392292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33055654 03 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_a ll.3305565403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/16.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.3174036317 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 1160321187 ps |
| CPU time | 15.32 seconds |
| Started | Aug 27 10:06:36 AM UTC 24 |
| Finished | Aug 27 10:06:52 AM UTC 24 |
| Peak memory | 221868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174036317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.3174036317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/16.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.3435193805 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 11231381410 ps |
| CPU time | 413.12 seconds |
| Started | Aug 27 10:04:22 AM UTC 24 |
| Finished | Aug 27 10:11:21 AM UTC 24 |
| Peak memory | 211756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435193805 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_pipeline.3435193805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/16.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.2178675779 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 774232962 ps |
| CPU time | 77.37 seconds |
| Started | Aug 27 10:05:08 AM UTC 24 |
| Finished | Aug 27 10:06:27 AM UTC 24 |
| Peak memory | 357860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2178675779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl _throughput_w_partial_write.2178675779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/16.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.721934884 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 51898373397 ps |
| CPU time | 806.42 seconds |
| Started | Aug 27 10:08:58 AM UTC 24 |
| Finished | Aug 27 10:22:33 AM UTC 24 |
| Peak memory | 388776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721934884 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_access_durin g_key_req.721934884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/17.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_alert_test.782297620 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 14565490 ps |
| CPU time | 1.03 seconds |
| Started | Aug 27 10:10:31 AM UTC 24 |
| Finished | Aug 27 10:10:33 AM UTC 24 |
| Peak memory | 210732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782297620 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_alert_test.782297620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/17.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_bijection.844436542 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 135076683181 ps |
| CPU time | 2291.27 seconds |
| Started | Aug 27 10:07:34 AM UTC 24 |
| Finished | Aug 27 10:46:11 AM UTC 24 |
| Peak memory | 213180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844436542 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection.844436542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/17.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_executable.2445448963 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 37781597832 ps |
| CPU time | 232.18 seconds |
| Started | Aug 27 10:08:59 AM UTC 24 |
| Finished | Aug 27 10:12:55 AM UTC 24 |
| Peak memory | 329256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445448963 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executable.2445448963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/17.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.2779509725 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 42675607227 ps |
| CPU time | 91.33 seconds |
| Started | Aug 27 10:08:45 AM UTC 24 |
| Finished | Aug 27 10:10:18 AM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779509725 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_escalation.2779509725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/17.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.852254637 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 1505280800 ps |
| CPU time | 69.66 seconds |
| Started | Aug 27 10:08:41 AM UTC 24 |
| Finished | Aug 27 10:09:52 AM UTC 24 |
| Peak memory | 355740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 852254637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_m ax_throughput.852254637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/17.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.3758672926 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 1647628001 ps |
| CPU time | 70.88 seconds |
| Started | Aug 27 10:09:55 AM UTC 24 |
| Finished | Aug 27 10:11:08 AM UTC 24 |
| Peak memory | 221808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758672926 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_mem_partial_access.3758672926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/17.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.2375122256 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 64139223576 ps |
| CPU time | 197.6 seconds |
| Started | Aug 27 10:09:53 AM UTC 24 |
| Finished | Aug 27 10:13:13 AM UTC 24 |
| Peak memory | 211692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375122256 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_mem_walk.2375122256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/17.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.2042500638 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 3929846326 ps |
| CPU time | 262.47 seconds |
| Started | Aug 27 10:07:33 AM UTC 24 |
| Finished | Aug 27 10:12:00 AM UTC 24 |
| Peak memory | 374296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042500638 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multiple_keys.2042500638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/17.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access.1480868703 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 5337274342 ps |
| CPU time | 28.3 seconds |
| Started | Aug 27 10:08:09 AM UTC 24 |
| Finished | Aug 27 10:08:40 AM UTC 24 |
| Peak memory | 211752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1480868703 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_partial_access.1480868703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/17.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.1431913424 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 45013401976 ps |
| CPU time | 317.31 seconds |
| Started | Aug 27 10:08:12 AM UTC 24 |
| Finished | Aug 27 10:13:33 AM UTC 24 |
| Peak memory | 211792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431913424 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_partial_a ccess_b2b.1431913424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/17.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.2122164484 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 364997601 ps |
| CPU time | 6.05 seconds |
| Started | Aug 27 10:09:53 AM UTC 24 |
| Finished | Aug 27 10:10:00 AM UTC 24 |
| Peak memory | 211644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122164484 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.2122164484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/17.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_regwen.1069271886 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 9941369541 ps |
| CPU time | 569.06 seconds |
| Started | Aug 27 10:09:18 AM UTC 24 |
| Finished | Aug 27 10:18:54 AM UTC 24 |
| Peak memory | 378328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069271886 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.1069271886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/17.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_smoke.50461280 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 1274517305 ps |
| CPU time | 98.05 seconds |
| Started | Aug 27 10:07:04 AM UTC 24 |
| Finished | Aug 27 10:08:44 AM UTC 24 |
| Peak memory | 378456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50461280 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.50461280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/17.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all.695143065 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 60152821452 ps |
| CPU time | 2658.66 seconds |
| Started | Aug 27 10:10:19 AM UTC 24 |
| Finished | Aug 27 10:55:03 AM UTC 24 |
| Peak memory | 400356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69514306 5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all.695143065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/17.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.1275592594 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 1540732190 ps |
| CPU time | 123.99 seconds |
| Started | Aug 27 10:10:01 AM UTC 24 |
| Finished | Aug 27 10:12:07 AM UTC 24 |
| Peak memory | 376428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275592594 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.1275592594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/17.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.2099156027 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 5184167622 ps |
| CPU time | 392 seconds |
| Started | Aug 27 10:08:07 AM UTC 24 |
| Finished | Aug 27 10:14:44 AM UTC 24 |
| Peak memory | 211576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099156027 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_pipeline.2099156027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/17.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.1136434001 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 1559076470 ps |
| CPU time | 66.39 seconds |
| Started | Aug 27 10:08:44 AM UTC 24 |
| Finished | Aug 27 10:09:52 AM UTC 24 |
| Peak memory | 322980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1136434001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl _throughput_w_partial_write.1136434001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/17.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.4004823502 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 38463264528 ps |
| CPU time | 691.51 seconds |
| Started | Aug 27 10:12:00 AM UTC 24 |
| Finished | Aug 27 10:23:40 AM UTC 24 |
| Peak memory | 382504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004823502 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_access_duri ng_key_req.4004823502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/18.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_alert_test.3293433141 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 25160649 ps |
| CPU time | 0.88 seconds |
| Started | Aug 27 10:13:14 AM UTC 24 |
| Finished | Aug 27 10:13:16 AM UTC 24 |
| Peak memory | 210876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293433141 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_alert_test.3293433141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/18.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_bijection.345486382 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 849271019860 ps |
| CPU time | 2937.77 seconds |
| Started | Aug 27 10:11:08 AM UTC 24 |
| Finished | Aug 27 11:00:41 AM UTC 24 |
| Peak memory | 213244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345486382 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection.345486382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/18.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_executable.264419830 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 19260465375 ps |
| CPU time | 1000.55 seconds |
| Started | Aug 27 10:12:08 AM UTC 24 |
| Finished | Aug 27 10:29:01 AM UTC 24 |
| Peak memory | 386712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264419830 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executable.264419830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/18.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.2972436033 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 57090213693 ps |
| CPU time | 156.68 seconds |
| Started | Aug 27 10:11:53 AM UTC 24 |
| Finished | Aug 27 10:14:32 AM UTC 24 |
| Peak memory | 221724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972436033 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_escalation.2972436033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/18.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.443806122 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 2870520650 ps |
| CPU time | 19.5 seconds |
| Started | Aug 27 10:11:32 AM UTC 24 |
| Finished | Aug 27 10:11:52 AM UTC 24 |
| Peak memory | 247456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 443806122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_m ax_throughput.443806122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/18.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.1196513918 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 2708300847 ps |
| CPU time | 96.27 seconds |
| Started | Aug 27 10:12:53 AM UTC 24 |
| Finished | Aug 27 10:14:31 AM UTC 24 |
| Peak memory | 221808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196513918 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_mem_partial_access.1196513918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/18.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.3939013103 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 28827407977 ps |
| CPU time | 153.3 seconds |
| Started | Aug 27 10:12:44 AM UTC 24 |
| Finished | Aug 27 10:15:19 AM UTC 24 |
| Peak memory | 221940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939013103 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_mem_walk.3939013103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/18.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.2490992272 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 32975405257 ps |
| CPU time | 1111.02 seconds |
| Started | Aug 27 10:10:37 AM UTC 24 |
| Finished | Aug 27 10:29:21 AM UTC 24 |
| Peak memory | 384464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490992272 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multiple_keys.2490992272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/18.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access.1885854544 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 3416861511 ps |
| CPU time | 28.98 seconds |
| Started | Aug 27 10:11:22 AM UTC 24 |
| Finished | Aug 27 10:11:52 AM UTC 24 |
| Peak memory | 211544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885854544 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_partial_access.1885854544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/18.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.3719325294 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 18405328774 ps |
| CPU time | 375.89 seconds |
| Started | Aug 27 10:11:28 AM UTC 24 |
| Finished | Aug 27 10:17:49 AM UTC 24 |
| Peak memory | 211652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719325294 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_partial_a ccess_b2b.3719325294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/18.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.1040035953 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 1402324595 ps |
| CPU time | 6.54 seconds |
| Started | Aug 27 10:12:36 AM UTC 24 |
| Finished | Aug 27 10:12:43 AM UTC 24 |
| Peak memory | 211644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040035953 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.1040035953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/18.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_regwen.1210909408 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 6106371229 ps |
| CPU time | 855.79 seconds |
| Started | Aug 27 10:12:17 AM UTC 24 |
| Finished | Aug 27 10:26:43 AM UTC 24 |
| Peak memory | 384560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210909408 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.1210909408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/18.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_smoke.1535739054 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 5266423901 ps |
| CPU time | 100.19 seconds |
| Started | Aug 27 10:10:34 AM UTC 24 |
| Finished | Aug 27 10:12:17 AM UTC 24 |
| Peak memory | 376484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535739054 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.1535739054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/18.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all.1908149066 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 19435064987 ps |
| CPU time | 1071.94 seconds |
| Started | Aug 27 10:13:09 AM UTC 24 |
| Finished | Aug 27 10:31:13 AM UTC 24 |
| Peak memory | 390696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19081490 66 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_a ll.1908149066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/18.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.1752985214 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 4912942951 ps |
| CPU time | 94.12 seconds |
| Started | Aug 27 10:12:56 AM UTC 24 |
| Finished | Aug 27 10:14:32 AM UTC 24 |
| Peak memory | 347744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752985214 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.1752985214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/18.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.4239046749 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 13696272839 ps |
| CPU time | 286.89 seconds |
| Started | Aug 27 10:11:15 AM UTC 24 |
| Finished | Aug 27 10:16:05 AM UTC 24 |
| Peak memory | 211584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239046749 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_pipeline.4239046749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/18.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.2109008788 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 904041962 ps |
| CPU time | 73.4 seconds |
| Started | Aug 27 10:11:53 AM UTC 24 |
| Finished | Aug 27 10:13:08 AM UTC 24 |
| Peak memory | 351716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2109008788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl _throughput_w_partial_write.2109008788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/18.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.694814315 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 15376552262 ps |
| CPU time | 846.61 seconds |
| Started | Aug 27 10:14:45 AM UTC 24 |
| Finished | Aug 27 10:29:01 AM UTC 24 |
| Peak memory | 380572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694814315 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_access_durin g_key_req.694814315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/19.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_alert_test.1090291653 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 19200203 ps |
| CPU time | 0.93 seconds |
| Started | Aug 27 10:16:51 AM UTC 24 |
| Finished | Aug 27 10:16:53 AM UTC 24 |
| Peak memory | 210816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090291653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_alert_test.1090291653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/19.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_bijection.1560814231 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 17388958694 ps |
| CPU time | 1107.29 seconds |
| Started | Aug 27 10:13:30 AM UTC 24 |
| Finished | Aug 27 10:32:10 AM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560814231 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection.1560814231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/19.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_executable.3061420695 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 19487045953 ps |
| CPU time | 872.83 seconds |
| Started | Aug 27 10:14:56 AM UTC 24 |
| Finished | Aug 27 10:29:39 AM UTC 24 |
| Peak memory | 378324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061420695 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executable.3061420695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/19.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.757764808 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 7899867264 ps |
| CPU time | 84.61 seconds |
| Started | Aug 27 10:14:33 AM UTC 24 |
| Finished | Aug 27 10:16:00 AM UTC 24 |
| Peak memory | 221740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757764808 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_escalation.757764808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/19.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.2873961406 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 3028192145 ps |
| CPU time | 22.48 seconds |
| Started | Aug 27 10:14:32 AM UTC 24 |
| Finished | Aug 27 10:14:56 AM UTC 24 |
| Peak memory | 261872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2873961406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ max_throughput.2873961406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/19.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.2790780110 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 3188652511 ps |
| CPU time | 130.76 seconds |
| Started | Aug 27 10:16:01 AM UTC 24 |
| Finished | Aug 27 10:18:14 AM UTC 24 |
| Peak memory | 222080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790780110 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_mem_partial_access.2790780110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/19.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.568486913 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 13851925722 ps |
| CPU time | 205.24 seconds |
| Started | Aug 27 10:15:32 AM UTC 24 |
| Finished | Aug 27 10:19:01 AM UTC 24 |
| Peak memory | 221808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568486913 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_mem_walk.568486913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/19.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.204261007 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 22278518912 ps |
| CPU time | 858.41 seconds |
| Started | Aug 27 10:13:17 AM UTC 24 |
| Finished | Aug 27 10:27:45 AM UTC 24 |
| Peak memory | 388640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204261007 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multiple_keys.204261007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/19.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access.3392374982 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 913341560 ps |
| CPU time | 13.05 seconds |
| Started | Aug 27 10:14:07 AM UTC 24 |
| Finished | Aug 27 10:14:21 AM UTC 24 |
| Peak memory | 211692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392374982 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_partial_access.3392374982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/19.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.3045278119 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 204380256631 ps |
| CPU time | 484.57 seconds |
| Started | Aug 27 10:14:22 AM UTC 24 |
| Finished | Aug 27 10:22:33 AM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045278119 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_partial_a ccess_b2b.3045278119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/19.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.643303121 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 1039589843 ps |
| CPU time | 6.44 seconds |
| Started | Aug 27 10:15:24 AM UTC 24 |
| Finished | Aug 27 10:15:31 AM UTC 24 |
| Peak memory | 211836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643303121 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.643303121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/19.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_regwen.3525873748 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 41977313738 ps |
| CPU time | 373.27 seconds |
| Started | Aug 27 10:15:21 AM UTC 24 |
| Finished | Aug 27 10:21:39 AM UTC 24 |
| Peak memory | 376356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525873748 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.3525873748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/19.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_smoke.463186625 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 1734487113 ps |
| CPU time | 13.15 seconds |
| Started | Aug 27 10:13:15 AM UTC 24 |
| Finished | Aug 27 10:13:30 AM UTC 24 |
| Peak memory | 249240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463186625 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.463186625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/19.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all.2113686689 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 100651553833 ps |
| CPU time | 325.43 seconds |
| Started | Aug 27 10:16:28 AM UTC 24 |
| Finished | Aug 27 10:21:59 AM UTC 24 |
| Peak memory | 267812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21136866 89 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_a ll.2113686689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/19.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.1531551641 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 977917175 ps |
| CPU time | 43.13 seconds |
| Started | Aug 27 10:16:06 AM UTC 24 |
| Finished | Aug 27 10:16:51 AM UTC 24 |
| Peak memory | 221872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531551641 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.1531551641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/19.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.2642408119 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 7973348709 ps |
| CPU time | 302.96 seconds |
| Started | Aug 27 10:13:34 AM UTC 24 |
| Finished | Aug 27 10:18:41 AM UTC 24 |
| Peak memory | 211556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642408119 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_pipeline.2642408119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/19.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.3329321508 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 825364133 ps |
| CPU time | 112.28 seconds |
| Started | Aug 27 10:14:33 AM UTC 24 |
| Finished | Aug 27 10:16:28 AM UTC 24 |
| Peak memory | 382564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3329321508 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl _throughput_w_partial_write.3329321508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/19.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.4276685895 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 10815162207 ps |
| CPU time | 644.9 seconds |
| Started | Aug 27 09:22:52 AM UTC 24 |
| Finished | Aug 27 09:33:45 AM UTC 24 |
| Peak memory | 384484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276685895 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_access_durin g_key_req.4276685895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/2.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_alert_test.1872751520 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 13382655 ps |
| CPU time | 0.98 seconds |
| Started | Aug 27 09:23:26 AM UTC 24 |
| Finished | Aug 27 09:23:28 AM UTC 24 |
| Peak memory | 210812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872751520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_alert_test.1872751520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/2.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_bijection.1838413688 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 435545417524 ps |
| CPU time | 2389.16 seconds |
| Started | Aug 27 09:20:56 AM UTC 24 |
| Finished | Aug 27 10:01:12 AM UTC 24 |
| Peak memory | 213176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838413688 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection.1838413688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/2.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_executable.2432959245 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 35195516343 ps |
| CPU time | 744.89 seconds |
| Started | Aug 27 09:22:57 AM UTC 24 |
| Finished | Aug 27 09:35:30 AM UTC 24 |
| Peak memory | 388772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432959245 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executable.2432959245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/2.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.2049001564 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 77676022032 ps |
| CPU time | 147.91 seconds |
| Started | Aug 27 09:22:18 AM UTC 24 |
| Finished | Aug 27 09:24:49 AM UTC 24 |
| Peak memory | 211692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049001564 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_escalation.2049001564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/2.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.4070944932 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 1666128624 ps |
| CPU time | 127.8 seconds |
| Started | Aug 27 09:21:46 AM UTC 24 |
| Finished | Aug 27 09:23:56 AM UTC 24 |
| Peak memory | 380324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4070944932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_m ax_throughput.4070944932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/2.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.3042370524 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 961738143 ps |
| CPU time | 92.55 seconds |
| Started | Aug 27 09:23:15 AM UTC 24 |
| Finished | Aug 27 09:24:50 AM UTC 24 |
| Peak memory | 221812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042370524 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_mem_partial_access.3042370524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/2.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.1543680016 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 71735325416 ps |
| CPU time | 376.1 seconds |
| Started | Aug 27 09:23:14 AM UTC 24 |
| Finished | Aug 27 09:29:35 AM UTC 24 |
| Peak memory | 222064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543680016 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_mem_walk.1543680016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/2.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.2305097557 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 10472419584 ps |
| CPU time | 127.41 seconds |
| Started | Aug 27 09:20:51 AM UTC 24 |
| Finished | Aug 27 09:23:01 AM UTC 24 |
| Peak memory | 300708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305097557 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multiple_keys.2305097557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/2.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access.1620869505 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 871276392 ps |
| CPU time | 17.09 seconds |
| Started | Aug 27 09:21:26 AM UTC 24 |
| Finished | Aug 27 09:21:45 AM UTC 24 |
| Peak memory | 247184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620869505 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_partial_access.1620869505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/2.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.1317886523 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 32328570445 ps |
| CPU time | 458.93 seconds |
| Started | Aug 27 09:21:42 AM UTC 24 |
| Finished | Aug 27 09:29:26 AM UTC 24 |
| Peak memory | 211548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317886523 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_partial_ac cess_b2b.1317886523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/2.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.3095143270 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 675854971 ps |
| CPU time | 4.35 seconds |
| Started | Aug 27 09:23:09 AM UTC 24 |
| Finished | Aug 27 09:23:15 AM UTC 24 |
| Peak memory | 211696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095143270 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.3095143270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/2.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_regwen.52495370 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 70088763487 ps |
| CPU time | 1075.59 seconds |
| Started | Aug 27 09:23:02 AM UTC 24 |
| Finished | Aug 27 09:41:09 AM UTC 24 |
| Peak memory | 384556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52495370 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.52495370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/2.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.1631928411 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 397934721 ps |
| CPU time | 2.9 seconds |
| Started | Aug 27 09:23:21 AM UTC 24 |
| Finished | Aug 27 09:23:25 AM UTC 24 |
| Peak memory | 247824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631928411 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_sec_cm.1631928411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_smoke.2002766943 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 370296124 ps |
| CPU time | 5.38 seconds |
| Started | Aug 27 09:20:49 AM UTC 24 |
| Finished | Aug 27 09:20:55 AM UTC 24 |
| Peak memory | 211572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002766943 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.2002766943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/2.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all.1749707075 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 544392317847 ps |
| CPU time | 5383.43 seconds |
| Started | Aug 27 09:23:18 AM UTC 24 |
| Finished | Aug 27 10:53:55 AM UTC 24 |
| Peak memory | 400544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17497070 75 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all.1749707075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/2.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.2903429825 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 763423895 ps |
| CPU time | 17.17 seconds |
| Started | Aug 27 09:23:15 AM UTC 24 |
| Finished | Aug 27 09:23:34 AM UTC 24 |
| Peak memory | 228076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903429825 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.2903429825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/2.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.1952346403 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 13462169470 ps |
| CPU time | 181.08 seconds |
| Started | Aug 27 09:21:04 AM UTC 24 |
| Finished | Aug 27 09:24:08 AM UTC 24 |
| Peak memory | 211624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952346403 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_pipeline.1952346403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/2.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.121776804 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 810895871 ps |
| CPU time | 97.34 seconds |
| Started | Aug 27 09:21:58 AM UTC 24 |
| Finished | Aug 27 09:23:37 AM UTC 24 |
| Peak memory | 380380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =121776804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_t hroughput_w_partial_write.121776804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/2.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.2734950002 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 14702224724 ps |
| CPU time | 710.6 seconds |
| Started | Aug 27 10:18:56 AM UTC 24 |
| Finished | Aug 27 10:30:55 AM UTC 24 |
| Peak memory | 388648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734950002 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_access_duri ng_key_req.2734950002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/20.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_alert_test.1788173660 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 67026026 ps |
| CPU time | 0.94 seconds |
| Started | Aug 27 10:20:44 AM UTC 24 |
| Finished | Aug 27 10:20:46 AM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788173660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_alert_test.1788173660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/20.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_bijection.1840088859 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 105902587889 ps |
| CPU time | 2703.3 seconds |
| Started | Aug 27 10:17:35 AM UTC 24 |
| Finished | Aug 27 11:03:09 AM UTC 24 |
| Peak memory | 213236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840088859 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection.1840088859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/20.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_executable.1913992241 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 15753166228 ps |
| CPU time | 616.84 seconds |
| Started | Aug 27 10:19:03 AM UTC 24 |
| Finished | Aug 27 10:29:27 AM UTC 24 |
| Peak memory | 388640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913992241 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executable.1913992241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/20.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.3947265369 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 33226832303 ps |
| CPU time | 118.51 seconds |
| Started | Aug 27 10:18:42 AM UTC 24 |
| Finished | Aug 27 10:20:43 AM UTC 24 |
| Peak memory | 225908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947265369 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_escalation.3947265369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/20.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.4148975366 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 1823595586 ps |
| CPU time | 67.75 seconds |
| Started | Aug 27 10:18:05 AM UTC 24 |
| Finished | Aug 27 10:19:15 AM UTC 24 |
| Peak memory | 349608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4148975366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ max_throughput.4148975366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/20.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.3186825209 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 8992183176 ps |
| CPU time | 210.64 seconds |
| Started | Aug 27 10:19:51 AM UTC 24 |
| Finished | Aug 27 10:23:25 AM UTC 24 |
| Peak memory | 221796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186825209 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_mem_partial_access.3186825209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/20.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.573271776 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 5474306403 ps |
| CPU time | 302.51 seconds |
| Started | Aug 27 10:19:39 AM UTC 24 |
| Finished | Aug 27 10:24:46 AM UTC 24 |
| Peak memory | 221808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573271776 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_mem_walk.573271776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/20.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.3283408731 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 65436291106 ps |
| CPU time | 813.53 seconds |
| Started | Aug 27 10:17:29 AM UTC 24 |
| Finished | Aug 27 10:31:11 AM UTC 24 |
| Peak memory | 386512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283408731 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multiple_keys.3283408731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/20.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access.173735420 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 1372764429 ps |
| CPU time | 99.41 seconds |
| Started | Aug 27 10:17:49 AM UTC 24 |
| Finished | Aug 27 10:19:31 AM UTC 24 |
| Peak memory | 364004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173735420 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_partial_access.173735420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/20.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.1929446496 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 15552017839 ps |
| CPU time | 541.57 seconds |
| Started | Aug 27 10:18:03 AM UTC 24 |
| Finished | Aug 27 10:27:11 AM UTC 24 |
| Peak memory | 211552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929446496 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_partial_a ccess_b2b.1929446496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/20.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.3588682875 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 356820696 ps |
| CPU time | 6 seconds |
| Started | Aug 27 10:19:31 AM UTC 24 |
| Finished | Aug 27 10:19:38 AM UTC 24 |
| Peak memory | 211912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588682875 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.3588682875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/20.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_regwen.2385926833 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 10167530537 ps |
| CPU time | 520.4 seconds |
| Started | Aug 27 10:19:16 AM UTC 24 |
| Finished | Aug 27 10:28:02 AM UTC 24 |
| Peak memory | 388656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385926833 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.2385926833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/20.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_smoke.3949931374 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 2037185008 ps |
| CPU time | 37.53 seconds |
| Started | Aug 27 10:16:54 AM UTC 24 |
| Finished | Aug 27 10:17:34 AM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949931374 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.3949931374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/20.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all.2070098958 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 23033500504 ps |
| CPU time | 2975.87 seconds |
| Started | Aug 27 10:20:35 AM UTC 24 |
| Finished | Aug 27 11:10:39 AM UTC 24 |
| Peak memory | 392288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20700989 58 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_a ll.2070098958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/20.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.2738758985 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 749558272 ps |
| CPU time | 13.52 seconds |
| Started | Aug 27 10:20:20 AM UTC 24 |
| Finished | Aug 27 10:20:35 AM UTC 24 |
| Peak memory | 221876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738758985 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.2738758985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/20.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.2339957969 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 3370115794 ps |
| CPU time | 236.67 seconds |
| Started | Aug 27 10:17:45 AM UTC 24 |
| Finished | Aug 27 10:21:45 AM UTC 24 |
| Peak memory | 211640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339957969 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_pipeline.2339957969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/20.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.1395524407 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 3145088212 ps |
| CPU time | 92.95 seconds |
| Started | Aug 27 10:18:15 AM UTC 24 |
| Finished | Aug 27 10:19:51 AM UTC 24 |
| Peak memory | 380452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1395524407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl _throughput_w_partial_write.1395524407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/20.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.3626796101 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 6695859813 ps |
| CPU time | 400.39 seconds |
| Started | Aug 27 10:23:24 AM UTC 24 |
| Finished | Aug 27 10:30:10 AM UTC 24 |
| Peak memory | 388644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626796101 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_access_duri ng_key_req.3626796101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/21.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_alert_test.2567096974 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 48210905 ps |
| CPU time | 1.03 seconds |
| Started | Aug 27 10:24:12 AM UTC 24 |
| Finished | Aug 27 10:24:14 AM UTC 24 |
| Peak memory | 210736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567096974 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_alert_test.2567096974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/21.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_bijection.1925267581 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 105557110406 ps |
| CPU time | 2695.15 seconds |
| Started | Aug 27 10:21:10 AM UTC 24 |
| Finished | Aug 27 11:06:36 AM UTC 24 |
| Peak memory | 213232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925267581 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection.1925267581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/21.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_executable.2493612925 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 125972453620 ps |
| CPU time | 1054.14 seconds |
| Started | Aug 27 10:23:26 AM UTC 24 |
| Finished | Aug 27 10:41:12 AM UTC 24 |
| Peak memory | 388808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493612925 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executable.2493612925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/21.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.3680984723 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 36101936283 ps |
| CPU time | 87.65 seconds |
| Started | Aug 27 10:22:34 AM UTC 24 |
| Finished | Aug 27 10:24:03 AM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680984723 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_escalation.3680984723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/21.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.2562871415 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 756650524 ps |
| CPU time | 86.11 seconds |
| Started | Aug 27 10:21:59 AM UTC 24 |
| Finished | Aug 27 10:23:28 AM UTC 24 |
| Peak memory | 359848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2562871415 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ max_throughput.2562871415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/21.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.2468966444 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 12810209539 ps |
| CPU time | 112.74 seconds |
| Started | Aug 27 10:23:40 AM UTC 24 |
| Finished | Aug 27 10:25:36 AM UTC 24 |
| Peak memory | 221872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468966444 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_mem_partial_access.2468966444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/21.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.4257025282 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 23178328343 ps |
| CPU time | 325.77 seconds |
| Started | Aug 27 10:23:40 AM UTC 24 |
| Finished | Aug 27 10:29:11 AM UTC 24 |
| Peak memory | 221816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257025282 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_mem_walk.4257025282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/21.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.3360704807 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 29667691407 ps |
| CPU time | 492.07 seconds |
| Started | Aug 27 10:21:09 AM UTC 24 |
| Finished | Aug 27 10:29:28 AM UTC 24 |
| Peak memory | 378396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360704807 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multiple_keys.3360704807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/21.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access.1941446675 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 2519140606 ps |
| CPU time | 95.42 seconds |
| Started | Aug 27 10:21:45 AM UTC 24 |
| Finished | Aug 27 10:23:23 AM UTC 24 |
| Peak memory | 370212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941446675 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_partial_access.1941446675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/21.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.2811976690 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 48481351074 ps |
| CPU time | 647.81 seconds |
| Started | Aug 27 10:21:46 AM UTC 24 |
| Finished | Aug 27 10:32:43 AM UTC 24 |
| Peak memory | 211780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811976690 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_partial_a ccess_b2b.2811976690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/21.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.1824209328 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 1523403371 ps |
| CPU time | 6.97 seconds |
| Started | Aug 27 10:23:31 AM UTC 24 |
| Finished | Aug 27 10:23:39 AM UTC 24 |
| Peak memory | 211840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824209328 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.1824209328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/21.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_regwen.1519802521 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 70951323238 ps |
| CPU time | 710 seconds |
| Started | Aug 27 10:23:28 AM UTC 24 |
| Finished | Aug 27 10:35:25 AM UTC 24 |
| Peak memory | 388584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519802521 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.1519802521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/21.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_smoke.283197429 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 779791064 ps |
| CPU time | 19.93 seconds |
| Started | Aug 27 10:20:48 AM UTC 24 |
| Finished | Aug 27 10:21:09 AM UTC 24 |
| Peak memory | 211432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283197429 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.283197429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/21.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all.1574864966 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 19559723409 ps |
| CPU time | 2140.72 seconds |
| Started | Aug 27 10:24:05 AM UTC 24 |
| Finished | Aug 27 11:00:05 AM UTC 24 |
| Peak memory | 392164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15748649 66 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_a ll.1574864966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/21.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.3771718324 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 3508100091 ps |
| CPU time | 94.53 seconds |
| Started | Aug 27 10:23:52 AM UTC 24 |
| Finished | Aug 27 10:25:29 AM UTC 24 |
| Peak memory | 228316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771718324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.3771718324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/21.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.3887405545 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 1305759144 ps |
| CPU time | 108.63 seconds |
| Started | Aug 27 10:21:39 AM UTC 24 |
| Finished | Aug 27 10:23:30 AM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887405545 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_pipeline.3887405545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/21.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.1192013677 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 810562253 ps |
| CPU time | 95.37 seconds |
| Started | Aug 27 10:22:34 AM UTC 24 |
| Finished | Aug 27 10:24:11 AM UTC 24 |
| Peak memory | 380304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1192013677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl _throughput_w_partial_write.1192013677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/21.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.2572870012 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 206760616885 ps |
| CPU time | 655.18 seconds |
| Started | Aug 27 10:27:05 AM UTC 24 |
| Finished | Aug 27 10:38:09 AM UTC 24 |
| Peak memory | 388628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572870012 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_access_duri ng_key_req.2572870012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/22.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_alert_test.1604279447 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 14796980 ps |
| CPU time | 0.91 seconds |
| Started | Aug 27 10:29:06 AM UTC 24 |
| Finished | Aug 27 10:29:08 AM UTC 24 |
| Peak memory | 210736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604279447 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_alert_test.1604279447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/22.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_bijection.2102028439 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 17562339235 ps |
| CPU time | 1274.4 seconds |
| Started | Aug 27 10:24:47 AM UTC 24 |
| Finished | Aug 27 10:46:16 AM UTC 24 |
| Peak memory | 213448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102028439 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection.2102028439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/22.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_executable.1723047714 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 130789205906 ps |
| CPU time | 657.54 seconds |
| Started | Aug 27 10:27:12 AM UTC 24 |
| Finished | Aug 27 10:38:18 AM UTC 24 |
| Peak memory | 380444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723047714 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executable.1723047714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/22.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.300788913 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 116052745194 ps |
| CPU time | 129.96 seconds |
| Started | Aug 27 10:26:53 AM UTC 24 |
| Finished | Aug 27 10:29:05 AM UTC 24 |
| Peak memory | 221944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300788913 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_escalation.300788913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/22.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.4144164580 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 2830658142 ps |
| CPU time | 77.76 seconds |
| Started | Aug 27 10:26:44 AM UTC 24 |
| Finished | Aug 27 10:28:03 AM UTC 24 |
| Peak memory | 382628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4144164580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ max_throughput.4144164580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/22.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.3085283955 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 16867302064 ps |
| CPU time | 159.94 seconds |
| Started | Aug 27 10:28:10 AM UTC 24 |
| Finished | Aug 27 10:30:53 AM UTC 24 |
| Peak memory | 228856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085283955 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_mem_partial_access.3085283955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/22.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.1422882026 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 62859181513 ps |
| CPU time | 206.43 seconds |
| Started | Aug 27 10:28:04 AM UTC 24 |
| Finished | Aug 27 10:31:33 AM UTC 24 |
| Peak memory | 211692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422882026 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_mem_walk.1422882026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/22.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.24214134 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 21980149211 ps |
| CPU time | 765.11 seconds |
| Started | Aug 27 10:24:30 AM UTC 24 |
| Finished | Aug 27 10:37:23 AM UTC 24 |
| Peak memory | 388568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24214134 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multiple_keys.24214134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/22.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access.1315620206 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 3738577276 ps |
| CPU time | 66.62 seconds |
| Started | Aug 27 10:25:36 AM UTC 24 |
| Finished | Aug 27 10:26:45 AM UTC 24 |
| Peak memory | 343520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315620206 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_partial_access.1315620206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/22.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.107479707 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 111472945261 ps |
| CPU time | 659.38 seconds |
| Started | Aug 27 10:26:10 AM UTC 24 |
| Finished | Aug 27 10:37:17 AM UTC 24 |
| Peak memory | 211564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107479707 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_partial_ac cess_b2b.107479707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/22.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.1240308770 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 1673679876 ps |
| CPU time | 5.45 seconds |
| Started | Aug 27 10:28:03 AM UTC 24 |
| Finished | Aug 27 10:28:09 AM UTC 24 |
| Peak memory | 211716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240308770 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.1240308770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/22.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_regwen.1398848347 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 25920292997 ps |
| CPU time | 886.3 seconds |
| Started | Aug 27 10:27:46 AM UTC 24 |
| Finished | Aug 27 10:42:42 AM UTC 24 |
| Peak memory | 388548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398848347 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.1398848347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/22.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_smoke.815025006 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 1711891728 ps |
| CPU time | 13.56 seconds |
| Started | Aug 27 10:24:15 AM UTC 24 |
| Finished | Aug 27 10:24:30 AM UTC 24 |
| Peak memory | 247252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815025006 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.815025006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/22.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all.1573850316 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 45680068303 ps |
| CPU time | 3751.57 seconds |
| Started | Aug 27 10:29:01 AM UTC 24 |
| Finished | Aug 27 11:32:11 AM UTC 24 |
| Peak memory | 398704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15738503 16 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_a ll.1573850316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/22.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.2138966487 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 1329557146 ps |
| CPU time | 18.36 seconds |
| Started | Aug 27 10:29:01 AM UTC 24 |
| Finished | Aug 27 10:29:21 AM UTC 24 |
| Peak memory | 221888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138966487 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.2138966487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/22.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.2389850570 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 14507338766 ps |
| CPU time | 289.45 seconds |
| Started | Aug 27 10:25:30 AM UTC 24 |
| Finished | Aug 27 10:30:24 AM UTC 24 |
| Peak memory | 211644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389850570 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_pipeline.2389850570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/22.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.318486417 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 704114834 ps |
| CPU time | 17.44 seconds |
| Started | Aug 27 10:26:46 AM UTC 24 |
| Finished | Aug 27 10:27:04 AM UTC 24 |
| Peak memory | 261728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =318486417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ throughput_w_partial_write.318486417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/22.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.2062579327 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 12891271545 ps |
| CPU time | 915.28 seconds |
| Started | Aug 27 10:30:22 AM UTC 24 |
| Finished | Aug 27 10:45:48 AM UTC 24 |
| Peak memory | 386596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062579327 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_access_duri ng_key_req.2062579327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/23.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_alert_test.2924772558 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 11831503 ps |
| CPU time | 1.02 seconds |
| Started | Aug 27 10:31:12 AM UTC 24 |
| Finished | Aug 27 10:31:14 AM UTC 24 |
| Peak memory | 210736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924772558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_alert_test.2924772558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/23.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_bijection.1279854909 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 144836406001 ps |
| CPU time | 577.32 seconds |
| Started | Aug 27 10:29:22 AM UTC 24 |
| Finished | Aug 27 10:39:06 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279854909 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection.1279854909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/23.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_executable.3333099337 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 201861501478 ps |
| CPU time | 772.82 seconds |
| Started | Aug 27 10:30:24 AM UTC 24 |
| Finished | Aug 27 10:43:26 AM UTC 24 |
| Peak memory | 382616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333099337 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executable.3333099337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/23.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.1309305492 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 12297356338 ps |
| CPU time | 73.75 seconds |
| Started | Aug 27 10:30:10 AM UTC 24 |
| Finished | Aug 27 10:31:26 AM UTC 24 |
| Peak memory | 221800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309305492 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_escalation.1309305492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/23.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.1388236294 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 1013688438 ps |
| CPU time | 60.23 seconds |
| Started | Aug 27 10:29:29 AM UTC 24 |
| Finished | Aug 27 10:30:31 AM UTC 24 |
| Peak memory | 327072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1388236294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ max_throughput.1388236294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/23.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.2167938747 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 1703051236 ps |
| CPU time | 154.25 seconds |
| Started | Aug 27 10:30:53 AM UTC 24 |
| Finished | Aug 27 10:33:30 AM UTC 24 |
| Peak memory | 228892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167938747 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_mem_partial_access.2167938747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/23.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.2271481207 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 17125852085 ps |
| CPU time | 231.42 seconds |
| Started | Aug 27 10:30:41 AM UTC 24 |
| Finished | Aug 27 10:34:36 AM UTC 24 |
| Peak memory | 221816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271481207 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_mem_walk.2271481207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/23.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.2189610920 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 4842784220 ps |
| CPU time | 475.76 seconds |
| Started | Aug 27 10:29:12 AM UTC 24 |
| Finished | Aug 27 10:37:12 AM UTC 24 |
| Peak memory | 382500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189610920 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multiple_keys.2189610920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/23.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access.2448596418 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 4325342284 ps |
| CPU time | 63.93 seconds |
| Started | Aug 27 10:29:28 AM UTC 24 |
| Finished | Aug 27 10:30:33 AM UTC 24 |
| Peak memory | 343592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448596418 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_partial_access.2448596418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/23.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.822538680 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 15116851383 ps |
| CPU time | 524.85 seconds |
| Started | Aug 27 10:29:28 AM UTC 24 |
| Finished | Aug 27 10:38:20 AM UTC 24 |
| Peak memory | 211620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822538680 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_partial_ac cess_b2b.822538680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/23.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.139362069 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 694111874 ps |
| CPU time | 4.41 seconds |
| Started | Aug 27 10:30:35 AM UTC 24 |
| Finished | Aug 27 10:30:40 AM UTC 24 |
| Peak memory | 211892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139362069 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.139362069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/23.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_regwen.1180274085 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 67852342749 ps |
| CPU time | 528.72 seconds |
| Started | Aug 27 10:30:32 AM UTC 24 |
| Finished | Aug 27 10:39:27 AM UTC 24 |
| Peak memory | 372256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180274085 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.1180274085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/23.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_smoke.671123025 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 866114467 ps |
| CPU time | 70.64 seconds |
| Started | Aug 27 10:29:09 AM UTC 24 |
| Finished | Aug 27 10:30:22 AM UTC 24 |
| Peak memory | 337364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671123025 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.671123025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/23.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all.3257298027 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 144769738725 ps |
| CPU time | 3442.15 seconds |
| Started | Aug 27 10:30:55 AM UTC 24 |
| Finished | Aug 27 11:28:52 AM UTC 24 |
| Peak memory | 386156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32572980 27 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_a ll.3257298027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/23.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.513632822 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 1336688304 ps |
| CPU time | 71.84 seconds |
| Started | Aug 27 10:30:53 AM UTC 24 |
| Finished | Aug 27 10:32:07 AM UTC 24 |
| Peak memory | 225956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513632822 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.513632822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/23.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.1547229306 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 14369063163 ps |
| CPU time | 244.23 seconds |
| Started | Aug 27 10:29:22 AM UTC 24 |
| Finished | Aug 27 10:33:29 AM UTC 24 |
| Peak memory | 211648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547229306 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_pipeline.1547229306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/23.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.3770365757 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 792448721 ps |
| CPU time | 69.95 seconds |
| Started | Aug 27 10:29:40 AM UTC 24 |
| Finished | Aug 27 10:30:52 AM UTC 24 |
| Peak memory | 376288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3770365757 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl _throughput_w_partial_write.3770365757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/23.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.3440615131 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 11166816947 ps |
| CPU time | 648.68 seconds |
| Started | Aug 27 10:33:04 AM UTC 24 |
| Finished | Aug 27 10:44:00 AM UTC 24 |
| Peak memory | 380380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440615131 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_access_duri ng_key_req.3440615131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/24.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_alert_test.1631663350 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 56460296 ps |
| CPU time | 0.88 seconds |
| Started | Aug 27 10:35:13 AM UTC 24 |
| Finished | Aug 27 10:35:15 AM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631663350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_alert_test.1631663350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/24.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_bijection.3594928977 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 27396342242 ps |
| CPU time | 2139.31 seconds |
| Started | Aug 27 10:31:27 AM UTC 24 |
| Finished | Aug 27 11:07:31 AM UTC 24 |
| Peak memory | 213248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594928977 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection.3594928977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/24.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_executable.389903977 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 50874195366 ps |
| CPU time | 819.09 seconds |
| Started | Aug 27 10:33:18 AM UTC 24 |
| Finished | Aug 27 10:47:07 AM UTC 24 |
| Peak memory | 370136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389903977 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executable.389903977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/24.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.659910708 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 26257946093 ps |
| CPU time | 74.67 seconds |
| Started | Aug 27 10:32:43 AM UTC 24 |
| Finished | Aug 27 10:34:00 AM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659910708 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_escalation.659910708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/24.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.3673540494 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 702480667 ps |
| CPU time | 10.39 seconds |
| Started | Aug 27 10:32:23 AM UTC 24 |
| Finished | Aug 27 10:32:35 AM UTC 24 |
| Peak memory | 247396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3673540494 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ max_throughput.3673540494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/24.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.1050593212 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 6640266402 ps |
| CPU time | 154.05 seconds |
| Started | Aug 27 10:34:01 AM UTC 24 |
| Finished | Aug 27 10:36:38 AM UTC 24 |
| Peak memory | 221924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050593212 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_mem_partial_access.1050593212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/24.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.2955168983 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 93839153449 ps |
| CPU time | 449.68 seconds |
| Started | Aug 27 10:33:40 AM UTC 24 |
| Finished | Aug 27 10:41:16 AM UTC 24 |
| Peak memory | 222084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955168983 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_mem_walk.2955168983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/24.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.775016313 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 52834753827 ps |
| CPU time | 427.37 seconds |
| Started | Aug 27 10:31:16 AM UTC 24 |
| Finished | Aug 27 10:38:28 AM UTC 24 |
| Peak memory | 384460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775016313 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multiple_keys.775016313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/24.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access.1949805273 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 699784220 ps |
| CPU time | 13.67 seconds |
| Started | Aug 27 10:32:08 AM UTC 24 |
| Finished | Aug 27 10:32:23 AM UTC 24 |
| Peak memory | 217640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949805273 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_partial_access.1949805273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/24.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.2282187553 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 41203290482 ps |
| CPU time | 824.62 seconds |
| Started | Aug 27 10:32:10 AM UTC 24 |
| Finished | Aug 27 10:46:05 AM UTC 24 |
| Peak memory | 211588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282187553 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_partial_a ccess_b2b.2282187553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/24.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.3432150205 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 1343052221 ps |
| CPU time | 7.19 seconds |
| Started | Aug 27 10:33:31 AM UTC 24 |
| Finished | Aug 27 10:33:39 AM UTC 24 |
| Peak memory | 211716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432150205 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.3432150205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/24.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_regwen.3530566167 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 2179022784 ps |
| CPU time | 394.81 seconds |
| Started | Aug 27 10:33:30 AM UTC 24 |
| Finished | Aug 27 10:40:10 AM UTC 24 |
| Peak memory | 386596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530566167 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.3530566167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/24.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_smoke.4268120315 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 783408576 ps |
| CPU time | 106.05 seconds |
| Started | Aug 27 10:31:14 AM UTC 24 |
| Finished | Aug 27 10:33:03 AM UTC 24 |
| Peak memory | 378260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268120315 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.4268120315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/24.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all.588452835 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 178152970994 ps |
| CPU time | 1858.23 seconds |
| Started | Aug 27 10:34:37 AM UTC 24 |
| Finished | Aug 27 11:05:53 AM UTC 24 |
| Peak memory | 390460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58845283 5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all.588452835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/24.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.2339599802 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 3159875081 ps |
| CPU time | 37.25 seconds |
| Started | Aug 27 10:34:33 AM UTC 24 |
| Finished | Aug 27 10:35:12 AM UTC 24 |
| Peak memory | 222012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339599802 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.2339599802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/24.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.1947921508 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 13868090972 ps |
| CPU time | 292.35 seconds |
| Started | Aug 27 10:31:34 AM UTC 24 |
| Finished | Aug 27 10:36:31 AM UTC 24 |
| Peak memory | 211624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947921508 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_pipeline.1947921508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/24.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.2307621066 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 1493318254 ps |
| CPU time | 39.63 seconds |
| Started | Aug 27 10:32:35 AM UTC 24 |
| Finished | Aug 27 10:33:16 AM UTC 24 |
| Peak memory | 298588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2307621066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl _throughput_w_partial_write.2307621066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/24.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.2323101888 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 11820080188 ps |
| CPU time | 246.96 seconds |
| Started | Aug 27 10:37:39 AM UTC 24 |
| Finished | Aug 27 10:41:49 AM UTC 24 |
| Peak memory | 386792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323101888 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_access_duri ng_key_req.2323101888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/25.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_alert_test.2380531424 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 34873960 ps |
| CPU time | 1 seconds |
| Started | Aug 27 10:39:16 AM UTC 24 |
| Finished | Aug 27 10:39:18 AM UTC 24 |
| Peak memory | 210816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380531424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_alert_test.2380531424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/25.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_bijection.3180729537 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 53784460005 ps |
| CPU time | 923.53 seconds |
| Started | Aug 27 10:36:14 AM UTC 24 |
| Finished | Aug 27 10:51:48 AM UTC 24 |
| Peak memory | 211572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180729537 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection.3180729537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/25.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_executable.2015858940 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 294286274229 ps |
| CPU time | 1879.93 seconds |
| Started | Aug 27 10:37:40 AM UTC 24 |
| Finished | Aug 27 11:09:20 AM UTC 24 |
| Peak memory | 390248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015858940 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executable.2015858940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/25.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.1664336121 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 13646627035 ps |
| CPU time | 102.69 seconds |
| Started | Aug 27 10:37:30 AM UTC 24 |
| Finished | Aug 27 10:39:15 AM UTC 24 |
| Peak memory | 221816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664336121 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_escalation.1664336121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/25.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.3459087248 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 724469011 ps |
| CPU time | 20.35 seconds |
| Started | Aug 27 10:37:18 AM UTC 24 |
| Finished | Aug 27 10:37:39 AM UTC 24 |
| Peak memory | 261736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3459087248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ max_throughput.3459087248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/25.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.3382343372 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 9776586554 ps |
| CPU time | 201.31 seconds |
| Started | Aug 27 10:38:27 AM UTC 24 |
| Finished | Aug 27 10:41:51 AM UTC 24 |
| Peak memory | 228940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382343372 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_mem_partial_access.3382343372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/25.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.508960458 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 5712132030 ps |
| CPU time | 303.05 seconds |
| Started | Aug 27 10:38:20 AM UTC 24 |
| Finished | Aug 27 10:43:28 AM UTC 24 |
| Peak memory | 221892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508960458 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_mem_walk.508960458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/25.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.583406706 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 5663597644 ps |
| CPU time | 310.7 seconds |
| Started | Aug 27 10:35:26 AM UTC 24 |
| Finished | Aug 27 10:40:41 AM UTC 24 |
| Peak memory | 329244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583406706 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multiple_keys.583406706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/25.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access.3357520519 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 2151844807 ps |
| CPU time | 48.32 seconds |
| Started | Aug 27 10:36:39 AM UTC 24 |
| Finished | Aug 27 10:37:29 AM UTC 24 |
| Peak memory | 333472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357520519 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_partial_access.3357520519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/25.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.3384101967 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 70756625055 ps |
| CPU time | 525.82 seconds |
| Started | Aug 27 10:37:14 AM UTC 24 |
| Finished | Aug 27 10:46:06 AM UTC 24 |
| Peak memory | 211504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384101967 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_partial_a ccess_b2b.3384101967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/25.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.1774751128 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 705155941 ps |
| CPU time | 6.52 seconds |
| Started | Aug 27 10:38:18 AM UTC 24 |
| Finished | Aug 27 10:38:26 AM UTC 24 |
| Peak memory | 211644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774751128 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.1774751128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/25.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_regwen.3935880002 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 19130178518 ps |
| CPU time | 756.2 seconds |
| Started | Aug 27 10:38:09 AM UTC 24 |
| Finished | Aug 27 10:50:54 AM UTC 24 |
| Peak memory | 386660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935880002 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.3935880002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/25.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_smoke.195980347 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 5441007640 ps |
| CPU time | 55.55 seconds |
| Started | Aug 27 10:35:16 AM UTC 24 |
| Finished | Aug 27 10:36:13 AM UTC 24 |
| Peak memory | 310748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195980347 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.195980347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/25.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all.4127791406 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 58640040607 ps |
| CPU time | 2509.3 seconds |
| Started | Aug 27 10:39:07 AM UTC 24 |
| Finished | Aug 27 11:21:24 AM UTC 24 |
| Peak memory | 392376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41277914 06 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_a ll.4127791406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/25.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.509842511 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 5289122971 ps |
| CPU time | 94.23 seconds |
| Started | Aug 27 10:38:29 AM UTC 24 |
| Finished | Aug 27 10:40:05 AM UTC 24 |
| Peak memory | 228996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509842511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.509842511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/25.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.2398970578 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 3079458031 ps |
| CPU time | 215.04 seconds |
| Started | Aug 27 10:36:32 AM UTC 24 |
| Finished | Aug 27 10:40:11 AM UTC 24 |
| Peak memory | 211776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398970578 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_pipeline.2398970578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/25.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.3282418868 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 1466647351 ps |
| CPU time | 12.05 seconds |
| Started | Aug 27 10:37:25 AM UTC 24 |
| Finished | Aug 27 10:37:38 AM UTC 24 |
| Peak memory | 221820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3282418868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl _throughput_w_partial_write.3282418868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/25.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.2801264107 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 16773298397 ps |
| CPU time | 687.24 seconds |
| Started | Aug 27 10:41:14 AM UTC 24 |
| Finished | Aug 27 10:52:49 AM UTC 24 |
| Peak memory | 386528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801264107 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_access_duri ng_key_req.2801264107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/26.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_alert_test.415472102 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 30262046 ps |
| CPU time | 0.97 seconds |
| Started | Aug 27 10:43:00 AM UTC 24 |
| Finished | Aug 27 10:43:02 AM UTC 24 |
| Peak memory | 210812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415472102 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_alert_test.415472102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/26.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_bijection.2055071683 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 690532254875 ps |
| CPU time | 3264.84 seconds |
| Started | Aug 27 10:40:06 AM UTC 24 |
| Finished | Aug 27 11:35:09 AM UTC 24 |
| Peak memory | 213160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055071683 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection.2055071683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/26.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_executable.2619593461 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 8056047143 ps |
| CPU time | 318.41 seconds |
| Started | Aug 27 10:41:17 AM UTC 24 |
| Finished | Aug 27 10:46:40 AM UTC 24 |
| Peak memory | 357852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619593461 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executable.2619593461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/26.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.3039804818 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 35470958233 ps |
| CPU time | 56.31 seconds |
| Started | Aug 27 10:41:12 AM UTC 24 |
| Finished | Aug 27 10:42:10 AM UTC 24 |
| Peak memory | 221988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039804818 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_escalation.3039804818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/26.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.1656312038 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 2861548457 ps |
| CPU time | 21.08 seconds |
| Started | Aug 27 10:40:51 AM UTC 24 |
| Finished | Aug 27 10:41:13 AM UTC 24 |
| Peak memory | 294368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1656312038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ max_throughput.1656312038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/26.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.704716741 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 6044883207 ps |
| CPU time | 208.01 seconds |
| Started | Aug 27 10:42:00 AM UTC 24 |
| Finished | Aug 27 10:45:31 AM UTC 24 |
| Peak memory | 221924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704716741 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_mem_partial_access.704716741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/26.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.3144566690 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 76810083071 ps |
| CPU time | 427.29 seconds |
| Started | Aug 27 10:41:52 AM UTC 24 |
| Finished | Aug 27 10:49:05 AM UTC 24 |
| Peak memory | 222080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144566690 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_mem_walk.3144566690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/26.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.3060080360 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 137454646720 ps |
| CPU time | 680.45 seconds |
| Started | Aug 27 10:39:27 AM UTC 24 |
| Finished | Aug 27 10:50:56 AM UTC 24 |
| Peak memory | 388624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060080360 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multiple_keys.3060080360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/26.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access.45569652 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 19201488901 ps |
| CPU time | 41.02 seconds |
| Started | Aug 27 10:40:11 AM UTC 24 |
| Finished | Aug 27 10:40:54 AM UTC 24 |
| Peak memory | 211496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45569652 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_partial_access.45569652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/26.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.576304949 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 16291614756 ps |
| CPU time | 616.79 seconds |
| Started | Aug 27 10:40:42 AM UTC 24 |
| Finished | Aug 27 10:51:07 AM UTC 24 |
| Peak memory | 211548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576304949 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_partial_ac cess_b2b.576304949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/26.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.2427930550 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 1359595635 ps |
| CPU time | 6.87 seconds |
| Started | Aug 27 10:41:51 AM UTC 24 |
| Finished | Aug 27 10:41:58 AM UTC 24 |
| Peak memory | 211716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427930550 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.2427930550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/26.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_regwen.2828763307 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 2445390142 ps |
| CPU time | 552.68 seconds |
| Started | Aug 27 10:41:36 AM UTC 24 |
| Finished | Aug 27 10:50:55 AM UTC 24 |
| Peak memory | 382404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828763307 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.2828763307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/26.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_smoke.760822622 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 5300448483 ps |
| CPU time | 88.84 seconds |
| Started | Aug 27 10:39:19 AM UTC 24 |
| Finished | Aug 27 10:40:50 AM UTC 24 |
| Peak memory | 376340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760822622 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.760822622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/26.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all.3264862808 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 184140321352 ps |
| CPU time | 3726.3 seconds |
| Started | Aug 27 10:42:43 AM UTC 24 |
| Finished | Aug 27 11:45:30 AM UTC 24 |
| Peak memory | 225532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32648628 08 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_a ll.3264862808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/26.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.383845592 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 5045292741 ps |
| CPU time | 46.95 seconds |
| Started | Aug 27 10:42:11 AM UTC 24 |
| Finished | Aug 27 10:42:59 AM UTC 24 |
| Peak memory | 221932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383845592 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.383845592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/26.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.646175379 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 21834614350 ps |
| CPU time | 462.9 seconds |
| Started | Aug 27 10:40:10 AM UTC 24 |
| Finished | Aug 27 10:47:59 AM UTC 24 |
| Peak memory | 211552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646175379 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_pipeline.646175379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/26.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.3180409943 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 3100080201 ps |
| CPU time | 39.17 seconds |
| Started | Aug 27 10:40:55 AM UTC 24 |
| Finished | Aug 27 10:41:35 AM UTC 24 |
| Peak memory | 321176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3180409943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl _throughput_w_partial_write.3180409943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/26.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.1195573897 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 80877745915 ps |
| CPU time | 1120.47 seconds |
| Started | Aug 27 10:46:06 AM UTC 24 |
| Finished | Aug 27 11:04:59 AM UTC 24 |
| Peak memory | 390328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195573897 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_access_duri ng_key_req.1195573897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/27.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_alert_test.2867034080 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 42605728 ps |
| CPU time | 1.01 seconds |
| Started | Aug 27 10:47:45 AM UTC 24 |
| Finished | Aug 27 10:47:47 AM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867034080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_alert_test.2867034080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/27.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_bijection.409232822 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 66952413402 ps |
| CPU time | 1273.32 seconds |
| Started | Aug 27 10:43:27 AM UTC 24 |
| Finished | Aug 27 11:04:56 AM UTC 24 |
| Peak memory | 213420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409232822 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection.409232822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/27.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_executable.1349382744 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 2339731593 ps |
| CPU time | 99.07 seconds |
| Started | Aug 27 10:46:12 AM UTC 24 |
| Finished | Aug 27 10:47:53 AM UTC 24 |
| Peak memory | 339628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349382744 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executable.1349382744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/27.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.3829761147 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 13717687025 ps |
| CPU time | 96.79 seconds |
| Started | Aug 27 10:46:05 AM UTC 24 |
| Finished | Aug 27 10:47:44 AM UTC 24 |
| Peak memory | 211576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829761147 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_escalation.3829761147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/27.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.4128100186 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 1485407121 ps |
| CPU time | 47.91 seconds |
| Started | Aug 27 10:45:32 AM UTC 24 |
| Finished | Aug 27 10:46:22 AM UTC 24 |
| Peak memory | 329116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4128100186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ max_throughput.4128100186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/27.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.1562417897 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 1575926864 ps |
| CPU time | 86.73 seconds |
| Started | Aug 27 10:46:41 AM UTC 24 |
| Finished | Aug 27 10:48:10 AM UTC 24 |
| Peak memory | 221864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562417897 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_mem_partial_access.1562417897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/27.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.2282554366 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 6902953361 ps |
| CPU time | 211.59 seconds |
| Started | Aug 27 10:46:32 AM UTC 24 |
| Finished | Aug 27 10:50:07 AM UTC 24 |
| Peak memory | 221944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282554366 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_mem_walk.2282554366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/27.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.3751913963 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 25047852394 ps |
| CPU time | 750.01 seconds |
| Started | Aug 27 10:43:25 AM UTC 24 |
| Finished | Aug 27 10:56:04 AM UTC 24 |
| Peak memory | 382512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751913963 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multiple_keys.3751913963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/27.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access.921527309 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 3660223955 ps |
| CPU time | 24.45 seconds |
| Started | Aug 27 10:44:02 AM UTC 24 |
| Finished | Aug 27 10:44:27 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921527309 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_partial_access.921527309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/27.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.2924940346 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 69248224796 ps |
| CPU time | 588.08 seconds |
| Started | Aug 27 10:44:28 AM UTC 24 |
| Finished | Aug 27 10:54:24 AM UTC 24 |
| Peak memory | 211632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924940346 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_partial_a ccess_b2b.2924940346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/27.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.3395259820 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 1469150029 ps |
| CPU time | 7.2 seconds |
| Started | Aug 27 10:46:23 AM UTC 24 |
| Finished | Aug 27 10:46:31 AM UTC 24 |
| Peak memory | 211716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395259820 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.3395259820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/27.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_regwen.4047689827 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 7124225840 ps |
| CPU time | 514.29 seconds |
| Started | Aug 27 10:46:17 AM UTC 24 |
| Finished | Aug 27 10:54:58 AM UTC 24 |
| Peak memory | 382620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047689827 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.4047689827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/27.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_smoke.2048092398 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 2787968155 ps |
| CPU time | 20.03 seconds |
| Started | Aug 27 10:43:03 AM UTC 24 |
| Finished | Aug 27 10:43:24 AM UTC 24 |
| Peak memory | 255520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048092398 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.2048092398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/27.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all.714765928 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 168632510328 ps |
| CPU time | 3112.67 seconds |
| Started | Aug 27 10:47:07 AM UTC 24 |
| Finished | Aug 27 11:39:33 AM UTC 24 |
| Peak memory | 392348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71476592 8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all.714765928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/27.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.1173579504 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 2124684928 ps |
| CPU time | 75.99 seconds |
| Started | Aug 27 10:46:54 AM UTC 24 |
| Finished | Aug 27 10:48:12 AM UTC 24 |
| Peak memory | 228868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173579504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.1173579504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/27.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.3430488775 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 5461265199 ps |
| CPU time | 416.08 seconds |
| Started | Aug 27 10:43:29 AM UTC 24 |
| Finished | Aug 27 10:50:30 AM UTC 24 |
| Peak memory | 211756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430488775 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_pipeline.3430488775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/27.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.1186825696 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 2807930180 ps |
| CPU time | 62.36 seconds |
| Started | Aug 27 10:45:48 AM UTC 24 |
| Finished | Aug 27 10:46:53 AM UTC 24 |
| Peak memory | 341460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1186825696 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl _throughput_w_partial_write.1186825696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/27.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.1756780664 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 31349557104 ps |
| CPU time | 339.72 seconds |
| Started | Aug 27 10:49:30 AM UTC 24 |
| Finished | Aug 27 10:55:15 AM UTC 24 |
| Peak memory | 370096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756780664 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_access_duri ng_key_req.1756780664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/28.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_alert_test.2712671639 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 89826313 ps |
| CPU time | 1.09 seconds |
| Started | Aug 27 10:50:57 AM UTC 24 |
| Finished | Aug 27 10:50:59 AM UTC 24 |
| Peak memory | 210876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712671639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_alert_test.2712671639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/28.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_bijection.2589482748 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 36140227450 ps |
| CPU time | 791.68 seconds |
| Started | Aug 27 10:47:57 AM UTC 24 |
| Finished | Aug 27 11:01:18 AM UTC 24 |
| Peak memory | 211572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589482748 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection.2589482748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/28.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_executable.2685948146 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 32721141951 ps |
| CPU time | 198.71 seconds |
| Started | Aug 27 10:50:03 AM UTC 24 |
| Finished | Aug 27 10:53:25 AM UTC 24 |
| Peak memory | 364308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685948146 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executable.2685948146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/28.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.3834471237 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 11755962482 ps |
| CPU time | 76.16 seconds |
| Started | Aug 27 10:49:10 AM UTC 24 |
| Finished | Aug 27 10:50:28 AM UTC 24 |
| Peak memory | 221792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834471237 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_escalation.3834471237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/28.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.1689946669 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 731570549 ps |
| CPU time | 27.21 seconds |
| Started | Aug 27 10:48:41 AM UTC 24 |
| Finished | Aug 27 10:49:09 AM UTC 24 |
| Peak memory | 265768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1689946669 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ max_throughput.1689946669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/28.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.1553387797 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 10174558261 ps |
| CPU time | 197.63 seconds |
| Started | Aug 27 10:50:35 AM UTC 24 |
| Finished | Aug 27 10:53:57 AM UTC 24 |
| Peak memory | 222000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553387797 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_mem_partial_access.1553387797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/28.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.13458817 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 55269851136 ps |
| CPU time | 384.87 seconds |
| Started | Aug 27 10:50:31 AM UTC 24 |
| Finished | Aug 27 10:57:01 AM UTC 24 |
| Peak memory | 221864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13458817 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_mem_walk.13458817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/28.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.677456233 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 54166060947 ps |
| CPU time | 880.8 seconds |
| Started | Aug 27 10:47:54 AM UTC 24 |
| Finished | Aug 27 11:02:45 AM UTC 24 |
| Peak memory | 378332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677456233 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multiple_keys.677456233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/28.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access.1313669545 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 3360257570 ps |
| CPU time | 28.39 seconds |
| Started | Aug 27 10:48:10 AM UTC 24 |
| Finished | Aug 27 10:48:40 AM UTC 24 |
| Peak memory | 296360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313669545 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_partial_access.1313669545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/28.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.3060515060 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 19036429782 ps |
| CPU time | 497.56 seconds |
| Started | Aug 27 10:48:12 AM UTC 24 |
| Finished | Aug 27 10:56:36 AM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060515060 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_partial_a ccess_b2b.3060515060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/28.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.3413000928 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 1350730966 ps |
| CPU time | 4.48 seconds |
| Started | Aug 27 10:50:29 AM UTC 24 |
| Finished | Aug 27 10:50:35 AM UTC 24 |
| Peak memory | 211720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413000928 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.3413000928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/28.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_regwen.3820560140 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 19785082436 ps |
| CPU time | 1140.55 seconds |
| Started | Aug 27 10:50:08 AM UTC 24 |
| Finished | Aug 27 11:09:22 AM UTC 24 |
| Peak memory | 390116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820560140 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.3820560140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/28.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_smoke.1039217970 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 768846049 ps |
| CPU time | 7.1 seconds |
| Started | Aug 27 10:47:48 AM UTC 24 |
| Finished | Aug 27 10:47:56 AM UTC 24 |
| Peak memory | 211480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039217970 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.1039217970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/28.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all.1682616305 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 509021660633 ps |
| CPU time | 5098.7 seconds |
| Started | Aug 27 10:50:56 AM UTC 24 |
| Finished | Aug 27 12:16:48 PM UTC 24 |
| Peak memory | 222396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16826163 05 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_a ll.1682616305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/28.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.1830266693 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 3373866156 ps |
| CPU time | 63.05 seconds |
| Started | Aug 27 10:50:55 AM UTC 24 |
| Finished | Aug 27 10:52:00 AM UTC 24 |
| Peak memory | 259684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830266693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.1830266693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/28.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.605729102 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 3971642323 ps |
| CPU time | 267.74 seconds |
| Started | Aug 27 10:48:00 AM UTC 24 |
| Finished | Aug 27 10:52:32 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605729102 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_pipeline.605729102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/28.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.1140967406 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 2916621501 ps |
| CPU time | 21.65 seconds |
| Started | Aug 27 10:49:06 AM UTC 24 |
| Finished | Aug 27 10:49:29 AM UTC 24 |
| Peak memory | 261584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1140967406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl _throughput_w_partial_write.1140967406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/28.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.13701097 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 8509460478 ps |
| CPU time | 414.02 seconds |
| Started | Aug 27 10:53:25 AM UTC 24 |
| Finished | Aug 27 11:00:24 AM UTC 24 |
| Peak memory | 359988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13701097 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_access_during _key_req.13701097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/29.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_alert_test.1707645606 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 21626806 ps |
| CPU time | 1.02 seconds |
| Started | Aug 27 10:54:46 AM UTC 24 |
| Finished | Aug 27 10:54:48 AM UTC 24 |
| Peak memory | 210816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707645606 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_alert_test.1707645606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/29.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_bijection.2992277515 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 64891406811 ps |
| CPU time | 2574.08 seconds |
| Started | Aug 27 10:51:14 AM UTC 24 |
| Finished | Aug 27 11:34:36 AM UTC 24 |
| Peak memory | 213228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992277515 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection.2992277515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/29.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_executable.829755034 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 75271213091 ps |
| CPU time | 1498.57 seconds |
| Started | Aug 27 10:53:56 AM UTC 24 |
| Finished | Aug 27 11:19:11 AM UTC 24 |
| Peak memory | 390332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829755034 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executable.829755034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/29.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.2220471877 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 15442242952 ps |
| CPU time | 95.97 seconds |
| Started | Aug 27 10:53:07 AM UTC 24 |
| Finished | Aug 27 10:54:45 AM UTC 24 |
| Peak memory | 211660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220471877 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_escalation.2220471877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/29.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.1017000205 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 3294974810 ps |
| CPU time | 97.7 seconds |
| Started | Aug 27 10:52:34 AM UTC 24 |
| Finished | Aug 27 10:54:14 AM UTC 24 |
| Peak memory | 368164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1017000205 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ max_throughput.1017000205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/29.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.1702839771 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 4746901752 ps |
| CPU time | 182.85 seconds |
| Started | Aug 27 10:54:17 AM UTC 24 |
| Finished | Aug 27 10:57:23 AM UTC 24 |
| Peak memory | 229064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702839771 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_mem_partial_access.1702839771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/29.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.2816241417 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 13815500764 ps |
| CPU time | 370.42 seconds |
| Started | Aug 27 10:54:15 AM UTC 24 |
| Finished | Aug 27 11:00:30 AM UTC 24 |
| Peak memory | 221880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816241417 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_mem_walk.2816241417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/29.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.96986715 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 65344772328 ps |
| CPU time | 622.21 seconds |
| Started | Aug 27 10:51:08 AM UTC 24 |
| Finished | Aug 27 11:01:37 AM UTC 24 |
| Peak memory | 388500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96986715 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multiple_keys.96986715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/29.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access.3817699534 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 6321471258 ps |
| CPU time | 30.6 seconds |
| Started | Aug 27 10:52:00 AM UTC 24 |
| Finished | Aug 27 10:52:32 AM UTC 24 |
| Peak memory | 211620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817699534 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_partial_access.3817699534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/29.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.958616375 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 22163414974 ps |
| CPU time | 304.61 seconds |
| Started | Aug 27 10:52:33 AM UTC 24 |
| Finished | Aug 27 10:57:41 AM UTC 24 |
| Peak memory | 211568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958616375 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_partial_ac cess_b2b.958616375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/29.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.573876146 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 1367288690 ps |
| CPU time | 5.96 seconds |
| Started | Aug 27 10:54:09 AM UTC 24 |
| Finished | Aug 27 10:54:16 AM UTC 24 |
| Peak memory | 211892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573876146 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.573876146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/29.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_regwen.2982906726 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 7018814949 ps |
| CPU time | 45.67 seconds |
| Started | Aug 27 10:53:58 AM UTC 24 |
| Finished | Aug 27 10:54:45 AM UTC 24 |
| Peak memory | 211512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982906726 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.2982906726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/29.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_smoke.2099653348 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 1902393262 ps |
| CPU time | 12.02 seconds |
| Started | Aug 27 10:51:00 AM UTC 24 |
| Finished | Aug 27 10:51:13 AM UTC 24 |
| Peak memory | 243096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099653348 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.2099653348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/29.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all.569775502 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 48711066989 ps |
| CPU time | 3029.64 seconds |
| Started | Aug 27 10:54:46 AM UTC 24 |
| Finished | Aug 27 11:45:48 AM UTC 24 |
| Peak memory | 392508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56977550 2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all.569775502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/29.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.588136791 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 5145739944 ps |
| CPU time | 60.65 seconds |
| Started | Aug 27 10:54:24 AM UTC 24 |
| Finished | Aug 27 10:55:26 AM UTC 24 |
| Peak memory | 224104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588136791 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.588136791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/29.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.3172779086 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 3394363516 ps |
| CPU time | 350.99 seconds |
| Started | Aug 27 10:51:48 AM UTC 24 |
| Finished | Aug 27 10:57:44 AM UTC 24 |
| Peak memory | 211584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172779086 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_pipeline.3172779086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/29.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.976208833 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 5551399916 ps |
| CPU time | 14.92 seconds |
| Started | Aug 27 10:52:50 AM UTC 24 |
| Finished | Aug 27 10:53:06 AM UTC 24 |
| Peak memory | 221740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =976208833 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ throughput_w_partial_write.976208833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/29.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.1151091899 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 23538150092 ps |
| CPU time | 606.85 seconds |
| Started | Aug 27 09:24:50 AM UTC 24 |
| Finished | Aug 27 09:35:04 AM UTC 24 |
| Peak memory | 380516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151091899 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_access_durin g_key_req.1151091899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/3.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_alert_test.1367854097 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 13730052 ps |
| CPU time | 0.96 seconds |
| Started | Aug 27 09:26:25 AM UTC 24 |
| Finished | Aug 27 09:26:27 AM UTC 24 |
| Peak memory | 210812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367854097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_alert_test.1367854097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/3.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_bijection.2034959747 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 304543852679 ps |
| CPU time | 1242.1 seconds |
| Started | Aug 27 09:23:34 AM UTC 24 |
| Finished | Aug 27 09:44:30 AM UTC 24 |
| Peak memory | 211500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034959747 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.2034959747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/3.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.1858793828 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 64421591634 ps |
| CPU time | 134.35 seconds |
| Started | Aug 27 09:24:43 AM UTC 24 |
| Finished | Aug 27 09:26:59 AM UTC 24 |
| Peak memory | 211692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858793828 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_escalation.1858793828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/3.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.3678469177 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 2725265155 ps |
| CPU time | 91.6 seconds |
| Started | Aug 27 09:23:57 AM UTC 24 |
| Finished | Aug 27 09:25:30 AM UTC 24 |
| Peak memory | 382500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3678469177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_m ax_throughput.3678469177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/3.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.333558390 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 4041740227 ps |
| CPU time | 103.85 seconds |
| Started | Aug 27 09:25:39 AM UTC 24 |
| Finished | Aug 27 09:27:25 AM UTC 24 |
| Peak memory | 221868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333558390 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_mem_partial_access.333558390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/3.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.2538145348 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 55302235993 ps |
| CPU time | 509.46 seconds |
| Started | Aug 27 09:25:31 AM UTC 24 |
| Finished | Aug 27 09:34:08 AM UTC 24 |
| Peak memory | 221940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538145348 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_mem_walk.2538145348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/3.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.1976953782 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 11527524082 ps |
| CPU time | 656.49 seconds |
| Started | Aug 27 09:23:29 AM UTC 24 |
| Finished | Aug 27 09:34:33 AM UTC 24 |
| Peak memory | 386700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976953782 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multiple_keys.1976953782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/3.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access.1119199975 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 1294690641 ps |
| CPU time | 116.18 seconds |
| Started | Aug 27 09:23:45 AM UTC 24 |
| Finished | Aug 27 09:25:44 AM UTC 24 |
| Peak memory | 370068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119199975 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_partial_access.1119199975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/3.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.4010085115 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 64163402761 ps |
| CPU time | 481.51 seconds |
| Started | Aug 27 09:23:46 AM UTC 24 |
| Finished | Aug 27 09:31:54 AM UTC 24 |
| Peak memory | 211692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010085115 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_partial_ac cess_b2b.4010085115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/3.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.924144350 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 1123499847 ps |
| CPU time | 6.95 seconds |
| Started | Aug 27 09:25:29 AM UTC 24 |
| Finished | Aug 27 09:25:38 AM UTC 24 |
| Peak memory | 211828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924144350 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.924144350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/3.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.2308582477 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 845338684 ps |
| CPU time | 4.55 seconds |
| Started | Aug 27 09:26:19 AM UTC 24 |
| Finished | Aug 27 09:26:24 AM UTC 24 |
| Peak memory | 247828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308582477 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_sec_cm.2308582477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/3.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_smoke.2934133854 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 4499151231 ps |
| CPU time | 17.16 seconds |
| Started | Aug 27 09:23:26 AM UTC 24 |
| Finished | Aug 27 09:23:44 AM UTC 24 |
| Peak memory | 211744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934133854 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.2934133854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/3.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all.1654112458 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 161447238767 ps |
| CPU time | 3756.65 seconds |
| Started | Aug 27 09:26:09 AM UTC 24 |
| Finished | Aug 27 10:29:27 AM UTC 24 |
| Peak memory | 390256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16541124 58 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all.1654112458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/3.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.3539542312 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 470909457 ps |
| CPU time | 22.65 seconds |
| Started | Aug 27 09:25:44 AM UTC 24 |
| Finished | Aug 27 09:26:08 AM UTC 24 |
| Peak memory | 221864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539542312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.3539542312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/3.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.3040207955 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 9422100879 ps |
| CPU time | 270.25 seconds |
| Started | Aug 27 09:23:38 AM UTC 24 |
| Finished | Aug 27 09:28:12 AM UTC 24 |
| Peak memory | 211552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040207955 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_pipeline.3040207955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/3.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.2398656609 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 1530902453 ps |
| CPU time | 59.11 seconds |
| Started | Aug 27 09:24:09 AM UTC 24 |
| Finished | Aug 27 09:25:10 AM UTC 24 |
| Peak memory | 329124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2398656609 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ throughput_w_partial_write.2398656609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/3.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.3550560347 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 17802287333 ps |
| CPU time | 629.55 seconds |
| Started | Aug 27 10:56:24 AM UTC 24 |
| Finished | Aug 27 11:07:01 AM UTC 24 |
| Peak memory | 388636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550560347 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_access_duri ng_key_req.3550560347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/30.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_alert_test.2254245102 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 11777194 ps |
| CPU time | 1.02 seconds |
| Started | Aug 27 10:58:17 AM UTC 24 |
| Finished | Aug 27 10:58:20 AM UTC 24 |
| Peak memory | 210736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254245102 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_alert_test.2254245102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/30.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_executable.4246879301 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 110296733551 ps |
| CPU time | 1303.28 seconds |
| Started | Aug 27 10:56:36 AM UTC 24 |
| Finished | Aug 27 11:18:33 AM UTC 24 |
| Peak memory | 389916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246879301 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executable.4246879301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/30.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.2751219543 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 21646798047 ps |
| CPU time | 128.14 seconds |
| Started | Aug 27 10:56:14 AM UTC 24 |
| Finished | Aug 27 10:58:25 AM UTC 24 |
| Peak memory | 221804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751219543 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_escalation.2751219543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/30.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.1346207859 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 3038264492 ps |
| CPU time | 39.7 seconds |
| Started | Aug 27 10:55:54 AM UTC 24 |
| Finished | Aug 27 10:56:35 AM UTC 24 |
| Peak memory | 312796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1346207859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ max_throughput.1346207859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/30.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.1312955166 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 2444328277 ps |
| CPU time | 170.93 seconds |
| Started | Aug 27 10:57:24 AM UTC 24 |
| Finished | Aug 27 11:00:18 AM UTC 24 |
| Peak memory | 221948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312955166 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_mem_partial_access.1312955166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/30.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.3461525469 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 14460378028 ps |
| CPU time | 244.28 seconds |
| Started | Aug 27 10:57:11 AM UTC 24 |
| Finished | Aug 27 11:01:19 AM UTC 24 |
| Peak memory | 221944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461525469 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_mem_walk.3461525469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/30.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.88373779 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 10321779686 ps |
| CPU time | 73.25 seconds |
| Started | Aug 27 10:54:58 AM UTC 24 |
| Finished | Aug 27 10:56:13 AM UTC 24 |
| Peak memory | 353756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88373779 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multiple_keys.88373779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/30.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access.996498199 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 1569205088 ps |
| CPU time | 36.22 seconds |
| Started | Aug 27 10:55:16 AM UTC 24 |
| Finished | Aug 27 10:55:53 AM UTC 24 |
| Peak memory | 211484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996498199 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_partial_access.996498199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/30.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.626379362 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 16135044756 ps |
| CPU time | 422.92 seconds |
| Started | Aug 27 10:55:27 AM UTC 24 |
| Finished | Aug 27 11:02:36 AM UTC 24 |
| Peak memory | 211548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626379362 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_partial_ac cess_b2b.626379362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/30.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.982951595 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 1408176359 ps |
| CPU time | 6.42 seconds |
| Started | Aug 27 10:57:03 AM UTC 24 |
| Finished | Aug 27 10:57:10 AM UTC 24 |
| Peak memory | 211892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982951595 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.982951595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/30.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_regwen.1498664392 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 24003895743 ps |
| CPU time | 289.49 seconds |
| Started | Aug 27 10:56:38 AM UTC 24 |
| Finished | Aug 27 11:01:31 AM UTC 24 |
| Peak memory | 343516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498664392 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.1498664392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/30.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_smoke.1850846938 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 1250242112 ps |
| CPU time | 24.43 seconds |
| Started | Aug 27 10:54:49 AM UTC 24 |
| Finished | Aug 27 10:55:15 AM UTC 24 |
| Peak memory | 211672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850846938 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.1850846938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/30.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_all.2267501254 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 78405838109 ps |
| CPU time | 3771.01 seconds |
| Started | Aug 27 10:57:45 AM UTC 24 |
| Finished | Aug 27 12:01:15 PM UTC 24 |
| Peak memory | 400500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22675012 54 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_a ll.2267501254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/30.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.3465094594 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 1790392260 ps |
| CPU time | 32.8 seconds |
| Started | Aug 27 10:57:42 AM UTC 24 |
| Finished | Aug 27 10:58:16 AM UTC 24 |
| Peak memory | 221948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465094594 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.3465094594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/30.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.1264811326 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 15660379696 ps |
| CPU time | 298.57 seconds |
| Started | Aug 27 10:55:16 AM UTC 24 |
| Finished | Aug 27 11:00:18 AM UTC 24 |
| Peak memory | 211628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264811326 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_pipeline.1264811326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/30.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.221272915 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 1807947708 ps |
| CPU time | 16.98 seconds |
| Started | Aug 27 10:56:05 AM UTC 24 |
| Finished | Aug 27 10:56:23 AM UTC 24 |
| Peak memory | 238996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =221272915 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ throughput_w_partial_write.221272915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/30.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.3273041514 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 32047346940 ps |
| CPU time | 941.33 seconds |
| Started | Aug 27 11:00:57 AM UTC 24 |
| Finished | Aug 27 11:16:49 AM UTC 24 |
| Peak memory | 386604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273041514 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_access_duri ng_key_req.3273041514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/31.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_alert_test.385871698 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 25642407 ps |
| CPU time | 1.04 seconds |
| Started | Aug 27 11:01:42 AM UTC 24 |
| Finished | Aug 27 11:01:44 AM UTC 24 |
| Peak memory | 210812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385871698 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_alert_test.385871698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/31.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_bijection.2693150374 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 517800605972 ps |
| CPU time | 2544.05 seconds |
| Started | Aug 27 11:00:07 AM UTC 24 |
| Finished | Aug 27 11:42:59 AM UTC 24 |
| Peak memory | 213248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693150374 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection.2693150374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/31.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_executable.2735970192 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 83506537636 ps |
| CPU time | 844.83 seconds |
| Started | Aug 27 11:01:16 AM UTC 24 |
| Finished | Aug 27 11:15:30 AM UTC 24 |
| Peak memory | 388904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735970192 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executable.2735970192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/31.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.2416663780 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 25008181670 ps |
| CPU time | 67.73 seconds |
| Started | Aug 27 11:00:42 AM UTC 24 |
| Finished | Aug 27 11:01:51 AM UTC 24 |
| Peak memory | 221796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416663780 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_escalation.2416663780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/31.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.1219757216 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 8403058907 ps |
| CPU time | 100.2 seconds |
| Started | Aug 27 11:00:25 AM UTC 24 |
| Finished | Aug 27 11:02:08 AM UTC 24 |
| Peak memory | 368296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1219757216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ max_throughput.1219757216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/31.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.1876352577 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 7375941590 ps |
| CPU time | 73.56 seconds |
| Started | Aug 27 11:01:27 AM UTC 24 |
| Finished | Aug 27 11:02:43 AM UTC 24 |
| Peak memory | 221808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876352577 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_mem_partial_access.1876352577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/31.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.1895141301 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 9550101208 ps |
| CPU time | 178.24 seconds |
| Started | Aug 27 11:01:26 AM UTC 24 |
| Finished | Aug 27 11:04:27 AM UTC 24 |
| Peak memory | 221892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895141301 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_mem_walk.1895141301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/31.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.3244578142 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 8361629010 ps |
| CPU time | 230.76 seconds |
| Started | Aug 27 10:58:26 AM UTC 24 |
| Finished | Aug 27 11:02:20 AM UTC 24 |
| Peak memory | 349728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244578142 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multiple_keys.3244578142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/31.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access.2347468842 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 29209192867 ps |
| CPU time | 34.79 seconds |
| Started | Aug 27 11:00:19 AM UTC 24 |
| Finished | Aug 27 11:00:55 AM UTC 24 |
| Peak memory | 211488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347468842 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_partial_access.2347468842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/31.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.574984186 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 11204937390 ps |
| CPU time | 376.67 seconds |
| Started | Aug 27 11:00:19 AM UTC 24 |
| Finished | Aug 27 11:06:41 AM UTC 24 |
| Peak memory | 211548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574984186 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_partial_ac cess_b2b.574984186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/31.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.4266532874 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 367798952 ps |
| CPU time | 5.14 seconds |
| Started | Aug 27 11:01:20 AM UTC 24 |
| Finished | Aug 27 11:01:26 AM UTC 24 |
| Peak memory | 211912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266532874 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.4266532874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/31.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_regwen.1249280426 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 12978662494 ps |
| CPU time | 888.39 seconds |
| Started | Aug 27 11:01:19 AM UTC 24 |
| Finished | Aug 27 11:16:17 AM UTC 24 |
| Peak memory | 386524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249280426 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.1249280426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/31.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_smoke.878754134 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 5425403487 ps |
| CPU time | 109.57 seconds |
| Started | Aug 27 10:58:20 AM UTC 24 |
| Finished | Aug 27 11:00:12 AM UTC 24 |
| Peak memory | 378372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878754134 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.878754134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/31.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_all.3321740576 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 123236928778 ps |
| CPU time | 3317.32 seconds |
| Started | Aug 27 11:01:38 AM UTC 24 |
| Finished | Aug 27 11:57:30 AM UTC 24 |
| Peak memory | 390252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33217405 76 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_a ll.3321740576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/31.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.2805689603 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 2213713614 ps |
| CPU time | 63.53 seconds |
| Started | Aug 27 11:01:32 AM UTC 24 |
| Finished | Aug 27 11:02:38 AM UTC 24 |
| Peak memory | 221948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805689603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.2805689603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/31.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.2398121567 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 4897467676 ps |
| CPU time | 292.02 seconds |
| Started | Aug 27 11:00:13 AM UTC 24 |
| Finished | Aug 27 11:05:09 AM UTC 24 |
| Peak memory | 211628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398121567 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_pipeline.2398121567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/31.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.2438308503 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 772503306 ps |
| CPU time | 68.69 seconds |
| Started | Aug 27 11:00:31 AM UTC 24 |
| Finished | Aug 27 11:01:41 AM UTC 24 |
| Peak memory | 341464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2438308503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl _throughput_w_partial_write.2438308503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/31.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.2458851507 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 4030167750 ps |
| CPU time | 228.25 seconds |
| Started | Aug 27 11:02:46 AM UTC 24 |
| Finished | Aug 27 11:06:37 AM UTC 24 |
| Peak memory | 384472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458851507 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_access_duri ng_key_req.2458851507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/32.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_alert_test.171961283 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 12019042 ps |
| CPU time | 0.97 seconds |
| Started | Aug 27 11:04:57 AM UTC 24 |
| Finished | Aug 27 11:04:59 AM UTC 24 |
| Peak memory | 210928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171961283 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_alert_test.171961283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/32.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_bijection.2651520982 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 98357436877 ps |
| CPU time | 1259.94 seconds |
| Started | Aug 27 11:02:09 AM UTC 24 |
| Finished | Aug 27 11:23:23 AM UTC 24 |
| Peak memory | 213112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651520982 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection.2651520982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/32.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_executable.513121474 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 16023563611 ps |
| CPU time | 401.9 seconds |
| Started | Aug 27 11:03:10 AM UTC 24 |
| Finished | Aug 27 11:09:57 AM UTC 24 |
| Peak memory | 386540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513121474 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executable.513121474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/32.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.1229995409 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 7948281044 ps |
| CPU time | 78.56 seconds |
| Started | Aug 27 11:02:45 AM UTC 24 |
| Finished | Aug 27 11:04:05 AM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229995409 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_escalation.1229995409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/32.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.921715552 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 769983909 ps |
| CPU time | 85.7 seconds |
| Started | Aug 27 11:02:38 AM UTC 24 |
| Finished | Aug 27 11:04:06 AM UTC 24 |
| Peak memory | 380388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 921715552 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_m ax_throughput.921715552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/32.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.3639248816 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 23489838040 ps |
| CPU time | 166.41 seconds |
| Started | Aug 27 11:04:05 AM UTC 24 |
| Finished | Aug 27 11:06:55 AM UTC 24 |
| Peak memory | 221864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639248816 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_mem_partial_access.3639248816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/32.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.825424053 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 9361946011 ps |
| CPU time | 182.39 seconds |
| Started | Aug 27 11:03:33 AM UTC 24 |
| Finished | Aug 27 11:06:39 AM UTC 24 |
| Peak memory | 211852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825424053 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_mem_walk.825424053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/32.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.3020510342 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 101222670257 ps |
| CPU time | 1108.03 seconds |
| Started | Aug 27 11:01:52 AM UTC 24 |
| Finished | Aug 27 11:20:32 AM UTC 24 |
| Peak memory | 386820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020510342 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multiple_keys.3020510342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/32.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access.1587567554 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 3091372582 ps |
| CPU time | 19.9 seconds |
| Started | Aug 27 11:02:22 AM UTC 24 |
| Finished | Aug 27 11:02:43 AM UTC 24 |
| Peak memory | 211704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587567554 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_partial_access.1587567554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/32.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.3566885754 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 2668212842 ps |
| CPU time | 228.68 seconds |
| Started | Aug 27 11:02:36 AM UTC 24 |
| Finished | Aug 27 11:06:28 AM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566885754 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_partial_a ccess_b2b.3566885754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/32.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.3539362439 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 1406688746 ps |
| CPU time | 6.22 seconds |
| Started | Aug 27 11:03:25 AM UTC 24 |
| Finished | Aug 27 11:03:32 AM UTC 24 |
| Peak memory | 211848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539362439 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.3539362439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/32.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_regwen.3528650626 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 15310613949 ps |
| CPU time | 1226.88 seconds |
| Started | Aug 27 11:03:18 AM UTC 24 |
| Finished | Aug 27 11:23:58 AM UTC 24 |
| Peak memory | 390236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528650626 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.3528650626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/32.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_smoke.3601718037 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 1342080131 ps |
| CPU time | 35.54 seconds |
| Started | Aug 27 11:01:45 AM UTC 24 |
| Finished | Aug 27 11:02:22 AM UTC 24 |
| Peak memory | 211628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601718037 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.3601718037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/32.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all.172434207 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 485516867562 ps |
| CPU time | 5497.98 seconds |
| Started | Aug 27 11:04:29 AM UTC 24 |
| Finished | Aug 27 12:37:03 PM UTC 24 |
| Peak memory | 390580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17243420 7 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all.172434207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/32.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.3318323946 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 2545409947 ps |
| CPU time | 198.24 seconds |
| Started | Aug 27 11:04:07 AM UTC 24 |
| Finished | Aug 27 11:07:28 AM UTC 24 |
| Peak memory | 360020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318323946 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.3318323946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/32.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.2433254668 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 5306591334 ps |
| CPU time | 403.42 seconds |
| Started | Aug 27 11:02:21 AM UTC 24 |
| Finished | Aug 27 11:09:10 AM UTC 24 |
| Peak memory | 211552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433254668 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_pipeline.2433254668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/32.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.2464267963 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 1271842444 ps |
| CPU time | 38.92 seconds |
| Started | Aug 27 11:02:44 AM UTC 24 |
| Finished | Aug 27 11:03:24 AM UTC 24 |
| Peak memory | 310696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2464267963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl _throughput_w_partial_write.2464267963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/32.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.542131524 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 38155831025 ps |
| CPU time | 876.72 seconds |
| Started | Aug 27 11:06:39 AM UTC 24 |
| Finished | Aug 27 11:21:26 AM UTC 24 |
| Peak memory | 386604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542131524 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_access_durin g_key_req.542131524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/33.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_alert_test.707374212 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 15531456 ps |
| CPU time | 1.01 seconds |
| Started | Aug 27 11:07:22 AM UTC 24 |
| Finished | Aug 27 11:07:25 AM UTC 24 |
| Peak memory | 210732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707374212 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_alert_test.707374212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/33.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_bijection.3692898099 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 21120032512 ps |
| CPU time | 1234.41 seconds |
| Started | Aug 27 11:05:10 AM UTC 24 |
| Finished | Aug 27 11:25:57 AM UTC 24 |
| Peak memory | 213224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692898099 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection.3692898099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/33.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_executable.2141528139 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 12839927019 ps |
| CPU time | 572.69 seconds |
| Started | Aug 27 11:06:41 AM UTC 24 |
| Finished | Aug 27 11:16:21 AM UTC 24 |
| Peak memory | 374236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141528139 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executable.2141528139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/33.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.851819995 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 5306680668 ps |
| CPU time | 16.44 seconds |
| Started | Aug 27 11:06:38 AM UTC 24 |
| Finished | Aug 27 11:06:56 AM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851819995 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_escalation.851819995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/33.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.3791638740 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 9073497685 ps |
| CPU time | 42.28 seconds |
| Started | Aug 27 11:06:29 AM UTC 24 |
| Finished | Aug 27 11:07:13 AM UTC 24 |
| Peak memory | 315108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3791638740 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ max_throughput.3791638740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/33.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.3910722222 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 5026013367 ps |
| CPU time | 149.85 seconds |
| Started | Aug 27 11:07:04 AM UTC 24 |
| Finished | Aug 27 11:09:36 AM UTC 24 |
| Peak memory | 229000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910722222 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_mem_partial_access.3910722222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/33.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.3061712187 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 43791952687 ps |
| CPU time | 304.94 seconds |
| Started | Aug 27 11:07:02 AM UTC 24 |
| Finished | Aug 27 11:12:12 AM UTC 24 |
| Peak memory | 222016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061712187 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_mem_walk.3061712187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/33.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.3991708480 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 7380144979 ps |
| CPU time | 547.15 seconds |
| Started | Aug 27 11:05:00 AM UTC 24 |
| Finished | Aug 27 11:14:14 AM UTC 24 |
| Peak memory | 388580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991708480 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multiple_keys.3991708480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/33.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access.160327726 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 1998604953 ps |
| CPU time | 16.63 seconds |
| Started | Aug 27 11:05:55 AM UTC 24 |
| Finished | Aug 27 11:06:13 AM UTC 24 |
| Peak memory | 211576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160327726 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_partial_access.160327726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/33.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.275028556 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 12143943419 ps |
| CPU time | 302.76 seconds |
| Started | Aug 27 11:06:14 AM UTC 24 |
| Finished | Aug 27 11:11:21 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275028556 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_partial_ac cess_b2b.275028556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/33.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.2529391386 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 368573764 ps |
| CPU time | 5.08 seconds |
| Started | Aug 27 11:06:57 AM UTC 24 |
| Finished | Aug 27 11:07:03 AM UTC 24 |
| Peak memory | 211716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529391386 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.2529391386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/33.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_regwen.1741730853 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 7711063443 ps |
| CPU time | 402.68 seconds |
| Started | Aug 27 11:06:56 AM UTC 24 |
| Finished | Aug 27 11:13:43 AM UTC 24 |
| Peak memory | 388776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741730853 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.1741730853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/33.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_smoke.1252336955 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 1049438849 ps |
| CPU time | 8.41 seconds |
| Started | Aug 27 11:05:00 AM UTC 24 |
| Finished | Aug 27 11:05:09 AM UTC 24 |
| Peak memory | 211420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252336955 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.1252336955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/33.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all.2519989465 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 161149664989 ps |
| CPU time | 5523.85 seconds |
| Started | Aug 27 11:07:14 AM UTC 24 |
| Finished | Aug 27 12:40:13 PM UTC 24 |
| Peak memory | 390116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25199894 65 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_a ll.2519989465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/33.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.2823511879 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 935337388 ps |
| CPU time | 11.03 seconds |
| Started | Aug 27 11:07:09 AM UTC 24 |
| Finished | Aug 27 11:07:22 AM UTC 24 |
| Peak memory | 223864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823511879 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.2823511879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/33.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.1984239564 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 20361506985 ps |
| CPU time | 293.43 seconds |
| Started | Aug 27 11:05:10 AM UTC 24 |
| Finished | Aug 27 11:10:08 AM UTC 24 |
| Peak memory | 211756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984239564 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_pipeline.1984239564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/33.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.2714907940 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 2892969222 ps |
| CPU time | 30.45 seconds |
| Started | Aug 27 11:06:36 AM UTC 24 |
| Finished | Aug 27 11:07:08 AM UTC 24 |
| Peak memory | 294360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2714907940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl _throughput_w_partial_write.2714907940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/33.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.3106393412 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 26861383631 ps |
| CPU time | 604.32 seconds |
| Started | Aug 27 11:09:22 AM UTC 24 |
| Finished | Aug 27 11:19:35 AM UTC 24 |
| Peak memory | 386528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106393412 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_access_duri ng_key_req.3106393412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/34.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_alert_test.3090119237 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 24768423 ps |
| CPU time | 1.06 seconds |
| Started | Aug 27 11:10:40 AM UTC 24 |
| Finished | Aug 27 11:10:42 AM UTC 24 |
| Peak memory | 210736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090119237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_alert_test.3090119237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/34.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_bijection.1626384447 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 52558717703 ps |
| CPU time | 1302.59 seconds |
| Started | Aug 27 11:07:32 AM UTC 24 |
| Finished | Aug 27 11:29:29 AM UTC 24 |
| Peak memory | 213040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626384447 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection.1626384447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/34.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.649681437 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 10747299649 ps |
| CPU time | 107.64 seconds |
| Started | Aug 27 11:09:20 AM UTC 24 |
| Finished | Aug 27 11:11:10 AM UTC 24 |
| Peak memory | 221812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649681437 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_escalation.649681437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/34.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.4160970948 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 2686942796 ps |
| CPU time | 11.34 seconds |
| Started | Aug 27 11:09:11 AM UTC 24 |
| Finished | Aug 27 11:09:24 AM UTC 24 |
| Peak memory | 227936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4160970948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ max_throughput.4160970948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/34.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.503268411 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 46979248191 ps |
| CPU time | 112.58 seconds |
| Started | Aug 27 11:09:56 AM UTC 24 |
| Finished | Aug 27 11:11:51 AM UTC 24 |
| Peak memory | 221804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503268411 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_mem_partial_access.503268411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/34.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.987511456 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 30881171378 ps |
| CPU time | 291.31 seconds |
| Started | Aug 27 11:09:44 AM UTC 24 |
| Finished | Aug 27 11:14:39 AM UTC 24 |
| Peak memory | 221884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987511456 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_mem_walk.987511456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/34.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.1659001558 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 1575709728 ps |
| CPU time | 32.32 seconds |
| Started | Aug 27 11:07:28 AM UTC 24 |
| Finished | Aug 27 11:08:02 AM UTC 24 |
| Peak memory | 211576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659001558 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multiple_keys.1659001558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/34.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access.2371723825 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 3293407950 ps |
| CPU time | 24.52 seconds |
| Started | Aug 27 11:08:31 AM UTC 24 |
| Finished | Aug 27 11:08:57 AM UTC 24 |
| Peak memory | 263632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371723825 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_partial_access.2371723825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/34.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.381356136 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 23301437644 ps |
| CPU time | 337.91 seconds |
| Started | Aug 27 11:08:57 AM UTC 24 |
| Finished | Aug 27 11:14:40 AM UTC 24 |
| Peak memory | 211748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381356136 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_partial_ac cess_b2b.381356136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/34.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.3362393282 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 682807792 ps |
| CPU time | 4.9 seconds |
| Started | Aug 27 11:09:37 AM UTC 24 |
| Finished | Aug 27 11:09:43 AM UTC 24 |
| Peak memory | 211912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362393282 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.3362393282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/34.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_regwen.3751644724 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 2523094959 ps |
| CPU time | 28.73 seconds |
| Started | Aug 27 11:09:25 AM UTC 24 |
| Finished | Aug 27 11:09:55 AM UTC 24 |
| Peak memory | 211640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751644724 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.3751644724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/34.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_smoke.1763151387 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 998151494 ps |
| CPU time | 102.27 seconds |
| Started | Aug 27 11:07:25 AM UTC 24 |
| Finished | Aug 27 11:09:10 AM UTC 24 |
| Peak memory | 376412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763151387 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.1763151387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/34.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all.788520119 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 81275870208 ps |
| CPU time | 3101.93 seconds |
| Started | Aug 27 11:10:08 AM UTC 24 |
| Finished | Aug 27 12:02:22 PM UTC 24 |
| Peak memory | 392184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78852011 9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all.788520119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/34.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.2027501334 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 2593924231 ps |
| CPU time | 145.5 seconds |
| Started | Aug 27 11:09:57 AM UTC 24 |
| Finished | Aug 27 11:12:25 AM UTC 24 |
| Peak memory | 228860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027501334 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.2027501334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/34.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.4052729832 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 2861175734 ps |
| CPU time | 165.5 seconds |
| Started | Aug 27 11:08:03 AM UTC 24 |
| Finished | Aug 27 11:10:51 AM UTC 24 |
| Peak memory | 211556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052729832 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_pipeline.4052729832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/34.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.2691654176 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 712312651 ps |
| CPU time | 10.8 seconds |
| Started | Aug 27 11:09:11 AM UTC 24 |
| Finished | Aug 27 11:09:23 AM UTC 24 |
| Peak memory | 221668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2691654176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl _throughput_w_partial_write.2691654176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/34.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.1964302348 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 10257736333 ps |
| CPU time | 516.19 seconds |
| Started | Aug 27 11:13:09 AM UTC 24 |
| Finished | Aug 27 11:21:51 AM UTC 24 |
| Peak memory | 370192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964302348 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_access_duri ng_key_req.1964302348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/35.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_alert_test.4218074138 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 18373860 ps |
| CPU time | 0.92 seconds |
| Started | Aug 27 11:14:40 AM UTC 24 |
| Finished | Aug 27 11:14:42 AM UTC 24 |
| Peak memory | 210876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218074138 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_alert_test.4218074138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/35.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_bijection.1640189786 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 230978265042 ps |
| CPU time | 1105.07 seconds |
| Started | Aug 27 11:11:11 AM UTC 24 |
| Finished | Aug 27 11:29:49 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640189786 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection.1640189786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/35.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_executable.1822662612 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 22005988676 ps |
| CPU time | 1231.43 seconds |
| Started | Aug 27 11:13:16 AM UTC 24 |
| Finished | Aug 27 11:34:02 AM UTC 24 |
| Peak memory | 390504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822662612 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executable.1822662612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/35.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.245988214 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 27751112674 ps |
| CPU time | 95.96 seconds |
| Started | Aug 27 11:12:52 AM UTC 24 |
| Finished | Aug 27 11:14:30 AM UTC 24 |
| Peak memory | 221880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245988214 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_escalation.245988214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/35.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.482413868 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 752227255 ps |
| CPU time | 36.74 seconds |
| Started | Aug 27 11:12:13 AM UTC 24 |
| Finished | Aug 27 11:12:51 AM UTC 24 |
| Peak memory | 310768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 482413868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_m ax_throughput.482413868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/35.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.398240580 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 13163310247 ps |
| CPU time | 77.66 seconds |
| Started | Aug 27 11:14:08 AM UTC 24 |
| Finished | Aug 27 11:15:28 AM UTC 24 |
| Peak memory | 222080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398240580 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_mem_partial_access.398240580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/35.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.819952770 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 10475167041 ps |
| CPU time | 214.71 seconds |
| Started | Aug 27 11:13:52 AM UTC 24 |
| Finished | Aug 27 11:17:30 AM UTC 24 |
| Peak memory | 221872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819952770 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_mem_walk.819952770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/35.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.60289573 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 82154893830 ps |
| CPU time | 496.45 seconds |
| Started | Aug 27 11:10:52 AM UTC 24 |
| Finished | Aug 27 11:19:14 AM UTC 24 |
| Peak memory | 382424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60289573 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multiple_keys.60289573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/35.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access.2881928166 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 1279410215 ps |
| CPU time | 106.89 seconds |
| Started | Aug 27 11:11:52 AM UTC 24 |
| Finished | Aug 27 11:13:42 AM UTC 24 |
| Peak memory | 363928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881928166 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_partial_access.2881928166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/35.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.528887870 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 14825458425 ps |
| CPU time | 457.47 seconds |
| Started | Aug 27 11:11:59 AM UTC 24 |
| Finished | Aug 27 11:19:42 AM UTC 24 |
| Peak memory | 211620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528887870 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_partial_ac cess_b2b.528887870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/35.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.398654936 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 1876787971 ps |
| CPU time | 6.7 seconds |
| Started | Aug 27 11:13:44 AM UTC 24 |
| Finished | Aug 27 11:13:52 AM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398654936 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.398654936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/35.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_regwen.3408756927 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 2808507210 ps |
| CPU time | 57.07 seconds |
| Started | Aug 27 11:13:42 AM UTC 24 |
| Finished | Aug 27 11:14:41 AM UTC 24 |
| Peak memory | 211752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408756927 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.3408756927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/35.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_smoke.810550175 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 1727386333 ps |
| CPU time | 74.19 seconds |
| Started | Aug 27 11:10:43 AM UTC 24 |
| Finished | Aug 27 11:11:58 AM UTC 24 |
| Peak memory | 339356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810550175 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.810550175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/35.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all.4185230610 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 266142130899 ps |
| CPU time | 5115.41 seconds |
| Started | Aug 27 11:14:31 AM UTC 24 |
| Finished | Aug 27 12:40:40 PM UTC 24 |
| Peak memory | 390324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41852306 10 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_a ll.4185230610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/35.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.3579724306 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 2040477349 ps |
| CPU time | 300.53 seconds |
| Started | Aug 27 11:14:15 AM UTC 24 |
| Finished | Aug 27 11:19:19 AM UTC 24 |
| Peak memory | 390672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579724306 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.3579724306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/35.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.3172011144 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 3704904182 ps |
| CPU time | 309.85 seconds |
| Started | Aug 27 11:11:21 AM UTC 24 |
| Finished | Aug 27 11:16:35 AM UTC 24 |
| Peak memory | 211572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172011144 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_pipeline.3172011144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/35.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.3929235624 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 764579534 ps |
| CPU time | 46.84 seconds |
| Started | Aug 27 11:12:27 AM UTC 24 |
| Finished | Aug 27 11:13:15 AM UTC 24 |
| Peak memory | 302680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3929235624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl _throughput_w_partial_write.3929235624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/35.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.1310205202 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 44500849125 ps |
| CPU time | 1869.62 seconds |
| Started | Aug 27 11:16:17 AM UTC 24 |
| Finished | Aug 27 11:47:47 AM UTC 24 |
| Peak memory | 390304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310205202 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_access_duri ng_key_req.1310205202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/36.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_alert_test.1543797441 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 40980570 ps |
| CPU time | 1.01 seconds |
| Started | Aug 27 11:17:31 AM UTC 24 |
| Finished | Aug 27 11:17:33 AM UTC 24 |
| Peak memory | 210736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543797441 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_alert_test.1543797441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/36.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_bijection.907801440 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 100962441655 ps |
| CPU time | 2113.17 seconds |
| Started | Aug 27 11:14:43 AM UTC 24 |
| Finished | Aug 27 11:50:20 AM UTC 24 |
| Peak memory | 213240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907801440 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection.907801440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/36.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_executable.3311173670 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 15609941661 ps |
| CPU time | 532.85 seconds |
| Started | Aug 27 11:16:21 AM UTC 24 |
| Finished | Aug 27 11:25:21 AM UTC 24 |
| Peak memory | 388640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311173670 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executable.3311173670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/36.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.2494481653 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 36390560740 ps |
| CPU time | 52.13 seconds |
| Started | Aug 27 11:16:16 AM UTC 24 |
| Finished | Aug 27 11:17:10 AM UTC 24 |
| Peak memory | 225828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494481653 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_escalation.2494481653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/36.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.290111341 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 3450576645 ps |
| CPU time | 96.74 seconds |
| Started | Aug 27 11:15:52 AM UTC 24 |
| Finished | Aug 27 11:17:30 AM UTC 24 |
| Peak memory | 370212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 290111341 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_m ax_throughput.290111341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/36.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.512904184 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 3932156179 ps |
| CPU time | 160.2 seconds |
| Started | Aug 27 11:17:10 AM UTC 24 |
| Finished | Aug 27 11:19:53 AM UTC 24 |
| Peak memory | 229072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512904184 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_mem_partial_access.512904184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/36.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.206493423 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 43178136889 ps |
| CPU time | 266.58 seconds |
| Started | Aug 27 11:16:57 AM UTC 24 |
| Finished | Aug 27 11:21:27 AM UTC 24 |
| Peak memory | 221888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206493423 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_mem_walk.206493423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/36.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.1614890991 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 34533181523 ps |
| CPU time | 632.01 seconds |
| Started | Aug 27 11:14:42 AM UTC 24 |
| Finished | Aug 27 11:25:22 AM UTC 24 |
| Peak memory | 374232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614890991 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multiple_keys.1614890991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/36.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access.3840934894 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 2190764042 ps |
| CPU time | 21.46 seconds |
| Started | Aug 27 11:15:29 AM UTC 24 |
| Finished | Aug 27 11:15:51 AM UTC 24 |
| Peak memory | 211576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840934894 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_partial_access.3840934894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/36.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.3974429291 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 117380648448 ps |
| CPU time | 387.06 seconds |
| Started | Aug 27 11:15:31 AM UTC 24 |
| Finished | Aug 27 11:22:03 AM UTC 24 |
| Peak memory | 211564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974429291 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_partial_a ccess_b2b.3974429291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/36.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.4237788653 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 365093584 ps |
| CPU time | 4.79 seconds |
| Started | Aug 27 11:16:50 AM UTC 24 |
| Finished | Aug 27 11:16:56 AM UTC 24 |
| Peak memory | 211644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237788653 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.4237788653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/36.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_regwen.4159520019 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 8605086126 ps |
| CPU time | 466.71 seconds |
| Started | Aug 27 11:16:36 AM UTC 24 |
| Finished | Aug 27 11:24:29 AM UTC 24 |
| Peak memory | 380376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159520019 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.4159520019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/36.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_smoke.1940544083 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 1636986192 ps |
| CPU time | 22.09 seconds |
| Started | Aug 27 11:14:41 AM UTC 24 |
| Finished | Aug 27 11:15:04 AM UTC 24 |
| Peak memory | 211500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940544083 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.1940544083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/36.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all.210868277 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 828720243957 ps |
| CPU time | 6131.04 seconds |
| Started | Aug 27 11:17:31 AM UTC 24 |
| Finished | Aug 27 01:00:47 PM UTC 24 |
| Peak memory | 388196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21086827 7 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all.210868277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/36.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.308168642 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 1009789597 ps |
| CPU time | 41.3 seconds |
| Started | Aug 27 11:17:11 AM UTC 24 |
| Finished | Aug 27 11:17:54 AM UTC 24 |
| Peak memory | 221800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308168642 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.308168642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/36.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.1910103786 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 5405308138 ps |
| CPU time | 372.5 seconds |
| Started | Aug 27 11:15:05 AM UTC 24 |
| Finished | Aug 27 11:21:23 AM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910103786 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_pipeline.1910103786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/36.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.3000476032 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 732279026 ps |
| CPU time | 14.91 seconds |
| Started | Aug 27 11:15:59 AM UTC 24 |
| Finished | Aug 27 11:16:15 AM UTC 24 |
| Peak memory | 245140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3000476032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl _throughput_w_partial_write.3000476032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/36.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.562951619 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 30845778783 ps |
| CPU time | 905.94 seconds |
| Started | Aug 27 11:19:53 AM UTC 24 |
| Finished | Aug 27 11:35:09 AM UTC 24 |
| Peak memory | 386516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562951619 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_access_durin g_key_req.562951619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/37.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_alert_test.2190014715 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 37640246 ps |
| CPU time | 1.01 seconds |
| Started | Aug 27 11:21:24 AM UTC 24 |
| Finished | Aug 27 11:21:26 AM UTC 24 |
| Peak memory | 210816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190014715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_alert_test.2190014715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/37.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_bijection.1210923212 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 112744221873 ps |
| CPU time | 1918 seconds |
| Started | Aug 27 11:18:03 AM UTC 24 |
| Finished | Aug 27 11:50:22 AM UTC 24 |
| Peak memory | 213244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210923212 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection.1210923212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/37.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_executable.505910325 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 11700771409 ps |
| CPU time | 1006.85 seconds |
| Started | Aug 27 11:19:54 AM UTC 24 |
| Finished | Aug 27 11:36:53 AM UTC 24 |
| Peak memory | 388788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505910325 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executable.505910325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/37.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.1425637886 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 4587383045 ps |
| CPU time | 44.35 seconds |
| Started | Aug 27 11:19:43 AM UTC 24 |
| Finished | Aug 27 11:20:29 AM UTC 24 |
| Peak memory | 211572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425637886 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_escalation.1425637886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/37.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.3131542637 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 1561974731 ps |
| CPU time | 109.56 seconds |
| Started | Aug 27 11:19:20 AM UTC 24 |
| Finished | Aug 27 11:21:12 AM UTC 24 |
| Peak memory | 380516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3131542637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ max_throughput.3131542637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/37.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.2373210317 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 5764861295 ps |
| CPU time | 90.58 seconds |
| Started | Aug 27 11:20:39 AM UTC 24 |
| Finished | Aug 27 11:22:12 AM UTC 24 |
| Peak memory | 229132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373210317 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_mem_partial_access.2373210317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/37.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.1417600184 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 13796915310 ps |
| CPU time | 370.52 seconds |
| Started | Aug 27 11:20:33 AM UTC 24 |
| Finished | Aug 27 11:26:48 AM UTC 24 |
| Peak memory | 221884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417600184 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_mem_walk.1417600184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/37.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.4283082240 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 69544997701 ps |
| CPU time | 1582.75 seconds |
| Started | Aug 27 11:17:54 AM UTC 24 |
| Finished | Aug 27 11:44:35 AM UTC 24 |
| Peak memory | 384312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283082240 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multiple_keys.4283082240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/37.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access.942976407 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 4736720882 ps |
| CPU time | 40.73 seconds |
| Started | Aug 27 11:19:12 AM UTC 24 |
| Finished | Aug 27 11:19:54 AM UTC 24 |
| Peak memory | 319004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942976407 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_partial_access.942976407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/37.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.3511379094 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 17479292433 ps |
| CPU time | 462.14 seconds |
| Started | Aug 27 11:19:14 AM UTC 24 |
| Finished | Aug 27 11:27:02 AM UTC 24 |
| Peak memory | 211568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511379094 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_partial_a ccess_b2b.3511379094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/37.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.372499801 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 6714054138 ps |
| CPU time | 7.33 seconds |
| Started | Aug 27 11:20:30 AM UTC 24 |
| Finished | Aug 27 11:20:38 AM UTC 24 |
| Peak memory | 211684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372499801 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.372499801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/37.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_regwen.3528764990 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 25556409630 ps |
| CPU time | 440.77 seconds |
| Started | Aug 27 11:19:57 AM UTC 24 |
| Finished | Aug 27 11:27:23 AM UTC 24 |
| Peak memory | 384460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528764990 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.3528764990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/37.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_smoke.2068597037 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 2035298679 ps |
| CPU time | 26.69 seconds |
| Started | Aug 27 11:17:34 AM UTC 24 |
| Finished | Aug 27 11:18:02 AM UTC 24 |
| Peak memory | 282076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068597037 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.2068597037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/37.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all.1160349482 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 90987179612 ps |
| CPU time | 2786.68 seconds |
| Started | Aug 27 11:21:24 AM UTC 24 |
| Finished | Aug 27 12:08:21 PM UTC 24 |
| Peak memory | 390244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11603494 82 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_a ll.1160349482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/37.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.1830643834 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 1997574362 ps |
| CPU time | 76.4 seconds |
| Started | Aug 27 11:21:13 AM UTC 24 |
| Finished | Aug 27 11:22:32 AM UTC 24 |
| Peak memory | 341600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830643834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.1830643834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/37.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.2660910159 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 7604404017 ps |
| CPU time | 295.27 seconds |
| Started | Aug 27 11:18:34 AM UTC 24 |
| Finished | Aug 27 11:23:33 AM UTC 24 |
| Peak memory | 211556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660910159 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_pipeline.2660910159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/37.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.4200363067 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 1479370981 ps |
| CPU time | 19.29 seconds |
| Started | Aug 27 11:19:35 AM UTC 24 |
| Finished | Aug 27 11:19:56 AM UTC 24 |
| Peak memory | 249436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =4200363067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl _throughput_w_partial_write.4200363067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/37.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.2348399861 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 12288583055 ps |
| CPU time | 634.38 seconds |
| Started | Aug 27 11:22:32 AM UTC 24 |
| Finished | Aug 27 11:33:14 AM UTC 24 |
| Peak memory | 380452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348399861 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_access_duri ng_key_req.2348399861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/38.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_alert_test.1019548477 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 29802378 ps |
| CPU time | 1 seconds |
| Started | Aug 27 11:24:30 AM UTC 24 |
| Finished | Aug 27 11:24:33 AM UTC 24 |
| Peak memory | 210736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019548477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_alert_test.1019548477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/38.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_bijection.3796979580 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 127039068051 ps |
| CPU time | 2172.07 seconds |
| Started | Aug 27 11:21:29 AM UTC 24 |
| Finished | Aug 27 11:58:04 AM UTC 24 |
| Peak memory | 213364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796979580 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection.3796979580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/38.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_executable.996407777 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 18150536602 ps |
| CPU time | 925.92 seconds |
| Started | Aug 27 11:22:56 AM UTC 24 |
| Finished | Aug 27 11:38:32 AM UTC 24 |
| Peak memory | 388640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996407777 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executable.996407777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/38.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.1751998293 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 17774070230 ps |
| CPU time | 29.42 seconds |
| Started | Aug 27 11:22:24 AM UTC 24 |
| Finished | Aug 27 11:22:55 AM UTC 24 |
| Peak memory | 221820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751998293 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_escalation.1751998293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/38.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.1994500712 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 729383616 ps |
| CPU time | 16.77 seconds |
| Started | Aug 27 11:22:05 AM UTC 24 |
| Finished | Aug 27 11:22:23 AM UTC 24 |
| Peak memory | 245352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1994500712 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ max_throughput.1994500712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/38.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.2118006632 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 2386064448 ps |
| CPU time | 80.37 seconds |
| Started | Aug 27 11:23:42 AM UTC 24 |
| Finished | Aug 27 11:25:04 AM UTC 24 |
| Peak memory | 229192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118006632 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_mem_partial_access.2118006632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/38.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.1929378960 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 2059616114 ps |
| CPU time | 142.77 seconds |
| Started | Aug 27 11:23:35 AM UTC 24 |
| Finished | Aug 27 11:26:00 AM UTC 24 |
| Peak memory | 221828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929378960 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_mem_walk.1929378960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/38.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.3492132667 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 23265426042 ps |
| CPU time | 1284.35 seconds |
| Started | Aug 27 11:21:27 AM UTC 24 |
| Finished | Aug 27 11:43:04 AM UTC 24 |
| Peak memory | 388640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492132667 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multiple_keys.3492132667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/38.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access.1318141202 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 2841526271 ps |
| CPU time | 11.5 seconds |
| Started | Aug 27 11:21:52 AM UTC 24 |
| Finished | Aug 27 11:22:04 AM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318141202 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_partial_access.1318141202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/38.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.1018822892 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 12343550801 ps |
| CPU time | 320.26 seconds |
| Started | Aug 27 11:22:04 AM UTC 24 |
| Finished | Aug 27 11:27:28 AM UTC 24 |
| Peak memory | 211632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018822892 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_partial_a ccess_b2b.1018822892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/38.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.1086498812 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 352769520 ps |
| CPU time | 6.21 seconds |
| Started | Aug 27 11:23:34 AM UTC 24 |
| Finished | Aug 27 11:23:41 AM UTC 24 |
| Peak memory | 211644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086498812 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.1086498812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/38.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_regwen.2970910332 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 47995232479 ps |
| CPU time | 625.94 seconds |
| Started | Aug 27 11:23:24 AM UTC 24 |
| Finished | Aug 27 11:33:57 AM UTC 24 |
| Peak memory | 386588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970910332 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.2970910332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/38.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_smoke.719882519 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 1352419593 ps |
| CPU time | 20.72 seconds |
| Started | Aug 27 11:21:26 AM UTC 24 |
| Finished | Aug 27 11:21:48 AM UTC 24 |
| Peak memory | 211704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719882519 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.719882519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/38.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all.829525311 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 190002000576 ps |
| CPU time | 5952.69 seconds |
| Started | Aug 27 11:24:12 AM UTC 24 |
| Finished | Aug 27 01:04:24 PM UTC 24 |
| Peak memory | 390252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82952531 1 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all.829525311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/38.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.2272105976 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1645339541 ps |
| CPU time | 82.95 seconds |
| Started | Aug 27 11:23:59 AM UTC 24 |
| Finished | Aug 27 11:25:24 AM UTC 24 |
| Peak memory | 316976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272105976 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.2272105976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/38.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.3620496796 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 5146711463 ps |
| CPU time | 403.74 seconds |
| Started | Aug 27 11:21:49 AM UTC 24 |
| Finished | Aug 27 11:28:38 AM UTC 24 |
| Peak memory | 211628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620496796 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_pipeline.3620496796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/38.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.1101327265 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 1663050413 ps |
| CPU time | 80.31 seconds |
| Started | Aug 27 11:22:12 AM UTC 24 |
| Finished | Aug 27 11:23:34 AM UTC 24 |
| Peak memory | 376216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1101327265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl _throughput_w_partial_write.1101327265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/38.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.2071060765 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 17488984059 ps |
| CPU time | 1189.03 seconds |
| Started | Aug 27 11:26:02 AM UTC 24 |
| Finished | Aug 27 11:46:05 AM UTC 24 |
| Peak memory | 388776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071060765 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_access_duri ng_key_req.2071060765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/39.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_alert_test.3469520333 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 15192991 ps |
| CPU time | 0.87 seconds |
| Started | Aug 27 11:28:07 AM UTC 24 |
| Finished | Aug 27 11:28:09 AM UTC 24 |
| Peak memory | 210876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469520333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_alert_test.3469520333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/39.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_bijection.2560344229 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 61484662270 ps |
| CPU time | 1216.79 seconds |
| Started | Aug 27 11:25:05 AM UTC 24 |
| Finished | Aug 27 11:45:36 AM UTC 24 |
| Peak memory | 211624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560344229 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection.2560344229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/39.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_executable.3413642014 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 29541295635 ps |
| CPU time | 635.17 seconds |
| Started | Aug 27 11:26:49 AM UTC 24 |
| Finished | Aug 27 11:37:31 AM UTC 24 |
| Peak memory | 382428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413642014 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executable.3413642014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/39.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.442861443 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 62823717049 ps |
| CPU time | 161.53 seconds |
| Started | Aug 27 11:25:57 AM UTC 24 |
| Finished | Aug 27 11:28:42 AM UTC 24 |
| Peak memory | 222008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442861443 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_escalation.442861443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/39.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.2582380208 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 3731534503 ps |
| CPU time | 10.31 seconds |
| Started | Aug 27 11:25:39 AM UTC 24 |
| Finished | Aug 27 11:25:51 AM UTC 24 |
| Peak memory | 228460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2582380208 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ max_throughput.2582380208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/39.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.4239018701 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 2650658657 ps |
| CPU time | 101.04 seconds |
| Started | Aug 27 11:27:23 AM UTC 24 |
| Finished | Aug 27 11:29:07 AM UTC 24 |
| Peak memory | 228888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239018701 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_mem_partial_access.4239018701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/39.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.1292298469 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 28786926180 ps |
| CPU time | 409.52 seconds |
| Started | Aug 27 11:27:10 AM UTC 24 |
| Finished | Aug 27 11:34:05 AM UTC 24 |
| Peak memory | 221944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292298469 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_mem_walk.1292298469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/39.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.313249447 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 5849628012 ps |
| CPU time | 113.48 seconds |
| Started | Aug 27 11:24:57 AM UTC 24 |
| Finished | Aug 27 11:26:52 AM UTC 24 |
| Peak memory | 337376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313249447 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multiple_keys.313249447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/39.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access.336847662 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 1491972365 ps |
| CPU time | 13.95 seconds |
| Started | Aug 27 11:25:23 AM UTC 24 |
| Finished | Aug 27 11:25:38 AM UTC 24 |
| Peak memory | 237152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336847662 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_partial_access.336847662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/39.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.908586550 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 36235912167 ps |
| CPU time | 468.6 seconds |
| Started | Aug 27 11:25:25 AM UTC 24 |
| Finished | Aug 27 11:33:19 AM UTC 24 |
| Peak memory | 211876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908586550 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_partial_ac cess_b2b.908586550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/39.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.3947173020 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 1527769852 ps |
| CPU time | 5.85 seconds |
| Started | Aug 27 11:27:02 AM UTC 24 |
| Finished | Aug 27 11:27:09 AM UTC 24 |
| Peak memory | 211644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947173020 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.3947173020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/39.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_regwen.2310137060 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 19987466268 ps |
| CPU time | 392.92 seconds |
| Started | Aug 27 11:26:53 AM UTC 24 |
| Finished | Aug 27 11:33:31 AM UTC 24 |
| Peak memory | 368164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310137060 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.2310137060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/39.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_smoke.3595835276 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 987001497 ps |
| CPU time | 20.34 seconds |
| Started | Aug 27 11:24:34 AM UTC 24 |
| Finished | Aug 27 11:24:55 AM UTC 24 |
| Peak memory | 211552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595835276 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.3595835276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/39.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all.2276370499 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 267684431701 ps |
| CPU time | 5357.1 seconds |
| Started | Aug 27 11:27:29 AM UTC 24 |
| Finished | Aug 27 12:57:39 PM UTC 24 |
| Peak memory | 392276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22763704 99 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_a ll.2276370499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/39.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.282629653 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 30098747426 ps |
| CPU time | 145.38 seconds |
| Started | Aug 27 11:27:26 AM UTC 24 |
| Finished | Aug 27 11:29:54 AM UTC 24 |
| Peak memory | 229140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282629653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.282629653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/39.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.1619991586 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 3444648157 ps |
| CPU time | 162.4 seconds |
| Started | Aug 27 11:25:21 AM UTC 24 |
| Finished | Aug 27 11:28:06 AM UTC 24 |
| Peak memory | 211904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619991586 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_pipeline.1619991586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/39.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.1781849066 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 790137490 ps |
| CPU time | 91.09 seconds |
| Started | Aug 27 11:25:51 AM UTC 24 |
| Finished | Aug 27 11:27:24 AM UTC 24 |
| Peak memory | 380380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1781849066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl _throughput_w_partial_write.1781849066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/39.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.3935393371 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 6721298262 ps |
| CPU time | 301.89 seconds |
| Started | Aug 27 09:27:32 AM UTC 24 |
| Finished | Aug 27 09:32:38 AM UTC 24 |
| Peak memory | 366248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935393371 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_access_durin g_key_req.3935393371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/4.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_alert_test.404041122 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 13950029 ps |
| CPU time | 0.92 seconds |
| Started | Aug 27 09:29:27 AM UTC 24 |
| Finished | Aug 27 09:29:29 AM UTC 24 |
| Peak memory | 210812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404041122 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_alert_test.404041122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/4.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_bijection.4160074972 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 42937796037 ps |
| CPU time | 816.92 seconds |
| Started | Aug 27 09:26:57 AM UTC 24 |
| Finished | Aug 27 09:40:43 AM UTC 24 |
| Peak memory | 211488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160074972 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection.4160074972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/4.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_executable.4104406547 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 40855289259 ps |
| CPU time | 306.53 seconds |
| Started | Aug 27 09:28:04 AM UTC 24 |
| Finished | Aug 27 09:33:15 AM UTC 24 |
| Peak memory | 372200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104406547 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executable.4104406547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/4.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.3937459900 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 3314565855 ps |
| CPU time | 56.81 seconds |
| Started | Aug 27 09:27:12 AM UTC 24 |
| Finished | Aug 27 09:28:10 AM UTC 24 |
| Peak memory | 319016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3937459900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_m ax_throughput.3937459900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/4.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.630846068 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 5167948343 ps |
| CPU time | 158.06 seconds |
| Started | Aug 27 09:28:28 AM UTC 24 |
| Finished | Aug 27 09:31:09 AM UTC 24 |
| Peak memory | 221864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630846068 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_mem_partial_access.630846068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/4.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.919381540 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 3946647049 ps |
| CPU time | 239.73 seconds |
| Started | Aug 27 09:28:21 AM UTC 24 |
| Finished | Aug 27 09:32:24 AM UTC 24 |
| Peak memory | 221924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919381540 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_mem_walk.919381540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/4.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.2576010412 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 8460637882 ps |
| CPU time | 763.25 seconds |
| Started | Aug 27 09:26:42 AM UTC 24 |
| Finished | Aug 27 09:39:34 AM UTC 24 |
| Peak memory | 388648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576010412 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multiple_keys.2576010412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/4.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access.1693108904 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 1342708856 ps |
| CPU time | 9.02 seconds |
| Started | Aug 27 09:27:01 AM UTC 24 |
| Finished | Aug 27 09:27:11 AM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693108904 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_partial_access.1693108904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/4.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.810159406 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 103297334475 ps |
| CPU time | 763.75 seconds |
| Started | Aug 27 09:27:07 AM UTC 24 |
| Finished | Aug 27 09:40:00 AM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810159406 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_partial_acc ess_b2b.810159406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/4.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.3240706034 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 611775156 ps |
| CPU time | 6.09 seconds |
| Started | Aug 27 09:28:13 AM UTC 24 |
| Finished | Aug 27 09:28:20 AM UTC 24 |
| Peak memory | 211840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240706034 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.3240706034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/4.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_regwen.1097065571 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 8718254894 ps |
| CPU time | 162.29 seconds |
| Started | Aug 27 09:28:12 AM UTC 24 |
| Finished | Aug 27 09:30:56 AM UTC 24 |
| Peak memory | 357920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097065571 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.1097065571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/4.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.2506052358 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 964810713 ps |
| CPU time | 3.81 seconds |
| Started | Aug 27 09:29:22 AM UTC 24 |
| Finished | Aug 27 09:29:27 AM UTC 24 |
| Peak memory | 247760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506052358 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_sec_cm.2506052358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/4.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_smoke.3258671513 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 2327222107 ps |
| CPU time | 36.95 seconds |
| Started | Aug 27 09:26:28 AM UTC 24 |
| Finished | Aug 27 09:27:06 AM UTC 24 |
| Peak memory | 286168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258671513 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.3258671513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/4.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all.4238687122 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 94049192678 ps |
| CPU time | 5486.88 seconds |
| Started | Aug 27 09:29:04 AM UTC 24 |
| Finished | Aug 27 11:01:25 AM UTC 24 |
| Peak memory | 400468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42386871 22 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all.4238687122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/4.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.1334098756 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 591488782 ps |
| CPU time | 7.78 seconds |
| Started | Aug 27 09:28:54 AM UTC 24 |
| Finished | Aug 27 09:29:02 AM UTC 24 |
| Peak memory | 221876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334098756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.1334098756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/4.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.4005801016 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 64590082660 ps |
| CPU time | 370.25 seconds |
| Started | Aug 27 09:26:58 AM UTC 24 |
| Finished | Aug 27 09:33:13 AM UTC 24 |
| Peak memory | 211552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005801016 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_pipeline.4005801016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/4.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.3645921672 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 2799139710 ps |
| CPU time | 11.3 seconds |
| Started | Aug 27 09:27:19 AM UTC 24 |
| Finished | Aug 27 09:27:32 AM UTC 24 |
| Peak memory | 222012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3645921672 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ throughput_w_partial_write.3645921672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/4.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.3992332899 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 81936844380 ps |
| CPU time | 938.89 seconds |
| Started | Aug 27 11:29:54 AM UTC 24 |
| Finished | Aug 27 11:45:44 AM UTC 24 |
| Peak memory | 384676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992332899 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_access_duri ng_key_req.3992332899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/40.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_alert_test.323949384 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 19973899 ps |
| CPU time | 1.05 seconds |
| Started | Aug 27 11:33:32 AM UTC 24 |
| Finished | Aug 27 11:33:34 AM UTC 24 |
| Peak memory | 210872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323949384 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_alert_test.323949384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/40.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_bijection.671417459 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 311466674023 ps |
| CPU time | 1445.7 seconds |
| Started | Aug 27 11:28:42 AM UTC 24 |
| Finished | Aug 27 11:53:05 AM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671417459 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection.671417459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/40.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_executable.858165433 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 7424112249 ps |
| CPU time | 289.31 seconds |
| Started | Aug 27 11:30:34 AM UTC 24 |
| Finished | Aug 27 11:35:27 AM UTC 24 |
| Peak memory | 386536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858165433 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executable.858165433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/40.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.3120094687 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 7171617610 ps |
| CPU time | 41.97 seconds |
| Started | Aug 27 11:29:50 AM UTC 24 |
| Finished | Aug 27 11:30:34 AM UTC 24 |
| Peak memory | 211640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120094687 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_escalation.3120094687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/40.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.1203748395 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 3048480871 ps |
| CPU time | 97.18 seconds |
| Started | Aug 27 11:29:14 AM UTC 24 |
| Finished | Aug 27 11:30:53 AM UTC 24 |
| Peak memory | 376356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1203748395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ max_throughput.1203748395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/40.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.20467815 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 5341807831 ps |
| CPU time | 218.99 seconds |
| Started | Aug 27 11:32:12 AM UTC 24 |
| Finished | Aug 27 11:35:55 AM UTC 24 |
| Peak memory | 228888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20467815 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_mem_partial_access.20467815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/40.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.738622144 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 33047434746 ps |
| CPU time | 235.28 seconds |
| Started | Aug 27 11:31:02 AM UTC 24 |
| Finished | Aug 27 11:35:01 AM UTC 24 |
| Peak memory | 221868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738622144 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_mem_walk.738622144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/40.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.910471400 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 96415369211 ps |
| CPU time | 1057.94 seconds |
| Started | Aug 27 11:28:38 AM UTC 24 |
| Finished | Aug 27 11:46:27 AM UTC 24 |
| Peak memory | 388640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910471400 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multiple_keys.910471400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/40.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access.1895180293 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 565505623 ps |
| CPU time | 18.2 seconds |
| Started | Aug 27 11:28:53 AM UTC 24 |
| Finished | Aug 27 11:29:13 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895180293 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_partial_access.1895180293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/40.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.3894960925 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 76620964652 ps |
| CPU time | 598.13 seconds |
| Started | Aug 27 11:29:08 AM UTC 24 |
| Finished | Aug 27 11:39:13 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894960925 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_partial_a ccess_b2b.3894960925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/40.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.3780601702 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 352319133 ps |
| CPU time | 6.32 seconds |
| Started | Aug 27 11:30:54 AM UTC 24 |
| Finished | Aug 27 11:31:01 AM UTC 24 |
| Peak memory | 211912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780601702 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.3780601702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/40.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_regwen.2160303212 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 18651400894 ps |
| CPU time | 221.44 seconds |
| Started | Aug 27 11:30:49 AM UTC 24 |
| Finished | Aug 27 11:34:33 AM UTC 24 |
| Peak memory | 360116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160303212 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.2160303212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/40.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_smoke.517164647 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 1998571452 ps |
| CPU time | 36.11 seconds |
| Started | Aug 27 11:28:10 AM UTC 24 |
| Finished | Aug 27 11:28:48 AM UTC 24 |
| Peak memory | 292240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517164647 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.517164647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/40.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all.2419979696 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 645620844020 ps |
| CPU time | 4037.7 seconds |
| Started | Aug 27 11:33:20 AM UTC 24 |
| Finished | Aug 27 12:41:19 PM UTC 24 |
| Peak memory | 396388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24199796 96 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_a ll.2419979696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/40.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.2247464725 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 5569676181 ps |
| CPU time | 563.09 seconds |
| Started | Aug 27 11:28:48 AM UTC 24 |
| Finished | Aug 27 11:38:19 AM UTC 24 |
| Peak memory | 211572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247464725 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_pipeline.2247464725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/40.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.4165755264 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 898273580 ps |
| CPU time | 75.62 seconds |
| Started | Aug 27 11:29:30 AM UTC 24 |
| Finished | Aug 27 11:30:47 AM UTC 24 |
| Peak memory | 343440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =4165755264 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl _throughput_w_partial_write.4165755264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/40.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.4075078033 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 97764297624 ps |
| CPU time | 1031.85 seconds |
| Started | Aug 27 11:35:01 AM UTC 24 |
| Finished | Aug 27 11:52:24 AM UTC 24 |
| Peak memory | 386728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075078033 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_access_duri ng_key_req.4075078033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/41.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_alert_test.3495328653 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 42211796 ps |
| CPU time | 1.01 seconds |
| Started | Aug 27 11:36:53 AM UTC 24 |
| Finished | Aug 27 11:36:55 AM UTC 24 |
| Peak memory | 210936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495328653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_alert_test.3495328653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/41.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_bijection.325639595 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 27378086193 ps |
| CPU time | 1983.66 seconds |
| Started | Aug 27 11:33:57 AM UTC 24 |
| Finished | Aug 27 12:07:22 PM UTC 24 |
| Peak memory | 213292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325639595 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection.325639595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/41.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_executable.548321045 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 14701741311 ps |
| CPU time | 358.25 seconds |
| Started | Aug 27 11:35:10 AM UTC 24 |
| Finished | Aug 27 11:41:14 AM UTC 24 |
| Peak memory | 380420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548321045 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executable.548321045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/41.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.1401887541 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 140743348916 ps |
| CPU time | 199.58 seconds |
| Started | Aug 27 11:34:54 AM UTC 24 |
| Finished | Aug 27 11:38:17 AM UTC 24 |
| Peak memory | 225892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401887541 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_escalation.1401887541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/41.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.1335155754 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 3216404401 ps |
| CPU time | 73.04 seconds |
| Started | Aug 27 11:34:37 AM UTC 24 |
| Finished | Aug 27 11:35:52 AM UTC 24 |
| Peak memory | 341544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1335155754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ max_throughput.1335155754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/41.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.2844215240 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 6382180431 ps |
| CPU time | 174.96 seconds |
| Started | Aug 27 11:35:29 AM UTC 24 |
| Finished | Aug 27 11:38:26 AM UTC 24 |
| Peak memory | 221920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844215240 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_mem_partial_access.2844215240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/41.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.2623648940 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 15473168797 ps |
| CPU time | 164.59 seconds |
| Started | Aug 27 11:35:22 AM UTC 24 |
| Finished | Aug 27 11:38:09 AM UTC 24 |
| Peak memory | 221812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623648940 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_mem_walk.2623648940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/41.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.2847032193 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 30885883314 ps |
| CPU time | 531.74 seconds |
| Started | Aug 27 11:33:50 AM UTC 24 |
| Finished | Aug 27 11:42:48 AM UTC 24 |
| Peak memory | 349872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847032193 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multiple_keys.2847032193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/41.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access.3771480696 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 4301766631 ps |
| CPU time | 45.84 seconds |
| Started | Aug 27 11:34:06 AM UTC 24 |
| Finished | Aug 27 11:34:53 AM UTC 24 |
| Peak memory | 302768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771480696 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_partial_access.3771480696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/41.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.2808094478 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 41824667764 ps |
| CPU time | 306.75 seconds |
| Started | Aug 27 11:34:34 AM UTC 24 |
| Finished | Aug 27 11:39:45 AM UTC 24 |
| Peak memory | 211504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808094478 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_partial_a ccess_b2b.2808094478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/41.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.3433808604 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 367187592 ps |
| CPU time | 4.87 seconds |
| Started | Aug 27 11:35:14 AM UTC 24 |
| Finished | Aug 27 11:35:21 AM UTC 24 |
| Peak memory | 211716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433808604 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.3433808604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/41.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_regwen.1661748978 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 32796319437 ps |
| CPU time | 1399.15 seconds |
| Started | Aug 27 11:35:10 AM UTC 24 |
| Finished | Aug 27 11:58:45 AM UTC 24 |
| Peak memory | 382532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661748978 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.1661748978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/41.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_smoke.494076198 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 1461054657 ps |
| CPU time | 12.53 seconds |
| Started | Aug 27 11:33:35 AM UTC 24 |
| Finished | Aug 27 11:33:49 AM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494076198 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.494076198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/41.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all.2794896168 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 724966224124 ps |
| CPU time | 4048.65 seconds |
| Started | Aug 27 11:35:56 AM UTC 24 |
| Finished | Aug 27 12:44:09 PM UTC 24 |
| Peak memory | 392376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27948961 68 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_a ll.2794896168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/41.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.3529617983 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 2376008897 ps |
| CPU time | 140.8 seconds |
| Started | Aug 27 11:35:53 AM UTC 24 |
| Finished | Aug 27 11:38:16 AM UTC 24 |
| Peak memory | 386736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529617983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.3529617983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/41.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.3106631752 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 16043993064 ps |
| CPU time | 391.11 seconds |
| Started | Aug 27 11:34:03 AM UTC 24 |
| Finished | Aug 27 11:40:40 AM UTC 24 |
| Peak memory | 211760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106631752 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_pipeline.3106631752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/41.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.3998789114 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 769419710 ps |
| CPU time | 28.55 seconds |
| Started | Aug 27 11:34:44 AM UTC 24 |
| Finished | Aug 27 11:35:14 AM UTC 24 |
| Peak memory | 306776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3998789114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl _throughput_w_partial_write.3998789114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/41.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.1538929054 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 15208109398 ps |
| CPU time | 920.09 seconds |
| Started | Aug 27 11:38:33 AM UTC 24 |
| Finished | Aug 27 11:54:03 AM UTC 24 |
| Peak memory | 386584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538929054 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_access_duri ng_key_req.1538929054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/42.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_alert_test.3671474452 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 29256781 ps |
| CPU time | 1.01 seconds |
| Started | Aug 27 11:40:19 AM UTC 24 |
| Finished | Aug 27 11:40:21 AM UTC 24 |
| Peak memory | 210736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671474452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_alert_test.3671474452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/42.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_bijection.1166092329 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 41652369492 ps |
| CPU time | 866.79 seconds |
| Started | Aug 27 11:37:32 AM UTC 24 |
| Finished | Aug 27 11:52:09 AM UTC 24 |
| Peak memory | 211576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166092329 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection.1166092329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/42.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_executable.1957352804 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 20052687752 ps |
| CPU time | 1333.12 seconds |
| Started | Aug 27 11:38:44 AM UTC 24 |
| Finished | Aug 27 12:01:11 PM UTC 24 |
| Peak memory | 388808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957352804 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executable.1957352804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/42.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.3897941961 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 4718105070 ps |
| CPU time | 42.92 seconds |
| Started | Aug 27 11:38:31 AM UTC 24 |
| Finished | Aug 27 11:39:16 AM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897941961 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_escalation.3897941961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/42.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.2106167204 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 3266949476 ps |
| CPU time | 22.93 seconds |
| Started | Aug 27 11:38:19 AM UTC 24 |
| Finished | Aug 27 11:38:43 AM UTC 24 |
| Peak memory | 298660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2106167204 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ max_throughput.2106167204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/42.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.3556587212 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 5810965307 ps |
| CPU time | 168.41 seconds |
| Started | Aug 27 11:39:29 AM UTC 24 |
| Finished | Aug 27 11:42:20 AM UTC 24 |
| Peak memory | 228880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556587212 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_mem_partial_access.3556587212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/42.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.2832849558 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 5255449289 ps |
| CPU time | 356.35 seconds |
| Started | Aug 27 11:39:25 AM UTC 24 |
| Finished | Aug 27 11:45:26 AM UTC 24 |
| Peak memory | 221888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832849558 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_mem_walk.2832849558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/42.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.2659749815 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 17503546902 ps |
| CPU time | 393.05 seconds |
| Started | Aug 27 11:37:15 AM UTC 24 |
| Finished | Aug 27 11:43:53 AM UTC 24 |
| Peak memory | 378416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659749815 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multiple_keys.2659749815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/42.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access.4215242217 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 2100979540 ps |
| CPU time | 12.06 seconds |
| Started | Aug 27 11:38:17 AM UTC 24 |
| Finished | Aug 27 11:38:30 AM UTC 24 |
| Peak memory | 211504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215242217 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_partial_access.4215242217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/42.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.2212791006 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 6539617645 ps |
| CPU time | 528.35 seconds |
| Started | Aug 27 11:38:18 AM UTC 24 |
| Finished | Aug 27 11:47:13 AM UTC 24 |
| Peak memory | 211564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212791006 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_partial_a ccess_b2b.2212791006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/42.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.275054669 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 347092334 ps |
| CPU time | 6.2 seconds |
| Started | Aug 27 11:39:17 AM UTC 24 |
| Finished | Aug 27 11:39:24 AM UTC 24 |
| Peak memory | 211620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275054669 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.275054669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/42.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_regwen.2241198482 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 19938816751 ps |
| CPU time | 907.22 seconds |
| Started | Aug 27 11:39:14 AM UTC 24 |
| Finished | Aug 27 11:54:30 AM UTC 24 |
| Peak memory | 390836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241198482 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.2241198482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/42.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_smoke.916015496 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 455308701 ps |
| CPU time | 16.21 seconds |
| Started | Aug 27 11:36:56 AM UTC 24 |
| Finished | Aug 27 11:37:14 AM UTC 24 |
| Peak memory | 211568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916015496 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.916015496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/42.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all.3057503844 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 20817049610 ps |
| CPU time | 1049.43 seconds |
| Started | Aug 27 11:39:45 AM UTC 24 |
| Finished | Aug 27 11:57:26 AM UTC 24 |
| Peak memory | 388592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30575038 44 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_a ll.3057503844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/42.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.2376837005 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 2105643153 ps |
| CPU time | 41.5 seconds |
| Started | Aug 27 11:39:34 AM UTC 24 |
| Finished | Aug 27 11:40:18 AM UTC 24 |
| Peak memory | 221876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376837005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.2376837005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/42.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.2513501212 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 15751553241 ps |
| CPU time | 388.02 seconds |
| Started | Aug 27 11:38:10 AM UTC 24 |
| Finished | Aug 27 11:44:44 AM UTC 24 |
| Peak memory | 211648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513501212 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_pipeline.2513501212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/42.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.3998091704 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 3113297373 ps |
| CPU time | 59.74 seconds |
| Started | Aug 27 11:38:27 AM UTC 24 |
| Finished | Aug 27 11:39:29 AM UTC 24 |
| Peak memory | 323096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3998091704 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl _throughput_w_partial_write.3998091704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/42.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.1178566305 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 20301283463 ps |
| CPU time | 559.35 seconds |
| Started | Aug 27 11:43:53 AM UTC 24 |
| Finished | Aug 27 11:53:19 AM UTC 24 |
| Peak memory | 382432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178566305 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_access_duri ng_key_req.1178566305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/43.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_alert_test.932466849 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 15098356 ps |
| CPU time | 1 seconds |
| Started | Aug 27 11:45:32 AM UTC 24 |
| Finished | Aug 27 11:45:33 AM UTC 24 |
| Peak memory | 210872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932466849 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_alert_test.932466849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/43.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_bijection.1371004618 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 65227761822 ps |
| CPU time | 1853.18 seconds |
| Started | Aug 27 11:40:47 AM UTC 24 |
| Finished | Aug 27 12:12:02 PM UTC 24 |
| Peak memory | 213184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371004618 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection.1371004618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/43.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_executable.1206384646 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 17401179284 ps |
| CPU time | 216.26 seconds |
| Started | Aug 27 11:43:54 AM UTC 24 |
| Finished | Aug 27 11:47:33 AM UTC 24 |
| Peak memory | 386596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206384646 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executable.1206384646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/43.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.1955688676 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 24395906741 ps |
| CPU time | 59.93 seconds |
| Started | Aug 27 11:43:05 AM UTC 24 |
| Finished | Aug 27 11:44:07 AM UTC 24 |
| Peak memory | 221812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955688676 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_escalation.1955688676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/43.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.657478120 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 2957411350 ps |
| CPU time | 58.39 seconds |
| Started | Aug 27 11:42:52 AM UTC 24 |
| Finished | Aug 27 11:43:52 AM UTC 24 |
| Peak memory | 335336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 657478120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_m ax_throughput.657478120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/43.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.247844356 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 17510940848 ps |
| CPU time | 141.64 seconds |
| Started | Aug 27 11:44:42 AM UTC 24 |
| Finished | Aug 27 11:47:06 AM UTC 24 |
| Peak memory | 228892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247844356 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_mem_partial_access.247844356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/43.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.221659802 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 24675629698 ps |
| CPU time | 179.1 seconds |
| Started | Aug 27 11:44:36 AM UTC 24 |
| Finished | Aug 27 11:47:38 AM UTC 24 |
| Peak memory | 221864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221659802 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_mem_walk.221659802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/43.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.3485755050 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 38152746875 ps |
| CPU time | 611.51 seconds |
| Started | Aug 27 11:40:41 AM UTC 24 |
| Finished | Aug 27 11:51:00 AM UTC 24 |
| Peak memory | 386724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485755050 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multiple_keys.3485755050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/43.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access.1035417314 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 762307910 ps |
| CPU time | 28.37 seconds |
| Started | Aug 27 11:42:22 AM UTC 24 |
| Finished | Aug 27 11:42:51 AM UTC 24 |
| Peak memory | 269780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035417314 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_partial_access.1035417314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/43.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.3248537828 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 12564772707 ps |
| CPU time | 533.02 seconds |
| Started | Aug 27 11:42:49 AM UTC 24 |
| Finished | Aug 27 11:51:49 AM UTC 24 |
| Peak memory | 211844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248537828 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_partial_a ccess_b2b.3248537828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/43.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.567778642 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 373271925 ps |
| CPU time | 4.66 seconds |
| Started | Aug 27 11:44:36 AM UTC 24 |
| Finished | Aug 27 11:44:42 AM UTC 24 |
| Peak memory | 211820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567778642 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.567778642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/43.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_regwen.278563846 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 4681115330 ps |
| CPU time | 129.04 seconds |
| Started | Aug 27 11:44:08 AM UTC 24 |
| Finished | Aug 27 11:46:19 AM UTC 24 |
| Peak memory | 316964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278563846 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.278563846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/43.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_smoke.3318061021 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 535062862 ps |
| CPU time | 22.74 seconds |
| Started | Aug 27 11:40:22 AM UTC 24 |
| Finished | Aug 27 11:40:46 AM UTC 24 |
| Peak memory | 211512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318061021 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.3318061021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/43.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all.2100055953 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 7418972501 ps |
| CPU time | 777.95 seconds |
| Started | Aug 27 11:45:27 AM UTC 24 |
| Finished | Aug 27 11:58:34 AM UTC 24 |
| Peak memory | 386572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21000559 53 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_a ll.2100055953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/43.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.2142487243 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 9571448590 ps |
| CPU time | 60.54 seconds |
| Started | Aug 27 11:44:44 AM UTC 24 |
| Finished | Aug 27 11:45:46 AM UTC 24 |
| Peak memory | 228888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142487243 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.2142487243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/43.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.489353225 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 6403767563 ps |
| CPU time | 471.74 seconds |
| Started | Aug 27 11:41:14 AM UTC 24 |
| Finished | Aug 27 11:49:11 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489353225 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_pipeline.489353225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/43.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.2874004978 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 804004459 ps |
| CPU time | 92.56 seconds |
| Started | Aug 27 11:43:00 AM UTC 24 |
| Finished | Aug 27 11:44:35 AM UTC 24 |
| Peak memory | 372188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2874004978 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl _throughput_w_partial_write.2874004978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/43.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.1079094745 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 7828481337 ps |
| CPU time | 383.31 seconds |
| Started | Aug 27 11:46:29 AM UTC 24 |
| Finished | Aug 27 11:52:57 AM UTC 24 |
| Peak memory | 366096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079094745 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_access_duri ng_key_req.1079094745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/44.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_alert_test.556057447 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 78314715 ps |
| CPU time | 1.09 seconds |
| Started | Aug 27 11:47:34 AM UTC 24 |
| Finished | Aug 27 11:47:37 AM UTC 24 |
| Peak memory | 210932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556057447 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_alert_test.556057447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/44.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_bijection.2664249978 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 125733399976 ps |
| CPU time | 699.85 seconds |
| Started | Aug 27 11:45:45 AM UTC 24 |
| Finished | Aug 27 11:57:34 AM UTC 24 |
| Peak memory | 211568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664249978 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection.2664249978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/44.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_executable.2803432783 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 81129925650 ps |
| CPU time | 1143.77 seconds |
| Started | Aug 27 11:46:37 AM UTC 24 |
| Finished | Aug 27 12:05:53 PM UTC 24 |
| Peak memory | 390312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803432783 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executable.2803432783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/44.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.1904195102 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 3400020462 ps |
| CPU time | 42.27 seconds |
| Started | Aug 27 11:46:20 AM UTC 24 |
| Finished | Aug 27 11:47:04 AM UTC 24 |
| Peak memory | 211584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904195102 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_escalation.1904195102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/44.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.3126419984 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 749106975 ps |
| CPU time | 64.69 seconds |
| Started | Aug 27 11:46:05 AM UTC 24 |
| Finished | Aug 27 11:47:12 AM UTC 24 |
| Peak memory | 343528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3126419984 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ max_throughput.3126419984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/44.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.2651503531 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 5219499723 ps |
| CPU time | 108.75 seconds |
| Started | Aug 27 11:47:13 AM UTC 24 |
| Finished | Aug 27 11:49:04 AM UTC 24 |
| Peak memory | 221844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651503531 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_mem_partial_access.2651503531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/44.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.3575927246 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 37428510713 ps |
| CPU time | 241.28 seconds |
| Started | Aug 27 11:47:12 AM UTC 24 |
| Finished | Aug 27 11:51:17 AM UTC 24 |
| Peak memory | 221936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575927246 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_mem_walk.3575927246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/44.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.3839420247 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 32016378093 ps |
| CPU time | 738.26 seconds |
| Started | Aug 27 11:45:37 AM UTC 24 |
| Finished | Aug 27 11:58:03 AM UTC 24 |
| Peak memory | 388644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839420247 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multiple_keys.3839420247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/44.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access.3409726073 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 607388068 ps |
| CPU time | 28.81 seconds |
| Started | Aug 27 11:45:49 AM UTC 24 |
| Finished | Aug 27 11:46:20 AM UTC 24 |
| Peak memory | 211496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409726073 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_partial_access.3409726073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/44.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.3930436534 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 196915880850 ps |
| CPU time | 744.37 seconds |
| Started | Aug 27 11:45:49 AM UTC 24 |
| Finished | Aug 27 11:58:23 AM UTC 24 |
| Peak memory | 211548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930436534 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_partial_a ccess_b2b.3930436534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/44.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.1830999783 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 351043784 ps |
| CPU time | 4.08 seconds |
| Started | Aug 27 11:47:07 AM UTC 24 |
| Finished | Aug 27 11:47:12 AM UTC 24 |
| Peak memory | 211912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830999783 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.1830999783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/44.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_regwen.903942439 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 20003016923 ps |
| CPU time | 403.59 seconds |
| Started | Aug 27 11:47:05 AM UTC 24 |
| Finished | Aug 27 11:53:54 AM UTC 24 |
| Peak memory | 368164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903942439 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.903942439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/44.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_smoke.798033931 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 2706115338 ps |
| CPU time | 12.08 seconds |
| Started | Aug 27 11:45:35 AM UTC 24 |
| Finished | Aug 27 11:45:48 AM UTC 24 |
| Peak memory | 211496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798033931 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.798033931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/44.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all.2558516383 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 261784302583 ps |
| CPU time | 5266.56 seconds |
| Started | Aug 27 11:47:29 AM UTC 24 |
| Finished | Aug 27 01:16:15 PM UTC 24 |
| Peak memory | 392240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25585163 83 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_a ll.2558516383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/44.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2156010444 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 173845011 ps |
| CPU time | 13.16 seconds |
| Started | Aug 27 11:47:14 AM UTC 24 |
| Finished | Aug 27 11:47:29 AM UTC 24 |
| Peak memory | 221884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156010444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.2156010444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/44.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.270805359 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 10685581386 ps |
| CPU time | 330.03 seconds |
| Started | Aug 27 11:45:47 AM UTC 24 |
| Finished | Aug 27 11:51:22 AM UTC 24 |
| Peak memory | 211624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270805359 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_pipeline.270805359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/44.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.3660811153 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 4590192500 ps |
| CPU time | 14.41 seconds |
| Started | Aug 27 11:46:20 AM UTC 24 |
| Finished | Aug 27 11:46:36 AM UTC 24 |
| Peak memory | 245404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3660811153 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl _throughput_w_partial_write.3660811153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/44.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.3226259698 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 38667550485 ps |
| CPU time | 568.69 seconds |
| Started | Aug 27 11:50:31 AM UTC 24 |
| Finished | Aug 27 12:00:07 PM UTC 24 |
| Peak memory | 386592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226259698 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_access_duri ng_key_req.3226259698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/45.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_alert_test.3618338930 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 62293626 ps |
| CPU time | 1.1 seconds |
| Started | Aug 27 11:52:10 AM UTC 24 |
| Finished | Aug 27 11:52:12 AM UTC 24 |
| Peak memory | 210736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618338930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_alert_test.3618338930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/45.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_bijection.261990237 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 17381348447 ps |
| CPU time | 1334.83 seconds |
| Started | Aug 27 11:47:48 AM UTC 24 |
| Finished | Aug 27 12:10:18 PM UTC 24 |
| Peak memory | 213248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261990237 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection.261990237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/45.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_executable.2964337203 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 15887070285 ps |
| CPU time | 628.74 seconds |
| Started | Aug 27 11:51:00 AM UTC 24 |
| Finished | Aug 27 12:01:36 PM UTC 24 |
| Peak memory | 351692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964337203 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executable.2964337203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/45.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.1628053047 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 43075822206 ps |
| CPU time | 94.85 seconds |
| Started | Aug 27 11:50:23 AM UTC 24 |
| Finished | Aug 27 11:52:00 AM UTC 24 |
| Peak memory | 211628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628053047 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_escalation.1628053047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/45.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.3745767431 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 3144961462 ps |
| CPU time | 58.92 seconds |
| Started | Aug 27 11:49:30 AM UTC 24 |
| Finished | Aug 27 11:50:30 AM UTC 24 |
| Peak memory | 368360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3745767431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ max_throughput.3745767431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/45.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.4194904727 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 10660208055 ps |
| CPU time | 126.31 seconds |
| Started | Aug 27 11:51:50 AM UTC 24 |
| Finished | Aug 27 11:53:59 AM UTC 24 |
| Peak memory | 222068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194904727 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_mem_partial_access.4194904727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/45.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.2265337308 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 69165174580 ps |
| CPU time | 195.97 seconds |
| Started | Aug 27 11:51:32 AM UTC 24 |
| Finished | Aug 27 11:54:51 AM UTC 24 |
| Peak memory | 221944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265337308 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_mem_walk.2265337308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/45.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.1139661146 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 9078618540 ps |
| CPU time | 388.1 seconds |
| Started | Aug 27 11:47:39 AM UTC 24 |
| Finished | Aug 27 11:54:12 AM UTC 24 |
| Peak memory | 364004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139661146 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multiple_keys.1139661146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/45.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access.1213628253 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 6182899883 ps |
| CPU time | 22.08 seconds |
| Started | Aug 27 11:49:05 AM UTC 24 |
| Finished | Aug 27 11:49:29 AM UTC 24 |
| Peak memory | 294428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213628253 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_partial_access.1213628253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/45.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.1773745469 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 8042264999 ps |
| CPU time | 532 seconds |
| Started | Aug 27 11:49:12 AM UTC 24 |
| Finished | Aug 27 11:58:11 AM UTC 24 |
| Peak memory | 211572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773745469 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_partial_a ccess_b2b.1773745469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/45.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.3394757840 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 1400503091 ps |
| CPU time | 7.36 seconds |
| Started | Aug 27 11:51:23 AM UTC 24 |
| Finished | Aug 27 11:51:31 AM UTC 24 |
| Peak memory | 211716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394757840 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.3394757840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/45.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_regwen.1519588383 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 18673663146 ps |
| CPU time | 744.55 seconds |
| Started | Aug 27 11:51:18 AM UTC 24 |
| Finished | Aug 27 12:03:52 PM UTC 24 |
| Peak memory | 388840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519588383 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.1519588383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/45.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_smoke.110393667 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 3511848296 ps |
| CPU time | 23.32 seconds |
| Started | Aug 27 11:47:38 AM UTC 24 |
| Finished | Aug 27 11:48:02 AM UTC 24 |
| Peak memory | 211556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110393667 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.110393667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/45.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all.2509020799 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 83853412549 ps |
| CPU time | 1963.27 seconds |
| Started | Aug 27 11:52:00 AM UTC 24 |
| Finished | Aug 27 12:25:03 PM UTC 24 |
| Peak memory | 394472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25090207 99 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_a ll.2509020799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/45.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1834947038 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 940513636 ps |
| CPU time | 19.62 seconds |
| Started | Aug 27 11:51:56 AM UTC 24 |
| Finished | Aug 27 11:52:17 AM UTC 24 |
| Peak memory | 221876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834947038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.1834947038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/45.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.3637920875 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 4351348324 ps |
| CPU time | 299.99 seconds |
| Started | Aug 27 11:48:03 AM UTC 24 |
| Finished | Aug 27 11:53:07 AM UTC 24 |
| Peak memory | 211512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637920875 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_pipeline.3637920875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/45.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.2933996080 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 3528388509 ps |
| CPU time | 92.06 seconds |
| Started | Aug 27 11:50:21 AM UTC 24 |
| Finished | Aug 27 11:51:55 AM UTC 24 |
| Peak memory | 374224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2933996080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl _throughput_w_partial_write.2933996080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/45.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.3927650633 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 1100083591 ps |
| CPU time | 14.64 seconds |
| Started | Aug 27 11:53:55 AM UTC 24 |
| Finished | Aug 27 11:54:10 AM UTC 24 |
| Peak memory | 211648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927650633 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_access_duri ng_key_req.3927650633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/46.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_alert_test.287401694 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 13858720 ps |
| CPU time | 1.01 seconds |
| Started | Aug 27 11:54:29 AM UTC 24 |
| Finished | Aug 27 11:54:31 AM UTC 24 |
| Peak memory | 210872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287401694 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_alert_test.287401694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/46.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_bijection.2973716082 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 201393745900 ps |
| CPU time | 2136.21 seconds |
| Started | Aug 27 11:52:25 AM UTC 24 |
| Finished | Aug 27 12:28:23 PM UTC 24 |
| Peak memory | 213236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973716082 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection.2973716082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/46.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_executable.2120962705 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 7997171706 ps |
| CPU time | 494.55 seconds |
| Started | Aug 27 11:54:00 AM UTC 24 |
| Finished | Aug 27 12:02:20 PM UTC 24 |
| Peak memory | 384540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120962705 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executable.2120962705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/46.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.728564702 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 5084305896 ps |
| CPU time | 62.64 seconds |
| Started | Aug 27 11:53:33 AM UTC 24 |
| Finished | Aug 27 11:54:37 AM UTC 24 |
| Peak memory | 221808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728564702 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_escalation.728564702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/46.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.3099059646 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 1123142595 ps |
| CPU time | 79.06 seconds |
| Started | Aug 27 11:53:08 AM UTC 24 |
| Finished | Aug 27 11:54:29 AM UTC 24 |
| Peak memory | 366196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3099059646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ max_throughput.3099059646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/46.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.1621478140 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 48560452309 ps |
| CPU time | 234.48 seconds |
| Started | Aug 27 11:54:11 AM UTC 24 |
| Finished | Aug 27 11:58:09 AM UTC 24 |
| Peak memory | 221856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621478140 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_mem_partial_access.1621478140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/46.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.1854349472 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 7131401990 ps |
| CPU time | 186.75 seconds |
| Started | Aug 27 11:54:11 AM UTC 24 |
| Finished | Aug 27 11:57:21 AM UTC 24 |
| Peak memory | 221812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854349472 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_mem_walk.1854349472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/46.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access.1818609027 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 5693215443 ps |
| CPU time | 31.69 seconds |
| Started | Aug 27 11:52:58 AM UTC 24 |
| Finished | Aug 27 11:53:31 AM UTC 24 |
| Peak memory | 211608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818609027 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_partial_access.1818609027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/46.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.2057591937 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 35256126229 ps |
| CPU time | 796.8 seconds |
| Started | Aug 27 11:53:06 AM UTC 24 |
| Finished | Aug 27 12:06:33 PM UTC 24 |
| Peak memory | 211496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057591937 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_partial_a ccess_b2b.2057591937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/46.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.2921683411 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 1364481774 ps |
| CPU time | 4.94 seconds |
| Started | Aug 27 11:54:04 AM UTC 24 |
| Finished | Aug 27 11:54:10 AM UTC 24 |
| Peak memory | 211840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921683411 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.2921683411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/46.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_regwen.3379593806 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 3954477841 ps |
| CPU time | 744.35 seconds |
| Started | Aug 27 11:54:00 AM UTC 24 |
| Finished | Aug 27 12:06:33 PM UTC 24 |
| Peak memory | 380568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379593806 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.3379593806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/46.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_smoke.1286722857 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 2273824059 ps |
| CPU time | 22.18 seconds |
| Started | Aug 27 11:52:13 AM UTC 24 |
| Finished | Aug 27 11:52:37 AM UTC 24 |
| Peak memory | 263644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286722857 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.1286722857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/46.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all.1417551260 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 37160766638 ps |
| CPU time | 2695.38 seconds |
| Started | Aug 27 11:54:13 AM UTC 24 |
| Finished | Aug 27 12:39:37 PM UTC 24 |
| Peak memory | 388284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14175512 60 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_a ll.1417551260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/46.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2749987152 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 2535118016 ps |
| CPU time | 13.56 seconds |
| Started | Aug 27 11:54:12 AM UTC 24 |
| Finished | Aug 27 11:54:27 AM UTC 24 |
| Peak memory | 221924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749987152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.2749987152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/46.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.3982964238 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 2681347403 ps |
| CPU time | 265.23 seconds |
| Started | Aug 27 11:52:38 AM UTC 24 |
| Finished | Aug 27 11:57:07 AM UTC 24 |
| Peak memory | 211556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982964238 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_pipeline.3982964238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/46.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.1265082973 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 1328841163 ps |
| CPU time | 38.24 seconds |
| Started | Aug 27 11:53:19 AM UTC 24 |
| Finished | Aug 27 11:53:59 AM UTC 24 |
| Peak memory | 300508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1265082973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl _throughput_w_partial_write.1265082973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/46.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.3890918557 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 26907292057 ps |
| CPU time | 570.89 seconds |
| Started | Aug 27 11:57:08 AM UTC 24 |
| Finished | Aug 27 12:06:46 PM UTC 24 |
| Peak memory | 351760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890918557 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_access_duri ng_key_req.3890918557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/47.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_alert_test.3605281597 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 15116749 ps |
| CPU time | 1.01 seconds |
| Started | Aug 27 11:58:10 AM UTC 24 |
| Finished | Aug 27 11:58:12 AM UTC 24 |
| Peak memory | 210876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605281597 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_alert_test.3605281597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/47.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_bijection.1302068708 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 30491319456 ps |
| CPU time | 2562.39 seconds |
| Started | Aug 27 11:54:32 AM UTC 24 |
| Finished | Aug 27 12:37:44 PM UTC 24 |
| Peak memory | 213296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302068708 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection.1302068708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/47.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_executable.3081662374 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 52678981311 ps |
| CPU time | 685.43 seconds |
| Started | Aug 27 11:57:21 AM UTC 24 |
| Finished | Aug 27 12:08:55 PM UTC 24 |
| Peak memory | 386608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081662374 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executable.3081662374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/47.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.1401407639 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 34873457720 ps |
| CPU time | 172.75 seconds |
| Started | Aug 27 11:56:20 AM UTC 24 |
| Finished | Aug 27 11:59:16 AM UTC 24 |
| Peak memory | 222008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401407639 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_escalation.1401407639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/47.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.805288759 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 2684852733 ps |
| CPU time | 18.94 seconds |
| Started | Aug 27 11:55:44 AM UTC 24 |
| Finished | Aug 27 11:56:04 AM UTC 24 |
| Peak memory | 251556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 805288759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_m ax_throughput.805288759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/47.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.4146338731 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 6303435566 ps |
| CPU time | 137.48 seconds |
| Started | Aug 27 11:57:37 AM UTC 24 |
| Finished | Aug 27 11:59:57 AM UTC 24 |
| Peak memory | 228960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146338731 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_mem_partial_access.4146338731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/47.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.2462247280 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 5975219683 ps |
| CPU time | 144.31 seconds |
| Started | Aug 27 11:57:35 AM UTC 24 |
| Finished | Aug 27 12:00:02 PM UTC 24 |
| Peak memory | 221884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462247280 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_mem_walk.2462247280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/47.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_multiple_keys.1423941226 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 67978050730 ps |
| CPU time | 793.71 seconds |
| Started | Aug 27 11:54:31 AM UTC 24 |
| Finished | Aug 27 12:07:53 PM UTC 24 |
| Peak memory | 386724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423941226 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multiple_keys.1423941226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/47.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access.326357215 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 4810548617 ps |
| CPU time | 48.02 seconds |
| Started | Aug 27 11:54:52 AM UTC 24 |
| Finished | Aug 27 11:55:42 AM UTC 24 |
| Peak memory | 304796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326357215 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_partial_access.326357215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/47.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.337879622 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 81322755066 ps |
| CPU time | 537.04 seconds |
| Started | Aug 27 11:55:43 AM UTC 24 |
| Finished | Aug 27 12:04:46 PM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337879622 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_partial_ac cess_b2b.337879622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/47.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.3705157658 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 354205181 ps |
| CPU time | 4.7 seconds |
| Started | Aug 27 11:57:31 AM UTC 24 |
| Finished | Aug 27 11:57:36 AM UTC 24 |
| Peak memory | 211644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705157658 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.3705157658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/47.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_regwen.3349847017 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 1475767482 ps |
| CPU time | 105.3 seconds |
| Started | Aug 27 11:57:28 AM UTC 24 |
| Finished | Aug 27 11:59:15 AM UTC 24 |
| Peak memory | 384424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349847017 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.3349847017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/47.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_smoke.319673816 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 900562478 ps |
| CPU time | 71.57 seconds |
| Started | Aug 27 11:54:30 AM UTC 24 |
| Finished | Aug 27 11:55:43 AM UTC 24 |
| Peak memory | 362064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319673816 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.319673816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/47.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all.1011293867 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 449172341824 ps |
| CPU time | 5990.36 seconds |
| Started | Aug 27 11:58:04 AM UTC 24 |
| Finished | Aug 27 01:38:59 PM UTC 24 |
| Peak memory | 398440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10112938 67 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_a ll.1011293867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/47.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.21436148 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 1936259146 ps |
| CPU time | 21.81 seconds |
| Started | Aug 27 11:58:03 AM UTC 24 |
| Finished | Aug 27 11:58:26 AM UTC 24 |
| Peak memory | 221940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21436148 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.21436148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/47.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.1802736508 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 4942848727 ps |
| CPU time | 385.84 seconds |
| Started | Aug 27 11:54:38 AM UTC 24 |
| Finished | Aug 27 12:01:09 PM UTC 24 |
| Peak memory | 211820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802736508 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_pipeline.1802736508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/47.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.26060752 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 2982444255 ps |
| CPU time | 12.98 seconds |
| Started | Aug 27 11:56:05 AM UTC 24 |
| Finished | Aug 27 11:56:19 AM UTC 24 |
| Peak memory | 228132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =26060752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_t hroughput_w_partial_write.26060752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/47.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.4199837785 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 12643210505 ps |
| CPU time | 475.61 seconds |
| Started | Aug 27 11:59:13 AM UTC 24 |
| Finished | Aug 27 12:07:14 PM UTC 24 |
| Peak memory | 358112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199837785 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_access_duri ng_key_req.4199837785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/48.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_alert_test.4010286002 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 16366015 ps |
| CPU time | 0.95 seconds |
| Started | Aug 27 12:01:11 PM UTC 24 |
| Finished | Aug 27 12:01:13 PM UTC 24 |
| Peak memory | 210736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010286002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_alert_test.4010286002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/48.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_bijection.1416452950 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 60001593178 ps |
| CPU time | 1496.94 seconds |
| Started | Aug 27 11:58:19 AM UTC 24 |
| Finished | Aug 27 12:23:33 PM UTC 24 |
| Peak memory | 213244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416452950 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection.1416452950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/48.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_executable.2249418214 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 58237487723 ps |
| CPU time | 419.89 seconds |
| Started | Aug 27 11:59:15 AM UTC 24 |
| Finished | Aug 27 12:06:20 PM UTC 24 |
| Peak memory | 380384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249418214 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executable.2249418214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/48.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.2695334524 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 1300527038 ps |
| CPU time | 14.93 seconds |
| Started | Aug 27 11:59:08 AM UTC 24 |
| Finished | Aug 27 11:59:24 AM UTC 24 |
| Peak memory | 222012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695334524 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_escalation.2695334524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/48.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.3885659404 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 747095704 ps |
| CPU time | 26.99 seconds |
| Started | Aug 27 11:58:39 AM UTC 24 |
| Finished | Aug 27 11:59:07 AM UTC 24 |
| Peak memory | 279968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3885659404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ max_throughput.3885659404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/48.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.2838868308 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 1471695653 ps |
| CPU time | 89.73 seconds |
| Started | Aug 27 11:59:58 AM UTC 24 |
| Finished | Aug 27 12:01:30 PM UTC 24 |
| Peak memory | 221948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838868308 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_mem_partial_access.2838868308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/48.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.3467690163 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 24700783224 ps |
| CPU time | 258.19 seconds |
| Started | Aug 27 11:59:33 AM UTC 24 |
| Finished | Aug 27 12:03:55 PM UTC 24 |
| Peak memory | 221948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467690163 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_mem_walk.3467690163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/48.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.2791240164 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 18662368158 ps |
| CPU time | 587 seconds |
| Started | Aug 27 11:58:13 AM UTC 24 |
| Finished | Aug 27 12:08:08 PM UTC 24 |
| Peak memory | 382444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791240164 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multiple_keys.2791240164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/48.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access.2460373298 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 536421352 ps |
| CPU time | 9.72 seconds |
| Started | Aug 27 11:58:27 AM UTC 24 |
| Finished | Aug 27 11:58:38 AM UTC 24 |
| Peak memory | 226780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460373298 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_partial_access.2460373298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/48.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.3076803766 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 10068653329 ps |
| CPU time | 336.14 seconds |
| Started | Aug 27 11:58:35 AM UTC 24 |
| Finished | Aug 27 12:04:16 PM UTC 24 |
| Peak memory | 211552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076803766 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_partial_a ccess_b2b.3076803766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/48.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.2923196187 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 360681151 ps |
| CPU time | 5.43 seconds |
| Started | Aug 27 11:59:26 AM UTC 24 |
| Finished | Aug 27 11:59:32 AM UTC 24 |
| Peak memory | 211716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923196187 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.2923196187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/48.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_regwen.259481538 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 14552689118 ps |
| CPU time | 481.56 seconds |
| Started | Aug 27 11:59:17 AM UTC 24 |
| Finished | Aug 27 12:07:24 PM UTC 24 |
| Peak memory | 386524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259481538 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.259481538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/48.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_smoke.1429771370 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 1411186991 ps |
| CPU time | 5.48 seconds |
| Started | Aug 27 11:58:12 AM UTC 24 |
| Finished | Aug 27 11:58:19 AM UTC 24 |
| Peak memory | 211496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429771370 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.1429771370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/48.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all.3988317457 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 1690857934626 ps |
| CPU time | 8358.52 seconds |
| Started | Aug 27 12:00:07 PM UTC 24 |
| Finished | Aug 27 02:20:52 PM UTC 24 |
| Peak memory | 392304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39883174 57 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_a ll.3988317457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/48.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.2268057606 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 15196694146 ps |
| CPU time | 86.74 seconds |
| Started | Aug 27 12:00:02 PM UTC 24 |
| Finished | Aug 27 12:01:34 PM UTC 24 |
| Peak memory | 226172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268057606 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.2268057606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/48.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.2256329133 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 9385689742 ps |
| CPU time | 301.06 seconds |
| Started | Aug 27 11:58:24 AM UTC 24 |
| Finished | Aug 27 12:03:29 PM UTC 24 |
| Peak memory | 211648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256329133 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_pipeline.2256329133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/48.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.493324921 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 2956317554 ps |
| CPU time | 25.23 seconds |
| Started | Aug 27 11:58:46 AM UTC 24 |
| Finished | Aug 27 11:59:13 AM UTC 24 |
| Peak memory | 269868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =493324921 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ throughput_w_partial_write.493324921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/48.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.2639676706 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 31847847647 ps |
| CPU time | 507.18 seconds |
| Started | Aug 27 12:02:22 PM UTC 24 |
| Finished | Aug 27 12:10:55 PM UTC 24 |
| Peak memory | 388644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639676706 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_access_duri ng_key_req.2639676706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/49.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_alert_test.2794506139 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 39666986 ps |
| CPU time | 1 seconds |
| Started | Aug 27 12:04:17 PM UTC 24 |
| Finished | Aug 27 12:04:19 PM UTC 24 |
| Peak memory | 210816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794506139 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_alert_test.2794506139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/49.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_bijection.28290647 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 99956153473 ps |
| CPU time | 2287.77 seconds |
| Started | Aug 27 12:01:16 PM UTC 24 |
| Finished | Aug 27 12:39:48 PM UTC 24 |
| Peak memory | 213252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28290647 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection.28290647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/49.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_executable.3954088863 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 36925705066 ps |
| CPU time | 1020.59 seconds |
| Started | Aug 27 12:02:23 PM UTC 24 |
| Finished | Aug 27 12:19:34 PM UTC 24 |
| Peak memory | 388744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954088863 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executable.3954088863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/49.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.3808341915 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 3633021475 ps |
| CPU time | 11.85 seconds |
| Started | Aug 27 12:02:21 PM UTC 24 |
| Finished | Aug 27 12:02:34 PM UTC 24 |
| Peak memory | 221544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808341915 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_escalation.3808341915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/49.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.675693482 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 761491249 ps |
| CPU time | 50.93 seconds |
| Started | Aug 27 12:01:37 PM UTC 24 |
| Finished | Aug 27 12:02:30 PM UTC 24 |
| Peak memory | 370144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 675693482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_m ax_throughput.675693482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/49.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.3282694915 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 29139729554 ps |
| CPU time | 85.95 seconds |
| Started | Aug 27 12:03:30 PM UTC 24 |
| Finished | Aug 27 12:04:58 PM UTC 24 |
| Peak memory | 223912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282694915 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_mem_partial_access.3282694915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/49.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.1990502335 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 9399059501 ps |
| CPU time | 140.44 seconds |
| Started | Aug 27 12:02:41 PM UTC 24 |
| Finished | Aug 27 12:05:04 PM UTC 24 |
| Peak memory | 221952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990502335 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_mem_walk.1990502335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/49.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.3542909275 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 24561081152 ps |
| CPU time | 1303.81 seconds |
| Started | Aug 27 12:01:14 PM UTC 24 |
| Finished | Aug 27 12:23:12 PM UTC 24 |
| Peak memory | 388280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542909275 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multiple_keys.3542909275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/49.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access.4233574253 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 3992533498 ps |
| CPU time | 10.62 seconds |
| Started | Aug 27 12:01:35 PM UTC 24 |
| Finished | Aug 27 12:01:47 PM UTC 24 |
| Peak memory | 217768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233574253 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_partial_access.4233574253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/49.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.3545811685 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 31828837596 ps |
| CPU time | 261.2 seconds |
| Started | Aug 27 12:01:35 PM UTC 24 |
| Finished | Aug 27 12:06:01 PM UTC 24 |
| Peak memory | 211632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545811685 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_partial_a ccess_b2b.3545811685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/49.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.4011036116 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 345716959 ps |
| CPU time | 5.61 seconds |
| Started | Aug 27 12:02:34 PM UTC 24 |
| Finished | Aug 27 12:02:41 PM UTC 24 |
| Peak memory | 211716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011036116 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.4011036116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/49.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_regwen.351554019 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 74030412344 ps |
| CPU time | 560.29 seconds |
| Started | Aug 27 12:02:31 PM UTC 24 |
| Finished | Aug 27 12:11:58 PM UTC 24 |
| Peak memory | 386724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351554019 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.351554019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/49.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_smoke.1099804362 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 488920395 ps |
| CPU time | 20.92 seconds |
| Started | Aug 27 12:01:12 PM UTC 24 |
| Finished | Aug 27 12:01:34 PM UTC 24 |
| Peak memory | 211488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099804362 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.1099804362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/49.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all.3732793675 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 152360147389 ps |
| CPU time | 1976.48 seconds |
| Started | Aug 27 12:03:56 PM UTC 24 |
| Finished | Aug 27 12:37:13 PM UTC 24 |
| Peak memory | 351408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37327936 75 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_a ll.3732793675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/49.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3021802523 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 1038314454 ps |
| CPU time | 32.37 seconds |
| Started | Aug 27 12:03:52 PM UTC 24 |
| Finished | Aug 27 12:04:26 PM UTC 24 |
| Peak memory | 221856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021802523 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.3021802523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/49.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.4086271413 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 5089427707 ps |
| CPU time | 391.89 seconds |
| Started | Aug 27 12:01:31 PM UTC 24 |
| Finished | Aug 27 12:08:08 PM UTC 24 |
| Peak memory | 211644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086271413 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_pipeline.4086271413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/49.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.3898309938 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 740233088 ps |
| CPU time | 32.13 seconds |
| Started | Aug 27 12:01:47 PM UTC 24 |
| Finished | Aug 27 12:02:21 PM UTC 24 |
| Peak memory | 288164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3898309938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl _throughput_w_partial_write.3898309938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/49.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.3015287330 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 26406815340 ps |
| CPU time | 577.38 seconds |
| Started | Aug 27 09:30:57 AM UTC 24 |
| Finished | Aug 27 09:40:41 AM UTC 24 |
| Peak memory | 386500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015287330 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_access_durin g_key_req.3015287330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/5.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_alert_test.2198808021 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 15052358 ps |
| CPU time | 1.06 seconds |
| Started | Aug 27 09:32:24 AM UTC 24 |
| Finished | Aug 27 09:32:26 AM UTC 24 |
| Peak memory | 210872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198808021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_alert_test.2198808021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/5.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_bijection.2439493364 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 69195506592 ps |
| CPU time | 1313.78 seconds |
| Started | Aug 27 09:29:36 AM UTC 24 |
| Finished | Aug 27 09:51:44 AM UTC 24 |
| Peak memory | 211572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439493364 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.2439493364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/5.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_executable.1785863792 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 10136156944 ps |
| CPU time | 391.11 seconds |
| Started | Aug 27 09:31:01 AM UTC 24 |
| Finished | Aug 27 09:37:37 AM UTC 24 |
| Peak memory | 386516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785863792 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executable.1785863792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/5.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.2435255794 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 32538106872 ps |
| CPU time | 77.32 seconds |
| Started | Aug 27 09:30:36 AM UTC 24 |
| Finished | Aug 27 09:31:55 AM UTC 24 |
| Peak memory | 211556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435255794 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_escalation.2435255794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/5.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.2660850884 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 2784827156 ps |
| CPU time | 15.58 seconds |
| Started | Aug 27 09:30:19 AM UTC 24 |
| Finished | Aug 27 09:30:36 AM UTC 24 |
| Peak memory | 232924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2660850884 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_m ax_throughput.2660850884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/5.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.535896960 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 11184455277 ps |
| CPU time | 176.54 seconds |
| Started | Aug 27 09:31:35 AM UTC 24 |
| Finished | Aug 27 09:34:34 AM UTC 24 |
| Peak memory | 228816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535896960 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_mem_partial_access.535896960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/5.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.518278694 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 14150583969 ps |
| CPU time | 224.42 seconds |
| Started | Aug 27 09:31:19 AM UTC 24 |
| Finished | Aug 27 09:35:07 AM UTC 24 |
| Peak memory | 221876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518278694 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_mem_walk.518278694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/5.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.3994880437 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 5881205175 ps |
| CPU time | 121.85 seconds |
| Started | Aug 27 09:29:30 AM UTC 24 |
| Finished | Aug 27 09:31:34 AM UTC 24 |
| Peak memory | 366116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994880437 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multiple_keys.3994880437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/5.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access.770146776 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 1758309458 ps |
| CPU time | 20.75 seconds |
| Started | Aug 27 09:29:46 AM UTC 24 |
| Finished | Aug 27 09:30:09 AM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770146776 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_partial_access.770146776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/5.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.721413803 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 14731254968 ps |
| CPU time | 393.11 seconds |
| Started | Aug 27 09:30:09 AM UTC 24 |
| Finished | Aug 27 09:36:48 AM UTC 24 |
| Peak memory | 211568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721413803 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_partial_acc ess_b2b.721413803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/5.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.784911170 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 1862148305 ps |
| CPU time | 5.68 seconds |
| Started | Aug 27 09:31:10 AM UTC 24 |
| Finished | Aug 27 09:31:17 AM UTC 24 |
| Peak memory | 211632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784911170 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.784911170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/5.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_regwen.3183667824 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 29459332208 ps |
| CPU time | 1058.35 seconds |
| Started | Aug 27 09:31:05 AM UTC 24 |
| Finished | Aug 27 09:48:56 AM UTC 24 |
| Peak memory | 390704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183667824 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.3183667824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/5.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_smoke.4191100561 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 1369233433 ps |
| CPU time | 11.21 seconds |
| Started | Aug 27 09:29:28 AM UTC 24 |
| Finished | Aug 27 09:29:40 AM UTC 24 |
| Peak memory | 211300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191100561 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.4191100561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/5.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all.2337868370 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 603293794317 ps |
| CPU time | 5426.45 seconds |
| Started | Aug 27 09:31:56 AM UTC 24 |
| Finished | Aug 27 11:03:17 AM UTC 24 |
| Peak memory | 392352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23378683 70 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all.2337868370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/5.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.74654059 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 10943626107 ps |
| CPU time | 373.24 seconds |
| Started | Aug 27 09:29:41 AM UTC 24 |
| Finished | Aug 27 09:35:59 AM UTC 24 |
| Peak memory | 211584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74654059 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_pipeline.74654059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/5.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.2662322735 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 2717418469 ps |
| CPU time | 33.75 seconds |
| Started | Aug 27 09:30:29 AM UTC 24 |
| Finished | Aug 27 09:31:04 AM UTC 24 |
| Peak memory | 302548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2662322735 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ throughput_w_partial_write.2662322735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/5.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.2078623273 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 13940345722 ps |
| CPU time | 781.78 seconds |
| Started | Aug 27 09:34:33 AM UTC 24 |
| Finished | Aug 27 09:47:44 AM UTC 24 |
| Peak memory | 382420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078623273 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_access_durin g_key_req.2078623273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/6.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_alert_test.837429397 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 32717571 ps |
| CPU time | 1.01 seconds |
| Started | Aug 27 09:35:33 AM UTC 24 |
| Finished | Aug 27 09:35:35 AM UTC 24 |
| Peak memory | 210736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837429397 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_alert_test.837429397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/6.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_bijection.2776458878 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 23304232807 ps |
| CPU time | 653.55 seconds |
| Started | Aug 27 09:32:39 AM UTC 24 |
| Finished | Aug 27 09:43:41 AM UTC 24 |
| Peak memory | 211564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776458878 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.2776458878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/6.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_executable.1023294574 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 63014908022 ps |
| CPU time | 567.44 seconds |
| Started | Aug 27 09:34:35 AM UTC 24 |
| Finished | Aug 27 09:44:09 AM UTC 24 |
| Peak memory | 364060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023294574 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executable.1023294574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/6.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.2394232380 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 13570616365 ps |
| CPU time | 161.41 seconds |
| Started | Aug 27 09:34:09 AM UTC 24 |
| Finished | Aug 27 09:36:53 AM UTC 24 |
| Peak memory | 221804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394232380 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_escalation.2394232380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/6.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.4102940417 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 3594478394 ps |
| CPU time | 91.57 seconds |
| Started | Aug 27 09:33:46 AM UTC 24 |
| Finished | Aug 27 09:35:19 AM UTC 24 |
| Peak memory | 368164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4102940417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_m ax_throughput.4102940417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/6.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.2525547957 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 42724366976 ps |
| CPU time | 186.06 seconds |
| Started | Aug 27 09:35:14 AM UTC 24 |
| Finished | Aug 27 09:38:23 AM UTC 24 |
| Peak memory | 221952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525547957 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_mem_partial_access.2525547957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/6.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.4080145115 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 21336353148 ps |
| CPU time | 519.56 seconds |
| Started | Aug 27 09:35:08 AM UTC 24 |
| Finished | Aug 27 09:43:54 AM UTC 24 |
| Peak memory | 221808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080145115 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_mem_walk.4080145115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/6.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.1332205246 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 80171013257 ps |
| CPU time | 1015.1 seconds |
| Started | Aug 27 09:32:27 AM UTC 24 |
| Finished | Aug 27 09:49:34 AM UTC 24 |
| Peak memory | 380576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332205246 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multiple_keys.1332205246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/6.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access.3309504777 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 1008921486 ps |
| CPU time | 16.44 seconds |
| Started | Aug 27 09:33:16 AM UTC 24 |
| Finished | Aug 27 09:33:33 AM UTC 24 |
| Peak memory | 211676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309504777 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_partial_access.3309504777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/6.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.2353045637 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 22880697463 ps |
| CPU time | 703.98 seconds |
| Started | Aug 27 09:33:34 AM UTC 24 |
| Finished | Aug 27 09:45:26 AM UTC 24 |
| Peak memory | 211548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353045637 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_partial_ac cess_b2b.2353045637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/6.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.1996497270 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 705561661 ps |
| CPU time | 6.3 seconds |
| Started | Aug 27 09:35:05 AM UTC 24 |
| Finished | Aug 27 09:35:13 AM UTC 24 |
| Peak memory | 211632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996497270 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.1996497270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/6.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_regwen.1628342877 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 3556827505 ps |
| CPU time | 637.59 seconds |
| Started | Aug 27 09:34:45 AM UTC 24 |
| Finished | Aug 27 09:45:31 AM UTC 24 |
| Peak memory | 386504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628342877 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.1628342877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/6.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_smoke.3315622674 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 3736517879 ps |
| CPU time | 97.44 seconds |
| Started | Aug 27 09:32:25 AM UTC 24 |
| Finished | Aug 27 09:34:05 AM UTC 24 |
| Peak memory | 374228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315622674 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.3315622674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/6.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all.401520384 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 49070225519 ps |
| CPU time | 1904.19 seconds |
| Started | Aug 27 09:35:31 AM UTC 24 |
| Finished | Aug 27 10:07:34 AM UTC 24 |
| Peak memory | 390240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40152038 4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all.401520384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/6.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.605699543 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 1179632000 ps |
| CPU time | 48.69 seconds |
| Started | Aug 27 09:35:20 AM UTC 24 |
| Finished | Aug 27 09:36:10 AM UTC 24 |
| Peak memory | 221872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605699543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.605699543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/6.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.2890150704 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 18046379031 ps |
| CPU time | 322.92 seconds |
| Started | Aug 27 09:33:13 AM UTC 24 |
| Finished | Aug 27 09:38:41 AM UTC 24 |
| Peak memory | 211708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890150704 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_pipeline.2890150704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/6.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.3816999863 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 747123469 ps |
| CPU time | 37.67 seconds |
| Started | Aug 27 09:34:06 AM UTC 24 |
| Finished | Aug 27 09:34:45 AM UTC 24 |
| Peak memory | 310700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3816999863 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ throughput_w_partial_write.3816999863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/6.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.3111638074 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 37803018779 ps |
| CPU time | 1318.01 seconds |
| Started | Aug 27 09:37:38 AM UTC 24 |
| Finished | Aug 27 09:59:50 AM UTC 24 |
| Peak memory | 388612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111638074 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_access_durin g_key_req.3111638074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/7.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_alert_test.3223909849 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 34658714 ps |
| CPU time | 1.05 seconds |
| Started | Aug 27 09:38:41 AM UTC 24 |
| Finished | Aug 27 09:38:43 AM UTC 24 |
| Peak memory | 210812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223909849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_alert_test.3223909849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/7.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_bijection.1524013445 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 85553217461 ps |
| CPU time | 1511.95 seconds |
| Started | Aug 27 09:36:00 AM UTC 24 |
| Finished | Aug 27 10:01:28 AM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524013445 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.1524013445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/7.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_executable.2451184021 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 16367432066 ps |
| CPU time | 702.19 seconds |
| Started | Aug 27 09:37:40 AM UTC 24 |
| Finished | Aug 27 09:49:30 AM UTC 24 |
| Peak memory | 384472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451184021 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executable.2451184021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/7.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.1793910079 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 2883419857 ps |
| CPU time | 23.7 seconds |
| Started | Aug 27 09:37:13 AM UTC 24 |
| Finished | Aug 27 09:37:38 AM UTC 24 |
| Peak memory | 225988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793910079 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_escalation.1793910079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/7.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.2489605666 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 3199847927 ps |
| CPU time | 82.63 seconds |
| Started | Aug 27 09:36:54 AM UTC 24 |
| Finished | Aug 27 09:38:19 AM UTC 24 |
| Peak memory | 380384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2489605666 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_m ax_throughput.2489605666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/7.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.4159896199 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 10865248274 ps |
| CPU time | 151.11 seconds |
| Started | Aug 27 09:38:20 AM UTC 24 |
| Finished | Aug 27 09:40:54 AM UTC 24 |
| Peak memory | 221952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159896199 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_mem_partial_access.4159896199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/7.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.1389464225 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 28789888735 ps |
| CPU time | 379.61 seconds |
| Started | Aug 27 09:38:05 AM UTC 24 |
| Finished | Aug 27 09:44:30 AM UTC 24 |
| Peak memory | 222076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389464225 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_mem_walk.1389464225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/7.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.178162618 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 21115305574 ps |
| CPU time | 1376.3 seconds |
| Started | Aug 27 09:35:47 AM UTC 24 |
| Finished | Aug 27 09:58:58 AM UTC 24 |
| Peak memory | 386844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178162618 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multiple_keys.178162618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/7.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access.777890033 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 611079881 ps |
| CPU time | 19.14 seconds |
| Started | Aug 27 09:36:41 AM UTC 24 |
| Finished | Aug 27 09:37:02 AM UTC 24 |
| Peak memory | 211592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777890033 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_partial_access.777890033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/7.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.335570919 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 4957191731 ps |
| CPU time | 264.98 seconds |
| Started | Aug 27 09:36:48 AM UTC 24 |
| Finished | Aug 27 09:41:17 AM UTC 24 |
| Peak memory | 211744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335570919 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_partial_acc ess_b2b.335570919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/7.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.2238439207 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 1344187307 ps |
| CPU time | 5.13 seconds |
| Started | Aug 27 09:37:58 AM UTC 24 |
| Finished | Aug 27 09:38:04 AM UTC 24 |
| Peak memory | 211632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238439207 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.2238439207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/7.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_regwen.3863179216 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 41122736102 ps |
| CPU time | 743.7 seconds |
| Started | Aug 27 09:37:42 AM UTC 24 |
| Finished | Aug 27 09:50:13 AM UTC 24 |
| Peak memory | 384472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863179216 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.3863179216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/7.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_smoke.862670098 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 521761659 ps |
| CPU time | 9.01 seconds |
| Started | Aug 27 09:35:36 AM UTC 24 |
| Finished | Aug 27 09:35:46 AM UTC 24 |
| Peak memory | 217644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862670098 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.862670098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/7.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all.3716161811 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 11490028817 ps |
| CPU time | 1287.44 seconds |
| Started | Aug 27 09:38:39 AM UTC 24 |
| Finished | Aug 27 10:00:20 AM UTC 24 |
| Peak memory | 386580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37161618 11 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all.3716161811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/7.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.739250126 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 442339763 ps |
| CPU time | 13.67 seconds |
| Started | Aug 27 09:38:23 AM UTC 24 |
| Finished | Aug 27 09:38:38 AM UTC 24 |
| Peak memory | 221876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739250126 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.739250126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/7.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.3999617061 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 58278410388 ps |
| CPU time | 363.4 seconds |
| Started | Aug 27 09:36:11 AM UTC 24 |
| Finished | Aug 27 09:42:19 AM UTC 24 |
| Peak memory | 211572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999617061 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_pipeline.3999617061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/7.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.2288395139 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 4391765714 ps |
| CPU time | 52.84 seconds |
| Started | Aug 27 09:37:02 AM UTC 24 |
| Finished | Aug 27 09:37:57 AM UTC 24 |
| Peak memory | 329176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2288395139 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ throughput_w_partial_write.2288395139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/7.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.2083842485 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 278253958433 ps |
| CPU time | 1328.26 seconds |
| Started | Aug 27 09:40:42 AM UTC 24 |
| Finished | Aug 27 10:03:06 AM UTC 24 |
| Peak memory | 388556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083842485 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_access_durin g_key_req.2083842485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/8.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_alert_test.767811342 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 61740027 ps |
| CPU time | 1 seconds |
| Started | Aug 27 09:42:20 AM UTC 24 |
| Finished | Aug 27 09:42:22 AM UTC 24 |
| Peak memory | 210872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767811342 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_alert_test.767811342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/8.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_bijection.2389649620 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 122301583620 ps |
| CPU time | 2276.26 seconds |
| Started | Aug 27 09:39:23 AM UTC 24 |
| Finished | Aug 27 10:17:44 AM UTC 24 |
| Peak memory | 213240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389649620 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection.2389649620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/8.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_executable.1683812167 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 8987040011 ps |
| CPU time | 628.69 seconds |
| Started | Aug 27 09:40:44 AM UTC 24 |
| Finished | Aug 27 09:51:20 AM UTC 24 |
| Peak memory | 386524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683812167 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executable.1683812167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/8.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.1906602590 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 58821385786 ps |
| CPU time | 160.09 seconds |
| Started | Aug 27 09:40:35 AM UTC 24 |
| Finished | Aug 27 09:43:18 AM UTC 24 |
| Peak memory | 225960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906602590 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_escalation.1906602590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/8.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.77346993 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 2962632343 ps |
| CPU time | 32.42 seconds |
| Started | Aug 27 09:40:01 AM UTC 24 |
| Finished | Aug 27 09:40:35 AM UTC 24 |
| Peak memory | 286376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 77346993 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_max _throughput.77346993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/8.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.2104419772 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 4010301251 ps |
| CPU time | 93.12 seconds |
| Started | Aug 27 09:41:18 AM UTC 24 |
| Finished | Aug 27 09:42:53 AM UTC 24 |
| Peak memory | 228948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104419772 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_mem_partial_access.2104419772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/8.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.2961511271 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 230244819050 ps |
| CPU time | 372.53 seconds |
| Started | Aug 27 09:41:13 AM UTC 24 |
| Finished | Aug 27 09:47:30 AM UTC 24 |
| Peak memory | 221860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961511271 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_mem_walk.2961511271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/8.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.2943986135 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 50932175935 ps |
| CPU time | 242.28 seconds |
| Started | Aug 27 09:38:53 AM UTC 24 |
| Finished | Aug 27 09:42:59 AM UTC 24 |
| Peak memory | 355872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943986135 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multiple_keys.2943986135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/8.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access.3964437365 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 1607691811 ps |
| CPU time | 35.25 seconds |
| Started | Aug 27 09:39:35 AM UTC 24 |
| Finished | Aug 27 09:40:12 AM UTC 24 |
| Peak memory | 211420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964437365 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_partial_access.3964437365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/8.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.3332191716 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 7286315322 ps |
| CPU time | 558.47 seconds |
| Started | Aug 27 09:39:49 AM UTC 24 |
| Finished | Aug 27 09:49:14 AM UTC 24 |
| Peak memory | 211632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332191716 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_partial_ac cess_b2b.3332191716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/8.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.2741632406 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 1409629638 ps |
| CPU time | 5.22 seconds |
| Started | Aug 27 09:41:11 AM UTC 24 |
| Finished | Aug 27 09:41:17 AM UTC 24 |
| Peak memory | 211632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741632406 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.2741632406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/8.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_regwen.2878178083 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 9628349214 ps |
| CPU time | 98.11 seconds |
| Started | Aug 27 09:40:54 AM UTC 24 |
| Finished | Aug 27 09:42:35 AM UTC 24 |
| Peak memory | 325140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878178083 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.2878178083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/8.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_smoke.672227956 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 1694251846 ps |
| CPU time | 7.57 seconds |
| Started | Aug 27 09:38:44 AM UTC 24 |
| Finished | Aug 27 09:38:53 AM UTC 24 |
| Peak memory | 211548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=672227956 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.672227956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/8.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all.2729861241 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 39228556131 ps |
| CPU time | 2367 seconds |
| Started | Aug 27 09:41:53 AM UTC 24 |
| Finished | Aug 27 10:21:44 AM UTC 24 |
| Peak memory | 398428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27298612 41 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all.2729861241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/8.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.242568802 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 1679000070 ps |
| CPU time | 32.9 seconds |
| Started | Aug 27 09:41:18 AM UTC 24 |
| Finished | Aug 27 09:41:52 AM UTC 24 |
| Peak memory | 222136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242568802 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.242568802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/8.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.4172317299 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 10336324534 ps |
| CPU time | 385.75 seconds |
| Started | Aug 27 09:39:26 AM UTC 24 |
| Finished | Aug 27 09:45:56 AM UTC 24 |
| Peak memory | 211576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172317299 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_pipeline.4172317299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/8.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.3688433504 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 5369996282 ps |
| CPU time | 58.04 seconds |
| Started | Aug 27 09:40:12 AM UTC 24 |
| Finished | Aug 27 09:41:12 AM UTC 24 |
| Peak memory | 339636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3688433504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ throughput_w_partial_write.3688433504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/8.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.1500901137 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 11406518328 ps |
| CPU time | 550.39 seconds |
| Started | Aug 27 09:43:34 AM UTC 24 |
| Finished | Aug 27 09:52:51 AM UTC 24 |
| Peak memory | 378348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500901137 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_access_durin g_key_req.1500901137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/9.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_alert_test.1175625183 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 76925401 ps |
| CPU time | 0.99 seconds |
| Started | Aug 27 09:44:31 AM UTC 24 |
| Finished | Aug 27 09:44:33 AM UTC 24 |
| Peak memory | 208828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175625183 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_alert_test.1175625183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/9.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_bijection.1520566936 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 694073990872 ps |
| CPU time | 1370.35 seconds |
| Started | Aug 27 09:42:35 AM UTC 24 |
| Finished | Aug 27 10:05:41 AM UTC 24 |
| Peak memory | 211564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520566936 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.1520566936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/9.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_executable.2109418018 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 67960576025 ps |
| CPU time | 573.67 seconds |
| Started | Aug 27 09:43:42 AM UTC 24 |
| Finished | Aug 27 09:53:22 AM UTC 24 |
| Peak memory | 378400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109418018 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executable.2109418018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/9.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.791416671 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 1869485838 ps |
| CPU time | 28.18 seconds |
| Started | Aug 27 09:43:24 AM UTC 24 |
| Finished | Aug 27 09:43:53 AM UTC 24 |
| Peak memory | 211696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791416671 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_escalation.791416671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/9.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.3426953654 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 756752482 ps |
| CPU time | 38.97 seconds |
| Started | Aug 27 09:43:17 AM UTC 24 |
| Finished | Aug 27 09:43:57 AM UTC 24 |
| Peak memory | 304740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3426953654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_m ax_throughput.3426953654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/9.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.974116950 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 3615907209 ps |
| CPU time | 75.85 seconds |
| Started | Aug 27 09:44:00 AM UTC 24 |
| Finished | Aug 27 09:45:18 AM UTC 24 |
| Peak memory | 228892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974116950 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_mem_partial_access.974116950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/9.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.92345457 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 7237362453 ps |
| CPU time | 233.38 seconds |
| Started | Aug 27 09:43:57 AM UTC 24 |
| Finished | Aug 27 09:47:55 AM UTC 24 |
| Peak memory | 222064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92345457 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_mem_walk.92345457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/9.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.3106488459 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 42606458230 ps |
| CPU time | 820.52 seconds |
| Started | Aug 27 09:42:30 AM UTC 24 |
| Finished | Aug 27 09:56:20 AM UTC 24 |
| Peak memory | 388656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106488459 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multiple_keys.3106488459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/9.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access.3587988635 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 1292391198 ps |
| CPU time | 20.93 seconds |
| Started | Aug 27 09:42:53 AM UTC 24 |
| Finished | Aug 27 09:43:16 AM UTC 24 |
| Peak memory | 211756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587988635 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_partial_access.3587988635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/9.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.2596323350 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 7986562516 ps |
| CPU time | 252.31 seconds |
| Started | Aug 27 09:43:01 AM UTC 24 |
| Finished | Aug 27 09:47:16 AM UTC 24 |
| Peak memory | 211620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596323350 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_partial_ac cess_b2b.2596323350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/9.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.3030579434 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 1405790999 ps |
| CPU time | 3.98 seconds |
| Started | Aug 27 09:43:54 AM UTC 24 |
| Finished | Aug 27 09:43:59 AM UTC 24 |
| Peak memory | 211624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030579434 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.3030579434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/9.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_regwen.2964738202 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 19172431706 ps |
| CPU time | 784.19 seconds |
| Started | Aug 27 09:43:54 AM UTC 24 |
| Finished | Aug 27 09:57:08 AM UTC 24 |
| Peak memory | 382624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964738202 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.2964738202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/9.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_smoke.4206610689 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 2810784908 ps |
| CPU time | 10.36 seconds |
| Started | Aug 27 09:42:23 AM UTC 24 |
| Finished | Aug 27 09:42:35 AM UTC 24 |
| Peak memory | 213596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206610689 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.4206610689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/9.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all.4047692460 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 67020332039 ps |
| CPU time | 2514.47 seconds |
| Started | Aug 27 09:44:31 AM UTC 24 |
| Finished | Aug 27 10:26:52 AM UTC 24 |
| Peak memory | 390236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40476924 60 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all.4047692460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/9.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.799751603 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 1728616395 ps |
| CPU time | 47.51 seconds |
| Started | Aug 27 09:44:11 AM UTC 24 |
| Finished | Aug 27 09:45:00 AM UTC 24 |
| Peak memory | 221880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799751603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.799751603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/9.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.2644352617 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 12543771306 ps |
| CPU time | 212.45 seconds |
| Started | Aug 27 09:42:35 AM UTC 24 |
| Finished | Aug 27 09:46:12 AM UTC 24 |
| Peak memory | 211644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644352617 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_pipeline.2644352617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/9.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.1363958258 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 2832503005 ps |
| CPU time | 12.89 seconds |
| Started | Aug 27 09:43:19 AM UTC 24 |
| Finished | Aug 27 09:43:33 AM UTC 24 |
| Peak memory | 228008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1363958258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ throughput_w_partial_write.1363958258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sram_ctrl_main-sim-vcs/9.sram_ctrl_throughput_w_partial_write/latest |
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