| T304 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.2993303948 |
|
|
Aug 29 12:50:41 AM UTC 24 |
Aug 29 01:06:23 AM UTC 24 |
24242122182 ps |
| T305 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_bijection.150942489 |
|
|
Aug 29 12:27:22 AM UTC 24 |
Aug 29 01:06:41 AM UTC 24 |
262130320255 ps |
| T306 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.285584287 |
|
|
Aug 29 01:05:38 AM UTC 24 |
Aug 29 01:06:44 AM UTC 24 |
19813439798 ps |
| T307 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.2522658715 |
|
|
Aug 29 01:04:21 AM UTC 24 |
Aug 29 01:06:50 AM UTC 24 |
4981216069 ps |
| T308 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.2147211979 |
|
|
Aug 29 01:06:45 AM UTC 24 |
Aug 29 01:06:52 AM UTC 24 |
714941378 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.2738082544 |
|
|
Aug 29 01:02:00 AM UTC 24 |
Aug 29 01:07:25 AM UTC 24 |
6338433819 ps |
| T310 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_regwen.3450356489 |
|
|
Aug 29 01:06:42 AM UTC 24 |
Aug 29 01:07:27 AM UTC 24 |
747255282 ps |
| T311 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.3694895693 |
|
|
Aug 29 01:05:36 AM UTC 24 |
Aug 29 01:07:30 AM UTC 24 |
3721904781 ps |
| T312 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_alert_test.1017543708 |
|
|
Aug 29 01:07:30 AM UTC 24 |
Aug 29 01:07:33 AM UTC 24 |
15139550 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.2919991169 |
|
|
Aug 29 01:07:26 AM UTC 24 |
Aug 29 01:07:39 AM UTC 24 |
107633251 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_bijection.2821458948 |
|
|
Aug 29 12:27:32 AM UTC 24 |
Aug 29 01:07:41 AM UTC 24 |
64904802058 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all.2550373552 |
|
|
Aug 29 12:45:20 AM UTC 24 |
Aug 29 01:07:50 AM UTC 24 |
80698284269 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_smoke.3889498806 |
|
|
Aug 29 01:07:34 AM UTC 24 |
Aug 29 01:08:05 AM UTC 24 |
2658373356 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.261964742 |
|
|
Aug 29 01:03:07 AM UTC 24 |
Aug 29 01:08:06 AM UTC 24 |
65674410711 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.1121704549 |
|
|
Aug 29 01:01:29 AM UTC 24 |
Aug 29 01:08:24 AM UTC 24 |
14751752120 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_executable.21221465 |
|
|
Aug 29 12:56:03 AM UTC 24 |
Aug 29 01:08:31 AM UTC 24 |
47469423549 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access.3938532967 |
|
|
Aug 29 01:08:06 AM UTC 24 |
Aug 29 01:08:33 AM UTC 24 |
829842235 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.2626446657 |
|
|
Aug 29 01:06:53 AM UTC 24 |
Aug 29 01:08:50 AM UTC 24 |
5116306689 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.3501426059 |
|
|
Aug 29 01:04:57 AM UTC 24 |
Aug 29 01:09:37 AM UTC 24 |
10215028689 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.2323266187 |
|
|
Aug 29 01:08:25 AM UTC 24 |
Aug 29 01:09:59 AM UTC 24 |
2987115708 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.3677210035 |
|
|
Aug 29 01:10:00 AM UTC 24 |
Aug 29 01:10:07 AM UTC 24 |
361204596 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.2550412916 |
|
|
Aug 29 01:08:31 AM UTC 24 |
Aug 29 01:10:14 AM UTC 24 |
3260694291 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.2102536424 |
|
|
Aug 29 01:08:33 AM UTC 24 |
Aug 29 01:10:15 AM UTC 24 |
25946097575 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_regwen.2555868474 |
|
|
Aug 29 12:53:49 AM UTC 24 |
Aug 29 01:10:17 AM UTC 24 |
11596402014 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.1422109344 |
|
|
Aug 29 01:10:15 AM UTC 24 |
Aug 29 01:10:29 AM UTC 24 |
234161385 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_executable.102996042 |
|
|
Aug 29 12:53:20 AM UTC 24 |
Aug 29 01:10:29 AM UTC 24 |
62453662680 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_alert_test.3827664431 |
|
|
Aug 29 01:10:30 AM UTC 24 |
Aug 29 01:10:32 AM UTC 24 |
19340192 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_smoke.3242109657 |
|
|
Aug 29 01:10:30 AM UTC 24 |
Aug 29 01:10:57 AM UTC 24 |
1682696647 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_bijection.144806254 |
|
|
Aug 29 12:45:49 AM UTC 24 |
Aug 29 01:11:29 AM UTC 24 |
66946462795 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_bijection.2295060157 |
|
|
Aug 29 12:55:12 AM UTC 24 |
Aug 29 01:11:50 AM UTC 24 |
97014285765 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.251033853 |
|
|
Aug 29 01:07:51 AM UTC 24 |
Aug 29 01:11:58 AM UTC 24 |
16222450296 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_regwen.1257538250 |
|
|
Aug 29 12:59:36 AM UTC 24 |
Aug 29 01:11:59 AM UTC 24 |
13004084663 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access.1635765783 |
|
|
Aug 29 01:11:51 AM UTC 24 |
Aug 29 01:12:15 AM UTC 24 |
1480748582 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.1719858428 |
|
|
Aug 29 12:56:00 AM UTC 24 |
Aug 29 01:12:19 AM UTC 24 |
35672840968 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.1620799275 |
|
|
Aug 29 01:12:00 AM UTC 24 |
Aug 29 01:12:28 AM UTC 24 |
1417111112 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.2919101020 |
|
|
Aug 29 01:05:07 AM UTC 24 |
Aug 29 01:13:07 AM UTC 24 |
17902045985 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.2979621507 |
|
|
Aug 29 12:57:21 AM UTC 24 |
Aug 29 01:13:11 AM UTC 24 |
66063574500 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.2673758835 |
|
|
Aug 29 12:59:10 AM UTC 24 |
Aug 29 01:13:17 AM UTC 24 |
10586743679 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.4079626708 |
|
|
Aug 29 01:13:18 AM UTC 24 |
Aug 29 01:13:25 AM UTC 24 |
468024967 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.1845012279 |
|
|
Aug 29 01:06:51 AM UTC 24 |
Aug 29 01:13:26 AM UTC 24 |
17942871273 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.2512092673 |
|
|
Aug 29 01:10:14 AM UTC 24 |
Aug 29 01:13:46 AM UTC 24 |
24183983844 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.3594857490 |
|
|
Aug 29 01:12:16 AM UTC 24 |
Aug 29 01:14:06 AM UTC 24 |
11154312715 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_regwen.2778389381 |
|
|
Aug 29 01:02:55 AM UTC 24 |
Aug 29 01:14:25 AM UTC 24 |
14073427621 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_alert_test.2290084051 |
|
|
Aug 29 01:14:26 AM UTC 24 |
Aug 29 01:14:28 AM UTC 24 |
41870475 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.3366122637 |
|
|
Aug 29 01:12:20 AM UTC 24 |
Aug 29 01:14:44 AM UTC 24 |
22924825710 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_smoke.4012626292 |
|
|
Aug 29 01:14:29 AM UTC 24 |
Aug 29 01:14:54 AM UTC 24 |
3357686893 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.1949321013 |
|
|
Aug 29 01:00:59 AM UTC 24 |
Aug 29 01:14:58 AM UTC 24 |
49437623275 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_bijection.1791567612 |
|
|
Aug 29 12:57:34 AM UTC 24 |
Aug 29 01:15:28 AM UTC 24 |
463789556384 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.3082439837 |
|
|
Aug 29 01:10:33 AM UTC 24 |
Aug 29 01:15:32 AM UTC 24 |
72259821171 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.2659235179 |
|
|
Aug 29 01:13:28 AM UTC 24 |
Aug 29 01:15:33 AM UTC 24 |
5356750416 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.3380149803 |
|
|
Aug 29 01:13:47 AM UTC 24 |
Aug 29 01:15:37 AM UTC 24 |
1750015073 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.3584237462 |
|
|
Aug 29 01:08:07 AM UTC 24 |
Aug 29 01:15:52 AM UTC 24 |
13122738417 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.263289599 |
|
|
Aug 29 01:15:38 AM UTC 24 |
Aug 29 01:15:54 AM UTC 24 |
2802778951 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_regwen.1547361908 |
|
|
Aug 29 12:56:11 AM UTC 24 |
Aug 29 01:16:09 AM UTC 24 |
91921976995 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.3820132937 |
|
|
Aug 29 01:15:34 AM UTC 24 |
Aug 29 01:16:05 AM UTC 24 |
738035639 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access.2916639326 |
|
|
Aug 29 01:15:29 AM UTC 24 |
Aug 29 01:16:09 AM UTC 24 |
4860131153 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.614306666 |
|
|
Aug 29 01:16:09 AM UTC 24 |
Aug 29 01:16:17 AM UTC 24 |
353873668 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_executable.2267170733 |
|
|
Aug 29 01:08:58 AM UTC 24 |
Aug 29 01:16:23 AM UTC 24 |
30186301473 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_executable.2660954557 |
|
|
Aug 29 01:02:25 AM UTC 24 |
Aug 29 01:16:39 AM UTC 24 |
14285051083 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.2002745510 |
|
|
Aug 29 01:11:59 AM UTC 24 |
Aug 29 01:16:56 AM UTC 24 |
5389936161 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.3376954384 |
|
|
Aug 29 01:11:30 AM UTC 24 |
Aug 29 01:17:04 AM UTC 24 |
20591945028 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_alert_test.2914148163 |
|
|
Aug 29 01:17:05 AM UTC 24 |
Aug 29 01:17:08 AM UTC 24 |
43899478 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.816408000 |
|
|
Aug 29 12:51:43 AM UTC 24 |
Aug 29 01:17:11 AM UTC 24 |
81037940491 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_executable.2908439298 |
|
|
Aug 29 01:06:25 AM UTC 24 |
Aug 29 01:17:16 AM UTC 24 |
9387840999 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_smoke.3659436704 |
|
|
Aug 29 01:17:08 AM UTC 24 |
Aug 29 01:17:28 AM UTC 24 |
1347531631 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_bijection.1749834000 |
|
|
Aug 29 12:27:24 AM UTC 24 |
Aug 29 01:17:32 AM UTC 24 |
269701116613 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.911262448 |
|
|
Aug 29 01:15:52 AM UTC 24 |
Aug 29 01:17:40 AM UTC 24 |
40653311242 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.2848084876 |
|
|
Aug 29 01:16:40 AM UTC 24 |
Aug 29 01:17:49 AM UTC 24 |
4641271124 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.2630658682 |
|
|
Aug 29 01:05:41 AM UTC 24 |
Aug 29 01:17:54 AM UTC 24 |
37234327732 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.2653573613 |
|
|
Aug 29 01:17:55 AM UTC 24 |
Aug 29 01:18:27 AM UTC 24 |
7919531150 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.1970801673 |
|
|
Aug 29 01:17:50 AM UTC 24 |
Aug 29 01:18:32 AM UTC 24 |
1495490904 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.4263440275 |
|
|
Aug 29 12:53:19 AM UTC 24 |
Aug 29 01:18:55 AM UTC 24 |
20851538288 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.122493793 |
|
|
Aug 29 01:10:08 AM UTC 24 |
Aug 29 01:18:58 AM UTC 24 |
37595896375 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.488378259 |
|
|
Aug 29 01:18:28 AM UTC 24 |
Aug 29 01:19:06 AM UTC 24 |
2589734893 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.988493831 |
|
|
Aug 29 01:19:07 AM UTC 24 |
Aug 29 01:19:13 AM UTC 24 |
354787831 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.92971733 |
|
|
Aug 29 01:13:26 AM UTC 24 |
Aug 29 01:19:18 AM UTC 24 |
21005651686 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access.1865200628 |
|
|
Aug 29 01:17:33 AM UTC 24 |
Aug 29 01:19:22 AM UTC 24 |
3219647964 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.2686233795 |
|
|
Aug 29 01:19:22 AM UTC 24 |
Aug 29 01:19:47 AM UTC 24 |
452546823 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.2944235944 |
|
|
Aug 29 01:16:25 AM UTC 24 |
Aug 29 01:19:51 AM UTC 24 |
17499324806 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_alert_test.349086429 |
|
|
Aug 29 01:19:52 AM UTC 24 |
Aug 29 01:19:54 AM UTC 24 |
13178196 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_bijection.102513357 |
|
|
Aug 29 12:34:27 AM UTC 24 |
Aug 29 01:20:02 AM UTC 24 |
146363433311 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_smoke.2689869742 |
|
|
Aug 29 01:19:55 AM UTC 24 |
Aug 29 01:20:09 AM UTC 24 |
1108846165 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all.2795124308 |
|
|
Aug 29 12:31:42 AM UTC 24 |
Aug 29 01:20:28 AM UTC 24 |
46385837401 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.1313912057 |
|
|
Aug 29 01:16:18 AM UTC 24 |
Aug 29 01:20:39 AM UTC 24 |
43038059597 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_executable.294082134 |
|
|
Aug 29 01:18:56 AM UTC 24 |
Aug 29 01:21:17 AM UTC 24 |
9573044115 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.3972115647 |
|
|
Aug 29 01:15:33 AM UTC 24 |
Aug 29 01:21:30 AM UTC 24 |
13387566896 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.2215557050 |
|
|
Aug 29 01:14:58 AM UTC 24 |
Aug 29 01:21:54 AM UTC 24 |
5414738521 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_bijection.970689572 |
|
|
Aug 29 12:32:05 AM UTC 24 |
Aug 29 01:22:08 AM UTC 24 |
603539467214 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.2881864672 |
|
|
Aug 29 01:21:55 AM UTC 24 |
Aug 29 01:22:09 AM UTC 24 |
1409977765 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.301472744 |
|
|
Aug 29 01:19:19 AM UTC 24 |
Aug 29 01:23:24 AM UTC 24 |
6034036124 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.3636235426 |
|
|
Aug 29 01:21:31 AM UTC 24 |
Aug 29 01:23:27 AM UTC 24 |
798724907 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.2560552059 |
|
|
Aug 29 01:19:13 AM UTC 24 |
Aug 29 01:23:30 AM UTC 24 |
41466623614 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.3127556088 |
|
|
Aug 29 01:23:28 AM UTC 24 |
Aug 29 01:23:35 AM UTC 24 |
3750774855 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.2687235135 |
|
|
Aug 29 01:17:30 AM UTC 24 |
Aug 29 01:23:45 AM UTC 24 |
17754092914 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.2531441002 |
|
|
Aug 29 01:17:41 AM UTC 24 |
Aug 29 01:23:46 AM UTC 24 |
38022056163 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_bijection.61952873 |
|
|
Aug 29 12:51:46 AM UTC 24 |
Aug 29 01:24:08 AM UTC 24 |
50663894346 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.1872021816 |
|
|
Aug 29 01:22:09 AM UTC 24 |
Aug 29 01:24:10 AM UTC 24 |
30934564573 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_alert_test.1494104328 |
|
|
Aug 29 01:24:08 AM UTC 24 |
Aug 29 01:24:10 AM UTC 24 |
34778455 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.202223110 |
|
|
Aug 29 01:08:51 AM UTC 24 |
Aug 29 01:24:18 AM UTC 24 |
14867619146 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_smoke.2475979657 |
|
|
Aug 29 01:24:10 AM UTC 24 |
Aug 29 01:24:48 AM UTC 24 |
1842219927 ps |
| T96 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.2032394287 |
|
|
Aug 29 01:23:36 AM UTC 24 |
Aug 29 01:24:49 AM UTC 24 |
2910142982 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.3316543332 |
|
|
Aug 29 01:20:29 AM UTC 24 |
Aug 29 01:25:00 AM UTC 24 |
5855687336 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access.3748156516 |
|
|
Aug 29 01:24:50 AM UTC 24 |
Aug 29 01:25:25 AM UTC 24 |
2846294374 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_regwen.2689676752 |
|
|
Aug 29 01:19:00 AM UTC 24 |
Aug 29 01:25:33 AM UTC 24 |
3107575647 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.1232504075 |
|
|
Aug 29 01:23:46 AM UTC 24 |
Aug 29 01:25:44 AM UTC 24 |
1457274975 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.1172885855 |
|
|
Aug 29 01:17:11 AM UTC 24 |
Aug 29 01:25:52 AM UTC 24 |
31612835660 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.3622556884 |
|
|
Aug 29 01:25:26 AM UTC 24 |
Aug 29 01:25:54 AM UTC 24 |
8665258989 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.3716938913 |
|
|
Aug 29 01:25:34 AM UTC 24 |
Aug 29 01:26:14 AM UTC 24 |
5618465897 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.1607403714 |
|
|
Aug 29 01:25:45 AM UTC 24 |
Aug 29 01:26:15 AM UTC 24 |
2495926962 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.1652542462 |
|
|
Aug 29 01:26:16 AM UTC 24 |
Aug 29 01:26:22 AM UTC 24 |
5607714769 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_regwen.2682261327 |
|
|
Aug 29 01:26:15 AM UTC 24 |
Aug 29 01:26:39 AM UTC 24 |
496012168 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.1902496559 |
|
|
Aug 29 01:07:40 AM UTC 24 |
Aug 29 01:26:54 AM UTC 24 |
42712707283 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_regwen.583716553 |
|
|
Aug 29 01:13:12 AM UTC 24 |
Aug 29 01:27:01 AM UTC 24 |
11368059040 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.1909867231 |
|
|
Aug 29 01:14:45 AM UTC 24 |
Aug 29 01:27:03 AM UTC 24 |
152061105813 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_alert_test.424080516 |
|
|
Aug 29 01:27:03 AM UTC 24 |
Aug 29 01:27:05 AM UTC 24 |
14443373 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_regwen.2719043821 |
|
|
Aug 29 01:09:38 AM UTC 24 |
Aug 29 01:27:37 AM UTC 24 |
16628129895 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_bijection.921692692 |
|
|
Aug 29 12:49:36 AM UTC 24 |
Aug 29 01:27:43 AM UTC 24 |
501663159574 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.3983939977 |
|
|
Aug 29 01:18:33 AM UTC 24 |
Aug 29 01:28:19 AM UTC 24 |
25994242160 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_bijection.414243033 |
|
|
Aug 29 12:37:52 AM UTC 24 |
Aug 29 01:28:33 AM UTC 24 |
191812832826 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.2423039372 |
|
|
Aug 29 01:26:54 AM UTC 24 |
Aug 29 01:28:36 AM UTC 24 |
8475258342 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_executable.2220543799 |
|
|
Aug 29 01:13:07 AM UTC 24 |
Aug 29 01:28:44 AM UTC 24 |
27152702060 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.3492617540 |
|
|
Aug 29 01:21:18 AM UTC 24 |
Aug 29 01:28:55 AM UTC 24 |
41294361341 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_smoke.272841436 |
|
|
Aug 29 01:27:06 AM UTC 24 |
Aug 29 01:29:02 AM UTC 24 |
3090749688 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.2359810189 |
|
|
Aug 29 01:28:45 AM UTC 24 |
Aug 29 01:29:12 AM UTC 24 |
715499161 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.2858694366 |
|
|
Aug 29 01:28:55 AM UTC 24 |
Aug 29 01:29:14 AM UTC 24 |
6225101559 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access.2950943797 |
|
|
Aug 29 01:28:34 AM UTC 24 |
Aug 29 01:29:17 AM UTC 24 |
1739676845 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_bijection.2568444 |
|
|
Aug 29 01:00:59 AM UTC 24 |
Aug 29 01:29:19 AM UTC 24 |
81234449322 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.278942665 |
|
|
Aug 29 01:29:19 AM UTC 24 |
Aug 29 01:29:25 AM UTC 24 |
1163705381 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.59199131 |
|
|
Aug 29 01:24:49 AM UTC 24 |
Aug 29 01:29:37 AM UTC 24 |
10642866051 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.898679693 |
|
|
Aug 29 01:23:31 AM UTC 24 |
Aug 29 01:29:42 AM UTC 24 |
30725058353 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.1880093587 |
|
|
Aug 29 01:26:40 AM UTC 24 |
Aug 29 01:29:37 AM UTC 24 |
2605204163 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.1450849645 |
|
|
Aug 29 01:26:23 AM UTC 24 |
Aug 29 01:29:50 AM UTC 24 |
21892120786 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_alert_test.4119082300 |
|
|
Aug 29 01:29:51 AM UTC 24 |
Aug 29 01:29:52 AM UTC 24 |
28673139 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.1839078020 |
|
|
Aug 29 01:12:29 AM UTC 24 |
Aug 29 01:29:54 AM UTC 24 |
86977390396 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all.1028068636 |
|
|
Aug 29 12:30:08 AM UTC 24 |
Aug 29 01:30:27 AM UTC 24 |
199819953072 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_smoke.1061549051 |
|
|
Aug 29 01:29:54 AM UTC 24 |
Aug 29 01:31:22 AM UTC 24 |
457938666 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.2578690512 |
|
|
Aug 29 01:29:38 AM UTC 24 |
Aug 29 01:31:35 AM UTC 24 |
1953084295 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.2111262784 |
|
|
Aug 29 01:25:01 AM UTC 24 |
Aug 29 01:31:53 AM UTC 24 |
19587728007 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.956825042 |
|
|
Aug 29 01:29:03 AM UTC 24 |
Aug 29 01:32:01 AM UTC 24 |
13020066069 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_executable.3743215765 |
|
|
Aug 29 01:22:26 AM UTC 24 |
Aug 29 01:32:05 AM UTC 24 |
32543451722 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access.784042308 |
|
|
Aug 29 01:31:36 AM UTC 24 |
Aug 29 01:32:11 AM UTC 24 |
2489999728 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_regwen.656523916 |
|
|
Aug 29 01:16:09 AM UTC 24 |
Aug 29 01:32:18 AM UTC 24 |
12838358758 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.3923838777 |
|
|
Aug 29 01:32:03 AM UTC 24 |
Aug 29 01:32:28 AM UTC 24 |
740765910 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.1624356916 |
|
|
Aug 29 01:32:06 AM UTC 24 |
Aug 29 01:32:40 AM UTC 24 |
719395829 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.3282634575 |
|
|
Aug 29 01:29:26 AM UTC 24 |
Aug 29 01:33:08 AM UTC 24 |
36983186553 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.2250010173 |
|
|
Aug 29 01:33:09 AM UTC 24 |
Aug 29 01:33:15 AM UTC 24 |
355119556 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.3518900650 |
|
|
Aug 29 01:29:38 AM UTC 24 |
Aug 29 01:33:26 AM UTC 24 |
21857856963 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.791489345 |
|
|
Aug 29 01:32:19 AM UTC 24 |
Aug 29 01:34:02 AM UTC 24 |
10370624506 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.1208637402 |
|
|
Aug 29 01:32:12 AM UTC 24 |
Aug 29 01:34:30 AM UTC 24 |
13886991895 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all.3853713447 |
|
|
Aug 29 12:34:06 AM UTC 24 |
Aug 29 01:34:32 AM UTC 24 |
207900532957 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.3170599413 |
|
|
Aug 29 01:27:39 AM UTC 24 |
Aug 29 01:34:35 AM UTC 24 |
7441514346 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_alert_test.3854509722 |
|
|
Aug 29 01:34:33 AM UTC 24 |
Aug 29 01:34:35 AM UTC 24 |
14423594 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.3703781115 |
|
|
Aug 29 01:28:36 AM UTC 24 |
Aug 29 01:34:47 AM UTC 24 |
50798198569 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_smoke.1524284869 |
|
|
Aug 29 01:34:35 AM UTC 24 |
Aug 29 01:34:49 AM UTC 24 |
2706791818 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.522972209 |
|
|
Aug 29 01:34:03 AM UTC 24 |
Aug 29 01:34:52 AM UTC 24 |
3141437691 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access.159357915 |
|
|
Aug 29 01:34:53 AM UTC 24 |
Aug 29 01:35:17 AM UTC 24 |
2238064063 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_executable.4108145819 |
|
|
Aug 29 01:16:05 AM UTC 24 |
Aug 29 01:36:15 AM UTC 24 |
49469392707 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_executable.4041446152 |
|
|
Aug 29 01:25:55 AM UTC 24 |
Aug 29 01:36:29 AM UTC 24 |
6600043075 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.2774290583 |
|
|
Aug 29 01:33:27 AM UTC 24 |
Aug 29 01:37:10 AM UTC 24 |
5001560960 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.3050412823 |
|
|
Aug 29 01:31:53 AM UTC 24 |
Aug 29 01:37:20 AM UTC 24 |
17798416389 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.1294504082 |
|
|
Aug 29 01:33:17 AM UTC 24 |
Aug 29 01:37:22 AM UTC 24 |
27630692470 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.3991012088 |
|
|
Aug 29 01:36:16 AM UTC 24 |
Aug 29 01:37:23 AM UTC 24 |
3068649625 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.3510939595 |
|
|
Aug 29 01:28:19 AM UTC 24 |
Aug 29 01:37:23 AM UTC 24 |
39565437440 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.995500013 |
|
|
Aug 29 01:36:29 AM UTC 24 |
Aug 29 01:37:27 AM UTC 24 |
774433096 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.2181717689 |
|
|
Aug 29 01:37:24 AM UTC 24 |
Aug 29 01:37:33 AM UTC 24 |
2397353752 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.3408581159 |
|
|
Aug 29 01:31:23 AM UTC 24 |
Aug 29 01:37:56 AM UTC 24 |
4462845143 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.1206470651 |
|
|
Aug 29 01:37:57 AM UTC 24 |
Aug 29 01:38:38 AM UTC 24 |
2470687658 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.164684586 |
|
|
Aug 29 01:37:11 AM UTC 24 |
Aug 29 01:38:43 AM UTC 24 |
39465067105 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.3586148625 |
|
|
Aug 29 01:24:11 AM UTC 24 |
Aug 29 01:38:45 AM UTC 24 |
9326218048 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_alert_test.2198535088 |
|
|
Aug 29 01:38:44 AM UTC 24 |
Aug 29 01:38:46 AM UTC 24 |
13547230 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_smoke.3110333478 |
|
|
Aug 29 01:38:46 AM UTC 24 |
Aug 29 01:38:55 AM UTC 24 |
1031199094 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_executable.4138371733 |
|
|
Aug 29 01:37:23 AM UTC 24 |
Aug 29 01:38:57 AM UTC 24 |
3271918605 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_regwen.118381405 |
|
|
Aug 29 01:23:25 AM UTC 24 |
Aug 29 01:39:18 AM UTC 24 |
16526448783 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_regwen.278279610 |
|
|
Aug 29 01:37:24 AM UTC 24 |
Aug 29 01:39:29 AM UTC 24 |
5321506387 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.1496212621 |
|
|
Aug 29 01:15:55 AM UTC 24 |
Aug 29 01:39:38 AM UTC 24 |
57329588052 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.3943423283 |
|
|
Aug 29 01:29:55 AM UTC 24 |
Aug 29 01:39:45 AM UTC 24 |
28948441828 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access.4054787017 |
|
|
Aug 29 01:39:18 AM UTC 24 |
Aug 29 01:39:56 AM UTC 24 |
1453445322 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all.2023839208 |
|
|
Aug 29 12:51:32 AM UTC 24 |
Aug 29 01:40:04 AM UTC 24 |
41361091607 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.1481578019 |
|
|
Aug 29 01:39:46 AM UTC 24 |
Aug 29 01:40:24 AM UTC 24 |
2902987400 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all.1296620999 |
|
|
Aug 29 01:23:47 AM UTC 24 |
Aug 29 01:40:25 AM UTC 24 |
16731012512 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.4019889782 |
|
|
Aug 29 01:37:27 AM UTC 24 |
Aug 29 01:40:33 AM UTC 24 |
43183341978 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.521124027 |
|
|
Aug 29 01:34:51 AM UTC 24 |
Aug 29 01:40:41 AM UTC 24 |
13819865770 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.3065084627 |
|
|
Aug 29 01:40:33 AM UTC 24 |
Aug 29 01:40:41 AM UTC 24 |
3369030017 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.212061822 |
|
|
Aug 29 01:39:40 AM UTC 24 |
Aug 29 01:40:43 AM UTC 24 |
738089894 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.384611753 |
|
|
Aug 29 01:37:33 AM UTC 24 |
Aug 29 01:40:56 AM UTC 24 |
24292977219 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.1692929906 |
|
|
Aug 29 01:40:44 AM UTC 24 |
Aug 29 01:41:05 AM UTC 24 |
5455766437 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_alert_test.2791185731 |
|
|
Aug 29 01:41:06 AM UTC 24 |
Aug 29 01:41:08 AM UTC 24 |
48557376 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_smoke.3110424686 |
|
|
Aug 29 01:41:09 AM UTC 24 |
Aug 29 01:41:28 AM UTC 24 |
2246370207 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.955655879 |
|
|
Aug 29 01:20:03 AM UTC 24 |
Aug 29 01:41:39 AM UTC 24 |
70600078778 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.1890299278 |
|
|
Aug 29 01:40:43 AM UTC 24 |
Aug 29 01:42:32 AM UTC 24 |
2485649010 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.1028406615 |
|
|
Aug 29 01:34:36 AM UTC 24 |
Aug 29 01:42:41 AM UTC 24 |
41894837766 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.3264912644 |
|
|
Aug 29 01:25:52 AM UTC 24 |
Aug 29 01:43:09 AM UTC 24 |
22218224489 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access.206246767 |
|
|
Aug 29 01:42:42 AM UTC 24 |
Aug 29 01:43:18 AM UTC 24 |
6095812152 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.917804998 |
|
|
Aug 29 01:43:18 AM UTC 24 |
Aug 29 01:43:30 AM UTC 24 |
1360729588 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.3619803666 |
|
|
Aug 29 01:38:57 AM UTC 24 |
Aug 29 01:43:31 AM UTC 24 |
3349020922 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.2444575214 |
|
|
Aug 29 01:40:05 AM UTC 24 |
Aug 29 01:43:32 AM UTC 24 |
2060460444 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all.1248368618 |
|
|
Aug 29 12:42:27 AM UTC 24 |
Aug 29 01:43:46 AM UTC 24 |
257758915469 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.866186155 |
|
|
Aug 29 01:43:31 AM UTC 24 |
Aug 29 01:43:50 AM UTC 24 |
2756800200 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.3115120300 |
|
|
Aug 29 01:39:57 AM UTC 24 |
Aug 29 01:44:16 AM UTC 24 |
67089425983 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.1469669065 |
|
|
Aug 29 01:43:33 AM UTC 24 |
Aug 29 01:44:23 AM UTC 24 |
16866129569 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.2123894995 |
|
|
Aug 29 01:44:17 AM UTC 24 |
Aug 29 01:44:24 AM UTC 24 |
364515070 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_bijection.1878985299 |
|
|
Aug 29 01:04:46 AM UTC 24 |
Aug 29 01:44:26 AM UTC 24 |
27957857632 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_bijection.493619702 |
|
|
Aug 29 01:10:58 AM UTC 24 |
Aug 29 01:44:28 AM UTC 24 |
27662836601 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all.26576695 |
|
|
Aug 29 01:38:40 AM UTC 24 |
Aug 29 01:44:44 AM UTC 24 |
37386542398 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_alert_test.4172827233 |
|
|
Aug 29 01:44:45 AM UTC 24 |
Aug 29 01:44:47 AM UTC 24 |
41046849 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.770505226 |
|
|
Aug 29 01:40:42 AM UTC 24 |
Aug 29 01:44:50 AM UTC 24 |
43254590653 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.3317591137 |
|
|
Aug 29 01:39:30 AM UTC 24 |
Aug 29 01:44:57 AM UTC 24 |
39740073290 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_regwen.1172551603 |
|
|
Aug 29 01:32:40 AM UTC 24 |
Aug 29 01:45:01 AM UTC 24 |
37307617299 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.2054231675 |
|
|
Aug 29 01:44:27 AM UTC 24 |
Aug 29 01:45:06 AM UTC 24 |
16499783246 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_smoke.1413946631 |
|
|
Aug 29 01:44:48 AM UTC 24 |
Aug 29 01:45:14 AM UTC 24 |
6665300928 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.943463149 |
|
|
Aug 29 01:35:18 AM UTC 24 |
Aug 29 01:45:27 AM UTC 24 |
36698620120 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access.3745179856 |
|
|
Aug 29 01:45:07 AM UTC 24 |
Aug 29 01:45:36 AM UTC 24 |
1212421167 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_regwen.2030180663 |
|
|
Aug 29 01:29:18 AM UTC 24 |
Aug 29 01:45:54 AM UTC 24 |
4504004841 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.2630644035 |
|
|
Aug 29 01:45:27 AM UTC 24 |
Aug 29 01:45:55 AM UTC 24 |
1538464323 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.4000149946 |
|
|
Aug 29 01:44:24 AM UTC 24 |
Aug 29 01:45:57 AM UTC 24 |
2802060790 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.2296580497 |
|
|
Aug 29 01:42:34 AM UTC 24 |
Aug 29 01:46:00 AM UTC 24 |
18379671023 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.2917292118 |
|
|
Aug 29 01:45:37 AM UTC 24 |
Aug 29 01:46:20 AM UTC 24 |
2892700886 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.3330522604 |
|
|
Aug 29 01:46:21 AM UTC 24 |
Aug 29 01:46:28 AM UTC 24 |
355784372 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_bijection.2520092853 |
|
|
Aug 29 01:14:54 AM UTC 24 |
Aug 29 01:46:45 AM UTC 24 |
67546377227 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.164023072 |
|
|
Aug 29 01:45:55 AM UTC 24 |
Aug 29 01:47:01 AM UTC 24 |
9986605257 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.412710601 |
|
|
Aug 29 01:47:02 AM UTC 24 |
Aug 29 01:47:36 AM UTC 24 |
485094058 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.129808788 |
|
|
Aug 29 01:44:24 AM UTC 24 |
Aug 29 01:47:40 AM UTC 24 |
20704940451 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_alert_test.3090583078 |
|
|
Aug 29 01:47:41 AM UTC 24 |
Aug 29 01:47:43 AM UTC 24 |
17899125 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.3115093340 |
|
|
Aug 29 01:46:45 AM UTC 24 |
Aug 29 01:48:12 AM UTC 24 |
1467910789 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_smoke.2193188441 |
|
|
Aug 29 01:47:44 AM UTC 24 |
Aug 29 01:48:16 AM UTC 24 |
4297075306 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_executable.3293466557 |
|
|
Aug 29 01:29:15 AM UTC 24 |
Aug 29 01:48:47 AM UTC 24 |
44758769106 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_regwen.740566334 |
|
|
Aug 29 01:46:01 AM UTC 24 |
Aug 29 01:49:20 AM UTC 24 |
15694991815 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_regwen.509266913 |
|
|
Aug 29 01:40:26 AM UTC 24 |
Aug 29 01:49:23 AM UTC 24 |
49998260319 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.3368657592 |
|
|
Aug 29 01:29:13 AM UTC 24 |
Aug 29 01:49:53 AM UTC 24 |
65911661008 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access.467532863 |
|
|
Aug 29 01:49:21 AM UTC 24 |
Aug 29 01:49:59 AM UTC 24 |
1528630072 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.329964458 |
|
|
Aug 29 01:49:54 AM UTC 24 |
Aug 29 01:50:16 AM UTC 24 |
6284835614 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_executable.1580222451 |
|
|
Aug 29 01:45:58 AM UTC 24 |
Aug 29 01:50:19 AM UTC 24 |
22762403379 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_bijection.1494161560 |
|
|
Aug 29 01:34:48 AM UTC 24 |
Aug 29 01:50:28 AM UTC 24 |
24274783359 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.3111424242 |
|
|
Aug 29 01:49:59 AM UTC 24 |
Aug 29 01:50:28 AM UTC 24 |
2948938443 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all.231922709 |
|
|
Aug 29 12:49:04 AM UTC 24 |
Aug 29 01:50:34 AM UTC 24 |
49340987375 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.3017879527 |
|
|
Aug 29 01:50:35 AM UTC 24 |
Aug 29 01:50:41 AM UTC 24 |
360518432 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.2262030053 |
|
|
Aug 29 01:43:09 AM UTC 24 |
Aug 29 01:50:41 AM UTC 24 |
227596060147 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.3672651271 |
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Aug 29 01:45:02 AM UTC 24 |
Aug 29 01:50:42 AM UTC 24 |
4009353256 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.990876553 |
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Aug 29 01:22:10 AM UTC 24 |
Aug 29 01:50:52 AM UTC 24 |
41159201750 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.3460153767 |
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Aug 29 01:44:51 AM UTC 24 |
Aug 29 01:51:25 AM UTC 24 |
56531619707 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_executable.883356898 |
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Aug 29 01:32:28 AM UTC 24 |
Aug 29 01:51:26 AM UTC 24 |
57789371556 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_alert_test.1081317272 |
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Aug 29 01:51:26 AM UTC 24 |
Aug 29 01:51:28 AM UTC 24 |
23708488 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.1043184809 |
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Aug 29 01:50:17 AM UTC 24 |
Aug 29 01:51:33 AM UTC 24 |
63798504398 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.45750560 |
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Aug 29 01:50:43 AM UTC 24 |
Aug 29 01:51:41 AM UTC 24 |
2909113907 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all.1567991021 |
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Aug 29 12:36:54 AM UTC 24 |
Aug 29 01:51:42 AM UTC 24 |
152866200443 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_smoke.2476312772 |
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|
Aug 29 01:51:27 AM UTC 24 |
Aug 29 01:51:52 AM UTC 24 |
1191401334 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.2573868441 |
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Aug 29 01:38:47 AM UTC 24 |
Aug 29 01:51:52 AM UTC 24 |
34374837713 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access.95291124 |
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Aug 29 01:51:43 AM UTC 24 |
Aug 29 01:51:53 AM UTC 24 |
420011362 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.1379362297 |
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Aug 29 01:51:53 AM UTC 24 |
Aug 29 01:52:15 AM UTC 24 |
2766922042 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.640958805 |
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Aug 29 01:52:16 AM UTC 24 |
Aug 29 01:52:35 AM UTC 24 |
1482308294 ps |