| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.94 | 99.19 | 94.27 | 99.72 | 100.00 | 96.03 | 99.12 | 97.26 |
| T1007 | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1574283226 | Aug 29 12:12:13 AM UTC 24 | Aug 29 12:12:17 AM UTC 24 | 4071403702 ps | ||
| T1008 | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3399780697 | Aug 29 12:12:15 AM UTC 24 | Aug 29 12:12:17 AM UTC 24 | 15046630 ps | ||
| T95 | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2152572578 | Aug 29 12:11:36 AM UTC 24 | Aug 29 12:12:17 AM UTC 24 | 23134394655 ps | ||
| T1009 | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2748149793 | Aug 29 12:12:12 AM UTC 24 | Aug 29 12:12:18 AM UTC 24 | 88277243 ps | ||
| T1010 | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.863337311 | Aug 29 12:12:11 AM UTC 24 | Aug 29 12:12:18 AM UTC 24 | 1088078780 ps | ||
| T1011 | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1147486261 | Aug 29 12:12:18 AM UTC 24 | Aug 29 12:12:20 AM UTC 24 | 25367245 ps | ||
| T1012 | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2246884137 | Aug 29 12:12:18 AM UTC 24 | Aug 29 12:12:21 AM UTC 24 | 35380635 ps | ||
| T1013 | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3973329639 | Aug 29 12:12:17 AM UTC 24 | Aug 29 12:12:21 AM UTC 24 | 157131217 ps | ||
| T1014 | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1108027760 | Aug 29 12:12:18 AM UTC 24 | Aug 29 12:12:23 AM UTC 24 | 846598695 ps | ||
| T1015 | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2340192905 | Aug 29 12:12:22 AM UTC 24 | Aug 29 12:12:24 AM UTC 24 | 18755448 ps | ||
| T98 | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1285159763 | Aug 29 12:12:22 AM UTC 24 | Aug 29 12:12:24 AM UTC 24 | 20456893 ps | ||
| T1016 | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3084682859 | Aug 29 12:12:17 AM UTC 24 | Aug 29 12:12:24 AM UTC 24 | 428441533 ps | ||
| T99 | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1104928621 | Aug 29 12:11:51 AM UTC 24 | Aug 29 12:12:25 AM UTC 24 | 15515021777 ps | ||
| T124 | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1509972270 | Aug 29 12:12:20 AM UTC 24 | Aug 29 12:12:26 AM UTC 24 | 771323072 ps | ||
| T1017 | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.182030809 | Aug 29 12:12:20 AM UTC 24 | Aug 29 12:12:27 AM UTC 24 | 1738334314 ps | ||
| T1018 | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1259451696 | Aug 29 12:12:20 AM UTC 24 | Aug 29 12:12:27 AM UTC 24 | 531763520 ps | ||
| T1019 | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3120229325 | Aug 29 12:12:23 AM UTC 24 | Aug 29 12:12:29 AM UTC 24 | 514086412 ps | ||
| T1020 | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3109901174 | Aug 29 12:11:22 AM UTC 24 | Aug 29 12:12:37 AM UTC 24 | 13972370312 ps | ||
| T100 | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2179947865 | Aug 29 12:11:24 AM UTC 24 | Aug 29 12:12:39 AM UTC 24 | 7371445584 ps | ||
| T1021 | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1165574130 | Aug 29 12:11:54 AM UTC 24 | Aug 29 12:12:42 AM UTC 24 | 7722752318 ps | ||
| T101 | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2988795044 | Aug 29 12:11:41 AM UTC 24 | Aug 29 12:12:52 AM UTC 24 | 21380996229 ps | ||
| T1022 | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2496165830 | Aug 29 12:12:08 AM UTC 24 | Aug 29 12:12:57 AM UTC 24 | 3868025706 ps | ||
| T1023 | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.410839800 | Aug 29 12:11:27 AM UTC 24 | Aug 29 12:12:58 AM UTC 24 | 7357623913 ps | ||
| T1024 | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.252362955 | Aug 29 12:11:49 AM UTC 24 | Aug 29 12:12:58 AM UTC 24 | 7266050000 ps | ||
| T1025 | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2851388105 | Aug 29 12:11:29 AM UTC 24 | Aug 29 12:13:01 AM UTC 24 | 29397528561 ps | ||
| T1026 | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2580861228 | Aug 29 12:11:43 AM UTC 24 | Aug 29 12:13:01 AM UTC 24 | 7462193089 ps | ||
| T1027 | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1571253369 | Aug 29 12:11:39 AM UTC 24 | Aug 29 12:13:02 AM UTC 24 | 14736863181 ps | ||
| T1028 | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2635284891 | Aug 29 12:12:20 AM UTC 24 | Aug 29 12:13:07 AM UTC 24 | 15352874973 ps | ||
| T1029 | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2558126069 | Aug 29 12:12:04 AM UTC 24 | Aug 29 12:13:11 AM UTC 24 | 70818331624 ps | ||
| T1030 | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.214886317 | Aug 29 12:12:17 AM UTC 24 | Aug 29 12:13:21 AM UTC 24 | 14087909562 ps | ||
| T1031 | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1647939629 | Aug 29 12:11:58 AM UTC 24 | Aug 29 12:13:23 AM UTC 24 | 29361842010 ps | ||
| T1032 | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3699704452 | Aug 29 12:12:12 AM UTC 24 | Aug 29 12:13:25 AM UTC 24 | 7528133271 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access.1438963175 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 2200786256 ps |
| CPU time | 8.77 seconds |
| Started | Aug 29 12:27:22 AM UTC 24 |
| Finished | Aug 29 12:27:36 AM UTC 24 |
| Peak memory | 211480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438963175 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_partial_access.1438963175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/0.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3747266194 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 2052143166 ps |
| CPU time | 96.8 seconds |
| Started | Aug 29 12:27:29 AM UTC 24 |
| Finished | Aug 29 12:29:07 AM UTC 24 |
| Peak memory | 221932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747266194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.3747266194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/1.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.3479611313 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 16892426011 ps |
| CPU time | 49.39 seconds |
| Started | Aug 29 12:27:25 AM UTC 24 |
| Finished | Aug 29 12:28:16 AM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479611313 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_escalation.3479611313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/1.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.1794646721 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 24976202111 ps |
| CPU time | 235.94 seconds |
| Started | Aug 29 12:31:35 AM UTC 24 |
| Finished | Aug 29 12:35:35 AM UTC 24 |
| Peak memory | 228944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794646721 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_mem_partial_access.1794646721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/4.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.2882871926 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 357317942 ps |
| CPU time | 5.09 seconds |
| Started | Aug 29 12:27:29 AM UTC 24 |
| Finished | Aug 29 12:27:35 AM UTC 24 |
| Peak memory | 247588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882871926 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_sec_cm.2882871926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_regwen.2512147935 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 70524116136 ps |
| CPU time | 611.78 seconds |
| Started | Aug 29 12:27:38 AM UTC 24 |
| Finished | Aug 29 12:37:57 AM UTC 24 |
| Peak memory | 386600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512147935 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.2512147935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/2.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1439938289 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 167464495 ps |
| CPU time | 3.64 seconds |
| Started | Aug 29 12:11:22 AM UTC 24 |
| Finished | Aug 29 12:11:26 AM UTC 24 |
| Peak memory | 223712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439 938289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_ intg_err.1439938289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/2.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.4235075395 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1936351814 ps |
| CPU time | 93.67 seconds |
| Started | Aug 29 12:27:33 AM UTC 24 |
| Finished | Aug 29 12:29:08 AM UTC 24 |
| Peak memory | 211564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235075395 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_pipeline.4235075395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/2.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_regwen.1412083063 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 75717507733 ps |
| CPU time | 1162.75 seconds |
| Started | Aug 29 12:33:31 AM UTC 24 |
| Finished | Aug 29 12:53:07 AM UTC 24 |
| Peak memory | 386516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412083063 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.1412083063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/5.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.3451611442 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 21766181213 ps |
| CPU time | 617.93 seconds |
| Started | Aug 29 12:27:25 AM UTC 24 |
| Finished | Aug 29 12:37:51 AM UTC 24 |
| Peak memory | 211504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451611442 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_partial_ac cess_b2b.3451611442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/1.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.3374805820 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 530483040 ps |
| CPU time | 12.3 seconds |
| Started | Aug 29 12:31:39 AM UTC 24 |
| Finished | Aug 29 12:31:53 AM UTC 24 |
| Peak memory | 222068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374805820 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.3374805820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/4.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.147943987 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 1458297453 ps |
| CPU time | 6.92 seconds |
| Started | Aug 29 12:27:28 AM UTC 24 |
| Finished | Aug 29 12:27:36 AM UTC 24 |
| Peak memory | 211704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147943987 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.147943987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/1.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3719618276 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 60738653 ps |
| CPU time | 1.02 seconds |
| Started | Aug 29 12:11:18 AM UTC 24 |
| Finished | Aug 29 12:11:20 AM UTC 24 |
| Peak memory | 212748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719618 276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_al iasing.3719618276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all.1780802016 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 151196685340 ps |
| CPU time | 1487.86 seconds |
| Started | Aug 29 12:27:23 AM UTC 24 |
| Finished | Aug 29 12:52:31 AM UTC 24 |
| Peak memory | 390608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17808020 16 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all.1780802016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/0.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.2877988927 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 10146614151 ps |
| CPU time | 102.72 seconds |
| Started | Aug 29 12:27:22 AM UTC 24 |
| Finished | Aug 29 12:29:11 AM UTC 24 |
| Peak memory | 221792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877988927 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_escalation.2877988927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/0.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.86520054 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 5826195966 ps |
| CPU time | 69.63 seconds |
| Started | Aug 29 02:00:51 AM UTC 24 |
| Finished | Aug 29 02:02:02 AM UTC 24 |
| Peak memory | 221864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86520054 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.86520054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/32.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2119704165 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 708864812 ps |
| CPU time | 2.88 seconds |
| Started | Aug 29 12:11:49 AM UTC 24 |
| Finished | Aug 29 12:11:53 AM UTC 24 |
| Peak memory | 223652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119 704165 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl _intg_err.2119704165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/11.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_alert_test.514518111 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 13572616 ps |
| CPU time | 0.61 seconds |
| Started | Aug 29 12:27:24 AM UTC 24 |
| Finished | Aug 29 12:27:27 AM UTC 24 |
| Peak memory | 210904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514518111 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_alert_test.514518111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/0.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1636077276 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 368745830 ps |
| CPU time | 4.19 seconds |
| Started | Aug 29 12:11:57 AM UTC 24 |
| Finished | Aug 29 12:12:03 AM UTC 24 |
| Peak memory | 223632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636 077276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl _intg_err.1636077276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/13.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.4020476277 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 45595413049 ps |
| CPU time | 91.73 seconds |
| Started | Aug 29 12:29:08 AM UTC 24 |
| Finished | Aug 29 12:30:42 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020476277 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_escalation.4020476277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/3.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3701707979 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 139774823 ps |
| CPU time | 2.27 seconds |
| Started | Aug 29 12:12:05 AM UTC 24 |
| Finished | Aug 29 12:12:08 AM UTC 24 |
| Peak memory | 223580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701 707979 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl _intg_err.3701707979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/15.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1509972270 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 771323072 ps |
| CPU time | 4.36 seconds |
| Started | Aug 29 12:12:20 AM UTC 24 |
| Finished | Aug 29 12:12:26 AM UTC 24 |
| Peak memory | 213408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509 972270 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl _intg_err.1509972270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/19.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2350057702 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 32619791 ps |
| CPU time | 1.06 seconds |
| Started | Aug 29 12:11:18 AM UTC 24 |
| Finished | Aug 29 12:11:20 AM UTC 24 |
| Peak memory | 212468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350057702 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_rw.2350057702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2916835051 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 3841042004 ps |
| CPU time | 49.58 seconds |
| Started | Aug 29 12:11:16 AM UTC 24 |
| Finished | Aug 29 12:12:08 AM UTC 24 |
| Peak memory | 213460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 916835051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ passthru_mem_tl_intg_err.2916835051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/0.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.3175522408 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 717261317 ps |
| CPU time | 17.66 seconds |
| Started | Aug 29 12:27:22 AM UTC 24 |
| Finished | Aug 29 12:27:45 AM UTC 24 |
| Peak memory | 245228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3175522408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_m ax_throughput.3175522408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/0.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1916193891 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 469875019 ps |
| CPU time | 3.26 seconds |
| Started | Aug 29 12:11:18 AM UTC 24 |
| Finished | Aug 29 12:11:22 AM UTC 24 |
| Peak memory | 213600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916193 891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_bi t_bash.1916193891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.72714082 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 25668000 ps |
| CPU time | 0.92 seconds |
| Started | Aug 29 12:11:18 AM UTC 24 |
| Finished | Aug 29 12:11:20 AM UTC 24 |
| Peak memory | 212748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7271408 2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_hw_r eset.72714082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1572860883 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 1535191344 ps |
| CPU time | 5.39 seconds |
| Started | Aug 29 12:11:18 AM UTC 24 |
| Finished | Aug 29 12:11:24 AM UTC 24 |
| Peak memory | 223580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=1572860883 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.1572860883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3342383663 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 17794874 ps |
| CPU time | 0.94 seconds |
| Started | Aug 29 12:11:18 AM UTC 24 |
| Finished | Aug 29 12:11:20 AM UTC 24 |
| Peak memory | 212524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3342383663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram _ctrl_same_csr_outstanding.3342383663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/0.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2859955934 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 173561743 ps |
| CPU time | 4.06 seconds |
| Started | Aug 29 12:11:16 AM UTC 24 |
| Finished | Aug 29 12:11:21 AM UTC 24 |
| Peak memory | 213540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859955934 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_tl_errors.2859955934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/0.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.431951382 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 367156070 ps |
| CPU time | 2.25 seconds |
| Started | Aug 29 12:11:18 AM UTC 24 |
| Finished | Aug 29 12:11:21 AM UTC 24 |
| Peak memory | 213472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4319 51382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_tl_i ntg_err.431951382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/0.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3532622116 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 18048698 ps |
| CPU time | 0.95 seconds |
| Started | Aug 29 12:11:18 AM UTC 24 |
| Finished | Aug 29 12:11:20 AM UTC 24 |
| Peak memory | 212464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532622 116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_al iasing.3532622116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/1.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2781350068 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 184332749 ps |
| CPU time | 2.15 seconds |
| Started | Aug 29 12:11:18 AM UTC 24 |
| Finished | Aug 29 12:11:22 AM UTC 24 |
| Peak memory | 213408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781350 068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_bi t_bash.2781350068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/1.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1430947785 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 23443825 ps |
| CPU time | 1.05 seconds |
| Started | Aug 29 12:11:18 AM UTC 24 |
| Finished | Aug 29 12:11:20 AM UTC 24 |
| Peak memory | 212464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430947 785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_hw _reset.1430947785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/1.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1366932411 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 727749484 ps |
| CPU time | 6.49 seconds |
| Started | Aug 29 12:11:20 AM UTC 24 |
| Finished | Aug 29 12:11:27 AM UTC 24 |
| Peak memory | 223960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=1366932411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.1366932411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3108392480 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 42501803 ps |
| CPU time | 0.92 seconds |
| Started | Aug 29 12:11:18 AM UTC 24 |
| Finished | Aug 29 12:11:20 AM UTC 24 |
| Peak memory | 212468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108392480 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_rw.3108392480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/1.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1884379272 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 46080170479 ps |
| CPU time | 51.57 seconds |
| Started | Aug 29 12:11:18 AM UTC 24 |
| Finished | Aug 29 12:12:11 AM UTC 24 |
| Peak memory | 213528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 884379272 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ passthru_mem_tl_intg_err.1884379272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/1.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1752304790 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 11803867 ps |
| CPU time | 0.99 seconds |
| Started | Aug 29 12:11:18 AM UTC 24 |
| Finished | Aug 29 12:11:20 AM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1752304790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram _ctrl_same_csr_outstanding.1752304790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/1.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2538592462 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 84301858 ps |
| CPU time | 3.97 seconds |
| Started | Aug 29 12:11:18 AM UTC 24 |
| Finished | Aug 29 12:11:23 AM UTC 24 |
| Peak memory | 213488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538592462 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_errors.2538592462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/1.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.920836552 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 191593918 ps |
| CPU time | 3.34 seconds |
| Started | Aug 29 12:11:18 AM UTC 24 |
| Finished | Aug 29 12:11:23 AM UTC 24 |
| Peak memory | 213608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9208 36552 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_i ntg_err.920836552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/1.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.4272442565 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 686037788 ps |
| CPU time | 6.73 seconds |
| Started | Aug 29 12:11:47 AM UTC 24 |
| Finished | Aug 29 12:11:55 AM UTC 24 |
| Peak memory | 223820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=4272442565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.4272442565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.234635961 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 21757092 ps |
| CPU time | 0.95 seconds |
| Started | Aug 29 12:11:47 AM UTC 24 |
| Finished | Aug 29 12:11:49 AM UTC 24 |
| Peak memory | 212748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234635961 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_rw.234635961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/10.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2580861228 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 7462193089 ps |
| CPU time | 75.93 seconds |
| Started | Aug 29 12:11:43 AM UTC 24 |
| Finished | Aug 29 12:13:01 AM UTC 24 |
| Peak memory | 213528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 580861228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl _passthru_mem_tl_intg_err.2580861228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/10.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.4181810602 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 54864713 ps |
| CPU time | 0.96 seconds |
| Started | Aug 29 12:11:47 AM UTC 24 |
| Finished | Aug 29 12:11:49 AM UTC 24 |
| Peak memory | 212704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=4181810602 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sra m_ctrl_same_csr_outstanding.4181810602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/10.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.436013383 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 37143435 ps |
| CPU time | 3.78 seconds |
| Started | Aug 29 12:11:46 AM UTC 24 |
| Finished | Aug 29 12:11:50 AM UTC 24 |
| Peak memory | 223712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436013383 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl_errors.436013383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/10.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1690016066 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 91033529 ps |
| CPU time | 2.23 seconds |
| Started | Aug 29 12:11:46 AM UTC 24 |
| Finished | Aug 29 12:11:49 AM UTC 24 |
| Peak memory | 223652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690 016066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl _intg_err.1690016066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/10.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1165562968 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 719106206 ps |
| CPU time | 5.83 seconds |
| Started | Aug 29 12:11:50 AM UTC 24 |
| Finished | Aug 29 12:11:58 AM UTC 24 |
| Peak memory | 223688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=1165562968 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.1165562968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2152362598 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 43189862 ps |
| CPU time | 0.93 seconds |
| Started | Aug 29 12:11:50 AM UTC 24 |
| Finished | Aug 29 12:11:53 AM UTC 24 |
| Peak memory | 212464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152362598 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_rw.2152362598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/11.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.252362955 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 7266050000 ps |
| CPU time | 67.44 seconds |
| Started | Aug 29 12:11:49 AM UTC 24 |
| Finished | Aug 29 12:12:58 AM UTC 24 |
| Peak memory | 213600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 52362955 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ passthru_mem_tl_intg_err.252362955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/11.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2256714241 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 79397743 ps |
| CPU time | 1.14 seconds |
| Started | Aug 29 12:11:50 AM UTC 24 |
| Finished | Aug 29 12:11:53 AM UTC 24 |
| Peak memory | 212812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2256714241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sra m_ctrl_same_csr_outstanding.2256714241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/11.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1467487671 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 125963597 ps |
| CPU time | 6.37 seconds |
| Started | Aug 29 12:11:49 AM UTC 24 |
| Finished | Aug 29 12:11:57 AM UTC 24 |
| Peak memory | 223772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467487671 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl_errors.1467487671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/11.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2445316119 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 677926323 ps |
| CPU time | 7.19 seconds |
| Started | Aug 29 12:11:54 AM UTC 24 |
| Finished | Aug 29 12:12:03 AM UTC 24 |
| Peak memory | 223572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=2445316119 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.2445316119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1623423652 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 14208390 ps |
| CPU time | 1.09 seconds |
| Started | Aug 29 12:11:54 AM UTC 24 |
| Finished | Aug 29 12:11:57 AM UTC 24 |
| Peak memory | 212048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623423652 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_rw.1623423652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/12.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1104928621 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 15515021777 ps |
| CPU time | 33 seconds |
| Started | Aug 29 12:11:51 AM UTC 24 |
| Finished | Aug 29 12:12:25 AM UTC 24 |
| Peak memory | 213384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 104928621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl _passthru_mem_tl_intg_err.1104928621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/12.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2728427973 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 75267241 ps |
| CPU time | 0.96 seconds |
| Started | Aug 29 12:11:54 AM UTC 24 |
| Finished | Aug 29 12:11:57 AM UTC 24 |
| Peak memory | 212696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2728427973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sra m_ctrl_same_csr_outstanding.2728427973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/12.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3377340032 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 141781740 ps |
| CPU time | 3.55 seconds |
| Started | Aug 29 12:11:52 AM UTC 24 |
| Finished | Aug 29 12:11:56 AM UTC 24 |
| Peak memory | 223700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377340032 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl_errors.3377340032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/12.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.4096310769 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 649485823 ps |
| CPU time | 3.85 seconds |
| Started | Aug 29 12:11:52 AM UTC 24 |
| Finished | Aug 29 12:11:57 AM UTC 24 |
| Peak memory | 223652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096 310769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl _intg_err.4096310769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/12.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2856285245 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 1809675981 ps |
| CPU time | 5.8 seconds |
| Started | Aug 29 12:11:57 AM UTC 24 |
| Finished | Aug 29 12:12:04 AM UTC 24 |
| Peak memory | 223572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=2856285245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.2856285245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.444863085 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 24794754 ps |
| CPU time | 0.88 seconds |
| Started | Aug 29 12:11:57 AM UTC 24 |
| Finished | Aug 29 12:11:59 AM UTC 24 |
| Peak memory | 212464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444863085 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_rw.444863085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/13.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1165574130 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 7722752318 ps |
| CPU time | 46.09 seconds |
| Started | Aug 29 12:11:54 AM UTC 24 |
| Finished | Aug 29 12:12:42 AM UTC 24 |
| Peak memory | 213380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 165574130 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl _passthru_mem_tl_intg_err.1165574130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/13.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2212632272 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 14824459 ps |
| CPU time | 0.92 seconds |
| Started | Aug 29 12:11:57 AM UTC 24 |
| Finished | Aug 29 12:11:59 AM UTC 24 |
| Peak memory | 212988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2212632272 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sra m_ctrl_same_csr_outstanding.2212632272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/13.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3920086132 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 1410468015 ps |
| CPU time | 6.75 seconds |
| Started | Aug 29 12:11:55 AM UTC 24 |
| Finished | Aug 29 12:12:04 AM UTC 24 |
| Peak memory | 223716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920086132 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl_errors.3920086132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/13.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2266854404 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 348479873 ps |
| CPU time | 4.98 seconds |
| Started | Aug 29 12:12:04 AM UTC 24 |
| Finished | Aug 29 12:12:10 AM UTC 24 |
| Peak memory | 223572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=2266854404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.2266854404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2231101448 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 18133130 ps |
| CPU time | 0.92 seconds |
| Started | Aug 29 12:12:01 AM UTC 24 |
| Finished | Aug 29 12:12:03 AM UTC 24 |
| Peak memory | 212748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231101448 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_rw.2231101448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/14.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1647939629 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 29361842010 ps |
| CPU time | 83.83 seconds |
| Started | Aug 29 12:11:58 AM UTC 24 |
| Finished | Aug 29 12:13:23 AM UTC 24 |
| Peak memory | 213456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 647939629 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl _passthru_mem_tl_intg_err.1647939629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/14.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.4011025656 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 26884973 ps |
| CPU time | 1.14 seconds |
| Started | Aug 29 12:12:04 AM UTC 24 |
| Finished | Aug 29 12:12:06 AM UTC 24 |
| Peak memory | 212504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=4011025656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sra m_ctrl_same_csr_outstanding.4011025656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/14.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3006854650 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 216150864 ps |
| CPU time | 6.01 seconds |
| Started | Aug 29 12:11:59 AM UTC 24 |
| Finished | Aug 29 12:12:06 AM UTC 24 |
| Peak memory | 223792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006854650 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_tl_errors.3006854650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/14.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.32763511 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 84308323 ps |
| CPU time | 2.03 seconds |
| Started | Aug 29 12:12:01 AM UTC 24 |
| Finished | Aug 29 12:12:04 AM UTC 24 |
| Peak memory | 223644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276 3511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_tl_i ntg_err.32763511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/14.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1222219417 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 4950837818 ps |
| CPU time | 8.17 seconds |
| Started | Aug 29 12:12:07 AM UTC 24 |
| Finished | Aug 29 12:12:17 AM UTC 24 |
| Peak memory | 223632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=1222219417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.1222219417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2421701012 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 16241088 ps |
| CPU time | 0.92 seconds |
| Started | Aug 29 12:12:05 AM UTC 24 |
| Finished | Aug 29 12:12:07 AM UTC 24 |
| Peak memory | 212808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421701012 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_rw.2421701012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/15.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2558126069 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 70818331624 ps |
| CPU time | 64.95 seconds |
| Started | Aug 29 12:12:04 AM UTC 24 |
| Finished | Aug 29 12:13:11 AM UTC 24 |
| Peak memory | 213596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 558126069 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl _passthru_mem_tl_intg_err.2558126069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/15.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3044251223 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 18047930 ps |
| CPU time | 1.06 seconds |
| Started | Aug 29 12:12:06 AM UTC 24 |
| Finished | Aug 29 12:12:08 AM UTC 24 |
| Peak memory | 212812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3044251223 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sra m_ctrl_same_csr_outstanding.3044251223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/15.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2738415765 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 142907847 ps |
| CPU time | 4.96 seconds |
| Started | Aug 29 12:12:05 AM UTC 24 |
| Finished | Aug 29 12:12:11 AM UTC 24 |
| Peak memory | 223972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738415765 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl_errors.2738415765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/15.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.863337311 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 1088078780 ps |
| CPU time | 6.23 seconds |
| Started | Aug 29 12:12:11 AM UTC 24 |
| Finished | Aug 29 12:12:18 AM UTC 24 |
| Peak memory | 223696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=863337311 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.863337311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1391077973 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 44027365 ps |
| CPU time | 0.98 seconds |
| Started | Aug 29 12:12:10 AM UTC 24 |
| Finished | Aug 29 12:12:12 AM UTC 24 |
| Peak memory | 212808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391077973 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_rw.1391077973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/16.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2496165830 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 3868025706 ps |
| CPU time | 46.98 seconds |
| Started | Aug 29 12:12:08 AM UTC 24 |
| Finished | Aug 29 12:12:57 AM UTC 24 |
| Peak memory | 213644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 496165830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl _passthru_mem_tl_intg_err.2496165830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/16.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.4126070081 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 48757969 ps |
| CPU time | 1.01 seconds |
| Started | Aug 29 12:12:11 AM UTC 24 |
| Finished | Aug 29 12:12:13 AM UTC 24 |
| Peak memory | 212532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=4126070081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sra m_ctrl_same_csr_outstanding.4126070081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/16.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2084321515 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 309261526 ps |
| CPU time | 6.17 seconds |
| Started | Aug 29 12:12:08 AM UTC 24 |
| Finished | Aug 29 12:12:16 AM UTC 24 |
| Peak memory | 223724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084321515 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl_errors.2084321515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/16.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3755711098 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 502106895 ps |
| CPU time | 3.15 seconds |
| Started | Aug 29 12:12:09 AM UTC 24 |
| Finished | Aug 29 12:12:14 AM UTC 24 |
| Peak memory | 223576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755 711098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl _intg_err.3755711098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/16.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3084682859 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 428441533 ps |
| CPU time | 5.74 seconds |
| Started | Aug 29 12:12:17 AM UTC 24 |
| Finished | Aug 29 12:12:24 AM UTC 24 |
| Peak memory | 223688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=3084682859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.3084682859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3676707467 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 37020720 ps |
| CPU time | 0.88 seconds |
| Started | Aug 29 12:12:14 AM UTC 24 |
| Finished | Aug 29 12:12:16 AM UTC 24 |
| Peak memory | 212636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676707467 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_rw.3676707467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/17.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3699704452 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 7528133271 ps |
| CPU time | 71.02 seconds |
| Started | Aug 29 12:12:12 AM UTC 24 |
| Finished | Aug 29 12:13:25 AM UTC 24 |
| Peak memory | 213596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 699704452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl _passthru_mem_tl_intg_err.3699704452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/17.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3399780697 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 15046630 ps |
| CPU time | 0.98 seconds |
| Started | Aug 29 12:12:15 AM UTC 24 |
| Finished | Aug 29 12:12:17 AM UTC 24 |
| Peak memory | 212532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3399780697 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sra m_ctrl_same_csr_outstanding.3399780697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/17.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2748149793 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 88277243 ps |
| CPU time | 5.09 seconds |
| Started | Aug 29 12:12:12 AM UTC 24 |
| Finished | Aug 29 12:12:18 AM UTC 24 |
| Peak memory | 223644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748149793 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_errors.2748149793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/17.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1574283226 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 4071403702 ps |
| CPU time | 3.01 seconds |
| Started | Aug 29 12:12:13 AM UTC 24 |
| Finished | Aug 29 12:12:17 AM UTC 24 |
| Peak memory | 213552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574 283226 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl _intg_err.1574283226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/17.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.182030809 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 1738334314 ps |
| CPU time | 5.79 seconds |
| Started | Aug 29 12:12:20 AM UTC 24 |
| Finished | Aug 29 12:12:27 AM UTC 24 |
| Peak memory | 223808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=182030809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.182030809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1147486261 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 25367245 ps |
| CPU time | 0.88 seconds |
| Started | Aug 29 12:12:18 AM UTC 24 |
| Finished | Aug 29 12:12:20 AM UTC 24 |
| Peak memory | 212464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147486261 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_rw.1147486261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/18.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.214886317 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 14087909562 ps |
| CPU time | 62.11 seconds |
| Started | Aug 29 12:12:17 AM UTC 24 |
| Finished | Aug 29 12:13:21 AM UTC 24 |
| Peak memory | 213476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 14886317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ passthru_mem_tl_intg_err.214886317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/18.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2246884137 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 35380635 ps |
| CPU time | 1.11 seconds |
| Started | Aug 29 12:12:18 AM UTC 24 |
| Finished | Aug 29 12:12:21 AM UTC 24 |
| Peak memory | 212532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2246884137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sra m_ctrl_same_csr_outstanding.2246884137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/18.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3973329639 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 157131217 ps |
| CPU time | 3.27 seconds |
| Started | Aug 29 12:12:17 AM UTC 24 |
| Finished | Aug 29 12:12:21 AM UTC 24 |
| Peak memory | 223984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973329639 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_tl_errors.3973329639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/18.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1108027760 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 846598695 ps |
| CPU time | 3.33 seconds |
| Started | Aug 29 12:12:18 AM UTC 24 |
| Finished | Aug 29 12:12:23 AM UTC 24 |
| Peak memory | 223708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108 027760 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_tl _intg_err.1108027760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/18.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3120229325 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 514086412 ps |
| CPU time | 4.75 seconds |
| Started | Aug 29 12:12:23 AM UTC 24 |
| Finished | Aug 29 12:12:29 AM UTC 24 |
| Peak memory | 223572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=3120229325 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.3120229325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1285159763 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 20456893 ps |
| CPU time | 1.07 seconds |
| Started | Aug 29 12:12:22 AM UTC 24 |
| Finished | Aug 29 12:12:24 AM UTC 24 |
| Peak memory | 212748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285159763 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_rw.1285159763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/19.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2635284891 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 15352874973 ps |
| CPU time | 45.13 seconds |
| Started | Aug 29 12:12:20 AM UTC 24 |
| Finished | Aug 29 12:13:07 AM UTC 24 |
| Peak memory | 213448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 635284891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl _passthru_mem_tl_intg_err.2635284891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/19.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2340192905 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 18755448 ps |
| CPU time | 1.07 seconds |
| Started | Aug 29 12:12:22 AM UTC 24 |
| Finished | Aug 29 12:12:24 AM UTC 24 |
| Peak memory | 212532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2340192905 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sra m_ctrl_same_csr_outstanding.2340192905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/19.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1259451696 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 531763520 ps |
| CPU time | 5.64 seconds |
| Started | Aug 29 12:12:20 AM UTC 24 |
| Finished | Aug 29 12:12:27 AM UTC 24 |
| Peak memory | 226020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259451696 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl_errors.1259451696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/19.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2515869833 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 22983509 ps |
| CPU time | 0.83 seconds |
| Started | Aug 29 12:11:22 AM UTC 24 |
| Finished | Aug 29 12:11:24 AM UTC 24 |
| Peak memory | 212464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515869 833 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_al iasing.2515869833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/2.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1974508338 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 85461623 ps |
| CPU time | 2.39 seconds |
| Started | Aug 29 12:11:22 AM UTC 24 |
| Finished | Aug 29 12:11:25 AM UTC 24 |
| Peak memory | 213620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974508 338 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_bi t_bash.1974508338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/2.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1092556084 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 45010555 ps |
| CPU time | 1.12 seconds |
| Started | Aug 29 12:11:22 AM UTC 24 |
| Finished | Aug 29 12:11:24 AM UTC 24 |
| Peak memory | 212808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092556 084 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_hw _reset.1092556084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/2.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3866245991 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 355952032 ps |
| CPU time | 6.27 seconds |
| Started | Aug 29 12:11:22 AM UTC 24 |
| Finished | Aug 29 12:11:29 AM UTC 24 |
| Peak memory | 223776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=3866245991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.3866245991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3082164175 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 16247215 ps |
| CPU time | 0.97 seconds |
| Started | Aug 29 12:11:22 AM UTC 24 |
| Finished | Aug 29 12:11:24 AM UTC 24 |
| Peak memory | 212640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082164175 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_rw.3082164175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/2.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3109901174 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 13972370312 ps |
| CPU time | 73.8 seconds |
| Started | Aug 29 12:11:22 AM UTC 24 |
| Finished | Aug 29 12:12:37 AM UTC 24 |
| Peak memory | 213796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 109901174 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ passthru_mem_tl_intg_err.3109901174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/2.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3072004176 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 28042939 ps |
| CPU time | 1.02 seconds |
| Started | Aug 29 12:11:22 AM UTC 24 |
| Finished | Aug 29 12:11:24 AM UTC 24 |
| Peak memory | 212524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3072004176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram _ctrl_same_csr_outstanding.3072004176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/2.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.82590455 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 23471953 ps |
| CPU time | 2.66 seconds |
| Started | Aug 29 12:11:22 AM UTC 24 |
| Finished | Aug 29 12:11:25 AM UTC 24 |
| Peak memory | 213548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82590455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_errors.82590455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/2.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3870845823 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 63883436 ps |
| CPU time | 1.03 seconds |
| Started | Aug 29 12:11:25 AM UTC 24 |
| Finished | Aug 29 12:11:27 AM UTC 24 |
| Peak memory | 212720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870845 823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_al iasing.3870845823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/3.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1491830324 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 187105394 ps |
| CPU time | 2.51 seconds |
| Started | Aug 29 12:11:24 AM UTC 24 |
| Finished | Aug 29 12:11:28 AM UTC 24 |
| Peak memory | 213400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491830 324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_bi t_bash.1491830324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/3.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2475217828 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 81592806 ps |
| CPU time | 0.92 seconds |
| Started | Aug 29 12:11:24 AM UTC 24 |
| Finished | Aug 29 12:11:26 AM UTC 24 |
| Peak memory | 212808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475217 828 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_hw _reset.2475217828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/3.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1172230550 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 3770638047 ps |
| CPU time | 6.76 seconds |
| Started | Aug 29 12:11:27 AM UTC 24 |
| Finished | Aug 29 12:11:35 AM UTC 24 |
| Peak memory | 223636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=1172230550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.1172230550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.4251361532 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 18394422 ps |
| CPU time | 0.91 seconds |
| Started | Aug 29 12:11:24 AM UTC 24 |
| Finished | Aug 29 12:11:26 AM UTC 24 |
| Peak memory | 212468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251361532 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_rw.4251361532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/3.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2179947865 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 7371445584 ps |
| CPU time | 73.34 seconds |
| Started | Aug 29 12:11:24 AM UTC 24 |
| Finished | Aug 29 12:12:39 AM UTC 24 |
| Peak memory | 213512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 179947865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ passthru_mem_tl_intg_err.2179947865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/3.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1950429040 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 86931374 ps |
| CPU time | 0.96 seconds |
| Started | Aug 29 12:11:27 AM UTC 24 |
| Finished | Aug 29 12:11:29 AM UTC 24 |
| Peak memory | 212144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1950429040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram _ctrl_same_csr_outstanding.1950429040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/3.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2842004234 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 440492911 ps |
| CPU time | 6.39 seconds |
| Started | Aug 29 12:11:24 AM UTC 24 |
| Finished | Aug 29 12:11:32 AM UTC 24 |
| Peak memory | 223976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842004234 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_errors.2842004234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/3.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2729737474 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 384854041 ps |
| CPU time | 2.27 seconds |
| Started | Aug 29 12:11:24 AM UTC 24 |
| Finished | Aug 29 12:11:28 AM UTC 24 |
| Peak memory | 223592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729 737474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_ intg_err.2729737474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/3.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.362139108 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 37675501 ps |
| CPU time | 0.87 seconds |
| Started | Aug 29 12:11:29 AM UTC 24 |
| Finished | Aug 29 12:11:31 AM UTC 24 |
| Peak memory | 212864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621391 08 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_ali asing.362139108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/4.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2683704035 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 1068590778 ps |
| CPU time | 2.49 seconds |
| Started | Aug 29 12:11:29 AM UTC 24 |
| Finished | Aug 29 12:11:33 AM UTC 24 |
| Peak memory | 213336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683704 035 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_bi t_bash.2683704035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/4.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1841985005 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 19129479 ps |
| CPU time | 0.94 seconds |
| Started | Aug 29 12:11:27 AM UTC 24 |
| Finished | Aug 29 12:11:29 AM UTC 24 |
| Peak memory | 212464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841985 005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_hw _reset.1841985005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/4.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3168079304 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 664965373 ps |
| CPU time | 6.91 seconds |
| Started | Aug 29 12:11:29 AM UTC 24 |
| Finished | Aug 29 12:11:37 AM UTC 24 |
| Peak memory | 223772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=3168079304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.3168079304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3160150298 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 42669075 ps |
| CPU time | 0.83 seconds |
| Started | Aug 29 12:11:27 AM UTC 24 |
| Finished | Aug 29 12:11:29 AM UTC 24 |
| Peak memory | 212468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160150298 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_rw.3160150298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/4.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.410839800 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 7357623913 ps |
| CPU time | 89.39 seconds |
| Started | Aug 29 12:11:27 AM UTC 24 |
| Finished | Aug 29 12:12:58 AM UTC 24 |
| Peak memory | 213360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 10839800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_p assthru_mem_tl_intg_err.410839800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/4.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1754388174 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 14981033 ps |
| CPU time | 1.02 seconds |
| Started | Aug 29 12:11:29 AM UTC 24 |
| Finished | Aug 29 12:11:31 AM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1754388174 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram _ctrl_same_csr_outstanding.1754388174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/4.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.317189032 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 157501289 ps |
| CPU time | 6.11 seconds |
| Started | Aug 29 12:11:27 AM UTC 24 |
| Finished | Aug 29 12:11:34 AM UTC 24 |
| Peak memory | 213720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317189032 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_errors.317189032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/4.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2705059907 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 580745967 ps |
| CPU time | 5.01 seconds |
| Started | Aug 29 12:11:27 AM UTC 24 |
| Finished | Aug 29 12:11:33 AM UTC 24 |
| Peak memory | 225692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705 059907 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_ intg_err.2705059907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/4.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1143489715 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 1462042984 ps |
| CPU time | 5.04 seconds |
| Started | Aug 29 12:11:32 AM UTC 24 |
| Finished | Aug 29 12:11:38 AM UTC 24 |
| Peak memory | 223820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=1143489715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.1143489715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.271216452 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 45575890 ps |
| CPU time | 0.87 seconds |
| Started | Aug 29 12:11:32 AM UTC 24 |
| Finished | Aug 29 12:11:33 AM UTC 24 |
| Peak memory | 212464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271216452 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_rw.271216452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/5.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2851388105 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 29397528561 ps |
| CPU time | 89.35 seconds |
| Started | Aug 29 12:11:29 AM UTC 24 |
| Finished | Aug 29 12:13:01 AM UTC 24 |
| Peak memory | 213544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 851388105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ passthru_mem_tl_intg_err.2851388105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/5.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3913425997 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 51114596 ps |
| CPU time | 0.93 seconds |
| Started | Aug 29 12:11:32 AM UTC 24 |
| Finished | Aug 29 12:11:34 AM UTC 24 |
| Peak memory | 212260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3913425997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram _ctrl_same_csr_outstanding.3913425997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/5.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.711717058 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 124004685 ps |
| CPU time | 4.01 seconds |
| Started | Aug 29 12:11:29 AM UTC 24 |
| Finished | Aug 29 12:11:34 AM UTC 24 |
| Peak memory | 223776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711717058 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_errors.711717058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/5.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.289477318 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 80365742 ps |
| CPU time | 2.04 seconds |
| Started | Aug 29 12:11:29 AM UTC 24 |
| Finished | Aug 29 12:11:32 AM UTC 24 |
| Peak memory | 223968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894 77318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_i ntg_err.289477318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/5.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3471838887 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 725689932 ps |
| CPU time | 5.27 seconds |
| Started | Aug 29 12:11:34 AM UTC 24 |
| Finished | Aug 29 12:11:40 AM UTC 24 |
| Peak memory | 223636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=3471838887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.3471838887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.492611761 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 10867865 ps |
| CPU time | 0.83 seconds |
| Started | Aug 29 12:11:34 AM UTC 24 |
| Finished | Aug 29 12:11:36 AM UTC 24 |
| Peak memory | 212644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492611761 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_rw.492611761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/6.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1899067056 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 73972912281 ps |
| CPU time | 36.11 seconds |
| Started | Aug 29 12:11:32 AM UTC 24 |
| Finished | Aug 29 12:12:09 AM UTC 24 |
| Peak memory | 213612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 899067056 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ passthru_mem_tl_intg_err.1899067056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/6.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2653717546 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 68631625 ps |
| CPU time | 0.93 seconds |
| Started | Aug 29 12:11:34 AM UTC 24 |
| Finished | Aug 29 12:11:36 AM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2653717546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram _ctrl_same_csr_outstanding.2653717546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/6.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3365238470 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 386996315 ps |
| CPU time | 5.3 seconds |
| Started | Aug 29 12:11:34 AM UTC 24 |
| Finished | Aug 29 12:11:40 AM UTC 24 |
| Peak memory | 213340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365238470 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_errors.3365238470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/6.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1162586790 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 411499989 ps |
| CPU time | 3.16 seconds |
| Started | Aug 29 12:11:34 AM UTC 24 |
| Finished | Aug 29 12:11:38 AM UTC 24 |
| Peak memory | 213676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162 586790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_ intg_err.1162586790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/6.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.4218344903 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 357314103 ps |
| CPU time | 4.96 seconds |
| Started | Aug 29 12:11:39 AM UTC 24 |
| Finished | Aug 29 12:11:45 AM UTC 24 |
| Peak memory | 223632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=4218344903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.4218344903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.4238186343 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 12068677 ps |
| CPU time | 0.99 seconds |
| Started | Aug 29 12:11:36 AM UTC 24 |
| Finished | Aug 29 12:11:38 AM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238186343 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_rw.4238186343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/7.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2152572578 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 23134394655 ps |
| CPU time | 39.74 seconds |
| Started | Aug 29 12:11:36 AM UTC 24 |
| Finished | Aug 29 12:12:17 AM UTC 24 |
| Peak memory | 213528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 152572578 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ passthru_mem_tl_intg_err.2152572578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/7.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3407220098 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 75791188 ps |
| CPU time | 1.07 seconds |
| Started | Aug 29 12:11:36 AM UTC 24 |
| Finished | Aug 29 12:11:38 AM UTC 24 |
| Peak memory | 212524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3407220098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram _ctrl_same_csr_outstanding.3407220098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/7.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1021753791 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 31957134 ps |
| CPU time | 3.46 seconds |
| Started | Aug 29 12:11:36 AM UTC 24 |
| Finished | Aug 29 12:11:41 AM UTC 24 |
| Peak memory | 213468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021753791 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_tl_errors.1021753791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/7.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.379577120 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 307852105 ps |
| CPU time | 2.23 seconds |
| Started | Aug 29 12:11:36 AM UTC 24 |
| Finished | Aug 29 12:11:40 AM UTC 24 |
| Peak memory | 223672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795 77120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_tl_i ntg_err.379577120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/7.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2673571973 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 1186451949 ps |
| CPU time | 5.63 seconds |
| Started | Aug 29 12:11:41 AM UTC 24 |
| Finished | Aug 29 12:11:48 AM UTC 24 |
| Peak memory | 223700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=2673571973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.2673571973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.4106845857 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 66148834 ps |
| CPU time | 1.02 seconds |
| Started | Aug 29 12:11:39 AM UTC 24 |
| Finished | Aug 29 12:11:41 AM UTC 24 |
| Peak memory | 212804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106845857 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_rw.4106845857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/8.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1571253369 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 14736863181 ps |
| CPU time | 81.35 seconds |
| Started | Aug 29 12:11:39 AM UTC 24 |
| Finished | Aug 29 12:13:02 AM UTC 24 |
| Peak memory | 213524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 571253369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ passthru_mem_tl_intg_err.1571253369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/8.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.709456566 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 13594835 ps |
| CPU time | 0.99 seconds |
| Started | Aug 29 12:11:41 AM UTC 24 |
| Finished | Aug 29 12:11:43 AM UTC 24 |
| Peak memory | 212700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=709456566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ ctrl_same_csr_outstanding.709456566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/8.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2171526272 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 158187147 ps |
| CPU time | 6.84 seconds |
| Started | Aug 29 12:11:39 AM UTC 24 |
| Finished | Aug 29 12:11:47 AM UTC 24 |
| Peak memory | 223696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171526272 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_errors.2171526272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/8.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3153663237 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 352220987 ps |
| CPU time | 2.13 seconds |
| Started | Aug 29 12:11:39 AM UTC 24 |
| Finished | Aug 29 12:11:42 AM UTC 24 |
| Peak memory | 223908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153 663237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_ intg_err.3153663237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/8.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3168052554 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 365063270 ps |
| CPU time | 5.87 seconds |
| Started | Aug 29 12:11:43 AM UTC 24 |
| Finished | Aug 29 12:11:50 AM UTC 24 |
| Peak memory | 223820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=3168052554 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.3168052554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.250919862 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 29073056 ps |
| CPU time | 1.01 seconds |
| Started | Aug 29 12:11:41 AM UTC 24 |
| Finished | Aug 29 12:11:43 AM UTC 24 |
| Peak memory | 212464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250919862 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_rw.250919862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/9.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2988795044 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 21380996229 ps |
| CPU time | 69.6 seconds |
| Started | Aug 29 12:11:41 AM UTC 24 |
| Finished | Aug 29 12:12:52 AM UTC 24 |
| Peak memory | 213600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 988795044 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ passthru_mem_tl_intg_err.2988795044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/9.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.732341366 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 76820233 ps |
| CPU time | 0.99 seconds |
| Started | Aug 29 12:11:43 AM UTC 24 |
| Finished | Aug 29 12:11:45 AM UTC 24 |
| Peak memory | 212528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=732341366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ ctrl_same_csr_outstanding.732341366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/9.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2265183990 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 506277343 ps |
| CPU time | 7.29 seconds |
| Started | Aug 29 12:11:41 AM UTC 24 |
| Finished | Aug 29 12:11:50 AM UTC 24 |
| Peak memory | 223716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265183990 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_errors.2265183990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/9.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.543077155 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 263312601 ps |
| CPU time | 1.86 seconds |
| Started | Aug 29 12:11:41 AM UTC 24 |
| Finished | Aug 29 12:11:44 AM UTC 24 |
| Peak memory | 212380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5430 77155 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_i ntg_err.543077155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/9.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.729636802 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 26086721200 ps |
| CPU time | 339.67 seconds |
| Started | Aug 29 12:27:22 AM UTC 24 |
| Finished | Aug 29 12:33:10 AM UTC 24 |
| Peak memory | 386668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729636802 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_access_during _key_req.729636802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/0.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_bijection.150942489 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 262130320255 ps |
| CPU time | 2329.71 seconds |
| Started | Aug 29 12:27:22 AM UTC 24 |
| Finished | Aug 29 01:06:41 AM UTC 24 |
| Peak memory | 213228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150942489 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.150942489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/0.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_executable.4125104661 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 12097305736 ps |
| CPU time | 734.99 seconds |
| Started | Aug 29 12:27:23 AM UTC 24 |
| Finished | Aug 29 12:39:49 AM UTC 24 |
| Peak memory | 386512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125104661 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executable.4125104661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/0.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.4210729352 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 6268293376 ps |
| CPU time | 70.59 seconds |
| Started | Aug 29 12:27:23 AM UTC 24 |
| Finished | Aug 29 12:28:38 AM UTC 24 |
| Peak memory | 221872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210729352 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_mem_partial_access.4210729352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/0.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.2727053902 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 10961506933 ps |
| CPU time | 158.54 seconds |
| Started | Aug 29 12:27:23 AM UTC 24 |
| Finished | Aug 29 12:30:07 AM UTC 24 |
| Peak memory | 222028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727053902 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_mem_walk.2727053902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/0.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.2467007401 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 6720391501 ps |
| CPU time | 444.85 seconds |
| Started | Aug 29 12:27:22 AM UTC 24 |
| Finished | Aug 29 12:34:56 AM UTC 24 |
| Peak memory | 382440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467007401 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multiple_keys.2467007401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/0.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.831840534 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 12747494163 ps |
| CPU time | 430.37 seconds |
| Started | Aug 29 12:27:22 AM UTC 24 |
| Finished | Aug 29 12:34:42 AM UTC 24 |
| Peak memory | 211816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831840534 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_partial_acc ess_b2b.831840534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/0.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.3753727129 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5582957919 ps |
| CPU time | 6.5 seconds |
| Started | Aug 29 12:27:23 AM UTC 24 |
| Finished | Aug 29 12:27:34 AM UTC 24 |
| Peak memory | 211896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753727129 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.3753727129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/0.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_regwen.1319165483 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 7107440334 ps |
| CPU time | 695.01 seconds |
| Started | Aug 29 12:27:23 AM UTC 24 |
| Finished | Aug 29 12:39:09 AM UTC 24 |
| Peak memory | 384552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319165483 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.1319165483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/0.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.1879708668 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 234419391 ps |
| CPU time | 1.85 seconds |
| Started | Aug 29 12:27:23 AM UTC 24 |
| Finished | Aug 29 12:27:29 AM UTC 24 |
| Peak memory | 246908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879708668 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_sec_cm.1879708668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_smoke.10698123 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 971531567 ps |
| CPU time | 9.4 seconds |
| Started | Aug 29 12:27:22 AM UTC 24 |
| Finished | Aug 29 12:27:36 AM UTC 24 |
| Peak memory | 211492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10698123 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.10698123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/0.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.278142390 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 5618845223 ps |
| CPU time | 228.38 seconds |
| Started | Aug 29 12:27:22 AM UTC 24 |
| Finished | Aug 29 12:31:18 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278142390 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_pipeline.278142390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/0.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.696400636 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 802422893 ps |
| CPU time | 50.1 seconds |
| Started | Aug 29 12:27:22 AM UTC 24 |
| Finished | Aug 29 12:28:18 AM UTC 24 |
| Peak memory | 327124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =696400636 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_t hroughput_w_partial_write.696400636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/0.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.3544576371 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 437759389000 ps |
| CPU time | 1061.84 seconds |
| Started | Aug 29 12:27:26 AM UTC 24 |
| Finished | Aug 29 12:45:19 AM UTC 24 |
| Peak memory | 388572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544576371 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_access_durin g_key_req.3544576371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/1.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_alert_test.2843480536 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 27985182 ps |
| CPU time | 0.92 seconds |
| Started | Aug 29 12:27:30 AM UTC 24 |
| Finished | Aug 29 12:27:32 AM UTC 24 |
| Peak memory | 210732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843480536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_alert_test.2843480536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/1.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_bijection.1749834000 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 269701116613 ps |
| CPU time | 2973.82 seconds |
| Started | Aug 29 12:27:24 AM UTC 24 |
| Finished | Aug 29 01:17:32 AM UTC 24 |
| Peak memory | 213264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749834000 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection.1749834000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/1.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_executable.3118171240 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 104131526988 ps |
| CPU time | 1151.86 seconds |
| Started | Aug 29 12:27:26 AM UTC 24 |
| Finished | Aug 29 12:46:52 AM UTC 24 |
| Peak memory | 386724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118171240 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executable.3118171240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/1.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.371804301 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 2700259092 ps |
| CPU time | 9.26 seconds |
| Started | Aug 29 12:27:25 AM UTC 24 |
| Finished | Aug 29 12:27:36 AM UTC 24 |
| Peak memory | 228460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 371804301 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ma x_throughput.371804301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/1.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.2594213237 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 6624640139 ps |
| CPU time | 173.36 seconds |
| Started | Aug 29 12:27:28 AM UTC 24 |
| Finished | Aug 29 12:30:25 AM UTC 24 |
| Peak memory | 228672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594213237 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_mem_partial_access.2594213237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/1.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.2427199899 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 37436403201 ps |
| CPU time | 246.25 seconds |
| Started | Aug 29 12:27:28 AM UTC 24 |
| Finished | Aug 29 12:31:39 AM UTC 24 |
| Peak memory | 221640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427199899 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_mem_walk.2427199899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/1.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.3005752759 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 10212969437 ps |
| CPU time | 261.55 seconds |
| Started | Aug 29 12:27:24 AM UTC 24 |
| Finished | Aug 29 12:31:50 AM UTC 24 |
| Peak memory | 386524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005752759 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multiple_keys.3005752759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/1.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access.2983351609 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 2797258384 ps |
| CPU time | 9.65 seconds |
| Started | Aug 29 12:27:24 AM UTC 24 |
| Finished | Aug 29 12:27:36 AM UTC 24 |
| Peak memory | 211288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983351609 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_partial_access.2983351609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/1.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_regwen.1260740764 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 2750741312 ps |
| CPU time | 388.99 seconds |
| Started | Aug 29 12:27:28 AM UTC 24 |
| Finished | Aug 29 12:34:02 AM UTC 24 |
| Peak memory | 378528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260740764 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.1260740764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/1.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_smoke.49742310 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 1073706013 ps |
| CPU time | 40.04 seconds |
| Started | Aug 29 12:27:24 AM UTC 24 |
| Finished | Aug 29 12:28:07 AM UTC 24 |
| Peak memory | 298456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49742310 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.49742310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/1.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all.2790986468 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 174814399496 ps |
| CPU time | 6917.13 seconds |
| Started | Aug 29 12:27:29 AM UTC 24 |
| Finished | Aug 29 02:23:56 AM UTC 24 |
| Peak memory | 394384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27909864 68 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all.2790986468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/1.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.681899089 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 7016259151 ps |
| CPU time | 349.06 seconds |
| Started | Aug 29 12:27:24 AM UTC 24 |
| Finished | Aug 29 12:33:20 AM UTC 24 |
| Peak memory | 211592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681899089 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_pipeline.681899089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/1.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.2443935680 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 2818592567 ps |
| CPU time | 9.98 seconds |
| Started | Aug 29 12:27:25 AM UTC 24 |
| Finished | Aug 29 12:27:37 AM UTC 24 |
| Peak memory | 228812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2443935680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ throughput_w_partial_write.2443935680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/1.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.4003735765 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 11237867678 ps |
| CPU time | 431.13 seconds |
| Started | Aug 29 12:47:55 AM UTC 24 |
| Finished | Aug 29 12:55:11 AM UTC 24 |
| Peak memory | 380436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003735765 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_access_duri ng_key_req.4003735765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/10.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_alert_test.1887373306 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 42508710 ps |
| CPU time | 1.03 seconds |
| Started | Aug 29 12:49:15 AM UTC 24 |
| Finished | Aug 29 12:49:17 AM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887373306 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_alert_test.1887373306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/10.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_bijection.144806254 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 66946462795 ps |
| CPU time | 1521.96 seconds |
| Started | Aug 29 12:45:49 AM UTC 24 |
| Finished | Aug 29 01:11:29 AM UTC 24 |
| Peak memory | 211748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144806254 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection.144806254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/10.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_executable.2434548678 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 15974678099 ps |
| CPU time | 749.24 seconds |
| Started | Aug 29 12:48:12 AM UTC 24 |
| Finished | Aug 29 01:00:50 AM UTC 24 |
| Peak memory | 382624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434548678 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executable.2434548678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/10.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.3285571036 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 36243828575 ps |
| CPU time | 163.76 seconds |
| Started | Aug 29 12:47:54 AM UTC 24 |
| Finished | Aug 29 12:50:40 AM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285571036 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_escalation.3285571036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/10.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.3315998894 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 770156974 ps |
| CPU time | 69.06 seconds |
| Started | Aug 29 12:47:13 AM UTC 24 |
| Finished | Aug 29 12:48:24 AM UTC 24 |
| Peak memory | 329120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3315998894 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ max_throughput.3315998894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/10.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.1742192322 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 1386355748 ps |
| CPU time | 98.16 seconds |
| Started | Aug 29 12:48:31 AM UTC 24 |
| Finished | Aug 29 12:50:12 AM UTC 24 |
| Peak memory | 221804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742192322 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_mem_partial_access.1742192322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/10.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.113168648 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 15759000539 ps |
| CPU time | 312.79 seconds |
| Started | Aug 29 12:48:31 AM UTC 24 |
| Finished | Aug 29 12:53:49 AM UTC 24 |
| Peak memory | 222004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113168648 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_mem_walk.113168648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/10.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.23601101 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 122902040578 ps |
| CPU time | 1154.34 seconds |
| Started | Aug 29 12:45:38 AM UTC 24 |
| Finished | Aug 29 01:05:06 AM UTC 24 |
| Peak memory | 384552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23601101 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multiple_keys.23601101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/10.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access.4037804919 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 2235266422 ps |
| CPU time | 75.75 seconds |
| Started | Aug 29 12:46:53 AM UTC 24 |
| Finished | Aug 29 12:48:11 AM UTC 24 |
| Peak memory | 335524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037804919 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_partial_access.4037804919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/10.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.1398495826 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 21050867905 ps |
| CPU time | 656.03 seconds |
| Started | Aug 29 12:46:59 AM UTC 24 |
| Finished | Aug 29 12:58:04 AM UTC 24 |
| Peak memory | 211652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398495826 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_partial_a ccess_b2b.1398495826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/10.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.2070116182 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 370043955 ps |
| CPU time | 4.72 seconds |
| Started | Aug 29 12:48:25 AM UTC 24 |
| Finished | Aug 29 12:48:31 AM UTC 24 |
| Peak memory | 211704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070116182 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.2070116182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/10.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_regwen.2884349984 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 13095122931 ps |
| CPU time | 731.84 seconds |
| Started | Aug 29 12:48:15 AM UTC 24 |
| Finished | Aug 29 01:00:36 AM UTC 24 |
| Peak memory | 390684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884349984 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.2884349984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/10.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_smoke.3774956582 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 788368774 ps |
| CPU time | 11.92 seconds |
| Started | Aug 29 12:45:35 AM UTC 24 |
| Finished | Aug 29 12:45:48 AM UTC 24 |
| Peak memory | 211500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774956582 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.3774956582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/10.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all.231922709 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 49340987375 ps |
| CPU time | 3652.29 seconds |
| Started | Aug 29 12:49:04 AM UTC 24 |
| Finished | Aug 29 01:50:34 AM UTC 24 |
| Peak memory | 400404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23192270 9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all.231922709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/10.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1752333343 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1792613754 ps |
| CPU time | 154.31 seconds |
| Started | Aug 29 12:48:53 AM UTC 24 |
| Finished | Aug 29 12:51:30 AM UTC 24 |
| Peak memory | 356192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752333343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.1752333343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/10.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.3120300398 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 3211359423 ps |
| CPU time | 309.66 seconds |
| Started | Aug 29 12:46:08 AM UTC 24 |
| Finished | Aug 29 12:51:22 AM UTC 24 |
| Peak memory | 211556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120300398 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_pipeline.3120300398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/10.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.1473430710 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 2903794043 ps |
| CPU time | 116.31 seconds |
| Started | Aug 29 12:47:16 AM UTC 24 |
| Finished | Aug 29 12:49:15 AM UTC 24 |
| Peak memory | 382420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1473430710 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl _throughput_w_partial_write.1473430710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/10.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.2993303948 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 24242122182 ps |
| CPU time | 933.21 seconds |
| Started | Aug 29 12:50:41 AM UTC 24 |
| Finished | Aug 29 01:06:23 AM UTC 24 |
| Peak memory | 388576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993303948 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_access_duri ng_key_req.2993303948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/11.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_alert_test.3685473938 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 12921784 ps |
| CPU time | 0.94 seconds |
| Started | Aug 29 12:51:40 AM UTC 24 |
| Finished | Aug 29 12:51:42 AM UTC 24 |
| Peak memory | 210816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685473938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_alert_test.3685473938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/11.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_bijection.921692692 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 501663159574 ps |
| CPU time | 2262.26 seconds |
| Started | Aug 29 12:49:36 AM UTC 24 |
| Finished | Aug 29 01:27:43 AM UTC 24 |
| Peak memory | 213228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921692692 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection.921692692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/11.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_executable.904669594 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 7507931395 ps |
| CPU time | 301.05 seconds |
| Started | Aug 29 12:50:53 AM UTC 24 |
| Finished | Aug 29 12:55:59 AM UTC 24 |
| Peak memory | 362148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904669594 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executable.904669594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/11.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.3297828233 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 24897409710 ps |
| CPU time | 36.05 seconds |
| Started | Aug 29 12:50:14 AM UTC 24 |
| Finished | Aug 29 12:50:52 AM UTC 24 |
| Peak memory | 211504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297828233 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_escalation.3297828233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/11.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.219015963 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 2254248488 ps |
| CPU time | 86.93 seconds |
| Started | Aug 29 12:50:10 AM UTC 24 |
| Finished | Aug 29 12:51:39 AM UTC 24 |
| Peak memory | 380644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 219015963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_m ax_throughput.219015963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/11.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.4171069620 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 12778424182 ps |
| CPU time | 112.72 seconds |
| Started | Aug 29 12:51:22 AM UTC 24 |
| Finished | Aug 29 12:53:17 AM UTC 24 |
| Peak memory | 222044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171069620 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_mem_partial_access.4171069620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/11.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.245647827 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 14787640685 ps |
| CPU time | 234.33 seconds |
| Started | Aug 29 12:51:12 AM UTC 24 |
| Finished | Aug 29 12:55:11 AM UTC 24 |
| Peak memory | 221812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245647827 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_mem_walk.245647827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/11.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.2832913984 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 45659867135 ps |
| CPU time | 864.19 seconds |
| Started | Aug 29 12:49:31 AM UTC 24 |
| Finished | Aug 29 01:04:04 AM UTC 24 |
| Peak memory | 382424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832913984 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multiple_keys.2832913984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/11.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access.2645935465 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 538911215 ps |
| CPU time | 11.57 seconds |
| Started | Aug 29 12:49:57 AM UTC 24 |
| Finished | Aug 29 12:50:10 AM UTC 24 |
| Peak memory | 211556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645935465 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_partial_access.2645935465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/11.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.1695266258 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 45681877246 ps |
| CPU time | 372.69 seconds |
| Started | Aug 29 12:50:03 AM UTC 24 |
| Finished | Aug 29 12:56:21 AM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695266258 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_partial_a ccess_b2b.1695266258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/11.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.1508410784 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 5599377762 ps |
| CPU time | 9.82 seconds |
| Started | Aug 29 12:51:11 AM UTC 24 |
| Finished | Aug 29 12:51:22 AM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508410784 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.1508410784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/11.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_regwen.3031748208 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 11015156878 ps |
| CPU time | 481.16 seconds |
| Started | Aug 29 12:50:53 AM UTC 24 |
| Finished | Aug 29 12:59:00 AM UTC 24 |
| Peak memory | 370348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031748208 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.3031748208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/11.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_smoke.853923691 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 1905614919 ps |
| CPU time | 15.6 seconds |
| Started | Aug 29 12:49:19 AM UTC 24 |
| Finished | Aug 29 12:49:35 AM UTC 24 |
| Peak memory | 211552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853923691 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.853923691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/11.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all.2023839208 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 41361091607 ps |
| CPU time | 2877.94 seconds |
| Started | Aug 29 12:51:32 AM UTC 24 |
| Finished | Aug 29 01:40:04 AM UTC 24 |
| Peak memory | 361564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20238392 08 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_a ll.2023839208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/11.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1761143395 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 330841313 ps |
| CPU time | 13.63 seconds |
| Started | Aug 29 12:51:24 AM UTC 24 |
| Finished | Aug 29 12:51:38 AM UTC 24 |
| Peak memory | 221872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761143395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.1761143395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/11.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.2083865749 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 12670275631 ps |
| CPU time | 360.74 seconds |
| Started | Aug 29 12:49:47 AM UTC 24 |
| Finished | Aug 29 12:55:53 AM UTC 24 |
| Peak memory | 211752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083865749 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_pipeline.2083865749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/11.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.49655625 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 3109248389 ps |
| CPU time | 57.83 seconds |
| Started | Aug 29 12:50:12 AM UTC 24 |
| Finished | Aug 29 12:51:12 AM UTC 24 |
| Peak memory | 320976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =49655625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_t hroughput_w_partial_write.49655625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/11.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.4263440275 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 20851538288 ps |
| CPU time | 1517.52 seconds |
| Started | Aug 29 12:53:19 AM UTC 24 |
| Finished | Aug 29 01:18:55 AM UTC 24 |
| Peak memory | 386668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263440275 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_access_duri ng_key_req.4263440275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/12.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_alert_test.3392265482 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 19897326 ps |
| CPU time | 0.97 seconds |
| Started | Aug 29 12:55:09 AM UTC 24 |
| Finished | Aug 29 12:55:11 AM UTC 24 |
| Peak memory | 210876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392265482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_alert_test.3392265482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/12.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_bijection.61952873 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 50663894346 ps |
| CPU time | 1919.54 seconds |
| Started | Aug 29 12:51:46 AM UTC 24 |
| Finished | Aug 29 01:24:08 AM UTC 24 |
| Peak memory | 211544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61952873 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection.61952873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/12.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_executable.102996042 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 62453662680 ps |
| CPU time | 1017.36 seconds |
| Started | Aug 29 12:53:20 AM UTC 24 |
| Finished | Aug 29 01:10:29 AM UTC 24 |
| Peak memory | 386520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102996042 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executable.102996042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/12.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.1083298642 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 19187471984 ps |
| CPU time | 129.53 seconds |
| Started | Aug 29 12:53:18 AM UTC 24 |
| Finished | Aug 29 12:55:30 AM UTC 24 |
| Peak memory | 211564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083298642 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_escalation.1083298642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/12.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.3280452282 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 1413773956 ps |
| CPU time | 18.14 seconds |
| Started | Aug 29 12:52:59 AM UTC 24 |
| Finished | Aug 29 12:53:18 AM UTC 24 |
| Peak memory | 261796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3280452282 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ max_throughput.3280452282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/12.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.2230753255 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 10706193926 ps |
| CPU time | 89.98 seconds |
| Started | Aug 29 12:54:37 AM UTC 24 |
| Finished | Aug 29 12:56:09 AM UTC 24 |
| Peak memory | 221796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230753255 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_mem_partial_access.2230753255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/12.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.2618470489 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 32851052121 ps |
| CPU time | 209.57 seconds |
| Started | Aug 29 12:54:27 AM UTC 24 |
| Finished | Aug 29 12:58:01 AM UTC 24 |
| Peak memory | 221888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618470489 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_mem_walk.2618470489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/12.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.816408000 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 81037940491 ps |
| CPU time | 1512.16 seconds |
| Started | Aug 29 12:51:43 AM UTC 24 |
| Finished | Aug 29 01:17:11 AM UTC 24 |
| Peak memory | 388636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816408000 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multiple_keys.816408000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/12.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access.3572546291 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 548976927 ps |
| CPU time | 122.11 seconds |
| Started | Aug 29 12:52:32 AM UTC 24 |
| Finished | Aug 29 12:54:36 AM UTC 24 |
| Peak memory | 378336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572546291 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_partial_access.3572546291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/12.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.4241454595 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 35667096635 ps |
| CPU time | 506.53 seconds |
| Started | Aug 29 12:52:55 AM UTC 24 |
| Finished | Aug 29 01:01:28 AM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241454595 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_partial_a ccess_b2b.4241454595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/12.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.596170578 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 677989334 ps |
| CPU time | 6.2 seconds |
| Started | Aug 29 12:54:19 AM UTC 24 |
| Finished | Aug 29 12:54:27 AM UTC 24 |
| Peak memory | 211632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596170578 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.596170578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/12.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_regwen.2555868474 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 11596402014 ps |
| CPU time | 975.52 seconds |
| Started | Aug 29 12:53:49 AM UTC 24 |
| Finished | Aug 29 01:10:17 AM UTC 24 |
| Peak memory | 380372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555868474 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.2555868474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/12.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_smoke.2220764828 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 867137525 ps |
| CPU time | 72.55 seconds |
| Started | Aug 29 12:51:40 AM UTC 24 |
| Finished | Aug 29 12:52:54 AM UTC 24 |
| Peak memory | 349660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220764828 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.2220764828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/12.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all.2205922926 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 215937305839 ps |
| CPU time | 5012.58 seconds |
| Started | Aug 29 12:55:07 AM UTC 24 |
| Finished | Aug 29 02:19:35 AM UTC 24 |
| Peak memory | 392284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22059229 26 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_a ll.2205922926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/12.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.1574249379 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 5719302287 ps |
| CPU time | 132.67 seconds |
| Started | Aug 29 12:55:05 AM UTC 24 |
| Finished | Aug 29 12:57:20 AM UTC 24 |
| Peak memory | 382752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574249379 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.1574249379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/12.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.3704497006 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 10727803830 ps |
| CPU time | 382.89 seconds |
| Started | Aug 29 12:51:56 AM UTC 24 |
| Finished | Aug 29 12:58:24 AM UTC 24 |
| Peak memory | 211628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704497006 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_pipeline.3704497006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/12.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.3212094629 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 695998357 ps |
| CPU time | 10.49 seconds |
| Started | Aug 29 12:53:08 AM UTC 24 |
| Finished | Aug 29 12:53:19 AM UTC 24 |
| Peak memory | 221552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3212094629 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl _throughput_w_partial_write.3212094629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/12.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.1719858428 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 35672840968 ps |
| CPU time | 968.32 seconds |
| Started | Aug 29 12:56:00 AM UTC 24 |
| Finished | Aug 29 01:12:19 AM UTC 24 |
| Peak memory | 384536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719858428 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_access_duri ng_key_req.1719858428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/13.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_alert_test.1242061293 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 40201173 ps |
| CPU time | 0.93 seconds |
| Started | Aug 29 12:57:15 AM UTC 24 |
| Finished | Aug 29 12:57:16 AM UTC 24 |
| Peak memory | 210876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242061293 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_alert_test.1242061293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/13.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_bijection.2295060157 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 97014285765 ps |
| CPU time | 985.48 seconds |
| Started | Aug 29 12:55:12 AM UTC 24 |
| Finished | Aug 29 01:11:50 AM UTC 24 |
| Peak memory | 211748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295060157 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection.2295060157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/13.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_executable.21221465 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 47469423549 ps |
| CPU time | 738.76 seconds |
| Started | Aug 29 12:56:03 AM UTC 24 |
| Finished | Aug 29 01:08:31 AM UTC 24 |
| Peak memory | 358040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21221465 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executable.21221465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/13.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.1425439167 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 29526500093 ps |
| CPU time | 67.64 seconds |
| Started | Aug 29 12:55:57 AM UTC 24 |
| Finished | Aug 29 12:57:06 AM UTC 24 |
| Peak memory | 211564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425439167 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_escalation.1425439167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/13.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.2390900506 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 2965593590 ps |
| CPU time | 84.24 seconds |
| Started | Aug 29 12:55:47 AM UTC 24 |
| Finished | Aug 29 12:57:14 AM UTC 24 |
| Peak memory | 343588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2390900506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ max_throughput.2390900506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/13.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.2243539906 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 10002343865 ps |
| CPU time | 161.12 seconds |
| Started | Aug 29 12:57:07 AM UTC 24 |
| Finished | Aug 29 12:59:51 AM UTC 24 |
| Peak memory | 221936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243539906 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_mem_partial_access.2243539906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/13.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.611180661 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 2156305270 ps |
| CPU time | 155.34 seconds |
| Started | Aug 29 12:56:30 AM UTC 24 |
| Finished | Aug 29 12:59:08 AM UTC 24 |
| Peak memory | 221948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611180661 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_mem_walk.611180661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/13.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.760848653 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 35289923481 ps |
| CPU time | 341.48 seconds |
| Started | Aug 29 12:55:12 AM UTC 24 |
| Finished | Aug 29 01:00:58 AM UTC 24 |
| Peak memory | 380592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760848653 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multiple_keys.760848653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/13.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access.3685502028 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 3087273351 ps |
| CPU time | 106.82 seconds |
| Started | Aug 29 12:55:21 AM UTC 24 |
| Finished | Aug 29 12:57:10 AM UTC 24 |
| Peak memory | 376356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685502028 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_partial_access.3685502028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/13.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.664507627 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 31060658373 ps |
| CPU time | 365.85 seconds |
| Started | Aug 29 12:55:30 AM UTC 24 |
| Finished | Aug 29 01:01:41 AM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664507627 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_partial_ac cess_b2b.664507627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/13.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.42225183 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 365617175 ps |
| CPU time | 6.32 seconds |
| Started | Aug 29 12:56:22 AM UTC 24 |
| Finished | Aug 29 12:56:29 AM UTC 24 |
| Peak memory | 211832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42225183 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.42225183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/13.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_regwen.1547361908 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 91921976995 ps |
| CPU time | 1184.34 seconds |
| Started | Aug 29 12:56:11 AM UTC 24 |
| Finished | Aug 29 01:16:09 AM UTC 24 |
| Peak memory | 388764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547361908 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.1547361908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/13.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_smoke.2340438868 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 2844473528 ps |
| CPU time | 33.56 seconds |
| Started | Aug 29 12:55:12 AM UTC 24 |
| Finished | Aug 29 12:55:47 AM UTC 24 |
| Peak memory | 282368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340438868 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.2340438868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/13.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all.2480639019 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 173133505403 ps |
| CPU time | 3859.83 seconds |
| Started | Aug 29 12:57:11 AM UTC 24 |
| Finished | Aug 29 02:02:13 AM UTC 24 |
| Peak memory | 392356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24806390 19 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_a ll.2480639019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/13.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.3019132457 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 1027402741 ps |
| CPU time | 20.54 seconds |
| Started | Aug 29 12:57:11 AM UTC 24 |
| Finished | Aug 29 12:57:33 AM UTC 24 |
| Peak memory | 221872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019132457 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.3019132457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/13.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.2755041878 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 4341380158 ps |
| CPU time | 349.43 seconds |
| Started | Aug 29 12:55:14 AM UTC 24 |
| Finished | Aug 29 01:01:08 AM UTC 24 |
| Peak memory | 211888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755041878 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_pipeline.2755041878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/13.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.1609846673 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 1473458420 ps |
| CPU time | 75.36 seconds |
| Started | Aug 29 12:55:54 AM UTC 24 |
| Finished | Aug 29 12:57:11 AM UTC 24 |
| Peak memory | 353764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1609846673 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl _throughput_w_partial_write.1609846673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/13.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.2673758835 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 10586743679 ps |
| CPU time | 837.71 seconds |
| Started | Aug 29 12:59:10 AM UTC 24 |
| Finished | Aug 29 01:13:17 AM UTC 24 |
| Peak memory | 388560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673758835 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_access_duri ng_key_req.2673758835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/14.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_alert_test.1451499226 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 39908173 ps |
| CPU time | 0.94 seconds |
| Started | Aug 29 01:00:51 AM UTC 24 |
| Finished | Aug 29 01:00:53 AM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451499226 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_alert_test.1451499226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/14.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_bijection.1791567612 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 463789556384 ps |
| CPU time | 1061 seconds |
| Started | Aug 29 12:57:34 AM UTC 24 |
| Finished | Aug 29 01:15:28 AM UTC 24 |
| Peak memory | 211624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791567612 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection.1791567612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/14.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_executable.2687176627 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 4197569274 ps |
| CPU time | 207.2 seconds |
| Started | Aug 29 12:59:24 AM UTC 24 |
| Finished | Aug 29 01:02:54 AM UTC 24 |
| Peak memory | 360092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687176627 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executable.2687176627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/14.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.359176224 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 24983850418 ps |
| CPU time | 94.77 seconds |
| Started | Aug 29 12:59:02 AM UTC 24 |
| Finished | Aug 29 01:00:39 AM UTC 24 |
| Peak memory | 211576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359176224 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_escalation.359176224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/14.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.172225200 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 2961765039 ps |
| CPU time | 55.71 seconds |
| Started | Aug 29 12:58:25 AM UTC 24 |
| Finished | Aug 29 12:59:23 AM UTC 24 |
| Peak memory | 341468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 172225200 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_m ax_throughput.172225200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/14.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.3276580914 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 9809601436 ps |
| CPU time | 105.82 seconds |
| Started | Aug 29 01:00:02 AM UTC 24 |
| Finished | Aug 29 01:01:53 AM UTC 24 |
| Peak memory | 228896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276580914 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_mem_partial_access.3276580914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/14.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.2296517824 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 4111160589 ps |
| CPU time | 293.01 seconds |
| Started | Aug 29 12:59:59 AM UTC 24 |
| Finished | Aug 29 01:04:56 AM UTC 24 |
| Peak memory | 221932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296517824 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_mem_walk.2296517824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/14.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.2979621507 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 66063574500 ps |
| CPU time | 940.04 seconds |
| Started | Aug 29 12:57:21 AM UTC 24 |
| Finished | Aug 29 01:13:11 AM UTC 24 |
| Peak memory | 374244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979621507 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multiple_keys.2979621507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/14.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access.625332947 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 7245348338 ps |
| CPU time | 26.55 seconds |
| Started | Aug 29 12:58:02 AM UTC 24 |
| Finished | Aug 29 12:58:30 AM UTC 24 |
| Peak memory | 269848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625332947 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_partial_access.625332947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/14.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.2029181748 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 43727933612 ps |
| CPU time | 301.59 seconds |
| Started | Aug 29 12:58:04 AM UTC 24 |
| Finished | Aug 29 01:03:10 AM UTC 24 |
| Peak memory | 211844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029181748 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_partial_a ccess_b2b.2029181748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/14.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.1395524145 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 1972916009 ps |
| CPU time | 4.96 seconds |
| Started | Aug 29 12:59:52 AM UTC 24 |
| Finished | Aug 29 12:59:58 AM UTC 24 |
| Peak memory | 211704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395524145 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.1395524145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/14.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_regwen.1257538250 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 13004084663 ps |
| CPU time | 734.45 seconds |
| Started | Aug 29 12:59:36 AM UTC 24 |
| Finished | Aug 29 01:11:59 AM UTC 24 |
| Peak memory | 382684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257538250 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.1257538250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/14.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_smoke.1701246031 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 1686696051 ps |
| CPU time | 29.82 seconds |
| Started | Aug 29 12:57:18 AM UTC 24 |
| Finished | Aug 29 12:57:49 AM UTC 24 |
| Peak memory | 290412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701246031 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.1701246031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/14.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.2453982989 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1043743724 ps |
| CPU time | 20.02 seconds |
| Started | Aug 29 01:00:36 AM UTC 24 |
| Finished | Aug 29 01:00:58 AM UTC 24 |
| Peak memory | 222204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453982989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.2453982989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/14.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.332154202 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 15741330995 ps |
| CPU time | 368.89 seconds |
| Started | Aug 29 12:57:50 AM UTC 24 |
| Finished | Aug 29 01:04:04 AM UTC 24 |
| Peak memory | 211512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332154202 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_pipeline.332154202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/14.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.813497514 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 946500543 ps |
| CPU time | 63.09 seconds |
| Started | Aug 29 12:58:30 AM UTC 24 |
| Finished | Aug 29 12:59:35 AM UTC 24 |
| Peak memory | 353684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =813497514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ throughput_w_partial_write.813497514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/14.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.2738082544 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 6338433819 ps |
| CPU time | 320.61 seconds |
| Started | Aug 29 01:02:00 AM UTC 24 |
| Finished | Aug 29 01:07:25 AM UTC 24 |
| Peak memory | 382496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738082544 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_access_duri ng_key_req.2738082544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/15.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_alert_test.1470098404 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 69130653 ps |
| CPU time | 1.06 seconds |
| Started | Aug 29 01:04:05 AM UTC 24 |
| Finished | Aug 29 01:04:07 AM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470098404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_alert_test.1470098404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/15.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_bijection.2568444 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 81234449322 ps |
| CPU time | 1680.84 seconds |
| Started | Aug 29 01:00:59 AM UTC 24 |
| Finished | Aug 29 01:29:19 AM UTC 24 |
| Peak memory | 213208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568444 -assert nopostproc +UVM_TESTN AME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection.2568444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/15.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_executable.2660954557 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 14285051083 ps |
| CPU time | 843.28 seconds |
| Started | Aug 29 01:02:25 AM UTC 24 |
| Finished | Aug 29 01:16:39 AM UTC 24 |
| Peak memory | 386528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660954557 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executable.2660954557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/15.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.4004365725 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 11456733449 ps |
| CPU time | 138.6 seconds |
| Started | Aug 29 01:01:58 AM UTC 24 |
| Finished | Aug 29 01:04:19 AM UTC 24 |
| Peak memory | 221804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004365725 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_escalation.4004365725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/15.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.1362339521 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 1945087403 ps |
| CPU time | 39.96 seconds |
| Started | Aug 29 01:01:42 AM UTC 24 |
| Finished | Aug 29 01:02:24 AM UTC 24 |
| Peak memory | 302760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1362339521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ max_throughput.1362339521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/15.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.1943184202 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 6023044656 ps |
| CPU time | 118.44 seconds |
| Started | Aug 29 01:03:11 AM UTC 24 |
| Finished | Aug 29 01:05:12 AM UTC 24 |
| Peak memory | 222044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943184202 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_mem_partial_access.1943184202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/15.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.261964742 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 65674410711 ps |
| CPU time | 294.74 seconds |
| Started | Aug 29 01:03:07 AM UTC 24 |
| Finished | Aug 29 01:08:06 AM UTC 24 |
| Peak memory | 222016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261964742 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_mem_walk.261964742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/15.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.1949321013 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 49437623275 ps |
| CPU time | 830.18 seconds |
| Started | Aug 29 01:00:59 AM UTC 24 |
| Finished | Aug 29 01:14:58 AM UTC 24 |
| Peak memory | 386384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949321013 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multiple_keys.1949321013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/15.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access.2311675991 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 1818374400 ps |
| CPU time | 47.42 seconds |
| Started | Aug 29 01:01:09 AM UTC 24 |
| Finished | Aug 29 01:01:58 AM UTC 24 |
| Peak memory | 312808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311675991 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_partial_access.2311675991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/15.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.1121704549 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 14751752120 ps |
| CPU time | 409.16 seconds |
| Started | Aug 29 01:01:29 AM UTC 24 |
| Finished | Aug 29 01:08:24 AM UTC 24 |
| Peak memory | 211568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121704549 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_partial_a ccess_b2b.1121704549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/15.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.2991540040 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 5556353155 ps |
| CPU time | 5.29 seconds |
| Started | Aug 29 01:03:00 AM UTC 24 |
| Finished | Aug 29 01:03:06 AM UTC 24 |
| Peak memory | 211840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991540040 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.2991540040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/15.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_regwen.2778389381 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 14073427621 ps |
| CPU time | 681.65 seconds |
| Started | Aug 29 01:02:55 AM UTC 24 |
| Finished | Aug 29 01:14:25 AM UTC 24 |
| Peak memory | 384472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778389381 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.2778389381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/15.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_smoke.2005968199 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 356064892 ps |
| CPU time | 6.84 seconds |
| Started | Aug 29 01:00:54 AM UTC 24 |
| Finished | Aug 29 01:01:02 AM UTC 24 |
| Peak memory | 211480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005968199 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.2005968199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/15.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all.729134565 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 116275932447 ps |
| CPU time | 4071.19 seconds |
| Started | Aug 29 01:04:05 AM UTC 24 |
| Finished | Aug 29 02:12:37 AM UTC 24 |
| Peak memory | 400820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72913456 5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all.729134565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/15.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.626595312 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 3339357426 ps |
| CPU time | 64.72 seconds |
| Started | Aug 29 01:03:38 AM UTC 24 |
| Finished | Aug 29 01:04:45 AM UTC 24 |
| Peak memory | 259664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626595312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.626595312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/15.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.1829711920 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 3212909403 ps |
| CPU time | 273.4 seconds |
| Started | Aug 29 01:01:03 AM UTC 24 |
| Finished | Aug 29 01:05:40 AM UTC 24 |
| Peak memory | 211632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829711920 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_pipeline.1829711920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/15.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.23298459 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 780597843 ps |
| CPU time | 64.45 seconds |
| Started | Aug 29 01:01:53 AM UTC 24 |
| Finished | Aug 29 01:02:59 AM UTC 24 |
| Peak memory | 337384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =23298459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_t hroughput_w_partial_write.23298459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/15.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.2630658682 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 37234327732 ps |
| CPU time | 724.12 seconds |
| Started | Aug 29 01:05:41 AM UTC 24 |
| Finished | Aug 29 01:17:54 AM UTC 24 |
| Peak memory | 366044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630658682 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_access_duri ng_key_req.2630658682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/16.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_alert_test.1017543708 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 15139550 ps |
| CPU time | 1.07 seconds |
| Started | Aug 29 01:07:30 AM UTC 24 |
| Finished | Aug 29 01:07:33 AM UTC 24 |
| Peak memory | 210876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017543708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_alert_test.1017543708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/16.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_bijection.1878985299 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 27957857632 ps |
| CPU time | 2352.96 seconds |
| Started | Aug 29 01:04:46 AM UTC 24 |
| Finished | Aug 29 01:44:26 AM UTC 24 |
| Peak memory | 213316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878985299 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection.1878985299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/16.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_executable.2908439298 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 9387840999 ps |
| CPU time | 643.17 seconds |
| Started | Aug 29 01:06:25 AM UTC 24 |
| Finished | Aug 29 01:17:16 AM UTC 24 |
| Peak memory | 386592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908439298 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executable.2908439298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/16.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.285584287 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 19813439798 ps |
| CPU time | 63.55 seconds |
| Started | Aug 29 01:05:38 AM UTC 24 |
| Finished | Aug 29 01:06:44 AM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285584287 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_escalation.285584287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/16.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.2574456594 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 1399416792 ps |
| CPU time | 20.78 seconds |
| Started | Aug 29 01:05:13 AM UTC 24 |
| Finished | Aug 29 01:05:35 AM UTC 24 |
| Peak memory | 255392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2574456594 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ max_throughput.2574456594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/16.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.2626446657 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 5116306689 ps |
| CPU time | 114.72 seconds |
| Started | Aug 29 01:06:53 AM UTC 24 |
| Finished | Aug 29 01:08:50 AM UTC 24 |
| Peak memory | 228892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626446657 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_mem_partial_access.2626446657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/16.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.1845012279 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 17942871273 ps |
| CPU time | 390.19 seconds |
| Started | Aug 29 01:06:51 AM UTC 24 |
| Finished | Aug 29 01:13:26 AM UTC 24 |
| Peak memory | 221932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845012279 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_mem_walk.1845012279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/16.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.2522658715 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 4981216069 ps |
| CPU time | 146.6 seconds |
| Started | Aug 29 01:04:21 AM UTC 24 |
| Finished | Aug 29 01:06:50 AM UTC 24 |
| Peak memory | 380376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522658715 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multiple_keys.2522658715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/16.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access.1051873758 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 5198380967 ps |
| CPU time | 33.58 seconds |
| Started | Aug 29 01:05:02 AM UTC 24 |
| Finished | Aug 29 01:05:37 AM UTC 24 |
| Peak memory | 211564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051873758 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_partial_access.1051873758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/16.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.2919101020 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 17902045985 ps |
| CPU time | 473.77 seconds |
| Started | Aug 29 01:05:07 AM UTC 24 |
| Finished | Aug 29 01:13:07 AM UTC 24 |
| Peak memory | 211760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919101020 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_partial_a ccess_b2b.2919101020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/16.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.2147211979 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 714941378 ps |
| CPU time | 5.77 seconds |
| Started | Aug 29 01:06:45 AM UTC 24 |
| Finished | Aug 29 01:06:52 AM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147211979 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.2147211979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/16.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_regwen.3450356489 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 747255282 ps |
| CPU time | 43.26 seconds |
| Started | Aug 29 01:06:42 AM UTC 24 |
| Finished | Aug 29 01:07:27 AM UTC 24 |
| Peak memory | 306796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450356489 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.3450356489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/16.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_smoke.647388330 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 4114015703 ps |
| CPU time | 50.89 seconds |
| Started | Aug 29 01:04:09 AM UTC 24 |
| Finished | Aug 29 01:05:01 AM UTC 24 |
| Peak memory | 325332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647388330 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.647388330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/16.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all.487599717 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 52852087991 ps |
| CPU time | 2858.1 seconds |
| Started | Aug 29 01:07:27 AM UTC 24 |
| Finished | Aug 29 01:55:35 AM UTC 24 |
| Peak memory | 390240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48759971 7 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all.487599717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/16.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.2919991169 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 107633251 ps |
| CPU time | 11.48 seconds |
| Started | Aug 29 01:07:26 AM UTC 24 |
| Finished | Aug 29 01:07:39 AM UTC 24 |
| Peak memory | 221808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919991169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.2919991169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/16.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.3501426059 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 10215028689 ps |
| CPU time | 275.95 seconds |
| Started | Aug 29 01:04:57 AM UTC 24 |
| Finished | Aug 29 01:09:37 AM UTC 24 |
| Peak memory | 211760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501426059 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_pipeline.3501426059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/16.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.3694895693 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 3721904781 ps |
| CPU time | 111.41 seconds |
| Started | Aug 29 01:05:36 AM UTC 24 |
| Finished | Aug 29 01:07:30 AM UTC 24 |
| Peak memory | 382504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3694895693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl _throughput_w_partial_write.3694895693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/16.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.202223110 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 14867619146 ps |
| CPU time | 916.4 seconds |
| Started | Aug 29 01:08:51 AM UTC 24 |
| Finished | Aug 29 01:24:18 AM UTC 24 |
| Peak memory | 388768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202223110 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_access_durin g_key_req.202223110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/17.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_alert_test.3827664431 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 19340192 ps |
| CPU time | 1.02 seconds |
| Started | Aug 29 01:10:30 AM UTC 24 |
| Finished | Aug 29 01:10:32 AM UTC 24 |
| Peak memory | 210876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827664431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_alert_test.3827664431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/17.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_bijection.554633389 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 101317992272 ps |
| CPU time | 2700.92 seconds |
| Started | Aug 29 01:07:42 AM UTC 24 |
| Finished | Aug 29 01:53:13 AM UTC 24 |
| Peak memory | 213032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554633389 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection.554633389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/17.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_executable.2267170733 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 30186301473 ps |
| CPU time | 440.47 seconds |
| Started | Aug 29 01:08:58 AM UTC 24 |
| Finished | Aug 29 01:16:23 AM UTC 24 |
| Peak memory | 380448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267170733 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executable.2267170733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/17.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.2102536424 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 25946097575 ps |
| CPU time | 99.2 seconds |
| Started | Aug 29 01:08:33 AM UTC 24 |
| Finished | Aug 29 01:10:15 AM UTC 24 |
| Peak memory | 226044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102536424 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_escalation.2102536424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/17.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.2323266187 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 2987115708 ps |
| CPU time | 91.78 seconds |
| Started | Aug 29 01:08:25 AM UTC 24 |
| Finished | Aug 29 01:09:59 AM UTC 24 |
| Peak memory | 351780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2323266187 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ max_throughput.2323266187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/17.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.2512092673 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 24183983844 ps |
| CPU time | 208.69 seconds |
| Started | Aug 29 01:10:14 AM UTC 24 |
| Finished | Aug 29 01:13:46 AM UTC 24 |
| Peak memory | 229024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512092673 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_mem_partial_access.2512092673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/17.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.122493793 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 37595896375 ps |
| CPU time | 522.99 seconds |
| Started | Aug 29 01:10:08 AM UTC 24 |
| Finished | Aug 29 01:18:58 AM UTC 24 |
| Peak memory | 211696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122493793 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_mem_walk.122493793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/17.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.1902496559 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 42712707283 ps |
| CPU time | 1140.38 seconds |
| Started | Aug 29 01:07:40 AM UTC 24 |
| Finished | Aug 29 01:26:54 AM UTC 24 |
| Peak memory | 388564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902496559 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multiple_keys.1902496559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/17.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access.3938532967 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 829842235 ps |
| CPU time | 24.99 seconds |
| Started | Aug 29 01:08:06 AM UTC 24 |
| Finished | Aug 29 01:08:33 AM UTC 24 |
| Peak memory | 211704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938532967 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_partial_access.3938532967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/17.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.3584237462 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 13122738417 ps |
| CPU time | 458.18 seconds |
| Started | Aug 29 01:08:07 AM UTC 24 |
| Finished | Aug 29 01:15:52 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584237462 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_partial_a ccess_b2b.3584237462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/17.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.3677210035 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 361204596 ps |
| CPU time | 6.18 seconds |
| Started | Aug 29 01:10:00 AM UTC 24 |
| Finished | Aug 29 01:10:07 AM UTC 24 |
| Peak memory | 211832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677210035 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.3677210035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/17.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_regwen.2719043821 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 16628129895 ps |
| CPU time | 1066.72 seconds |
| Started | Aug 29 01:09:38 AM UTC 24 |
| Finished | Aug 29 01:27:37 AM UTC 24 |
| Peak memory | 388844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719043821 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.2719043821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/17.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_smoke.3889498806 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 2658373356 ps |
| CPU time | 29.83 seconds |
| Started | Aug 29 01:07:34 AM UTC 24 |
| Finished | Aug 29 01:08:05 AM UTC 24 |
| Peak memory | 277976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889498806 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.3889498806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/17.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all.503788997 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 56715136554 ps |
| CPU time | 5868.04 seconds |
| Started | Aug 29 01:10:18 AM UTC 24 |
| Finished | Aug 29 02:49:07 AM UTC 24 |
| Peak memory | 404592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50378899 7 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all.503788997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/17.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.1422109344 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 234161385 ps |
| CPU time | 12.15 seconds |
| Started | Aug 29 01:10:15 AM UTC 24 |
| Finished | Aug 29 01:10:29 AM UTC 24 |
| Peak memory | 221884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422109344 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.1422109344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/17.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.251033853 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 16222450296 ps |
| CPU time | 243.93 seconds |
| Started | Aug 29 01:07:51 AM UTC 24 |
| Finished | Aug 29 01:11:58 AM UTC 24 |
| Peak memory | 211648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251033853 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_pipeline.251033853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/17.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.2550412916 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 3260694291 ps |
| CPU time | 100.57 seconds |
| Started | Aug 29 01:08:31 AM UTC 24 |
| Finished | Aug 29 01:10:14 AM UTC 24 |
| Peak memory | 382684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2550412916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl _throughput_w_partial_write.2550412916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/17.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.1839078020 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 86977390396 ps |
| CPU time | 1034.08 seconds |
| Started | Aug 29 01:12:29 AM UTC 24 |
| Finished | Aug 29 01:29:54 AM UTC 24 |
| Peak memory | 384464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839078020 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_access_duri ng_key_req.1839078020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/18.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_alert_test.2290084051 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 41870475 ps |
| CPU time | 1.01 seconds |
| Started | Aug 29 01:14:26 AM UTC 24 |
| Finished | Aug 29 01:14:28 AM UTC 24 |
| Peak memory | 210876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290084051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_alert_test.2290084051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/18.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_bijection.493619702 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 27662836601 ps |
| CPU time | 1984.7 seconds |
| Started | Aug 29 01:10:58 AM UTC 24 |
| Finished | Aug 29 01:44:28 AM UTC 24 |
| Peak memory | 213296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493619702 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection.493619702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/18.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_executable.2220543799 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 27152702060 ps |
| CPU time | 926.31 seconds |
| Started | Aug 29 01:13:07 AM UTC 24 |
| Finished | Aug 29 01:28:44 AM UTC 24 |
| Peak memory | 382428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220543799 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executable.2220543799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/18.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.3366122637 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 22924825710 ps |
| CPU time | 142.14 seconds |
| Started | Aug 29 01:12:20 AM UTC 24 |
| Finished | Aug 29 01:14:44 AM UTC 24 |
| Peak memory | 221876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366122637 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_escalation.3366122637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/18.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.1620799275 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 1417111112 ps |
| CPU time | 27.03 seconds |
| Started | Aug 29 01:12:00 AM UTC 24 |
| Finished | Aug 29 01:12:28 AM UTC 24 |
| Peak memory | 279968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1620799275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ max_throughput.1620799275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/18.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.2659235179 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 5356750416 ps |
| CPU time | 123.06 seconds |
| Started | Aug 29 01:13:28 AM UTC 24 |
| Finished | Aug 29 01:15:33 AM UTC 24 |
| Peak memory | 221928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659235179 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_mem_partial_access.2659235179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/18.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.92971733 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 21005651686 ps |
| CPU time | 346.57 seconds |
| Started | Aug 29 01:13:26 AM UTC 24 |
| Finished | Aug 29 01:19:18 AM UTC 24 |
| Peak memory | 222016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92971733 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_mem_walk.92971733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/18.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.3082439837 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 72259821171 ps |
| CPU time | 295.12 seconds |
| Started | Aug 29 01:10:33 AM UTC 24 |
| Finished | Aug 29 01:15:32 AM UTC 24 |
| Peak memory | 312848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082439837 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multiple_keys.3082439837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/18.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access.1635765783 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 1480748582 ps |
| CPU time | 22.73 seconds |
| Started | Aug 29 01:11:51 AM UTC 24 |
| Finished | Aug 29 01:12:15 AM UTC 24 |
| Peak memory | 211500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635765783 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_partial_access.1635765783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/18.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.2002745510 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 5389936161 ps |
| CPU time | 292.51 seconds |
| Started | Aug 29 01:11:59 AM UTC 24 |
| Finished | Aug 29 01:16:56 AM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002745510 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_partial_a ccess_b2b.2002745510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/18.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.4079626708 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 468024967 ps |
| CPU time | 6.07 seconds |
| Started | Aug 29 01:13:18 AM UTC 24 |
| Finished | Aug 29 01:13:25 AM UTC 24 |
| Peak memory | 211704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079626708 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.4079626708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/18.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_regwen.583716553 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 11368059040 ps |
| CPU time | 820.84 seconds |
| Started | Aug 29 01:13:12 AM UTC 24 |
| Finished | Aug 29 01:27:01 AM UTC 24 |
| Peak memory | 384484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583716553 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.583716553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/18.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_smoke.3242109657 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 1682696647 ps |
| CPU time | 25.98 seconds |
| Started | Aug 29 01:10:30 AM UTC 24 |
| Finished | Aug 29 01:10:57 AM UTC 24 |
| Peak memory | 211500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242109657 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.3242109657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/18.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all.1658420765 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 51356628232 ps |
| CPU time | 3354.24 seconds |
| Started | Aug 29 01:14:07 AM UTC 24 |
| Finished | Aug 29 02:10:34 AM UTC 24 |
| Peak memory | 390252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16584207 65 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_a ll.1658420765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/18.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.3380149803 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 1750015073 ps |
| CPU time | 107.8 seconds |
| Started | Aug 29 01:13:47 AM UTC 24 |
| Finished | Aug 29 01:15:37 AM UTC 24 |
| Peak memory | 228020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380149803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.3380149803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/18.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.3376954384 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 20591945028 ps |
| CPU time | 329.32 seconds |
| Started | Aug 29 01:11:30 AM UTC 24 |
| Finished | Aug 29 01:17:04 AM UTC 24 |
| Peak memory | 211556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376954384 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_pipeline.3376954384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/18.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.3594857490 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 11154312715 ps |
| CPU time | 107.66 seconds |
| Started | Aug 29 01:12:16 AM UTC 24 |
| Finished | Aug 29 01:14:06 AM UTC 24 |
| Peak memory | 380376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3594857490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl _throughput_w_partial_write.3594857490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/18.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.1496212621 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 57329588052 ps |
| CPU time | 1406.7 seconds |
| Started | Aug 29 01:15:55 AM UTC 24 |
| Finished | Aug 29 01:39:38 AM UTC 24 |
| Peak memory | 386520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496212621 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_access_duri ng_key_req.1496212621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/19.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_alert_test.2914148163 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 43899478 ps |
| CPU time | 0.94 seconds |
| Started | Aug 29 01:17:05 AM UTC 24 |
| Finished | Aug 29 01:17:08 AM UTC 24 |
| Peak memory | 210876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914148163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_alert_test.2914148163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/19.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_bijection.2520092853 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 67546377227 ps |
| CPU time | 1888.01 seconds |
| Started | Aug 29 01:14:54 AM UTC 24 |
| Finished | Aug 29 01:46:45 AM UTC 24 |
| Peak memory | 213104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520092853 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection.2520092853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/19.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_executable.4108145819 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 49469392707 ps |
| CPU time | 1197.06 seconds |
| Started | Aug 29 01:16:05 AM UTC 24 |
| Finished | Aug 29 01:36:15 AM UTC 24 |
| Peak memory | 388640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108145819 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executable.4108145819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/19.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.911262448 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 40653311242 ps |
| CPU time | 105.74 seconds |
| Started | Aug 29 01:15:52 AM UTC 24 |
| Finished | Aug 29 01:17:40 AM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911262448 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_escalation.911262448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/19.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.3820132937 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 738035639 ps |
| CPU time | 29.03 seconds |
| Started | Aug 29 01:15:34 AM UTC 24 |
| Finished | Aug 29 01:16:05 AM UTC 24 |
| Peak memory | 277920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3820132937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ max_throughput.3820132937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/19.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.2944235944 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 17499324806 ps |
| CPU time | 202.58 seconds |
| Started | Aug 29 01:16:25 AM UTC 24 |
| Finished | Aug 29 01:19:51 AM UTC 24 |
| Peak memory | 222072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944235944 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_mem_partial_access.2944235944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/19.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.1313912057 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 43038059597 ps |
| CPU time | 257.48 seconds |
| Started | Aug 29 01:16:18 AM UTC 24 |
| Finished | Aug 29 01:20:39 AM UTC 24 |
| Peak memory | 221888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313912057 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_mem_walk.1313912057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/19.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.1909867231 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 152061105813 ps |
| CPU time | 729.03 seconds |
| Started | Aug 29 01:14:45 AM UTC 24 |
| Finished | Aug 29 01:27:03 AM UTC 24 |
| Peak memory | 388564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909867231 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multiple_keys.1909867231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/19.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access.2916639326 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 4860131153 ps |
| CPU time | 38.17 seconds |
| Started | Aug 29 01:15:29 AM UTC 24 |
| Finished | Aug 29 01:16:09 AM UTC 24 |
| Peak memory | 211632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916639326 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_partial_access.2916639326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/19.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.3972115647 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 13387566896 ps |
| CPU time | 351.58 seconds |
| Started | Aug 29 01:15:33 AM UTC 24 |
| Finished | Aug 29 01:21:30 AM UTC 24 |
| Peak memory | 211776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972115647 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_partial_a ccess_b2b.3972115647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/19.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.614306666 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 353873668 ps |
| CPU time | 6.39 seconds |
| Started | Aug 29 01:16:09 AM UTC 24 |
| Finished | Aug 29 01:16:17 AM UTC 24 |
| Peak memory | 211696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614306666 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.614306666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/19.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_regwen.656523916 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 12838358758 ps |
| CPU time | 958.56 seconds |
| Started | Aug 29 01:16:09 AM UTC 24 |
| Finished | Aug 29 01:32:18 AM UTC 24 |
| Peak memory | 388564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656523916 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.656523916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/19.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_smoke.4012626292 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 3357686893 ps |
| CPU time | 23.37 seconds |
| Started | Aug 29 01:14:29 AM UTC 24 |
| Finished | Aug 29 01:14:54 AM UTC 24 |
| Peak memory | 211616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012626292 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.4012626292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/19.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all.3041111401 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 118389665946 ps |
| CPU time | 3653.52 seconds |
| Started | Aug 29 01:16:57 AM UTC 24 |
| Finished | Aug 29 02:18:31 AM UTC 24 |
| Peak memory | 398436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30411114 01 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_a ll.3041111401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/19.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.2848084876 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 4641271124 ps |
| CPU time | 67.78 seconds |
| Started | Aug 29 01:16:40 AM UTC 24 |
| Finished | Aug 29 01:17:49 AM UTC 24 |
| Peak memory | 222184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848084876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.2848084876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/19.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.2215557050 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 5414738521 ps |
| CPU time | 409.62 seconds |
| Started | Aug 29 01:14:58 AM UTC 24 |
| Finished | Aug 29 01:21:54 AM UTC 24 |
| Peak memory | 211556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215557050 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_pipeline.2215557050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/19.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.263289599 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 2802778951 ps |
| CPU time | 14.81 seconds |
| Started | Aug 29 01:15:38 AM UTC 24 |
| Finished | Aug 29 01:15:54 AM UTC 24 |
| Peak memory | 261592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =263289599 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ throughput_w_partial_write.263289599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/19.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.3582692017 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 42235966701 ps |
| CPU time | 1162.47 seconds |
| Started | Aug 29 12:27:37 AM UTC 24 |
| Finished | Aug 29 12:47:13 AM UTC 24 |
| Peak memory | 368104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582692017 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_access_durin g_key_req.3582692017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/2.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_alert_test.3350248534 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 29397636 ps |
| CPU time | 0.99 seconds |
| Started | Aug 29 12:28:17 AM UTC 24 |
| Finished | Aug 29 12:28:19 AM UTC 24 |
| Peak memory | 210872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350248534 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_alert_test.3350248534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/2.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_bijection.2821458948 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 64904802058 ps |
| CPU time | 2384.04 seconds |
| Started | Aug 29 12:27:32 AM UTC 24 |
| Finished | Aug 29 01:07:41 AM UTC 24 |
| Peak memory | 213240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821458948 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection.2821458948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/2.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_executable.387548519 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 11283661190 ps |
| CPU time | 861.56 seconds |
| Started | Aug 29 12:27:37 AM UTC 24 |
| Finished | Aug 29 12:42:09 AM UTC 24 |
| Peak memory | 384544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387548519 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executable.387548519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/2.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.900493780 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 143258763037 ps |
| CPU time | 201.82 seconds |
| Started | Aug 29 12:27:37 AM UTC 24 |
| Finished | Aug 29 12:31:02 AM UTC 24 |
| Peak memory | 211644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900493780 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_escalation.900493780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/2.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.2207258320 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 3060922934 ps |
| CPU time | 77.21 seconds |
| Started | Aug 29 12:27:37 AM UTC 24 |
| Finished | Aug 29 12:28:56 AM UTC 24 |
| Peak memory | 380380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2207258320 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_m ax_throughput.2207258320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/2.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.762596387 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 2445641266 ps |
| CPU time | 183.93 seconds |
| Started | Aug 29 12:27:52 AM UTC 24 |
| Finished | Aug 29 12:31:00 AM UTC 24 |
| Peak memory | 228932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762596387 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_mem_partial_access.762596387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/2.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.2570154085 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 9406500327 ps |
| CPU time | 177.19 seconds |
| Started | Aug 29 12:27:47 AM UTC 24 |
| Finished | Aug 29 12:30:48 AM UTC 24 |
| Peak memory | 221884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570154085 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_mem_walk.2570154085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/2.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access.3136402762 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 10246470158 ps |
| CPU time | 17.29 seconds |
| Started | Aug 29 12:27:35 AM UTC 24 |
| Finished | Aug 29 12:27:53 AM UTC 24 |
| Peak memory | 211536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136402762 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_partial_access.3136402762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/2.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.795765417 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 5597484361 ps |
| CPU time | 436.5 seconds |
| Started | Aug 29 12:27:36 AM UTC 24 |
| Finished | Aug 29 12:34:59 AM UTC 24 |
| Peak memory | 211812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795765417 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_partial_acc ess_b2b.795765417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/2.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.2901853284 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 705806900 ps |
| CPU time | 4.98 seconds |
| Started | Aug 29 12:27:45 AM UTC 24 |
| Finished | Aug 29 12:27:51 AM UTC 24 |
| Peak memory | 211704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901853284 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.2901853284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/2.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.2200370199 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 1100565581 ps |
| CPU time | 3.21 seconds |
| Started | Aug 29 12:28:14 AM UTC 24 |
| Finished | Aug 29 12:28:18 AM UTC 24 |
| Peak memory | 247772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200370199 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_sec_cm.2200370199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_smoke.2010734472 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 1993250530 ps |
| CPU time | 13.78 seconds |
| Started | Aug 29 12:27:31 AM UTC 24 |
| Finished | Aug 29 12:27:46 AM UTC 24 |
| Peak memory | 211564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010734472 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.2010734472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/2.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all.1929509955 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 1205295575748 ps |
| CPU time | 8059.92 seconds |
| Started | Aug 29 12:28:08 AM UTC 24 |
| Finished | Aug 29 02:43:51 AM UTC 24 |
| Peak memory | 390252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19295099 55 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all.1929509955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/2.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.866700977 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 3566822881 ps |
| CPU time | 39.2 seconds |
| Started | Aug 29 12:27:54 AM UTC 24 |
| Finished | Aug 29 12:28:35 AM UTC 24 |
| Peak memory | 222200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866700977 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.866700977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/2.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.1321454910 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 2690746812 ps |
| CPU time | 45.15 seconds |
| Started | Aug 29 12:27:37 AM UTC 24 |
| Finished | Aug 29 12:28:24 AM UTC 24 |
| Peak memory | 296476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1321454910 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ throughput_w_partial_write.1321454910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/2.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.3983939977 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 25994242160 ps |
| CPU time | 578.38 seconds |
| Started | Aug 29 01:18:33 AM UTC 24 |
| Finished | Aug 29 01:28:19 AM UTC 24 |
| Peak memory | 386528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983939977 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_access_duri ng_key_req.3983939977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/20.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_alert_test.349086429 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 13178196 ps |
| CPU time | 1 seconds |
| Started | Aug 29 01:19:52 AM UTC 24 |
| Finished | Aug 29 01:19:54 AM UTC 24 |
| Peak memory | 210812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349086429 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_alert_test.349086429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/20.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_bijection.1321742656 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 43555575672 ps |
| CPU time | 2381.17 seconds |
| Started | Aug 29 01:17:17 AM UTC 24 |
| Finished | Aug 29 01:57:27 AM UTC 24 |
| Peak memory | 213244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321742656 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection.1321742656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/20.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_executable.294082134 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 9573044115 ps |
| CPU time | 138.22 seconds |
| Started | Aug 29 01:18:56 AM UTC 24 |
| Finished | Aug 29 01:21:17 AM UTC 24 |
| Peak memory | 320980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294082134 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executable.294082134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/20.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.488378259 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 2589734893 ps |
| CPU time | 36.46 seconds |
| Started | Aug 29 01:18:28 AM UTC 24 |
| Finished | Aug 29 01:19:06 AM UTC 24 |
| Peak memory | 225980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488378259 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_escalation.488378259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/20.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.1970801673 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 1495490904 ps |
| CPU time | 40.65 seconds |
| Started | Aug 29 01:17:50 AM UTC 24 |
| Finished | Aug 29 01:18:32 AM UTC 24 |
| Peak memory | 298412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1970801673 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ max_throughput.1970801673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/20.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.301472744 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 6034036124 ps |
| CPU time | 241.32 seconds |
| Started | Aug 29 01:19:19 AM UTC 24 |
| Finished | Aug 29 01:23:24 AM UTC 24 |
| Peak memory | 221796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301472744 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_mem_partial_access.301472744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/20.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.2560552059 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 41466623614 ps |
| CPU time | 252.83 seconds |
| Started | Aug 29 01:19:13 AM UTC 24 |
| Finished | Aug 29 01:23:30 AM UTC 24 |
| Peak memory | 211624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560552059 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_mem_walk.2560552059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/20.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.1172885855 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 31612835660 ps |
| CPU time | 514.6 seconds |
| Started | Aug 29 01:17:11 AM UTC 24 |
| Finished | Aug 29 01:25:52 AM UTC 24 |
| Peak memory | 380368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172885855 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multiple_keys.1172885855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/20.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access.1865200628 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 3219647964 ps |
| CPU time | 106.75 seconds |
| Started | Aug 29 01:17:33 AM UTC 24 |
| Finished | Aug 29 01:19:22 AM UTC 24 |
| Peak memory | 362144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865200628 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_partial_access.1865200628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/20.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.2531441002 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 38022056163 ps |
| CPU time | 360.24 seconds |
| Started | Aug 29 01:17:41 AM UTC 24 |
| Finished | Aug 29 01:23:46 AM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531441002 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_partial_a ccess_b2b.2531441002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/20.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.988493831 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 354787831 ps |
| CPU time | 4.66 seconds |
| Started | Aug 29 01:19:07 AM UTC 24 |
| Finished | Aug 29 01:19:13 AM UTC 24 |
| Peak memory | 211828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988493831 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.988493831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/20.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_regwen.2689676752 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 3107575647 ps |
| CPU time | 388.48 seconds |
| Started | Aug 29 01:19:00 AM UTC 24 |
| Finished | Aug 29 01:25:33 AM UTC 24 |
| Peak memory | 384468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689676752 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.2689676752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/20.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_smoke.3659436704 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 1347531631 ps |
| CPU time | 18.7 seconds |
| Started | Aug 29 01:17:08 AM UTC 24 |
| Finished | Aug 29 01:17:28 AM UTC 24 |
| Peak memory | 211548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659436704 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.3659436704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/20.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all.455161255 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 3305888053630 ps |
| CPU time | 6961.31 seconds |
| Started | Aug 29 01:19:47 AM UTC 24 |
| Finished | Aug 29 03:17:02 AM UTC 24 |
| Peak memory | 392384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45516125 5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all.455161255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/20.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.2686233795 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 452546823 ps |
| CPU time | 23.46 seconds |
| Started | Aug 29 01:19:22 AM UTC 24 |
| Finished | Aug 29 01:19:47 AM UTC 24 |
| Peak memory | 221940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686233795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.2686233795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/20.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.2687235135 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 17754092914 ps |
| CPU time | 371.05 seconds |
| Started | Aug 29 01:17:30 AM UTC 24 |
| Finished | Aug 29 01:23:45 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687235135 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_pipeline.2687235135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/20.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.2653573613 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 7919531150 ps |
| CPU time | 30.61 seconds |
| Started | Aug 29 01:17:55 AM UTC 24 |
| Finished | Aug 29 01:18:27 AM UTC 24 |
| Peak memory | 278184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2653573613 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl _throughput_w_partial_write.2653573613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/20.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.990876553 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 41159201750 ps |
| CPU time | 1703.36 seconds |
| Started | Aug 29 01:22:10 AM UTC 24 |
| Finished | Aug 29 01:50:52 AM UTC 24 |
| Peak memory | 390236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990876553 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_access_durin g_key_req.990876553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/21.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_alert_test.1494104328 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 34778455 ps |
| CPU time | 0.98 seconds |
| Started | Aug 29 01:24:08 AM UTC 24 |
| Finished | Aug 29 01:24:10 AM UTC 24 |
| Peak memory | 210816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494104328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_alert_test.1494104328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/21.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_bijection.2115892215 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 95772991206 ps |
| CPU time | 2078.72 seconds |
| Started | Aug 29 01:20:10 AM UTC 24 |
| Finished | Aug 29 01:55:13 AM UTC 24 |
| Peak memory | 213092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115892215 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection.2115892215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/21.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_executable.3743215765 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 32543451722 ps |
| CPU time | 571.32 seconds |
| Started | Aug 29 01:22:26 AM UTC 24 |
| Finished | Aug 29 01:32:05 AM UTC 24 |
| Peak memory | 382416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743215765 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executable.3743215765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/21.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.1872021816 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 30934564573 ps |
| CPU time | 118.54 seconds |
| Started | Aug 29 01:22:09 AM UTC 24 |
| Finished | Aug 29 01:24:10 AM UTC 24 |
| Peak memory | 211644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872021816 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_escalation.1872021816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/21.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.3636235426 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 798724907 ps |
| CPU time | 113.94 seconds |
| Started | Aug 29 01:21:31 AM UTC 24 |
| Finished | Aug 29 01:23:27 AM UTC 24 |
| Peak memory | 380392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3636235426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ max_throughput.3636235426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/21.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.2032394287 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 2910142982 ps |
| CPU time | 71.89 seconds |
| Started | Aug 29 01:23:36 AM UTC 24 |
| Finished | Aug 29 01:24:49 AM UTC 24 |
| Peak memory | 222052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032394287 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_mem_partial_access.2032394287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/21.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.898679693 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 30725058353 ps |
| CPU time | 365.96 seconds |
| Started | Aug 29 01:23:31 AM UTC 24 |
| Finished | Aug 29 01:29:42 AM UTC 24 |
| Peak memory | 211604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898679693 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_mem_walk.898679693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/21.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.955655879 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 70600078778 ps |
| CPU time | 1282.32 seconds |
| Started | Aug 29 01:20:03 AM UTC 24 |
| Finished | Aug 29 01:41:39 AM UTC 24 |
| Peak memory | 380492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955655879 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multiple_keys.955655879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/21.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.3492617540 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 41294361341 ps |
| CPU time | 451.31 seconds |
| Started | Aug 29 01:21:18 AM UTC 24 |
| Finished | Aug 29 01:28:55 AM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492617540 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_partial_a ccess_b2b.3492617540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/21.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.3127556088 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 3750774855 ps |
| CPU time | 6.72 seconds |
| Started | Aug 29 01:23:28 AM UTC 24 |
| Finished | Aug 29 01:23:35 AM UTC 24 |
| Peak memory | 211828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127556088 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.3127556088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/21.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_regwen.118381405 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 16526448783 ps |
| CPU time | 942.02 seconds |
| Started | Aug 29 01:23:25 AM UTC 24 |
| Finished | Aug 29 01:39:18 AM UTC 24 |
| Peak memory | 386516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118381405 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.118381405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/21.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_smoke.2689869742 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 1108846165 ps |
| CPU time | 13.17 seconds |
| Started | Aug 29 01:19:55 AM UTC 24 |
| Finished | Aug 29 01:20:09 AM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689869742 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.2689869742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/21.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all.1296620999 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 16731012512 ps |
| CPU time | 987.2 seconds |
| Started | Aug 29 01:23:47 AM UTC 24 |
| Finished | Aug 29 01:40:25 AM UTC 24 |
| Peak memory | 386728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12966209 99 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_a ll.1296620999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/21.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.1232504075 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 1457274975 ps |
| CPU time | 116.27 seconds |
| Started | Aug 29 01:23:46 AM UTC 24 |
| Finished | Aug 29 01:25:44 AM UTC 24 |
| Peak memory | 362020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232504075 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.1232504075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/21.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.3316543332 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 5855687336 ps |
| CPU time | 266.41 seconds |
| Started | Aug 29 01:20:29 AM UTC 24 |
| Finished | Aug 29 01:25:00 AM UTC 24 |
| Peak memory | 211644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316543332 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_pipeline.3316543332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/21.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.2881864672 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 1409977765 ps |
| CPU time | 13.12 seconds |
| Started | Aug 29 01:21:55 AM UTC 24 |
| Finished | Aug 29 01:22:09 AM UTC 24 |
| Peak memory | 228360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2881864672 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl _throughput_w_partial_write.2881864672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/21.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.3264912644 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 22218224489 ps |
| CPU time | 1023.57 seconds |
| Started | Aug 29 01:25:52 AM UTC 24 |
| Finished | Aug 29 01:43:09 AM UTC 24 |
| Peak memory | 382420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264912644 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_access_duri ng_key_req.3264912644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/22.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_alert_test.424080516 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 14443373 ps |
| CPU time | 0.97 seconds |
| Started | Aug 29 01:27:03 AM UTC 24 |
| Finished | Aug 29 01:27:05 AM UTC 24 |
| Peak memory | 210732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424080516 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_alert_test.424080516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/22.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_bijection.3859328452 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 206937146328 ps |
| CPU time | 2275.5 seconds |
| Started | Aug 29 01:24:18 AM UTC 24 |
| Finished | Aug 29 02:02:40 AM UTC 24 |
| Peak memory | 213172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859328452 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection.3859328452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/22.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_executable.4041446152 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 6600043075 ps |
| CPU time | 626.76 seconds |
| Started | Aug 29 01:25:55 AM UTC 24 |
| Finished | Aug 29 01:36:29 AM UTC 24 |
| Peak memory | 382508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041446152 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executable.4041446152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/22.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.1607403714 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 2495926962 ps |
| CPU time | 28.25 seconds |
| Started | Aug 29 01:25:45 AM UTC 24 |
| Finished | Aug 29 01:26:15 AM UTC 24 |
| Peak memory | 221616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607403714 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_escalation.1607403714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/22.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.3622556884 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 8665258989 ps |
| CPU time | 26.23 seconds |
| Started | Aug 29 01:25:26 AM UTC 24 |
| Finished | Aug 29 01:25:54 AM UTC 24 |
| Peak memory | 261612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3622556884 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ max_throughput.3622556884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/22.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.1880093587 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 2605204163 ps |
| CPU time | 174.28 seconds |
| Started | Aug 29 01:26:40 AM UTC 24 |
| Finished | Aug 29 01:29:37 AM UTC 24 |
| Peak memory | 221868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880093587 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_mem_partial_access.1880093587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/22.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.1450849645 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 21892120786 ps |
| CPU time | 203.92 seconds |
| Started | Aug 29 01:26:23 AM UTC 24 |
| Finished | Aug 29 01:29:50 AM UTC 24 |
| Peak memory | 221888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450849645 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_mem_walk.1450849645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/22.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.3586148625 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 9326218048 ps |
| CPU time | 864.39 seconds |
| Started | Aug 29 01:24:11 AM UTC 24 |
| Finished | Aug 29 01:38:45 AM UTC 24 |
| Peak memory | 380436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586148625 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multiple_keys.3586148625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/22.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access.3748156516 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 2846294374 ps |
| CPU time | 33.67 seconds |
| Started | Aug 29 01:24:50 AM UTC 24 |
| Finished | Aug 29 01:25:25 AM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748156516 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_partial_access.3748156516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/22.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.2111262784 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 19587728007 ps |
| CPU time | 406.49 seconds |
| Started | Aug 29 01:25:01 AM UTC 24 |
| Finished | Aug 29 01:31:53 AM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111262784 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_partial_a ccess_b2b.2111262784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/22.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.1652542462 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 5607714769 ps |
| CPU time | 5.47 seconds |
| Started | Aug 29 01:26:16 AM UTC 24 |
| Finished | Aug 29 01:26:22 AM UTC 24 |
| Peak memory | 211692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652542462 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.1652542462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/22.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_regwen.2682261327 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 496012168 ps |
| CPU time | 22.98 seconds |
| Started | Aug 29 01:26:15 AM UTC 24 |
| Finished | Aug 29 01:26:39 AM UTC 24 |
| Peak memory | 239072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682261327 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.2682261327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/22.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_smoke.2475979657 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 1842219927 ps |
| CPU time | 35.93 seconds |
| Started | Aug 29 01:24:10 AM UTC 24 |
| Finished | Aug 29 01:24:48 AM UTC 24 |
| Peak memory | 211552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475979657 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.2475979657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/22.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all.2243860146 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 138529984416 ps |
| CPU time | 4525.89 seconds |
| Started | Aug 29 01:27:02 AM UTC 24 |
| Finished | Aug 29 02:43:17 AM UTC 24 |
| Peak memory | 388128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22438601 46 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_a ll.2243860146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/22.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.2423039372 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 8475258342 ps |
| CPU time | 99.38 seconds |
| Started | Aug 29 01:26:54 AM UTC 24 |
| Finished | Aug 29 01:28:36 AM UTC 24 |
| Peak memory | 233124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423039372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.2423039372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/22.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.59199131 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 10642866051 ps |
| CPU time | 284.08 seconds |
| Started | Aug 29 01:24:49 AM UTC 24 |
| Finished | Aug 29 01:29:37 AM UTC 24 |
| Peak memory | 211628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59199131 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_pipeline.59199131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/22.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.3716938913 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 5618465897 ps |
| CPU time | 38.06 seconds |
| Started | Aug 29 01:25:34 AM UTC 24 |
| Finished | Aug 29 01:26:14 AM UTC 24 |
| Peak memory | 302552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3716938913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl _throughput_w_partial_write.3716938913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/22.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.3368657592 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 65911661008 ps |
| CPU time | 1226.83 seconds |
| Started | Aug 29 01:29:13 AM UTC 24 |
| Finished | Aug 29 01:49:53 AM UTC 24 |
| Peak memory | 386796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368657592 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_access_duri ng_key_req.3368657592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/23.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_alert_test.4119082300 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 28673139 ps |
| CPU time | 1.04 seconds |
| Started | Aug 29 01:29:51 AM UTC 24 |
| Finished | Aug 29 01:29:52 AM UTC 24 |
| Peak memory | 210940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119082300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_alert_test.4119082300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/23.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_bijection.2767785732 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 737159071515 ps |
| CPU time | 2069.06 seconds |
| Started | Aug 29 01:27:44 AM UTC 24 |
| Finished | Aug 29 02:02:36 AM UTC 24 |
| Peak memory | 213320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767785732 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection.2767785732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/23.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_executable.3293466557 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 44758769106 ps |
| CPU time | 1160.04 seconds |
| Started | Aug 29 01:29:15 AM UTC 24 |
| Finished | Aug 29 01:48:47 AM UTC 24 |
| Peak memory | 388636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293466557 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executable.3293466557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/23.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.956825042 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 13020066069 ps |
| CPU time | 175.89 seconds |
| Started | Aug 29 01:29:03 AM UTC 24 |
| Finished | Aug 29 01:32:01 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956825042 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_escalation.956825042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/23.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.2359810189 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 715499161 ps |
| CPU time | 25.15 seconds |
| Started | Aug 29 01:28:45 AM UTC 24 |
| Finished | Aug 29 01:29:12 AM UTC 24 |
| Peak memory | 277992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2359810189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ max_throughput.2359810189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/23.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.3518900650 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 21857856963 ps |
| CPU time | 224.37 seconds |
| Started | Aug 29 01:29:38 AM UTC 24 |
| Finished | Aug 29 01:33:26 AM UTC 24 |
| Peak memory | 221928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518900650 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_mem_partial_access.3518900650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/23.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.3282634575 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 36983186553 ps |
| CPU time | 218.3 seconds |
| Started | Aug 29 01:29:26 AM UTC 24 |
| Finished | Aug 29 01:33:08 AM UTC 24 |
| Peak memory | 211832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282634575 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_mem_walk.3282634575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/23.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.3170599413 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 7441514346 ps |
| CPU time | 410.61 seconds |
| Started | Aug 29 01:27:39 AM UTC 24 |
| Finished | Aug 29 01:34:35 AM UTC 24 |
| Peak memory | 386500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170599413 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multiple_keys.3170599413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/23.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access.2950943797 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 1739676845 ps |
| CPU time | 41.43 seconds |
| Started | Aug 29 01:28:34 AM UTC 24 |
| Finished | Aug 29 01:29:17 AM UTC 24 |
| Peak memory | 294372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950943797 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_partial_access.2950943797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/23.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.3703781115 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 50798198569 ps |
| CPU time | 366.02 seconds |
| Started | Aug 29 01:28:36 AM UTC 24 |
| Finished | Aug 29 01:34:47 AM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703781115 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_partial_a ccess_b2b.3703781115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/23.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.278942665 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 1163705381 ps |
| CPU time | 5.36 seconds |
| Started | Aug 29 01:29:19 AM UTC 24 |
| Finished | Aug 29 01:29:25 AM UTC 24 |
| Peak memory | 211696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278942665 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.278942665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/23.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_regwen.2030180663 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 4504004841 ps |
| CPU time | 985.7 seconds |
| Started | Aug 29 01:29:18 AM UTC 24 |
| Finished | Aug 29 01:45:54 AM UTC 24 |
| Peak memory | 390616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030180663 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.2030180663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/23.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_smoke.272841436 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 3090749688 ps |
| CPU time | 112.87 seconds |
| Started | Aug 29 01:27:06 AM UTC 24 |
| Finished | Aug 29 01:29:02 AM UTC 24 |
| Peak memory | 378396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272841436 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.272841436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/23.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all.2440329232 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 48087846925 ps |
| CPU time | 2988.87 seconds |
| Started | Aug 29 01:29:42 AM UTC 24 |
| Finished | Aug 29 02:20:06 AM UTC 24 |
| Peak memory | 394416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24403292 32 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_a ll.2440329232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/23.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.2578690512 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 1953084295 ps |
| CPU time | 114.77 seconds |
| Started | Aug 29 01:29:38 AM UTC 24 |
| Finished | Aug 29 01:31:35 AM UTC 24 |
| Peak memory | 351856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578690512 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.2578690512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/23.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.3510939595 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 39565437440 ps |
| CPU time | 537.01 seconds |
| Started | Aug 29 01:28:19 AM UTC 24 |
| Finished | Aug 29 01:37:23 AM UTC 24 |
| Peak memory | 211552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510939595 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_pipeline.3510939595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/23.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.2858694366 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 6225101559 ps |
| CPU time | 17.07 seconds |
| Started | Aug 29 01:28:55 AM UTC 24 |
| Finished | Aug 29 01:29:14 AM UTC 24 |
| Peak memory | 235040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2858694366 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl _throughput_w_partial_write.2858694366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/23.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.791489345 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 10370624506 ps |
| CPU time | 100.81 seconds |
| Started | Aug 29 01:32:19 AM UTC 24 |
| Finished | Aug 29 01:34:02 AM UTC 24 |
| Peak memory | 273876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791489345 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_access_durin g_key_req.791489345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/24.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_alert_test.3854509722 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 14423594 ps |
| CPU time | 1.03 seconds |
| Started | Aug 29 01:34:33 AM UTC 24 |
| Finished | Aug 29 01:34:35 AM UTC 24 |
| Peak memory | 208832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854509722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_alert_test.3854509722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/24.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_bijection.2998475852 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 58434801338 ps |
| CPU time | 1437.05 seconds |
| Started | Aug 29 01:30:28 AM UTC 24 |
| Finished | Aug 29 01:54:41 AM UTC 24 |
| Peak memory | 213436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998475852 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection.2998475852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/24.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_executable.883356898 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 57789371556 ps |
| CPU time | 1124.59 seconds |
| Started | Aug 29 01:32:28 AM UTC 24 |
| Finished | Aug 29 01:51:26 AM UTC 24 |
| Peak memory | 386580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883356898 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executable.883356898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/24.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.1208637402 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 13886991895 ps |
| CPU time | 135.59 seconds |
| Started | Aug 29 01:32:12 AM UTC 24 |
| Finished | Aug 29 01:34:30 AM UTC 24 |
| Peak memory | 221816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208637402 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_escalation.1208637402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/24.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.3923838777 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 740765910 ps |
| CPU time | 23.85 seconds |
| Started | Aug 29 01:32:03 AM UTC 24 |
| Finished | Aug 29 01:32:28 AM UTC 24 |
| Peak memory | 263656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3923838777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ max_throughput.3923838777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/24.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.2774290583 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 5001560960 ps |
| CPU time | 219.86 seconds |
| Started | Aug 29 01:33:27 AM UTC 24 |
| Finished | Aug 29 01:37:10 AM UTC 24 |
| Peak memory | 229032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774290583 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_mem_partial_access.2774290583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/24.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.1294504082 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 27630692470 ps |
| CPU time | 241.1 seconds |
| Started | Aug 29 01:33:17 AM UTC 24 |
| Finished | Aug 29 01:37:22 AM UTC 24 |
| Peak memory | 221872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294504082 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_mem_walk.1294504082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/24.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.3943423283 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 28948441828 ps |
| CPU time | 583.22 seconds |
| Started | Aug 29 01:29:55 AM UTC 24 |
| Finished | Aug 29 01:39:45 AM UTC 24 |
| Peak memory | 388560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943423283 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multiple_keys.3943423283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/24.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access.784042308 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 2489999728 ps |
| CPU time | 33.43 seconds |
| Started | Aug 29 01:31:36 AM UTC 24 |
| Finished | Aug 29 01:32:11 AM UTC 24 |
| Peak memory | 211616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784042308 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_partial_access.784042308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/24.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.3050412823 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 17798416389 ps |
| CPU time | 321.71 seconds |
| Started | Aug 29 01:31:53 AM UTC 24 |
| Finished | Aug 29 01:37:20 AM UTC 24 |
| Peak memory | 211652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050412823 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_partial_a ccess_b2b.3050412823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/24.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.2250010173 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 355119556 ps |
| CPU time | 4.98 seconds |
| Started | Aug 29 01:33:09 AM UTC 24 |
| Finished | Aug 29 01:33:15 AM UTC 24 |
| Peak memory | 211840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250010173 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.2250010173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/24.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_regwen.1172551603 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 37307617299 ps |
| CPU time | 732.04 seconds |
| Started | Aug 29 01:32:40 AM UTC 24 |
| Finished | Aug 29 01:45:01 AM UTC 24 |
| Peak memory | 390884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172551603 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.1172551603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/24.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_smoke.1061549051 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 457938666 ps |
| CPU time | 86.62 seconds |
| Started | Aug 29 01:29:54 AM UTC 24 |
| Finished | Aug 29 01:31:22 AM UTC 24 |
| Peak memory | 366044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061549051 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.1061549051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/24.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all.1025172259 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 130434933379 ps |
| CPU time | 3045.53 seconds |
| Started | Aug 29 01:34:31 AM UTC 24 |
| Finished | Aug 29 02:25:49 AM UTC 24 |
| Peak memory | 390320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10251722 59 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_a ll.1025172259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/24.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.522972209 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 3141437691 ps |
| CPU time | 47.13 seconds |
| Started | Aug 29 01:34:03 AM UTC 24 |
| Finished | Aug 29 01:34:52 AM UTC 24 |
| Peak memory | 222000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522972209 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.522972209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/24.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.3408581159 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 4462845143 ps |
| CPU time | 387.3 seconds |
| Started | Aug 29 01:31:23 AM UTC 24 |
| Finished | Aug 29 01:37:56 AM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408581159 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_pipeline.3408581159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/24.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.1624356916 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 719395829 ps |
| CPU time | 32.75 seconds |
| Started | Aug 29 01:32:06 AM UTC 24 |
| Finished | Aug 29 01:32:40 AM UTC 24 |
| Peak memory | 280168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1624356916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl _throughput_w_partial_write.1624356916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/24.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.540716565 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 135665318903 ps |
| CPU time | 1354.83 seconds |
| Started | Aug 29 01:37:21 AM UTC 24 |
| Finished | Aug 29 02:00:11 AM UTC 24 |
| Peak memory | 386148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540716565 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_access_durin g_key_req.540716565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/25.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_alert_test.2198535088 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 13547230 ps |
| CPU time | 1.06 seconds |
| Started | Aug 29 01:38:44 AM UTC 24 |
| Finished | Aug 29 01:38:46 AM UTC 24 |
| Peak memory | 210816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198535088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_alert_test.2198535088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/25.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_bijection.1494161560 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 24274783359 ps |
| CPU time | 927.94 seconds |
| Started | Aug 29 01:34:48 AM UTC 24 |
| Finished | Aug 29 01:50:28 AM UTC 24 |
| Peak memory | 211640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494161560 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection.1494161560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/25.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_executable.4138371733 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 3271918605 ps |
| CPU time | 91.66 seconds |
| Started | Aug 29 01:37:23 AM UTC 24 |
| Finished | Aug 29 01:38:57 AM UTC 24 |
| Peak memory | 341644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138371733 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executable.4138371733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/25.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.164684586 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 39465067105 ps |
| CPU time | 90.02 seconds |
| Started | Aug 29 01:37:11 AM UTC 24 |
| Finished | Aug 29 01:38:43 AM UTC 24 |
| Peak memory | 221828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164684586 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_escalation.164684586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/25.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.3991012088 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 3068649625 ps |
| CPU time | 64.56 seconds |
| Started | Aug 29 01:36:16 AM UTC 24 |
| Finished | Aug 29 01:37:23 AM UTC 24 |
| Peak memory | 333364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3991012088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ max_throughput.3991012088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/25.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.384611753 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 24292977219 ps |
| CPU time | 199.45 seconds |
| Started | Aug 29 01:37:33 AM UTC 24 |
| Finished | Aug 29 01:40:56 AM UTC 24 |
| Peak memory | 221924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384611753 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_mem_partial_access.384611753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/25.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.4019889782 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 43183341978 ps |
| CPU time | 182.46 seconds |
| Started | Aug 29 01:37:27 AM UTC 24 |
| Finished | Aug 29 01:40:33 AM UTC 24 |
| Peak memory | 221872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019889782 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_mem_walk.4019889782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/25.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.1028406615 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 41894837766 ps |
| CPU time | 479.15 seconds |
| Started | Aug 29 01:34:36 AM UTC 24 |
| Finished | Aug 29 01:42:41 AM UTC 24 |
| Peak memory | 386584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028406615 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multiple_keys.1028406615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/25.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access.159357915 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 2238064063 ps |
| CPU time | 22.82 seconds |
| Started | Aug 29 01:34:53 AM UTC 24 |
| Finished | Aug 29 01:35:17 AM UTC 24 |
| Peak memory | 267924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159357915 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_partial_access.159357915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/25.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.943463149 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 36698620120 ps |
| CPU time | 600.92 seconds |
| Started | Aug 29 01:35:18 AM UTC 24 |
| Finished | Aug 29 01:45:27 AM UTC 24 |
| Peak memory | 211760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943463149 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_partial_ac cess_b2b.943463149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/25.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.2181717689 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 2397353752 ps |
| CPU time | 7.48 seconds |
| Started | Aug 29 01:37:24 AM UTC 24 |
| Finished | Aug 29 01:37:33 AM UTC 24 |
| Peak memory | 212032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181717689 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.2181717689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/25.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_regwen.278279610 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 5321506387 ps |
| CPU time | 122.82 seconds |
| Started | Aug 29 01:37:24 AM UTC 24 |
| Finished | Aug 29 01:39:29 AM UTC 24 |
| Peak memory | 382500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278279610 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.278279610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/25.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_smoke.1524284869 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 2706791818 ps |
| CPU time | 12.91 seconds |
| Started | Aug 29 01:34:35 AM UTC 24 |
| Finished | Aug 29 01:34:49 AM UTC 24 |
| Peak memory | 222748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524284869 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.1524284869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/25.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all.26576695 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 37386542398 ps |
| CPU time | 359.71 seconds |
| Started | Aug 29 01:38:40 AM UTC 24 |
| Finished | Aug 29 01:44:44 AM UTC 24 |
| Peak memory | 384680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26576695 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all.26576695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/25.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.1206470651 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 2470687658 ps |
| CPU time | 39.73 seconds |
| Started | Aug 29 01:37:57 AM UTC 24 |
| Finished | Aug 29 01:38:38 AM UTC 24 |
| Peak memory | 224060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206470651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.1206470651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/25.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.521124027 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 13819865770 ps |
| CPU time | 345.24 seconds |
| Started | Aug 29 01:34:51 AM UTC 24 |
| Finished | Aug 29 01:40:41 AM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521124027 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_pipeline.521124027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/25.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.995500013 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 774433096 ps |
| CPU time | 55.35 seconds |
| Started | Aug 29 01:36:29 AM UTC 24 |
| Finished | Aug 29 01:37:27 AM UTC 24 |
| Peak memory | 314772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =995500013 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ throughput_w_partial_write.995500013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/25.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.2444575214 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 2060460444 ps |
| CPU time | 204.05 seconds |
| Started | Aug 29 01:40:05 AM UTC 24 |
| Finished | Aug 29 01:43:32 AM UTC 24 |
| Peak memory | 386524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444575214 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_access_duri ng_key_req.2444575214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/26.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_alert_test.2791185731 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 48557376 ps |
| CPU time | 0.97 seconds |
| Started | Aug 29 01:41:06 AM UTC 24 |
| Finished | Aug 29 01:41:08 AM UTC 24 |
| Peak memory | 210936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791185731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_alert_test.2791185731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/26.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_bijection.3562449163 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 120776613627 ps |
| CPU time | 1629.01 seconds |
| Started | Aug 29 01:38:56 AM UTC 24 |
| Finished | Aug 29 02:06:25 AM UTC 24 |
| Peak memory | 213160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562449163 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection.3562449163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/26.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_executable.218425981 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 58510173500 ps |
| CPU time | 1205.84 seconds |
| Started | Aug 29 01:40:25 AM UTC 24 |
| Finished | Aug 29 02:00:45 AM UTC 24 |
| Peak memory | 376456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218425981 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executable.218425981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/26.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.3115120300 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 67089425983 ps |
| CPU time | 255.41 seconds |
| Started | Aug 29 01:39:57 AM UTC 24 |
| Finished | Aug 29 01:44:16 AM UTC 24 |
| Peak memory | 222012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115120300 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_escalation.3115120300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/26.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.212061822 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 738089894 ps |
| CPU time | 61.44 seconds |
| Started | Aug 29 01:39:40 AM UTC 24 |
| Finished | Aug 29 01:40:43 AM UTC 24 |
| Peak memory | 327072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 212061822 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_m ax_throughput.212061822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/26.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.1890299278 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 2485649010 ps |
| CPU time | 107.49 seconds |
| Started | Aug 29 01:40:43 AM UTC 24 |
| Finished | Aug 29 01:42:32 AM UTC 24 |
| Peak memory | 221852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890299278 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_mem_partial_access.1890299278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/26.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.770505226 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 43254590653 ps |
| CPU time | 244.36 seconds |
| Started | Aug 29 01:40:42 AM UTC 24 |
| Finished | Aug 29 01:44:50 AM UTC 24 |
| Peak memory | 222116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770505226 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_mem_walk.770505226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/26.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.2573868441 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 34374837713 ps |
| CPU time | 776.19 seconds |
| Started | Aug 29 01:38:47 AM UTC 24 |
| Finished | Aug 29 01:51:52 AM UTC 24 |
| Peak memory | 380440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573868441 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multiple_keys.2573868441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/26.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access.4054787017 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 1453445322 ps |
| CPU time | 35.86 seconds |
| Started | Aug 29 01:39:18 AM UTC 24 |
| Finished | Aug 29 01:39:56 AM UTC 24 |
| Peak memory | 288224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054787017 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_partial_access.4054787017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/26.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.3317591137 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 39740073290 ps |
| CPU time | 322.48 seconds |
| Started | Aug 29 01:39:30 AM UTC 24 |
| Finished | Aug 29 01:44:57 AM UTC 24 |
| Peak memory | 211548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317591137 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_partial_a ccess_b2b.3317591137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/26.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.3065084627 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 3369030017 ps |
| CPU time | 6.97 seconds |
| Started | Aug 29 01:40:33 AM UTC 24 |
| Finished | Aug 29 01:40:41 AM UTC 24 |
| Peak memory | 211896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065084627 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.3065084627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/26.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_regwen.509266913 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 49998260319 ps |
| CPU time | 530.39 seconds |
| Started | Aug 29 01:40:26 AM UTC 24 |
| Finished | Aug 29 01:49:23 AM UTC 24 |
| Peak memory | 362004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509266913 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.509266913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/26.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_smoke.3110333478 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 1031199094 ps |
| CPU time | 8.09 seconds |
| Started | Aug 29 01:38:46 AM UTC 24 |
| Finished | Aug 29 01:38:55 AM UTC 24 |
| Peak memory | 211552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110333478 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.3110333478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/26.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all.2345196447 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 224472166273 ps |
| CPU time | 3756.04 seconds |
| Started | Aug 29 01:40:57 AM UTC 24 |
| Finished | Aug 29 02:44:14 AM UTC 24 |
| Peak memory | 390172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23451964 47 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_a ll.2345196447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/26.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.1692929906 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 5455766437 ps |
| CPU time | 20.24 seconds |
| Started | Aug 29 01:40:44 AM UTC 24 |
| Finished | Aug 29 01:41:05 AM UTC 24 |
| Peak memory | 222004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692929906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.1692929906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/26.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.3619803666 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 3349020922 ps |
| CPU time | 269.82 seconds |
| Started | Aug 29 01:38:57 AM UTC 24 |
| Finished | Aug 29 01:43:31 AM UTC 24 |
| Peak memory | 211576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619803666 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_pipeline.3619803666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/26.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.1481578019 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 2902987400 ps |
| CPU time | 36.49 seconds |
| Started | Aug 29 01:39:46 AM UTC 24 |
| Finished | Aug 29 01:40:24 AM UTC 24 |
| Peak memory | 298652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1481578019 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl _throughput_w_partial_write.1481578019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/26.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.99165763 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 35663009779 ps |
| CPU time | 1598.69 seconds |
| Started | Aug 29 01:43:33 AM UTC 24 |
| Finished | Aug 29 02:10:30 AM UTC 24 |
| Peak memory | 388196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99165763 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_access_during _key_req.99165763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/27.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_alert_test.4172827233 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 41046849 ps |
| CPU time | 0.85 seconds |
| Started | Aug 29 01:44:45 AM UTC 24 |
| Finished | Aug 29 01:44:47 AM UTC 24 |
| Peak memory | 210816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172827233 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_alert_test.4172827233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/27.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_bijection.3410447801 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 15062553208 ps |
| CPU time | 1496.85 seconds |
| Started | Aug 29 01:41:40 AM UTC 24 |
| Finished | Aug 29 02:06:55 AM UTC 24 |
| Peak memory | 213244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410447801 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection.3410447801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/27.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_executable.2731613141 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 26497026860 ps |
| CPU time | 784.68 seconds |
| Started | Aug 29 01:43:47 AM UTC 24 |
| Finished | Aug 29 01:57:00 AM UTC 24 |
| Peak memory | 380368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731613141 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executable.2731613141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/27.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.1469669065 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 16866129569 ps |
| CPU time | 49.05 seconds |
| Started | Aug 29 01:43:33 AM UTC 24 |
| Finished | Aug 29 01:44:23 AM UTC 24 |
| Peak memory | 211564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469669065 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_escalation.1469669065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/27.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.917804998 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 1360729588 ps |
| CPU time | 10.81 seconds |
| Started | Aug 29 01:43:18 AM UTC 24 |
| Finished | Aug 29 01:43:30 AM UTC 24 |
| Peak memory | 211312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 917804998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_m ax_throughput.917804998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/27.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.4000149946 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 2802060790 ps |
| CPU time | 91.1 seconds |
| Started | Aug 29 01:44:24 AM UTC 24 |
| Finished | Aug 29 01:45:57 AM UTC 24 |
| Peak memory | 222064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000149946 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_mem_partial_access.4000149946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/27.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.129808788 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 20704940451 ps |
| CPU time | 192.57 seconds |
| Started | Aug 29 01:44:24 AM UTC 24 |
| Finished | Aug 29 01:47:40 AM UTC 24 |
| Peak memory | 221796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129808788 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_mem_walk.129808788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/27.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.364532863 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 25755868874 ps |
| CPU time | 741.56 seconds |
| Started | Aug 29 01:41:29 AM UTC 24 |
| Finished | Aug 29 01:54:00 AM UTC 24 |
| Peak memory | 380384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364532863 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multiple_keys.364532863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/27.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access.206246767 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 6095812152 ps |
| CPU time | 34.33 seconds |
| Started | Aug 29 01:42:42 AM UTC 24 |
| Finished | Aug 29 01:43:18 AM UTC 24 |
| Peak memory | 211628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206246767 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_partial_access.206246767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/27.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.2262030053 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 227596060147 ps |
| CPU time | 445.27 seconds |
| Started | Aug 29 01:43:09 AM UTC 24 |
| Finished | Aug 29 01:50:41 AM UTC 24 |
| Peak memory | 211856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262030053 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_partial_a ccess_b2b.2262030053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/27.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.2123894995 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 364515070 ps |
| CPU time | 5.5 seconds |
| Started | Aug 29 01:44:17 AM UTC 24 |
| Finished | Aug 29 01:44:24 AM UTC 24 |
| Peak memory | 211704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123894995 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.2123894995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/27.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_regwen.1668206332 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 19743246938 ps |
| CPU time | 614.26 seconds |
| Started | Aug 29 01:43:51 AM UTC 24 |
| Finished | Aug 29 01:54:13 AM UTC 24 |
| Peak memory | 382620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668206332 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.1668206332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/27.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_smoke.3110424686 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 2246370207 ps |
| CPU time | 17.83 seconds |
| Started | Aug 29 01:41:09 AM UTC 24 |
| Finished | Aug 29 01:41:28 AM UTC 24 |
| Peak memory | 211680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110424686 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.3110424686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/27.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all.3056624319 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 246670000377 ps |
| CPU time | 3761.17 seconds |
| Started | Aug 29 01:44:28 AM UTC 24 |
| Finished | Aug 29 02:47:53 AM UTC 24 |
| Peak memory | 398496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30566243 19 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_a ll.3056624319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/27.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.2054231675 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 16499783246 ps |
| CPU time | 37.61 seconds |
| Started | Aug 29 01:44:27 AM UTC 24 |
| Finished | Aug 29 01:45:06 AM UTC 24 |
| Peak memory | 223996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054231675 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.2054231675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/27.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.2296580497 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 18379671023 ps |
| CPU time | 202.61 seconds |
| Started | Aug 29 01:42:34 AM UTC 24 |
| Finished | Aug 29 01:46:00 AM UTC 24 |
| Peak memory | 211652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296580497 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_pipeline.2296580497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/27.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.866186155 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 2756800200 ps |
| CPU time | 17.58 seconds |
| Started | Aug 29 01:43:31 AM UTC 24 |
| Finished | Aug 29 01:43:50 AM UTC 24 |
| Peak memory | 245192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =866186155 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ throughput_w_partial_write.866186155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/27.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.2778950195 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 17339562718 ps |
| CPU time | 917.71 seconds |
| Started | Aug 29 01:45:56 AM UTC 24 |
| Finished | Aug 29 02:01:24 AM UTC 24 |
| Peak memory | 388624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778950195 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_access_duri ng_key_req.2778950195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/28.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_alert_test.3090583078 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 17899125 ps |
| CPU time | 1.05 seconds |
| Started | Aug 29 01:47:41 AM UTC 24 |
| Finished | Aug 29 01:47:43 AM UTC 24 |
| Peak memory | 210876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090583078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_alert_test.3090583078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/28.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_bijection.1567131590 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 93149732851 ps |
| CPU time | 1175.97 seconds |
| Started | Aug 29 01:44:58 AM UTC 24 |
| Finished | Aug 29 02:04:48 AM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567131590 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection.1567131590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/28.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_executable.1580222451 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 22762403379 ps |
| CPU time | 256.99 seconds |
| Started | Aug 29 01:45:58 AM UTC 24 |
| Finished | Aug 29 01:50:19 AM UTC 24 |
| Peak memory | 364004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580222451 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executable.1580222451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/28.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.164023072 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 9986605257 ps |
| CPU time | 64.63 seconds |
| Started | Aug 29 01:45:55 AM UTC 24 |
| Finished | Aug 29 01:47:01 AM UTC 24 |
| Peak memory | 225976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164023072 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_escalation.164023072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/28.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.2630644035 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 1538464323 ps |
| CPU time | 26.69 seconds |
| Started | Aug 29 01:45:27 AM UTC 24 |
| Finished | Aug 29 01:45:55 AM UTC 24 |
| Peak memory | 269812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2630644035 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ max_throughput.2630644035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/28.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.3115093340 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 1467910789 ps |
| CPU time | 84.42 seconds |
| Started | Aug 29 01:46:45 AM UTC 24 |
| Finished | Aug 29 01:48:12 AM UTC 24 |
| Peak memory | 221744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115093340 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_mem_partial_access.3115093340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/28.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.1636611786 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 295367759211 ps |
| CPU time | 639.3 seconds |
| Started | Aug 29 01:46:28 AM UTC 24 |
| Finished | Aug 29 01:57:16 AM UTC 24 |
| Peak memory | 221812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636611786 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_mem_walk.1636611786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/28.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.3460153767 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 56531619707 ps |
| CPU time | 389.5 seconds |
| Started | Aug 29 01:44:51 AM UTC 24 |
| Finished | Aug 29 01:51:25 AM UTC 24 |
| Peak memory | 363980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460153767 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multiple_keys.3460153767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/28.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access.3745179856 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 1212421167 ps |
| CPU time | 27.56 seconds |
| Started | Aug 29 01:45:07 AM UTC 24 |
| Finished | Aug 29 01:45:36 AM UTC 24 |
| Peak memory | 211484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745179856 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_partial_access.3745179856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/28.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.2280313401 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 64730015502 ps |
| CPU time | 625.84 seconds |
| Started | Aug 29 01:45:14 AM UTC 24 |
| Finished | Aug 29 01:55:48 AM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280313401 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_partial_a ccess_b2b.2280313401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/28.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.3330522604 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 355784372 ps |
| CPU time | 5.58 seconds |
| Started | Aug 29 01:46:21 AM UTC 24 |
| Finished | Aug 29 01:46:28 AM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330522604 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.3330522604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/28.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_regwen.740566334 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 15694991815 ps |
| CPU time | 196.49 seconds |
| Started | Aug 29 01:46:01 AM UTC 24 |
| Finished | Aug 29 01:49:20 AM UTC 24 |
| Peak memory | 386528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740566334 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.740566334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/28.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_smoke.1413946631 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 6665300928 ps |
| CPU time | 24.71 seconds |
| Started | Aug 29 01:44:48 AM UTC 24 |
| Finished | Aug 29 01:45:14 AM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413946631 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.1413946631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/28.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all.4127889983 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 108408072957 ps |
| CPU time | 3586.42 seconds |
| Started | Aug 29 01:47:37 AM UTC 24 |
| Finished | Aug 29 02:48:03 AM UTC 24 |
| Peak memory | 384100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41278899 83 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_a ll.4127889983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/28.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.412710601 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 485094058 ps |
| CPU time | 33.22 seconds |
| Started | Aug 29 01:47:02 AM UTC 24 |
| Finished | Aug 29 01:47:36 AM UTC 24 |
| Peak memory | 221808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412710601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.412710601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/28.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.3672651271 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 4009353256 ps |
| CPU time | 335.31 seconds |
| Started | Aug 29 01:45:02 AM UTC 24 |
| Finished | Aug 29 01:50:42 AM UTC 24 |
| Peak memory | 211652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672651271 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_pipeline.3672651271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/28.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.2917292118 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 2892700886 ps |
| CPU time | 42.46 seconds |
| Started | Aug 29 01:45:37 AM UTC 24 |
| Finished | Aug 29 01:46:20 AM UTC 24 |
| Peak memory | 294440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2917292118 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl _throughput_w_partial_write.2917292118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/28.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.3390323843 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 10944251718 ps |
| CPU time | 619.78 seconds |
| Started | Aug 29 01:50:20 AM UTC 24 |
| Finished | Aug 29 02:00:48 AM UTC 24 |
| Peak memory | 384484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390323843 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_access_duri ng_key_req.3390323843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/29.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_alert_test.1081317272 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 23708488 ps |
| CPU time | 0.97 seconds |
| Started | Aug 29 01:51:26 AM UTC 24 |
| Finished | Aug 29 01:51:28 AM UTC 24 |
| Peak memory | 210736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081317272 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_alert_test.1081317272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/29.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_bijection.1068645869 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 35511018838 ps |
| CPU time | 1631.65 seconds |
| Started | Aug 29 01:48:16 AM UTC 24 |
| Finished | Aug 29 02:15:48 AM UTC 24 |
| Peak memory | 213376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068645869 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection.1068645869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/29.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_executable.3865428167 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 6016430116 ps |
| CPU time | 547.08 seconds |
| Started | Aug 29 01:50:29 AM UTC 24 |
| Finished | Aug 29 01:59:42 AM UTC 24 |
| Peak memory | 388488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865428167 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executable.3865428167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/29.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.1043184809 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 63798504398 ps |
| CPU time | 73.67 seconds |
| Started | Aug 29 01:50:17 AM UTC 24 |
| Finished | Aug 29 01:51:33 AM UTC 24 |
| Peak memory | 211512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043184809 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_escalation.1043184809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/29.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.329964458 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 6284835614 ps |
| CPU time | 20.98 seconds |
| Started | Aug 29 01:49:54 AM UTC 24 |
| Finished | Aug 29 01:50:16 AM UTC 24 |
| Peak memory | 255464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 329964458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_m ax_throughput.329964458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/29.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.1571958038 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 5139617844 ps |
| CPU time | 221.71 seconds |
| Started | Aug 29 01:50:42 AM UTC 24 |
| Finished | Aug 29 01:54:27 AM UTC 24 |
| Peak memory | 221996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571958038 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_mem_partial_access.1571958038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/29.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.3708326615 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 82675722383 ps |
| CPU time | 401 seconds |
| Started | Aug 29 01:50:42 AM UTC 24 |
| Finished | Aug 29 01:57:28 AM UTC 24 |
| Peak memory | 221940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708326615 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_mem_walk.3708326615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/29.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.236220615 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 21321292492 ps |
| CPU time | 1284.11 seconds |
| Started | Aug 29 01:48:12 AM UTC 24 |
| Finished | Aug 29 02:09:51 AM UTC 24 |
| Peak memory | 390708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236220615 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multiple_keys.236220615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/29.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access.467532863 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 1528630072 ps |
| CPU time | 36.37 seconds |
| Started | Aug 29 01:49:21 AM UTC 24 |
| Finished | Aug 29 01:49:59 AM UTC 24 |
| Peak memory | 286148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467532863 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_partial_access.467532863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/29.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.2322837699 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 31652304764 ps |
| CPU time | 630.48 seconds |
| Started | Aug 29 01:49:24 AM UTC 24 |
| Finished | Aug 29 02:00:03 AM UTC 24 |
| Peak memory | 211572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322837699 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_partial_a ccess_b2b.2322837699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/29.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.3017879527 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 360518432 ps |
| CPU time | 4.86 seconds |
| Started | Aug 29 01:50:35 AM UTC 24 |
| Finished | Aug 29 01:50:41 AM UTC 24 |
| Peak memory | 211840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017879527 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.3017879527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/29.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_regwen.1556852391 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 27163034254 ps |
| CPU time | 571.78 seconds |
| Started | Aug 29 01:50:29 AM UTC 24 |
| Finished | Aug 29 02:00:07 AM UTC 24 |
| Peak memory | 384552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556852391 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.1556852391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/29.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_smoke.2193188441 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 4297075306 ps |
| CPU time | 30.35 seconds |
| Started | Aug 29 01:47:44 AM UTC 24 |
| Finished | Aug 29 01:48:16 AM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193188441 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.2193188441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/29.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all.272989621 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 834309930644 ps |
| CPU time | 7195.25 seconds |
| Started | Aug 29 01:50:53 AM UTC 24 |
| Finished | Aug 29 03:52:02 AM UTC 24 |
| Peak memory | 390192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27298962 1 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all.272989621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/29.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.45750560 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 2909113907 ps |
| CPU time | 56.39 seconds |
| Started | Aug 29 01:50:43 AM UTC 24 |
| Finished | Aug 29 01:51:41 AM UTC 24 |
| Peak memory | 249444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45750560 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.45750560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/29.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.246522927 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 7030015674 ps |
| CPU time | 228.62 seconds |
| Started | Aug 29 01:48:48 AM UTC 24 |
| Finished | Aug 29 01:52:40 AM UTC 24 |
| Peak memory | 211752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246522927 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_pipeline.246522927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/29.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.3111424242 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 2948938443 ps |
| CPU time | 27.59 seconds |
| Started | Aug 29 01:49:59 AM UTC 24 |
| Finished | Aug 29 01:50:28 AM UTC 24 |
| Peak memory | 269868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3111424242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl _throughput_w_partial_write.3111424242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/29.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.1143612416 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 16337437699 ps |
| CPU time | 1232.74 seconds |
| Started | Aug 29 12:29:09 AM UTC 24 |
| Finished | Aug 29 12:49:56 AM UTC 24 |
| Peak memory | 386520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143612416 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_access_durin g_key_req.1143612416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/3.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_alert_test.4289400238 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 18624708 ps |
| CPU time | 0.97 seconds |
| Started | Aug 29 12:30:26 AM UTC 24 |
| Finished | Aug 29 12:30:28 AM UTC 24 |
| Peak memory | 210812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289400238 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_alert_test.4289400238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/3.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_bijection.921130160 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 290311411744 ps |
| CPU time | 2093.32 seconds |
| Started | Aug 29 12:28:21 AM UTC 24 |
| Finished | Aug 29 01:03:37 AM UTC 24 |
| Peak memory | 213308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921130160 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.921130160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/3.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_executable.3155987641 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 26723877381 ps |
| CPU time | 291.1 seconds |
| Started | Aug 29 12:29:11 AM UTC 24 |
| Finished | Aug 29 12:34:07 AM UTC 24 |
| Peak memory | 386600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155987641 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executable.3155987641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/3.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.3399281521 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 767350395 ps |
| CPU time | 53.76 seconds |
| Started | Aug 29 12:28:42 AM UTC 24 |
| Finished | Aug 29 12:29:38 AM UTC 24 |
| Peak memory | 319096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3399281521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_m ax_throughput.3399281521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/3.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.4121646195 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 10029737277 ps |
| CPU time | 210.23 seconds |
| Started | Aug 29 12:29:39 AM UTC 24 |
| Finished | Aug 29 12:33:12 AM UTC 24 |
| Peak memory | 221816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121646195 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_mem_partial_access.4121646195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/3.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.2933052989 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 10686050186 ps |
| CPU time | 216.58 seconds |
| Started | Aug 29 12:29:26 AM UTC 24 |
| Finished | Aug 29 12:33:06 AM UTC 24 |
| Peak memory | 221808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933052989 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_mem_walk.2933052989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/3.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.273209225 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 17172140422 ps |
| CPU time | 749.07 seconds |
| Started | Aug 29 12:28:20 AM UTC 24 |
| Finished | Aug 29 12:40:58 AM UTC 24 |
| Peak memory | 363996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273209225 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multiple_keys.273209225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/3.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access.3401828674 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 587033060 ps |
| CPU time | 38.51 seconds |
| Started | Aug 29 12:28:36 AM UTC 24 |
| Finished | Aug 29 12:29:16 AM UTC 24 |
| Peak memory | 286104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401828674 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_partial_access.3401828674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/3.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.3880283438 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 8737852378 ps |
| CPU time | 286.83 seconds |
| Started | Aug 29 12:28:39 AM UTC 24 |
| Finished | Aug 29 12:33:30 AM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880283438 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_partial_ac cess_b2b.3880283438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/3.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.2460089181 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 5589886730 ps |
| CPU time | 6.85 seconds |
| Started | Aug 29 12:29:17 AM UTC 24 |
| Finished | Aug 29 12:29:24 AM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460089181 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.2460089181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/3.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_regwen.2982052664 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 2782251518 ps |
| CPU time | 618.53 seconds |
| Started | Aug 29 12:29:13 AM UTC 24 |
| Finished | Aug 29 12:39:39 AM UTC 24 |
| Peak memory | 382416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982052664 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.2982052664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/3.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.3113966188 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 250260572 ps |
| CPU time | 3.31 seconds |
| Started | Aug 29 12:30:23 AM UTC 24 |
| Finished | Aug 29 12:30:27 AM UTC 24 |
| Peak memory | 247768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113966188 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_sec_cm.3113966188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/3.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_smoke.954073648 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 497625755 ps |
| CPU time | 21.52 seconds |
| Started | Aug 29 12:28:18 AM UTC 24 |
| Finished | Aug 29 12:28:41 AM UTC 24 |
| Peak memory | 211740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954073648 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.954073648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/3.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all.1028068636 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 199819953072 ps |
| CPU time | 3577.92 seconds |
| Started | Aug 29 12:30:08 AM UTC 24 |
| Finished | Aug 29 01:30:27 AM UTC 24 |
| Peak memory | 398428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10280686 36 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all.1028068636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/3.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.3759564025 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1563385198 ps |
| CPU time | 17.31 seconds |
| Started | Aug 29 12:30:04 AM UTC 24 |
| Finished | Aug 29 12:30:22 AM UTC 24 |
| Peak memory | 228012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759564025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.3759564025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/3.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.3341206613 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 33994295466 ps |
| CPU time | 336.43 seconds |
| Started | Aug 29 12:28:25 AM UTC 24 |
| Finished | Aug 29 12:34:06 AM UTC 24 |
| Peak memory | 211752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341206613 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_pipeline.3341206613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/3.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.722873866 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 4255921166 ps |
| CPU time | 14.76 seconds |
| Started | Aug 29 12:28:57 AM UTC 24 |
| Finished | Aug 29 12:29:13 AM UTC 24 |
| Peak memory | 232988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =722873866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_t hroughput_w_partial_write.722873866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/3.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.2192467992 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 25937959252 ps |
| CPU time | 704.25 seconds |
| Started | Aug 29 01:52:36 AM UTC 24 |
| Finished | Aug 29 02:04:28 AM UTC 24 |
| Peak memory | 386592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192467992 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_access_duri ng_key_req.2192467992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/30.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_alert_test.429650368 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 31658193 ps |
| CPU time | 1.08 seconds |
| Started | Aug 29 01:54:43 AM UTC 24 |
| Finished | Aug 29 01:54:45 AM UTC 24 |
| Peak memory | 210812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429650368 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_alert_test.429650368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/30.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_bijection.1221382506 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 33783359187 ps |
| CPU time | 869.25 seconds |
| Started | Aug 29 01:51:34 AM UTC 24 |
| Finished | Aug 29 02:06:14 AM UTC 24 |
| Peak memory | 211776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221382506 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection.1221382506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/30.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_executable.100710933 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 13471111572 ps |
| CPU time | 693.51 seconds |
| Started | Aug 29 01:52:41 AM UTC 24 |
| Finished | Aug 29 02:04:22 AM UTC 24 |
| Peak memory | 380440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100710933 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executable.100710933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/30.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.640958805 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 1482308294 ps |
| CPU time | 17.04 seconds |
| Started | Aug 29 01:52:16 AM UTC 24 |
| Finished | Aug 29 01:52:35 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640958805 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_escalation.640958805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/30.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.3575959319 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 3210885531 ps |
| CPU time | 98.71 seconds |
| Started | Aug 29 01:51:53 AM UTC 24 |
| Finished | Aug 29 01:53:34 AM UTC 24 |
| Peak memory | 382632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3575959319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ max_throughput.3575959319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/30.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.1651462557 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 6269916314 ps |
| CPU time | 114.07 seconds |
| Started | Aug 29 01:54:00 AM UTC 24 |
| Finished | Aug 29 01:55:57 AM UTC 24 |
| Peak memory | 221860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651462557 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_mem_partial_access.1651462557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/30.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.2235310036 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 28180424354 ps |
| CPU time | 446.84 seconds |
| Started | Aug 29 01:53:42 AM UTC 24 |
| Finished | Aug 29 02:01:15 AM UTC 24 |
| Peak memory | 221936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235310036 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_mem_walk.2235310036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/30.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.2365805061 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 19346511177 ps |
| CPU time | 531.19 seconds |
| Started | Aug 29 01:51:30 AM UTC 24 |
| Finished | Aug 29 02:00:28 AM UTC 24 |
| Peak memory | 386508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365805061 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multiple_keys.2365805061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/30.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access.95291124 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 420011362 ps |
| CPU time | 8.67 seconds |
| Started | Aug 29 01:51:43 AM UTC 24 |
| Finished | Aug 29 01:51:53 AM UTC 24 |
| Peak memory | 211424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95291124 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_partial_access.95291124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/30.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.807509616 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 9832859459 ps |
| CPU time | 185.65 seconds |
| Started | Aug 29 01:51:53 AM UTC 24 |
| Finished | Aug 29 01:55:02 AM UTC 24 |
| Peak memory | 211652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807509616 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_partial_ac cess_b2b.807509616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/30.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.954746702 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 346843039 ps |
| CPU time | 5.63 seconds |
| Started | Aug 29 01:53:35 AM UTC 24 |
| Finished | Aug 29 01:53:42 AM UTC 24 |
| Peak memory | 211840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954746702 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.954746702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/30.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_regwen.1719713598 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 14152504631 ps |
| CPU time | 409.22 seconds |
| Started | Aug 29 01:53:14 AM UTC 24 |
| Finished | Aug 29 02:00:09 AM UTC 24 |
| Peak memory | 372260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719713598 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.1719713598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/30.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_smoke.2476312772 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 1191401334 ps |
| CPU time | 24.07 seconds |
| Started | Aug 29 01:51:27 AM UTC 24 |
| Finished | Aug 29 01:51:52 AM UTC 24 |
| Peak memory | 211680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476312772 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.2476312772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/30.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_all.359600658 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 200791897180 ps |
| CPU time | 5906.29 seconds |
| Started | Aug 29 01:54:29 AM UTC 24 |
| Finished | Aug 29 03:33:58 AM UTC 24 |
| Peak memory | 392624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35960065 8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all.359600658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/30.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.1513623019 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 7443100070 ps |
| CPU time | 64.55 seconds |
| Started | Aug 29 01:54:14 AM UTC 24 |
| Finished | Aug 29 01:55:21 AM UTC 24 |
| Peak memory | 221936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513623019 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.1513623019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/30.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.3088503019 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 4509514411 ps |
| CPU time | 387.06 seconds |
| Started | Aug 29 01:51:42 AM UTC 24 |
| Finished | Aug 29 01:58:14 AM UTC 24 |
| Peak memory | 211652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088503019 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_pipeline.3088503019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/30.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.1379362297 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 2766922042 ps |
| CPU time | 20.55 seconds |
| Started | Aug 29 01:51:53 AM UTC 24 |
| Finished | Aug 29 01:52:15 AM UTC 24 |
| Peak memory | 247460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1379362297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl _throughput_w_partial_write.1379362297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/30.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.883561384 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 65802445480 ps |
| CPU time | 1255.8 seconds |
| Started | Aug 29 01:56:15 AM UTC 24 |
| Finished | Aug 29 02:17:26 AM UTC 24 |
| Peak memory | 386596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883561384 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_access_durin g_key_req.883561384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/31.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_alert_test.424389112 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 36237765 ps |
| CPU time | 1.02 seconds |
| Started | Aug 29 01:57:50 AM UTC 24 |
| Finished | Aug 29 01:57:52 AM UTC 24 |
| Peak memory | 210932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424389112 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_alert_test.424389112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/31.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_bijection.269471738 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 171573989502 ps |
| CPU time | 1045.77 seconds |
| Started | Aug 29 01:55:14 AM UTC 24 |
| Finished | Aug 29 02:12:52 AM UTC 24 |
| Peak memory | 211492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269471738 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection.269471738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/31.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_executable.451686417 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 24973165969 ps |
| CPU time | 860.23 seconds |
| Started | Aug 29 01:56:24 AM UTC 24 |
| Finished | Aug 29 02:10:54 AM UTC 24 |
| Peak memory | 388560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451686417 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executable.451686417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/31.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.1538177078 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 12435103960 ps |
| CPU time | 23.26 seconds |
| Started | Aug 29 01:55:59 AM UTC 24 |
| Finished | Aug 29 01:56:23 AM UTC 24 |
| Peak memory | 221804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538177078 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_escalation.1538177078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/31.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.2562668991 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 706676944 ps |
| CPU time | 22.91 seconds |
| Started | Aug 29 01:55:49 AM UTC 24 |
| Finished | Aug 29 01:56:14 AM UTC 24 |
| Peak memory | 265700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2562668991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ max_throughput.2562668991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/31.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.1323030092 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 17578539684 ps |
| CPU time | 201.34 seconds |
| Started | Aug 29 01:57:17 AM UTC 24 |
| Finished | Aug 29 02:00:42 AM UTC 24 |
| Peak memory | 222064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323030092 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_mem_partial_access.1323030092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/31.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.2947441822 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 43039691488 ps |
| CPU time | 409 seconds |
| Started | Aug 29 01:57:09 AM UTC 24 |
| Finished | Aug 29 02:04:04 AM UTC 24 |
| Peak memory | 211640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947441822 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_mem_walk.2947441822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/31.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.554907413 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 7857983355 ps |
| CPU time | 194.83 seconds |
| Started | Aug 29 01:55:03 AM UTC 24 |
| Finished | Aug 29 01:58:21 AM UTC 24 |
| Peak memory | 374452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554907413 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multiple_keys.554907413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/31.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access.2905290151 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 4666924081 ps |
| CPU time | 33.17 seconds |
| Started | Aug 29 01:55:23 AM UTC 24 |
| Finished | Aug 29 01:55:58 AM UTC 24 |
| Peak memory | 211568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905290151 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_partial_access.2905290151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/31.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.1408615955 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 12404050065 ps |
| CPU time | 317.47 seconds |
| Started | Aug 29 01:55:35 AM UTC 24 |
| Finished | Aug 29 02:00:57 AM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408615955 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_partial_a ccess_b2b.1408615955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/31.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.3385248176 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 358825266 ps |
| CPU time | 6.16 seconds |
| Started | Aug 29 01:57:01 AM UTC 24 |
| Finished | Aug 29 01:57:08 AM UTC 24 |
| Peak memory | 211840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385248176 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.3385248176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/31.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_regwen.304773182 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 22932145997 ps |
| CPU time | 1408.88 seconds |
| Started | Aug 29 01:56:41 AM UTC 24 |
| Finished | Aug 29 02:20:25 AM UTC 24 |
| Peak memory | 392368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304773182 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.304773182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/31.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_smoke.1418142365 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 3036006756 ps |
| CPU time | 34.81 seconds |
| Started | Aug 29 01:54:46 AM UTC 24 |
| Finished | Aug 29 01:55:22 AM UTC 24 |
| Peak memory | 304684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418142365 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.1418142365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/31.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_all.7255349 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 109767910559 ps |
| CPU time | 3596.91 seconds |
| Started | Aug 29 01:57:30 AM UTC 24 |
| Finished | Aug 29 02:58:03 AM UTC 24 |
| Peak memory | 394336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7255349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all.7255349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/31.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.330932292 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 1240632887 ps |
| CPU time | 101.53 seconds |
| Started | Aug 29 01:57:28 AM UTC 24 |
| Finished | Aug 29 01:59:11 AM UTC 24 |
| Peak memory | 329428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330932292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.330932292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/31.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.3398969562 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 10783957034 ps |
| CPU time | 340.01 seconds |
| Started | Aug 29 01:55:21 AM UTC 24 |
| Finished | Aug 29 02:01:06 AM UTC 24 |
| Peak memory | 211556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398969562 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_pipeline.3398969562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/31.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.3922174512 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 748622000 ps |
| CPU time | 40.62 seconds |
| Started | Aug 29 01:55:58 AM UTC 24 |
| Finished | Aug 29 01:56:40 AM UTC 24 |
| Peak memory | 304616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3922174512 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl _throughput_w_partial_write.3922174512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/31.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.2971331013 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 13007005416 ps |
| CPU time | 612.76 seconds |
| Started | Aug 29 02:00:09 AM UTC 24 |
| Finished | Aug 29 02:10:29 AM UTC 24 |
| Peak memory | 384528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971331013 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_access_duri ng_key_req.2971331013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/32.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_alert_test.1846683933 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 17288457 ps |
| CPU time | 1.06 seconds |
| Started | Aug 29 02:00:58 AM UTC 24 |
| Finished | Aug 29 02:01:00 AM UTC 24 |
| Peak memory | 210936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846683933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_alert_test.1846683933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/32.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_bijection.3030690502 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 46442109084 ps |
| CPU time | 1884.77 seconds |
| Started | Aug 29 01:58:15 AM UTC 24 |
| Finished | Aug 29 02:30:03 AM UTC 24 |
| Peak memory | 213224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030690502 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection.3030690502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/32.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_executable.671190542 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 3534939470 ps |
| CPU time | 271.32 seconds |
| Started | Aug 29 02:00:12 AM UTC 24 |
| Finished | Aug 29 02:04:48 AM UTC 24 |
| Peak memory | 378392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671190542 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executable.671190542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/32.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.3361393285 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 6287527528 ps |
| CPU time | 53.54 seconds |
| Started | Aug 29 02:00:08 AM UTC 24 |
| Finished | Aug 29 02:01:03 AM UTC 24 |
| Peak memory | 225976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361393285 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_escalation.3361393285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/32.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.2726363722 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 1568624962 ps |
| CPU time | 93.12 seconds |
| Started | Aug 29 01:59:43 AM UTC 24 |
| Finished | Aug 29 02:01:18 AM UTC 24 |
| Peak memory | 380392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2726363722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ max_throughput.2726363722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/32.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.2949341126 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 5138270538 ps |
| CPU time | 169.5 seconds |
| Started | Aug 29 02:00:49 AM UTC 24 |
| Finished | Aug 29 02:03:41 AM UTC 24 |
| Peak memory | 228836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949341126 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_mem_partial_access.2949341126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/32.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.3623953668 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 20740124906 ps |
| CPU time | 382.17 seconds |
| Started | Aug 29 02:00:46 AM UTC 24 |
| Finished | Aug 29 02:07:13 AM UTC 24 |
| Peak memory | 221888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623953668 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_mem_walk.3623953668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/32.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.1360126911 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 2984154109 ps |
| CPU time | 252.61 seconds |
| Started | Aug 29 01:58:08 AM UTC 24 |
| Finished | Aug 29 02:02:24 AM UTC 24 |
| Peak memory | 382512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360126911 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multiple_keys.1360126911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/32.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access.2852778446 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 563638477 ps |
| CPU time | 11.1 seconds |
| Started | Aug 29 01:59:13 AM UTC 24 |
| Finished | Aug 29 01:59:25 AM UTC 24 |
| Peak memory | 211628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852778446 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_partial_access.2852778446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/32.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.2478836095 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 18979387823 ps |
| CPU time | 233.9 seconds |
| Started | Aug 29 01:59:26 AM UTC 24 |
| Finished | Aug 29 02:03:23 AM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478836095 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_partial_a ccess_b2b.2478836095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/32.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.3489906053 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 355730768 ps |
| CPU time | 6.57 seconds |
| Started | Aug 29 02:00:43 AM UTC 24 |
| Finished | Aug 29 02:00:50 AM UTC 24 |
| Peak memory | 211840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489906053 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.3489906053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/32.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_regwen.318528753 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 6609406825 ps |
| CPU time | 943.83 seconds |
| Started | Aug 29 02:00:28 AM UTC 24 |
| Finished | Aug 29 02:16:22 AM UTC 24 |
| Peak memory | 386512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318528753 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.318528753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/32.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_smoke.1324521405 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 2916200671 ps |
| CPU time | 12.95 seconds |
| Started | Aug 29 01:57:53 AM UTC 24 |
| Finished | Aug 29 01:58:07 AM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324521405 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.1324521405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/32.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all.4153034990 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 46901267432 ps |
| CPU time | 2449.53 seconds |
| Started | Aug 29 02:00:55 AM UTC 24 |
| Finished | Aug 29 02:42:08 AM UTC 24 |
| Peak memory | 396252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41530349 90 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_a ll.4153034990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/32.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.808938160 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 5277375299 ps |
| CPU time | 568.89 seconds |
| Started | Aug 29 01:58:21 AM UTC 24 |
| Finished | Aug 29 02:07:58 AM UTC 24 |
| Peak memory | 211776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808938160 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_pipeline.808938160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/32.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.2268652519 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 779618271 ps |
| CPU time | 46.81 seconds |
| Started | Aug 29 02:00:06 AM UTC 24 |
| Finished | Aug 29 02:00:54 AM UTC 24 |
| Peak memory | 321124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2268652519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl _throughput_w_partial_write.2268652519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/32.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.1145496274 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 46610154031 ps |
| CPU time | 1245.61 seconds |
| Started | Aug 29 02:02:14 AM UTC 24 |
| Finished | Aug 29 02:23:14 AM UTC 24 |
| Peak memory | 388640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145496274 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_access_duri ng_key_req.1145496274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/33.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_alert_test.2559468581 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 15250876 ps |
| CPU time | 1.04 seconds |
| Started | Aug 29 02:03:24 AM UTC 24 |
| Finished | Aug 29 02:03:26 AM UTC 24 |
| Peak memory | 210876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559468581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_alert_test.2559468581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/33.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_bijection.1361394495 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 42391664310 ps |
| CPU time | 1037.61 seconds |
| Started | Aug 29 02:01:06 AM UTC 24 |
| Finished | Aug 29 02:18:36 AM UTC 24 |
| Peak memory | 211568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361394495 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection.1361394495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/33.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_executable.912945005 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 57749939805 ps |
| CPU time | 812.62 seconds |
| Started | Aug 29 02:02:25 AM UTC 24 |
| Finished | Aug 29 02:16:08 AM UTC 24 |
| Peak memory | 380384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912945005 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executable.912945005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/33.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.1538070232 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 52593204220 ps |
| CPU time | 198.6 seconds |
| Started | Aug 29 02:02:03 AM UTC 24 |
| Finished | Aug 29 02:05:25 AM UTC 24 |
| Peak memory | 221808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538070232 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_escalation.1538070232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/33.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.671063443 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 3142084331 ps |
| CPU time | 76.41 seconds |
| Started | Aug 29 02:01:25 AM UTC 24 |
| Finished | Aug 29 02:02:43 AM UTC 24 |
| Peak memory | 366248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 671063443 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_m ax_throughput.671063443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/33.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.2442183566 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 1800598675 ps |
| CPU time | 148 seconds |
| Started | Aug 29 02:02:51 AM UTC 24 |
| Finished | Aug 29 02:05:21 AM UTC 24 |
| Peak memory | 221736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442183566 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_mem_partial_access.2442183566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/33.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.1949289122 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 43044631921 ps |
| CPU time | 464.37 seconds |
| Started | Aug 29 02:02:44 AM UTC 24 |
| Finished | Aug 29 02:10:35 AM UTC 24 |
| Peak memory | 221928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949289122 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_mem_walk.1949289122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/33.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.646865291 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 13563708216 ps |
| CPU time | 480.88 seconds |
| Started | Aug 29 02:01:04 AM UTC 24 |
| Finished | Aug 29 02:09:11 AM UTC 24 |
| Peak memory | 390900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646865291 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multiple_keys.646865291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/33.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access.1742609002 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 1534562075 ps |
| CPU time | 9.32 seconds |
| Started | Aug 29 02:01:19 AM UTC 24 |
| Finished | Aug 29 02:01:29 AM UTC 24 |
| Peak memory | 211592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742609002 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_partial_access.1742609002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/33.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.3395071849 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 5049192066 ps |
| CPU time | 332.8 seconds |
| Started | Aug 29 02:01:25 AM UTC 24 |
| Finished | Aug 29 02:07:02 AM UTC 24 |
| Peak memory | 211812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395071849 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_partial_a ccess_b2b.3395071849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/33.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.880802850 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 3743511104 ps |
| CPU time | 8.64 seconds |
| Started | Aug 29 02:02:41 AM UTC 24 |
| Finished | Aug 29 02:02:50 AM UTC 24 |
| Peak memory | 211892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880802850 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.880802850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/33.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_regwen.425527449 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 1163100624 ps |
| CPU time | 150.37 seconds |
| Started | Aug 29 02:02:37 AM UTC 24 |
| Finished | Aug 29 02:05:10 AM UTC 24 |
| Peak memory | 376408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425527449 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.425527449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/33.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_smoke.3007035723 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 3371199449 ps |
| CPU time | 21.64 seconds |
| Started | Aug 29 02:01:01 AM UTC 24 |
| Finished | Aug 29 02:01:24 AM UTC 24 |
| Peak memory | 211740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007035723 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.3007035723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/33.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all.59369256 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 234944544622 ps |
| CPU time | 1761.76 seconds |
| Started | Aug 29 02:03:20 AM UTC 24 |
| Finished | Aug 29 02:33:02 AM UTC 24 |
| Peak memory | 306288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59369256 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all.59369256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/33.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.4123902590 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 553612242 ps |
| CPU time | 12.48 seconds |
| Started | Aug 29 02:03:06 AM UTC 24 |
| Finished | Aug 29 02:03:20 AM UTC 24 |
| Peak memory | 222076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123902590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.4123902590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/33.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.167929984 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 3971530812 ps |
| CPU time | 321.29 seconds |
| Started | Aug 29 02:01:16 AM UTC 24 |
| Finished | Aug 29 02:06:42 AM UTC 24 |
| Peak memory | 211512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167929984 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_pipeline.167929984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/33.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.4078214996 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 808991926 ps |
| CPU time | 92.44 seconds |
| Started | Aug 29 02:01:30 AM UTC 24 |
| Finished | Aug 29 02:03:05 AM UTC 24 |
| Peak memory | 368360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =4078214996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl _throughput_w_partial_write.4078214996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/33.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.730225746 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 49603559878 ps |
| CPU time | 575.01 seconds |
| Started | Aug 29 02:05:10 AM UTC 24 |
| Finished | Aug 29 02:14:53 AM UTC 24 |
| Peak memory | 374232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730225746 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_access_durin g_key_req.730225746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/34.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_alert_test.3960250211 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 43308621 ps |
| CPU time | 1.01 seconds |
| Started | Aug 29 02:06:42 AM UTC 24 |
| Finished | Aug 29 02:06:45 AM UTC 24 |
| Peak memory | 210876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960250211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_alert_test.3960250211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/34.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_bijection.378435704 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 507117846795 ps |
| CPU time | 1853.62 seconds |
| Started | Aug 29 02:04:05 AM UTC 24 |
| Finished | Aug 29 02:35:20 AM UTC 24 |
| Peak memory | 213180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378435704 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection.378435704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/34.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_executable.4098076408 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 103427670829 ps |
| CPU time | 1261.02 seconds |
| Started | Aug 29 02:05:23 AM UTC 24 |
| Finished | Aug 29 02:26:38 AM UTC 24 |
| Peak memory | 388584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098076408 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executable.4098076408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/34.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.3403902241 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 12237242238 ps |
| CPU time | 120.8 seconds |
| Started | Aug 29 02:05:07 AM UTC 24 |
| Finished | Aug 29 02:07:10 AM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403902241 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_escalation.3403902241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/34.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.2254433814 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 2824271520 ps |
| CPU time | 13.15 seconds |
| Started | Aug 29 02:04:49 AM UTC 24 |
| Finished | Aug 29 02:05:03 AM UTC 24 |
| Peak memory | 228200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2254433814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ max_throughput.2254433814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/34.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.2514993875 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 23723325912 ps |
| CPU time | 132.06 seconds |
| Started | Aug 29 02:06:15 AM UTC 24 |
| Finished | Aug 29 02:08:30 AM UTC 24 |
| Peak memory | 221852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514993875 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_mem_partial_access.2514993875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/34.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.3601300263 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 38408135047 ps |
| CPU time | 224.27 seconds |
| Started | Aug 29 02:05:38 AM UTC 24 |
| Finished | Aug 29 02:09:26 AM UTC 24 |
| Peak memory | 222076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601300263 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_mem_walk.3601300263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/34.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.92677585 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 132668969448 ps |
| CPU time | 1408.84 seconds |
| Started | Aug 29 02:03:42 AM UTC 24 |
| Finished | Aug 29 02:27:27 AM UTC 24 |
| Peak memory | 386584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92677585 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multiple_keys.92677585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/34.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access.2700878949 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 1001417399 ps |
| CPU time | 107.75 seconds |
| Started | Aug 29 02:04:29 AM UTC 24 |
| Finished | Aug 29 02:06:19 AM UTC 24 |
| Peak memory | 378264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700878949 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_partial_access.2700878949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/34.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.785156185 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 14671125810 ps |
| CPU time | 360.83 seconds |
| Started | Aug 29 02:04:49 AM UTC 24 |
| Finished | Aug 29 02:10:55 AM UTC 24 |
| Peak memory | 211648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785156185 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_partial_ac cess_b2b.785156185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/34.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.2555022567 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 516735748 ps |
| CPU time | 4.81 seconds |
| Started | Aug 29 02:05:31 AM UTC 24 |
| Finished | Aug 29 02:05:37 AM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555022567 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.2555022567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/34.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_regwen.557145170 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 88679365985 ps |
| CPU time | 1180.13 seconds |
| Started | Aug 29 02:05:26 AM UTC 24 |
| Finished | Aug 29 02:25:19 AM UTC 24 |
| Peak memory | 386524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557145170 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.557145170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/34.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_smoke.201098543 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 1278729898 ps |
| CPU time | 96.65 seconds |
| Started | Aug 29 02:03:27 AM UTC 24 |
| Finished | Aug 29 02:05:06 AM UTC 24 |
| Peak memory | 357788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201098543 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.201098543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/34.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all.635126400 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 267385875150 ps |
| CPU time | 3677.35 seconds |
| Started | Aug 29 02:06:25 AM UTC 24 |
| Finished | Aug 29 03:08:24 AM UTC 24 |
| Peak memory | 384068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63512640 0 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all.635126400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/34.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.1040527498 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 1834531796 ps |
| CPU time | 23.7 seconds |
| Started | Aug 29 02:06:20 AM UTC 24 |
| Finished | Aug 29 02:06:45 AM UTC 24 |
| Peak memory | 221948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040527498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.1040527498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/34.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.2149520169 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 15851911418 ps |
| CPU time | 344.75 seconds |
| Started | Aug 29 02:04:23 AM UTC 24 |
| Finished | Aug 29 02:10:13 AM UTC 24 |
| Peak memory | 211888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149520169 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_pipeline.2149520169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/34.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.1483410586 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 5041301306 ps |
| CPU time | 24.38 seconds |
| Started | Aug 29 02:05:04 AM UTC 24 |
| Finished | Aug 29 02:05:30 AM UTC 24 |
| Peak memory | 265744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1483410586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl _throughput_w_partial_write.1483410586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/34.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.436195516 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 13432927577 ps |
| CPU time | 711.28 seconds |
| Started | Aug 29 02:07:47 AM UTC 24 |
| Finished | Aug 29 02:19:47 AM UTC 24 |
| Peak memory | 382684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436195516 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_access_durin g_key_req.436195516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/35.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_alert_test.1241180246 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 21336101 ps |
| CPU time | 0.94 seconds |
| Started | Aug 29 02:09:52 AM UTC 24 |
| Finished | Aug 29 02:09:54 AM UTC 24 |
| Peak memory | 210816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241180246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_alert_test.1241180246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/35.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_bijection.3346970237 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 411005399171 ps |
| CPU time | 3070.81 seconds |
| Started | Aug 29 02:06:56 AM UTC 24 |
| Finished | Aug 29 02:58:41 AM UTC 24 |
| Peak memory | 213228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346970237 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection.3346970237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/35.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_executable.465164201 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 7377026974 ps |
| CPU time | 341.46 seconds |
| Started | Aug 29 02:07:59 AM UTC 24 |
| Finished | Aug 29 02:13:45 AM UTC 24 |
| Peak memory | 386448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465164201 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executable.465164201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/35.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.1577052808 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 18171112685 ps |
| CPU time | 119.16 seconds |
| Started | Aug 29 02:07:40 AM UTC 24 |
| Finished | Aug 29 02:09:41 AM UTC 24 |
| Peak memory | 211644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577052808 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_escalation.1577052808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/35.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.3805729750 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 2886837839 ps |
| CPU time | 22.71 seconds |
| Started | Aug 29 02:07:15 AM UTC 24 |
| Finished | Aug 29 02:07:39 AM UTC 24 |
| Peak memory | 261672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3805729750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ max_throughput.3805729750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/35.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.395769284 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 10121942978 ps |
| CPU time | 161.12 seconds |
| Started | Aug 29 02:09:27 AM UTC 24 |
| Finished | Aug 29 02:12:10 AM UTC 24 |
| Peak memory | 228952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395769284 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_mem_partial_access.395769284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/35.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.1928189382 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 49351258750 ps |
| CPU time | 509.96 seconds |
| Started | Aug 29 02:09:19 AM UTC 24 |
| Finished | Aug 29 02:17:56 AM UTC 24 |
| Peak memory | 221944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928189382 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_mem_walk.1928189382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/35.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.3775685133 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 58044871635 ps |
| CPU time | 1539.28 seconds |
| Started | Aug 29 02:06:46 AM UTC 24 |
| Finished | Aug 29 02:32:43 AM UTC 24 |
| Peak memory | 388736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775685133 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multiple_keys.3775685133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/35.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access.2591745300 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 2842780238 ps |
| CPU time | 18.01 seconds |
| Started | Aug 29 02:07:11 AM UTC 24 |
| Finished | Aug 29 02:07:30 AM UTC 24 |
| Peak memory | 211656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591745300 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_partial_access.2591745300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/35.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.591105082 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 15040849886 ps |
| CPU time | 392.24 seconds |
| Started | Aug 29 02:07:14 AM UTC 24 |
| Finished | Aug 29 02:13:52 AM UTC 24 |
| Peak memory | 211504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591105082 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_partial_ac cess_b2b.591105082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/35.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.915783969 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 1355564637 ps |
| CPU time | 6.49 seconds |
| Started | Aug 29 02:09:11 AM UTC 24 |
| Finished | Aug 29 02:09:19 AM UTC 24 |
| Peak memory | 211696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915783969 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.915783969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/35.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_regwen.27301096 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 22625195419 ps |
| CPU time | 1351.36 seconds |
| Started | Aug 29 02:08:30 AM UTC 24 |
| Finished | Aug 29 02:31:17 AM UTC 24 |
| Peak memory | 386716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27301096 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.27301096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/35.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_smoke.4157607384 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 1082261230 ps |
| CPU time | 27.07 seconds |
| Started | Aug 29 02:06:46 AM UTC 24 |
| Finished | Aug 29 02:07:14 AM UTC 24 |
| Peak memory | 211548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157607384 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.4157607384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/35.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all.3007375217 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 156605916692 ps |
| CPU time | 2646.16 seconds |
| Started | Aug 29 02:09:52 AM UTC 24 |
| Finished | Aug 29 02:54:27 AM UTC 24 |
| Peak memory | 394328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30073752 17 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_a ll.3007375217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/35.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.1359754144 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 250592233 ps |
| CPU time | 8.35 seconds |
| Started | Aug 29 02:09:42 AM UTC 24 |
| Finished | Aug 29 02:09:51 AM UTC 24 |
| Peak memory | 221820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359754144 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.1359754144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/35.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.2978106040 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 4431650323 ps |
| CPU time | 349.16 seconds |
| Started | Aug 29 02:07:03 AM UTC 24 |
| Finished | Aug 29 02:12:57 AM UTC 24 |
| Peak memory | 211588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978106040 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_pipeline.2978106040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/35.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.776909266 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 3522996471 ps |
| CPU time | 12.98 seconds |
| Started | Aug 29 02:07:31 AM UTC 24 |
| Finished | Aug 29 02:07:46 AM UTC 24 |
| Peak memory | 221976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =776909266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ throughput_w_partial_write.776909266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/35.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.2693501032 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 16624996991 ps |
| CPU time | 778.46 seconds |
| Started | Aug 29 02:11:12 AM UTC 24 |
| Finished | Aug 29 02:24:19 AM UTC 24 |
| Peak memory | 386528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693501032 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_access_duri ng_key_req.2693501032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/36.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_alert_test.691640618 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 16457819 ps |
| CPU time | 0.91 seconds |
| Started | Aug 29 02:13:08 AM UTC 24 |
| Finished | Aug 29 02:13:10 AM UTC 24 |
| Peak memory | 210732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691640618 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_alert_test.691640618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/36.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_bijection.3146067815 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 215337150934 ps |
| CPU time | 2063.27 seconds |
| Started | Aug 29 02:10:29 AM UTC 24 |
| Finished | Aug 29 02:45:15 AM UTC 24 |
| Peak memory | 213256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146067815 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection.3146067815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/36.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_executable.817408222 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 21882313946 ps |
| CPU time | 1319.72 seconds |
| Started | Aug 29 02:11:17 AM UTC 24 |
| Finished | Aug 29 02:33:31 AM UTC 24 |
| Peak memory | 388640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817408222 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executable.817408222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/36.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.4116724132 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 99515916192 ps |
| CPU time | 129.09 seconds |
| Started | Aug 29 02:10:56 AM UTC 24 |
| Finished | Aug 29 02:13:07 AM UTC 24 |
| Peak memory | 211644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116724132 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_escalation.4116724132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/36.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.335581057 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 755064332 ps |
| CPU time | 25.48 seconds |
| Started | Aug 29 02:10:50 AM UTC 24 |
| Finished | Aug 29 02:11:16 AM UTC 24 |
| Peak memory | 269728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 335581057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_m ax_throughput.335581057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/36.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.2183028117 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 10943434989 ps |
| CPU time | 104.76 seconds |
| Started | Aug 29 02:12:39 AM UTC 24 |
| Finished | Aug 29 02:14:26 AM UTC 24 |
| Peak memory | 228864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183028117 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_mem_partial_access.2183028117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/36.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.246405170 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 41418881087 ps |
| CPU time | 182.76 seconds |
| Started | Aug 29 02:12:20 AM UTC 24 |
| Finished | Aug 29 02:15:25 AM UTC 24 |
| Peak memory | 211620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246405170 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_mem_walk.246405170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/36.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.148532132 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 39395085149 ps |
| CPU time | 800.41 seconds |
| Started | Aug 29 02:10:13 AM UTC 24 |
| Finished | Aug 29 02:23:43 AM UTC 24 |
| Peak memory | 384548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148532132 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multiple_keys.148532132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/36.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access.4199552187 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 970590254 ps |
| CPU time | 66.05 seconds |
| Started | Aug 29 02:10:35 AM UTC 24 |
| Finished | Aug 29 02:11:43 AM UTC 24 |
| Peak memory | 349660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199552187 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_partial_access.4199552187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/36.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.411783505 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 43031403929 ps |
| CPU time | 698.46 seconds |
| Started | Aug 29 02:10:36 AM UTC 24 |
| Finished | Aug 29 02:22:23 AM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411783505 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_partial_ac cess_b2b.411783505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/36.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.3667206641 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 357674501 ps |
| CPU time | 6.33 seconds |
| Started | Aug 29 02:12:12 AM UTC 24 |
| Finished | Aug 29 02:12:19 AM UTC 24 |
| Peak memory | 211840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667206641 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.3667206641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/36.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_regwen.1731585675 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 29224318081 ps |
| CPU time | 912.21 seconds |
| Started | Aug 29 02:11:44 AM UTC 24 |
| Finished | Aug 29 02:27:07 AM UTC 24 |
| Peak memory | 388572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731585675 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.1731585675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/36.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_smoke.796636404 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 421187544 ps |
| CPU time | 52.63 seconds |
| Started | Aug 29 02:09:55 AM UTC 24 |
| Finished | Aug 29 02:10:49 AM UTC 24 |
| Peak memory | 333200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796636404 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.796636404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/36.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all.1106670835 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 252818412678 ps |
| CPU time | 5066.91 seconds |
| Started | Aug 29 02:12:58 AM UTC 24 |
| Finished | Aug 29 03:38:21 AM UTC 24 |
| Peak memory | 390440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11066708 35 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_a ll.1106670835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/36.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.4128439271 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1149561422 ps |
| CPU time | 84.68 seconds |
| Started | Aug 29 02:12:53 AM UTC 24 |
| Finished | Aug 29 02:14:20 AM UTC 24 |
| Peak memory | 374324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128439271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.4128439271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/36.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.768025133 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 1892104360 ps |
| CPU time | 182.53 seconds |
| Started | Aug 29 02:10:31 AM UTC 24 |
| Finished | Aug 29 02:13:37 AM UTC 24 |
| Peak memory | 211584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768025133 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_pipeline.768025133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/36.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.4131845012 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 700230872 ps |
| CPU time | 15.29 seconds |
| Started | Aug 29 02:10:55 AM UTC 24 |
| Finished | Aug 29 02:11:11 AM UTC 24 |
| Peak memory | 230880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =4131845012 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl _throughput_w_partial_write.4131845012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/36.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.2549493691 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 27483809117 ps |
| CPU time | 286.48 seconds |
| Started | Aug 29 02:14:54 AM UTC 24 |
| Finished | Aug 29 02:19:45 AM UTC 24 |
| Peak memory | 374300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549493691 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_access_duri ng_key_req.2549493691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/37.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_alert_test.3934557536 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 30077803 ps |
| CPU time | 1.04 seconds |
| Started | Aug 29 02:16:56 AM UTC 24 |
| Finished | Aug 29 02:16:59 AM UTC 24 |
| Peak memory | 210876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934557536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_alert_test.3934557536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/37.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_bijection.21909297 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 965458386413 ps |
| CPU time | 2839.27 seconds |
| Started | Aug 29 02:13:38 AM UTC 24 |
| Finished | Aug 29 03:01:28 AM UTC 24 |
| Peak memory | 213224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21909297 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection.21909297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/37.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_executable.2008094322 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 84266822930 ps |
| CPU time | 466 seconds |
| Started | Aug 29 02:15:27 AM UTC 24 |
| Finished | Aug 29 02:23:18 AM UTC 24 |
| Peak memory | 384464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008094322 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executable.2008094322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/37.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.2828275415 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 24955408984 ps |
| CPU time | 81.17 seconds |
| Started | Aug 29 02:14:36 AM UTC 24 |
| Finished | Aug 29 02:15:59 AM UTC 24 |
| Peak memory | 221804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828275415 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_escalation.2828275415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/37.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.1664619924 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 2672810925 ps |
| CPU time | 12.77 seconds |
| Started | Aug 29 02:14:21 AM UTC 24 |
| Finished | Aug 29 02:14:35 AM UTC 24 |
| Peak memory | 221864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1664619924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ max_throughput.1664619924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/37.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.1033738751 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 5020052524 ps |
| CPU time | 163.17 seconds |
| Started | Aug 29 02:16:09 AM UTC 24 |
| Finished | Aug 29 02:18:55 AM UTC 24 |
| Peak memory | 228856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033738751 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_mem_partial_access.1033738751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/37.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.766105556 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 13984250208 ps |
| CPU time | 362.42 seconds |
| Started | Aug 29 02:16:08 AM UTC 24 |
| Finished | Aug 29 02:22:15 AM UTC 24 |
| Peak memory | 221804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766105556 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_mem_walk.766105556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/37.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.865154719 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 40119189529 ps |
| CPU time | 476.71 seconds |
| Started | Aug 29 02:13:33 AM UTC 24 |
| Finished | Aug 29 02:21:36 AM UTC 24 |
| Peak memory | 370136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865154719 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multiple_keys.865154719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/37.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access.3603439492 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 1629029086 ps |
| CPU time | 26.41 seconds |
| Started | Aug 29 02:13:53 AM UTC 24 |
| Finished | Aug 29 02:14:20 AM UTC 24 |
| Peak memory | 269796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603439492 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_partial_access.3603439492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/37.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.3892760578 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 4911753352 ps |
| CPU time | 299.51 seconds |
| Started | Aug 29 02:14:20 AM UTC 24 |
| Finished | Aug 29 02:19:24 AM UTC 24 |
| Peak memory | 211576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892760578 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_partial_a ccess_b2b.3892760578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/37.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.1575977391 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 1396727452 ps |
| CPU time | 5.73 seconds |
| Started | Aug 29 02:16:00 AM UTC 24 |
| Finished | Aug 29 02:16:07 AM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575977391 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.1575977391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/37.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_regwen.514418950 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 3875569403 ps |
| CPU time | 440.1 seconds |
| Started | Aug 29 02:15:49 AM UTC 24 |
| Finished | Aug 29 02:23:15 AM UTC 24 |
| Peak memory | 376348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514418950 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.514418950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/37.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_smoke.2167945875 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 10157638814 ps |
| CPU time | 19.97 seconds |
| Started | Aug 29 02:13:11 AM UTC 24 |
| Finished | Aug 29 02:13:33 AM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167945875 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.2167945875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/37.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all.3549902777 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 650455270049 ps |
| CPU time | 4098.64 seconds |
| Started | Aug 29 02:16:23 AM UTC 24 |
| Finished | Aug 29 03:25:27 AM UTC 24 |
| Peak memory | 390236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35499027 77 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_a ll.3549902777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/37.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.4152090809 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 8702696039 ps |
| CPU time | 39.99 seconds |
| Started | Aug 29 02:16:14 AM UTC 24 |
| Finished | Aug 29 02:16:56 AM UTC 24 |
| Peak memory | 222152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152090809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.4152090809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/37.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.2653967754 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 3211509315 ps |
| CPU time | 246.73 seconds |
| Started | Aug 29 02:13:46 AM UTC 24 |
| Finished | Aug 29 02:17:56 AM UTC 24 |
| Peak memory | 211752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653967754 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_pipeline.2653967754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/37.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.776372011 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 6472501183 ps |
| CPU time | 103.64 seconds |
| Started | Aug 29 02:14:27 AM UTC 24 |
| Finished | Aug 29 02:16:13 AM UTC 24 |
| Peak memory | 370400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =776372011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ throughput_w_partial_write.776372011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/37.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.3419764258 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 10680097288 ps |
| CPU time | 611.05 seconds |
| Started | Aug 29 02:19:23 AM UTC 24 |
| Finished | Aug 29 02:29:42 AM UTC 24 |
| Peak memory | 382560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419764258 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_access_duri ng_key_req.3419764258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/38.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_alert_test.218398203 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 49242714 ps |
| CPU time | 0.98 seconds |
| Started | Aug 29 02:20:14 AM UTC 24 |
| Finished | Aug 29 02:20:16 AM UTC 24 |
| Peak memory | 210872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218398203 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_alert_test.218398203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/38.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_bijection.3689297500 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 431409010004 ps |
| CPU time | 2388.63 seconds |
| Started | Aug 29 02:17:57 AM UTC 24 |
| Finished | Aug 29 02:58:15 AM UTC 24 |
| Peak memory | 213180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689297500 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection.3689297500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/38.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_executable.2102058056 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 10421131096 ps |
| CPU time | 730.23 seconds |
| Started | Aug 29 02:19:25 AM UTC 24 |
| Finished | Aug 29 02:31:45 AM UTC 24 |
| Peak memory | 388772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102058056 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executable.2102058056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/38.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.3932346886 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 51325505180 ps |
| CPU time | 74.77 seconds |
| Started | Aug 29 02:19:07 AM UTC 24 |
| Finished | Aug 29 02:20:23 AM UTC 24 |
| Peak memory | 211632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932346886 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_escalation.3932346886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/38.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.3013662862 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 732401733 ps |
| CPU time | 26.31 seconds |
| Started | Aug 29 02:18:54 AM UTC 24 |
| Finished | Aug 29 02:19:22 AM UTC 24 |
| Peak memory | 298416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3013662862 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ max_throughput.3013662862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/38.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.2059740774 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 5107408822 ps |
| CPU time | 169.33 seconds |
| Started | Aug 29 02:19:53 AM UTC 24 |
| Finished | Aug 29 02:22:45 AM UTC 24 |
| Peak memory | 229068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059740774 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_mem_partial_access.2059740774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/38.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.886153999 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 52533906964 ps |
| CPU time | 192.9 seconds |
| Started | Aug 29 02:19:47 AM UTC 24 |
| Finished | Aug 29 02:23:03 AM UTC 24 |
| Peak memory | 221880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886153999 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_mem_walk.886153999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/38.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.1441530698 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 33495227391 ps |
| CPU time | 365.39 seconds |
| Started | Aug 29 02:17:27 AM UTC 24 |
| Finished | Aug 29 02:23:37 AM UTC 24 |
| Peak memory | 380456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441530698 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multiple_keys.1441530698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/38.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access.910429313 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 7392463247 ps |
| CPU time | 32.92 seconds |
| Started | Aug 29 02:18:31 AM UTC 24 |
| Finished | Aug 29 02:19:06 AM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910429313 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_partial_access.910429313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/38.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.3286869085 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 252338844199 ps |
| CPU time | 441.04 seconds |
| Started | Aug 29 02:18:37 AM UTC 24 |
| Finished | Aug 29 02:26:04 AM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286869085 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_partial_a ccess_b2b.3286869085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/38.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.368980655 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 3721011524 ps |
| CPU time | 6.36 seconds |
| Started | Aug 29 02:19:45 AM UTC 24 |
| Finished | Aug 29 02:19:53 AM UTC 24 |
| Peak memory | 211896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368980655 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.368980655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/38.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_regwen.2526367614 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 77103022167 ps |
| CPU time | 1336.61 seconds |
| Started | Aug 29 02:19:35 AM UTC 24 |
| Finished | Aug 29 02:42:07 AM UTC 24 |
| Peak memory | 388652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526367614 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.2526367614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/38.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_smoke.4053872924 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 3947295168 ps |
| CPU time | 111.96 seconds |
| Started | Aug 29 02:17:00 AM UTC 24 |
| Finished | Aug 29 02:18:54 AM UTC 24 |
| Peak memory | 376272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053872924 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.4053872924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/38.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all.1805081364 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 35482142147 ps |
| CPU time | 2593.56 seconds |
| Started | Aug 29 02:20:07 AM UTC 24 |
| Finished | Aug 29 03:03:48 AM UTC 24 |
| Peak memory | 390448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18050813 64 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_a ll.1805081364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/38.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.2853750645 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 271335435 ps |
| CPU time | 18.45 seconds |
| Started | Aug 29 02:19:54 AM UTC 24 |
| Finished | Aug 29 02:20:13 AM UTC 24 |
| Peak memory | 223924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853750645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.2853750645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/38.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.80112289 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 6286957182 ps |
| CPU time | 455.04 seconds |
| Started | Aug 29 02:17:57 AM UTC 24 |
| Finished | Aug 29 02:25:38 AM UTC 24 |
| Peak memory | 211628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80112289 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_pipeline.80112289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/38.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.673705707 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 764629149 ps |
| CPU time | 54.94 seconds |
| Started | Aug 29 02:18:56 AM UTC 24 |
| Finished | Aug 29 02:19:53 AM UTC 24 |
| Peak memory | 318880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =673705707 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ throughput_w_partial_write.673705707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/38.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.1973237080 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 10439031512 ps |
| CPU time | 1058.2 seconds |
| Started | Aug 29 02:23:13 AM UTC 24 |
| Finished | Aug 29 02:41:05 AM UTC 24 |
| Peak memory | 380444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973237080 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_access_duri ng_key_req.1973237080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/39.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_alert_test.3846131960 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 49142104 ps |
| CPU time | 1.01 seconds |
| Started | Aug 29 02:23:50 AM UTC 24 |
| Finished | Aug 29 02:23:52 AM UTC 24 |
| Peak memory | 210816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846131960 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_alert_test.3846131960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/39.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_bijection.186487277 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 331789648006 ps |
| CPU time | 1879.21 seconds |
| Started | Aug 29 02:20:26 AM UTC 24 |
| Finished | Aug 29 02:52:07 AM UTC 24 |
| Peak memory | 213224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186487277 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection.186487277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/39.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_executable.4089180853 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 23028262428 ps |
| CPU time | 598.48 seconds |
| Started | Aug 29 02:23:15 AM UTC 24 |
| Finished | Aug 29 02:33:21 AM UTC 24 |
| Peak memory | 380584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089180853 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executable.4089180853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/39.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.3026060756 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 198990055571 ps |
| CPU time | 138.43 seconds |
| Started | Aug 29 02:23:04 AM UTC 24 |
| Finished | Aug 29 02:25:25 AM UTC 24 |
| Peak memory | 225980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026060756 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_escalation.3026060756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/39.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.1110669303 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 799992867 ps |
| CPU time | 83.45 seconds |
| Started | Aug 29 02:22:24 AM UTC 24 |
| Finished | Aug 29 02:23:49 AM UTC 24 |
| Peak memory | 361956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1110669303 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ max_throughput.1110669303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/39.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.3831270433 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 7428655025 ps |
| CPU time | 93.83 seconds |
| Started | Aug 29 02:23:33 AM UTC 24 |
| Finished | Aug 29 02:25:09 AM UTC 24 |
| Peak memory | 221800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831270433 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_mem_partial_access.3831270433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/39.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.2946321525 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 138549064990 ps |
| CPU time | 176.43 seconds |
| Started | Aug 29 02:23:25 AM UTC 24 |
| Finished | Aug 29 02:26:24 AM UTC 24 |
| Peak memory | 221872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946321525 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_mem_walk.2946321525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/39.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.2584493818 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 22092444848 ps |
| CPU time | 1153.02 seconds |
| Started | Aug 29 02:20:24 AM UTC 24 |
| Finished | Aug 29 02:39:50 AM UTC 24 |
| Peak memory | 388636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584493818 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multiple_keys.2584493818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/39.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access.3174238357 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 1783773605 ps |
| CPU time | 84.22 seconds |
| Started | Aug 29 02:22:06 AM UTC 24 |
| Finished | Aug 29 02:23:32 AM UTC 24 |
| Peak memory | 376288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174238357 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_partial_access.3174238357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/39.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.3656555199 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 7387106134 ps |
| CPU time | 446.4 seconds |
| Started | Aug 29 02:22:16 AM UTC 24 |
| Finished | Aug 29 02:29:48 AM UTC 24 |
| Peak memory | 211504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656555199 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_partial_a ccess_b2b.3656555199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/39.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.2293473591 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 710353761 ps |
| CPU time | 4.31 seconds |
| Started | Aug 29 02:23:19 AM UTC 24 |
| Finished | Aug 29 02:23:24 AM UTC 24 |
| Peak memory | 211624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293473591 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.2293473591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/39.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_regwen.3265574342 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 27370673227 ps |
| CPU time | 551.9 seconds |
| Started | Aug 29 02:23:16 AM UTC 24 |
| Finished | Aug 29 02:32:34 AM UTC 24 |
| Peak memory | 384552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265574342 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.3265574342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/39.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_smoke.568193492 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 2536815890 ps |
| CPU time | 105.61 seconds |
| Started | Aug 29 02:20:17 AM UTC 24 |
| Finished | Aug 29 02:22:05 AM UTC 24 |
| Peak memory | 378344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568193492 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.568193492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/39.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all.741549304 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 76380330398 ps |
| CPU time | 2519.4 seconds |
| Started | Aug 29 02:23:44 AM UTC 24 |
| Finished | Aug 29 03:06:10 AM UTC 24 |
| Peak memory | 398432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74154930 4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all.741549304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/39.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.1237987765 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 7508840609 ps |
| CPU time | 55.15 seconds |
| Started | Aug 29 02:23:37 AM UTC 24 |
| Finished | Aug 29 02:24:34 AM UTC 24 |
| Peak memory | 223996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237987765 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.1237987765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/39.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.3354158240 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 35805540204 ps |
| CPU time | 329.11 seconds |
| Started | Aug 29 02:21:38 AM UTC 24 |
| Finished | Aug 29 02:27:11 AM UTC 24 |
| Peak memory | 211576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354158240 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_pipeline.3354158240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/39.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.592892618 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 2806006548 ps |
| CPU time | 25.26 seconds |
| Started | Aug 29 02:22:46 AM UTC 24 |
| Finished | Aug 29 02:23:13 AM UTC 24 |
| Peak memory | 261908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =592892618 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ throughput_w_partial_write.592892618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/39.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.2431259725 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 11087505164 ps |
| CPU time | 638.11 seconds |
| Started | Aug 29 12:31:09 AM UTC 24 |
| Finished | Aug 29 12:41:55 AM UTC 24 |
| Peak memory | 380376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431259725 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_access_durin g_key_req.2431259725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/4.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_alert_test.476281394 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 22039370 ps |
| CPU time | 0.99 seconds |
| Started | Aug 29 12:31:53 AM UTC 24 |
| Finished | Aug 29 12:31:55 AM UTC 24 |
| Peak memory | 210740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476281394 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_alert_test.476281394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/4.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_bijection.2043055443 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 22558359688 ps |
| CPU time | 778.41 seconds |
| Started | Aug 29 12:30:32 AM UTC 24 |
| Finished | Aug 29 12:43:40 AM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043055443 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection.2043055443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/4.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_executable.1935874309 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 7603536764 ps |
| CPU time | 73.38 seconds |
| Started | Aug 29 12:31:13 AM UTC 24 |
| Finished | Aug 29 12:32:28 AM UTC 24 |
| Peak memory | 329164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935874309 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executable.1935874309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/4.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.1236355393 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 6154126999 ps |
| CPU time | 58.73 seconds |
| Started | Aug 29 12:31:03 AM UTC 24 |
| Finished | Aug 29 12:32:03 AM UTC 24 |
| Peak memory | 221944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236355393 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_escalation.1236355393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/4.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.50698890 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 1491463302 ps |
| CPU time | 38.5 seconds |
| Started | Aug 29 12:31:01 AM UTC 24 |
| Finished | Aug 29 12:31:41 AM UTC 24 |
| Peak memory | 296344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 50698890 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_max _throughput.50698890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/4.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.4292088659 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 2687938703 ps |
| CPU time | 152.99 seconds |
| Started | Aug 29 12:31:27 AM UTC 24 |
| Finished | Aug 29 12:34:03 AM UTC 24 |
| Peak memory | 221812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292088659 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_mem_walk.4292088659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/4.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.1838339795 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 25473709948 ps |
| CPU time | 642.76 seconds |
| Started | Aug 29 12:30:29 AM UTC 24 |
| Finished | Aug 29 12:41:20 AM UTC 24 |
| Peak memory | 380380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838339795 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multiple_keys.1838339795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/4.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access.3736818108 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 1775378063 ps |
| CPU time | 47.28 seconds |
| Started | Aug 29 12:30:45 AM UTC 24 |
| Finished | Aug 29 12:31:34 AM UTC 24 |
| Peak memory | 306836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736818108 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_partial_access.3736818108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/4.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.3948491581 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 91894822706 ps |
| CPU time | 787.65 seconds |
| Started | Aug 29 12:30:49 AM UTC 24 |
| Finished | Aug 29 12:44:06 AM UTC 24 |
| Peak memory | 211708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948491581 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_partial_ac cess_b2b.3948491581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/4.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.2901097147 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 497469310 ps |
| CPU time | 6.35 seconds |
| Started | Aug 29 12:31:19 AM UTC 24 |
| Finished | Aug 29 12:31:26 AM UTC 24 |
| Peak memory | 211896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901097147 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.2901097147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/4.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_regwen.1163406869 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 237248547570 ps |
| CPU time | 1286.43 seconds |
| Started | Aug 29 12:31:17 AM UTC 24 |
| Finished | Aug 29 12:52:58 AM UTC 24 |
| Peak memory | 386464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163406869 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.1163406869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/4.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.2652305000 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 176914576 ps |
| CPU time | 2.77 seconds |
| Started | Aug 29 12:31:51 AM UTC 24 |
| Finished | Aug 29 12:31:55 AM UTC 24 |
| Peak memory | 247736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652305000 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_sec_cm.2652305000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/4.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_smoke.2664823004 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 1199823115 ps |
| CPU time | 38.52 seconds |
| Started | Aug 29 12:30:28 AM UTC 24 |
| Finished | Aug 29 12:31:08 AM UTC 24 |
| Peak memory | 312936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664823004 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.2664823004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/4.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all.2795124308 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 46385837401 ps |
| CPU time | 2898.26 seconds |
| Started | Aug 29 12:31:42 AM UTC 24 |
| Finished | Aug 29 01:20:28 AM UTC 24 |
| Peak memory | 392272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27951243 08 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all.2795124308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/4.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.1012075501 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 5054410718 ps |
| CPU time | 277.9 seconds |
| Started | Aug 29 12:30:43 AM UTC 24 |
| Finished | Aug 29 12:35:24 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012075501 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_pipeline.1012075501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/4.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.2187140757 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 4216975848 ps |
| CPU time | 12.2 seconds |
| Started | Aug 29 12:31:02 AM UTC 24 |
| Finished | Aug 29 12:31:15 AM UTC 24 |
| Peak memory | 225952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2187140757 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ throughput_w_partial_write.2187140757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/4.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.2223792377 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 64891896363 ps |
| CPU time | 841.02 seconds |
| Started | Aug 29 02:25:40 AM UTC 24 |
| Finished | Aug 29 02:39:50 AM UTC 24 |
| Peak memory | 388580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223792377 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_access_duri ng_key_req.2223792377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/40.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_alert_test.1246889080 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 46818684 ps |
| CPU time | 0.94 seconds |
| Started | Aug 29 02:26:46 AM UTC 24 |
| Finished | Aug 29 02:26:48 AM UTC 24 |
| Peak memory | 210876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246889080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_alert_test.1246889080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/40.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_bijection.2014919391 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 129648341347 ps |
| CPU time | 972.95 seconds |
| Started | Aug 29 02:24:20 AM UTC 24 |
| Finished | Aug 29 02:40:43 AM UTC 24 |
| Peak memory | 211288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014919391 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection.2014919391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/40.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_executable.2030494187 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 39813723555 ps |
| CPU time | 464.67 seconds |
| Started | Aug 29 02:25:50 AM UTC 24 |
| Finished | Aug 29 02:33:40 AM UTC 24 |
| Peak memory | 357920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030494187 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executable.2030494187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/40.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.2323720539 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 94428419765 ps |
| CPU time | 80 seconds |
| Started | Aug 29 02:25:25 AM UTC 24 |
| Finished | Aug 29 02:26:48 AM UTC 24 |
| Peak memory | 226176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323720539 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_escalation.2323720539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/40.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.890736282 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 813084420 ps |
| CPU time | 72.76 seconds |
| Started | Aug 29 02:25:09 AM UTC 24 |
| Finished | Aug 29 02:26:24 AM UTC 24 |
| Peak memory | 372328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 890736282 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_m ax_throughput.890736282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/40.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.2431616740 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 10043733071 ps |
| CPU time | 128.02 seconds |
| Started | Aug 29 02:26:24 AM UTC 24 |
| Finished | Aug 29 02:28:35 AM UTC 24 |
| Peak memory | 222052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431616740 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_mem_partial_access.2431616740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/40.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.2001293369 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 5258052425 ps |
| CPU time | 306.77 seconds |
| Started | Aug 29 02:26:13 AM UTC 24 |
| Finished | Aug 29 02:31:24 AM UTC 24 |
| Peak memory | 221884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001293369 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_mem_walk.2001293369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/40.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.1348113458 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 8092299544 ps |
| CPU time | 599.32 seconds |
| Started | Aug 29 02:23:56 AM UTC 24 |
| Finished | Aug 29 02:34:03 AM UTC 24 |
| Peak memory | 386596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348113458 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multiple_keys.1348113458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/40.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access.1826188067 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 1923107864 ps |
| CPU time | 28.84 seconds |
| Started | Aug 29 02:24:35 AM UTC 24 |
| Finished | Aug 29 02:25:05 AM UTC 24 |
| Peak memory | 267744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826188067 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_partial_access.1826188067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/40.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.4240587664 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 8275519819 ps |
| CPU time | 627.51 seconds |
| Started | Aug 29 02:25:06 AM UTC 24 |
| Finished | Aug 29 02:35:42 AM UTC 24 |
| Peak memory | 211768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240587664 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_partial_a ccess_b2b.4240587664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/40.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.3326680750 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 1871120135 ps |
| CPU time | 6 seconds |
| Started | Aug 29 02:26:05 AM UTC 24 |
| Finished | Aug 29 02:26:12 AM UTC 24 |
| Peak memory | 211840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326680750 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.3326680750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/40.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_regwen.2871826965 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 111406998852 ps |
| CPU time | 949.51 seconds |
| Started | Aug 29 02:25:52 AM UTC 24 |
| Finished | Aug 29 02:41:52 AM UTC 24 |
| Peak memory | 382440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871826965 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.2871826965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/40.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_smoke.1554156629 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 3726103174 ps |
| CPU time | 24.63 seconds |
| Started | Aug 29 02:23:53 AM UTC 24 |
| Finished | Aug 29 02:24:19 AM UTC 24 |
| Peak memory | 271816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554156629 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.1554156629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/40.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all.140680098 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 27991081503 ps |
| CPU time | 2822.01 seconds |
| Started | Aug 29 02:26:39 AM UTC 24 |
| Finished | Aug 29 03:14:10 AM UTC 24 |
| Peak memory | 392288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14068009 8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all.140680098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/40.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.273464340 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 3971414827 ps |
| CPU time | 17.86 seconds |
| Started | Aug 29 02:26:25 AM UTC 24 |
| Finished | Aug 29 02:26:44 AM UTC 24 |
| Peak memory | 221936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273464340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.273464340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/40.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.240465281 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 10183322681 ps |
| CPU time | 232.44 seconds |
| Started | Aug 29 02:24:20 AM UTC 24 |
| Finished | Aug 29 02:28:16 AM UTC 24 |
| Peak memory | 211232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240465281 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_pipeline.240465281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/40.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.699607555 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 8733904244 ps |
| CPU time | 29.27 seconds |
| Started | Aug 29 02:25:20 AM UTC 24 |
| Finished | Aug 29 02:25:51 AM UTC 24 |
| Peak memory | 261652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =699607555 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ throughput_w_partial_write.699607555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/40.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.3440171584 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 70992442320 ps |
| CPU time | 1451.67 seconds |
| Started | Aug 29 02:29:42 AM UTC 24 |
| Finished | Aug 29 02:54:10 AM UTC 24 |
| Peak memory | 388728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440171584 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_access_duri ng_key_req.3440171584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/41.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_alert_test.1911321380 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 14933434 ps |
| CPU time | 1.02 seconds |
| Started | Aug 29 02:31:18 AM UTC 24 |
| Finished | Aug 29 02:31:20 AM UTC 24 |
| Peak memory | 210876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911321380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_alert_test.1911321380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/41.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_executable.1913720089 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 30603147195 ps |
| CPU time | 460 seconds |
| Started | Aug 29 02:29:49 AM UTC 24 |
| Finished | Aug 29 02:37:35 AM UTC 24 |
| Peak memory | 382420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913720089 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executable.1913720089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/41.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.1545128379 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 19483470676 ps |
| CPU time | 91.07 seconds |
| Started | Aug 29 02:28:36 AM UTC 24 |
| Finished | Aug 29 02:30:09 AM UTC 24 |
| Peak memory | 221860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545128379 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_escalation.1545128379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/41.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.2650853850 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 963875423 ps |
| CPU time | 92.96 seconds |
| Started | Aug 29 02:28:17 AM UTC 24 |
| Finished | Aug 29 02:29:52 AM UTC 24 |
| Peak memory | 376360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2650853850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ max_throughput.2650853850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/41.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.3211989913 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 6548323723 ps |
| CPU time | 166.55 seconds |
| Started | Aug 29 02:30:04 AM UTC 24 |
| Finished | Aug 29 02:32:54 AM UTC 24 |
| Peak memory | 221944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211989913 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_mem_partial_access.3211989913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/41.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.694023612 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 9175026619 ps |
| CPU time | 235.93 seconds |
| Started | Aug 29 02:30:03 AM UTC 24 |
| Finished | Aug 29 02:34:03 AM UTC 24 |
| Peak memory | 221928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694023612 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_mem_walk.694023612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/41.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.2638982786 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 31935828467 ps |
| CPU time | 447.5 seconds |
| Started | Aug 29 02:26:49 AM UTC 24 |
| Finished | Aug 29 02:34:21 AM UTC 24 |
| Peak memory | 370144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638982786 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multiple_keys.2638982786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/41.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access.1559901480 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 884981747 ps |
| CPU time | 12.23 seconds |
| Started | Aug 29 02:27:28 AM UTC 24 |
| Finished | Aug 29 02:27:42 AM UTC 24 |
| Peak memory | 226780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559901480 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_partial_access.1559901480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/41.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.215442141 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 32614712654 ps |
| CPU time | 465.65 seconds |
| Started | Aug 29 02:27:43 AM UTC 24 |
| Finished | Aug 29 02:35:34 AM UTC 24 |
| Peak memory | 211776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215442141 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_partial_ac cess_b2b.215442141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/41.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.2648454496 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 709887533 ps |
| CPU time | 5.09 seconds |
| Started | Aug 29 02:29:56 AM UTC 24 |
| Finished | Aug 29 02:30:02 AM UTC 24 |
| Peak memory | 211700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648454496 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.2648454496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/41.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_regwen.1942136301 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 72714212989 ps |
| CPU time | 1344.79 seconds |
| Started | Aug 29 02:29:53 AM UTC 24 |
| Finished | Aug 29 02:52:31 AM UTC 24 |
| Peak memory | 390828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942136301 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.1942136301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/41.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_smoke.4122289945 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 437763740 ps |
| CPU time | 85.14 seconds |
| Started | Aug 29 02:26:49 AM UTC 24 |
| Finished | Aug 29 02:28:16 AM UTC 24 |
| Peak memory | 357852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122289945 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.4122289945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/41.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all.1932057352 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 207408227272 ps |
| CPU time | 3488.06 seconds |
| Started | Aug 29 02:30:26 AM UTC 24 |
| Finished | Aug 29 03:29:11 AM UTC 24 |
| Peak memory | 400548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19320573 52 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_a ll.1932057352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/41.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.3971489664 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 1104917241 ps |
| CPU time | 13.57 seconds |
| Started | Aug 29 02:30:10 AM UTC 24 |
| Finished | Aug 29 02:30:25 AM UTC 24 |
| Peak memory | 221864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971489664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.3971489664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/41.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.2558826842 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 21138010831 ps |
| CPU time | 246.85 seconds |
| Started | Aug 29 02:27:12 AM UTC 24 |
| Finished | Aug 29 02:31:23 AM UTC 24 |
| Peak memory | 211760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558826842 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_pipeline.2558826842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/41.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.2523110658 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 812706694 ps |
| CPU time | 96.15 seconds |
| Started | Aug 29 02:28:17 AM UTC 24 |
| Finished | Aug 29 02:29:55 AM UTC 24 |
| Peak memory | 368216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2523110658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl _throughput_w_partial_write.2523110658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/41.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.1017253123 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 5709363390 ps |
| CPU time | 479.18 seconds |
| Started | Aug 29 02:33:06 AM UTC 24 |
| Finished | Aug 29 02:41:12 AM UTC 24 |
| Peak memory | 380388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017253123 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_access_duri ng_key_req.1017253123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/42.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_alert_test.1046623293 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 24478519 ps |
| CPU time | 1.03 seconds |
| Started | Aug 29 02:34:04 AM UTC 24 |
| Finished | Aug 29 02:34:06 AM UTC 24 |
| Peak memory | 210876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046623293 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_alert_test.1046623293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/42.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_bijection.1812670507 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 230829678212 ps |
| CPU time | 1262.98 seconds |
| Started | Aug 29 02:31:25 AM UTC 24 |
| Finished | Aug 29 02:52:44 AM UTC 24 |
| Peak memory | 211632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812670507 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection.1812670507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/42.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_executable.2007120962 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 7300981799 ps |
| CPU time | 561.88 seconds |
| Started | Aug 29 02:33:22 AM UTC 24 |
| Finished | Aug 29 02:42:51 AM UTC 24 |
| Peak memory | 380636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007120962 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executable.2007120962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/42.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.518940926 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 17662091645 ps |
| CPU time | 68.27 seconds |
| Started | Aug 29 02:33:03 AM UTC 24 |
| Finished | Aug 29 02:34:13 AM UTC 24 |
| Peak memory | 211564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518940926 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_escalation.518940926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/42.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.871465849 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 3137138987 ps |
| CPU time | 73.99 seconds |
| Started | Aug 29 02:32:44 AM UTC 24 |
| Finished | Aug 29 02:33:59 AM UTC 24 |
| Peak memory | 362160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 871465849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_m ax_throughput.871465849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/42.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.1107802695 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 42770666977 ps |
| CPU time | 289.51 seconds |
| Started | Aug 29 02:33:49 AM UTC 24 |
| Finished | Aug 29 02:38:43 AM UTC 24 |
| Peak memory | 221880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107802695 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_mem_partial_access.1107802695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/42.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.174846691 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 10890955008 ps |
| CPU time | 267.05 seconds |
| Started | Aug 29 02:33:46 AM UTC 24 |
| Finished | Aug 29 02:38:17 AM UTC 24 |
| Peak memory | 221876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174846691 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_mem_walk.174846691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/42.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.285345225 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 1568867909 ps |
| CPU time | 138.55 seconds |
| Started | Aug 29 02:31:24 AM UTC 24 |
| Finished | Aug 29 02:33:45 AM UTC 24 |
| Peak memory | 353888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285345225 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multiple_keys.285345225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/42.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access.1857107761 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 1218189751 ps |
| CPU time | 28.38 seconds |
| Started | Aug 29 02:32:36 AM UTC 24 |
| Finished | Aug 29 02:33:05 AM UTC 24 |
| Peak memory | 211556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857107761 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_partial_access.1857107761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/42.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.2757156642 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 154598504358 ps |
| CPU time | 565.76 seconds |
| Started | Aug 29 02:32:36 AM UTC 24 |
| Finished | Aug 29 02:42:08 AM UTC 24 |
| Peak memory | 211776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757156642 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_partial_a ccess_b2b.2757156642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/42.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.244829789 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 1347652084 ps |
| CPU time | 6.44 seconds |
| Started | Aug 29 02:33:41 AM UTC 24 |
| Finished | Aug 29 02:33:48 AM UTC 24 |
| Peak memory | 211692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244829789 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.244829789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/42.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_regwen.1251738194 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 4678011069 ps |
| CPU time | 261.37 seconds |
| Started | Aug 29 02:33:31 AM UTC 24 |
| Finished | Aug 29 02:37:56 AM UTC 24 |
| Peak memory | 359892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251738194 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.1251738194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/42.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_smoke.2636186753 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 3857856288 ps |
| CPU time | 71.93 seconds |
| Started | Aug 29 02:31:21 AM UTC 24 |
| Finished | Aug 29 02:32:34 AM UTC 24 |
| Peak memory | 339744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636186753 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.2636186753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/42.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all.3528044093 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 427940232587 ps |
| CPU time | 5809.75 seconds |
| Started | Aug 29 02:34:04 AM UTC 24 |
| Finished | Aug 29 04:11:53 AM UTC 24 |
| Peak memory | 390076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35280440 93 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_a ll.3528044093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/42.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.2581946805 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 782115315 ps |
| CPU time | 33.51 seconds |
| Started | Aug 29 02:34:00 AM UTC 24 |
| Finished | Aug 29 02:34:35 AM UTC 24 |
| Peak memory | 222072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581946805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.2581946805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/42.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.2680525514 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 4925922254 ps |
| CPU time | 371.57 seconds |
| Started | Aug 29 02:31:45 AM UTC 24 |
| Finished | Aug 29 02:38:02 AM UTC 24 |
| Peak memory | 211580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680525514 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_pipeline.2680525514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/42.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.23578763 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 804005290 ps |
| CPU time | 92.52 seconds |
| Started | Aug 29 02:32:55 AM UTC 24 |
| Finished | Aug 29 02:34:29 AM UTC 24 |
| Peak memory | 374164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =23578763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_t hroughput_w_partial_write.23578763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/42.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.2135638232 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 13089267916 ps |
| CPU time | 551.45 seconds |
| Started | Aug 29 02:35:27 AM UTC 24 |
| Finished | Aug 29 02:44:45 AM UTC 24 |
| Peak memory | 386496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135638232 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_access_duri ng_key_req.2135638232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/43.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_alert_test.2995903824 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 21127987 ps |
| CPU time | 1.02 seconds |
| Started | Aug 29 02:38:18 AM UTC 24 |
| Finished | Aug 29 02:38:20 AM UTC 24 |
| Peak memory | 210876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995903824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_alert_test.2995903824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/43.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_bijection.976410302 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 66976864404 ps |
| CPU time | 1285.25 seconds |
| Started | Aug 29 02:34:23 AM UTC 24 |
| Finished | Aug 29 02:56:04 AM UTC 24 |
| Peak memory | 211572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976410302 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection.976410302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/43.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_executable.1563290174 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 14053837404 ps |
| CPU time | 714.21 seconds |
| Started | Aug 29 02:35:35 AM UTC 24 |
| Finished | Aug 29 02:47:37 AM UTC 24 |
| Peak memory | 382404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563290174 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executable.1563290174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/43.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.1671018305 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 9614127994 ps |
| CPU time | 120.31 seconds |
| Started | Aug 29 02:35:21 AM UTC 24 |
| Finished | Aug 29 02:37:24 AM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671018305 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_escalation.1671018305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/43.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.200686601 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 1377452868 ps |
| CPU time | 10.08 seconds |
| Started | Aug 29 02:35:01 AM UTC 24 |
| Finished | Aug 29 02:35:12 AM UTC 24 |
| Peak memory | 221732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 200686601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_m ax_throughput.200686601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/43.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.3106504741 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 9171002805 ps |
| CPU time | 194.3 seconds |
| Started | Aug 29 02:37:36 AM UTC 24 |
| Finished | Aug 29 02:40:53 AM UTC 24 |
| Peak memory | 221888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106504741 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_mem_partial_access.3106504741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/43.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.1896753308 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 10547102828 ps |
| CPU time | 267.25 seconds |
| Started | Aug 29 02:37:33 AM UTC 24 |
| Finished | Aug 29 02:42:05 AM UTC 24 |
| Peak memory | 211568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896753308 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_mem_walk.1896753308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/43.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.3450823779 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 9093699781 ps |
| CPU time | 1406.29 seconds |
| Started | Aug 29 02:34:14 AM UTC 24 |
| Finished | Aug 29 02:57:55 AM UTC 24 |
| Peak memory | 388740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450823779 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multiple_keys.3450823779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/43.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access.259958320 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 1368270937 ps |
| CPU time | 29.22 seconds |
| Started | Aug 29 02:34:30 AM UTC 24 |
| Finished | Aug 29 02:35:01 AM UTC 24 |
| Peak memory | 211676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259958320 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_partial_access.259958320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/43.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.4265446602 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 6609572072 ps |
| CPU time | 457.63 seconds |
| Started | Aug 29 02:34:36 AM UTC 24 |
| Finished | Aug 29 02:42:20 AM UTC 24 |
| Peak memory | 211496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265446602 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_partial_a ccess_b2b.4265446602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/43.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.84597778 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 357717980 ps |
| CPU time | 5.8 seconds |
| Started | Aug 29 02:37:25 AM UTC 24 |
| Finished | Aug 29 02:37:32 AM UTC 24 |
| Peak memory | 211832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84597778 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.84597778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/43.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_regwen.586217832 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 904114897 ps |
| CPU time | 168.63 seconds |
| Started | Aug 29 02:35:43 AM UTC 24 |
| Finished | Aug 29 02:38:34 AM UTC 24 |
| Peak memory | 368296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586217832 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.586217832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/43.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_smoke.3160592415 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 954736640 ps |
| CPU time | 16.43 seconds |
| Started | Aug 29 02:34:07 AM UTC 24 |
| Finished | Aug 29 02:34:25 AM UTC 24 |
| Peak memory | 211568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160592415 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.3160592415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/43.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all.967526624 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 309234322958 ps |
| CPU time | 4317.79 seconds |
| Started | Aug 29 02:38:03 AM UTC 24 |
| Finished | Aug 29 03:50:47 AM UTC 24 |
| Peak memory | 394348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96752662 4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all.967526624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/43.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3743469865 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 599694641 ps |
| CPU time | 26.82 seconds |
| Started | Aug 29 02:37:58 AM UTC 24 |
| Finished | Aug 29 02:38:26 AM UTC 24 |
| Peak memory | 221868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743469865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.3743469865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/43.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.3219191579 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 16609036488 ps |
| CPU time | 350.17 seconds |
| Started | Aug 29 02:34:26 AM UTC 24 |
| Finished | Aug 29 02:40:21 AM UTC 24 |
| Peak memory | 211568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219191579 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_pipeline.3219191579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/43.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.659658930 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 719532213 ps |
| CPU time | 11.69 seconds |
| Started | Aug 29 02:35:13 AM UTC 24 |
| Finished | Aug 29 02:35:26 AM UTC 24 |
| Peak memory | 228832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =659658930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ throughput_w_partial_write.659658930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/43.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.1875720157 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 44852221780 ps |
| CPU time | 764.27 seconds |
| Started | Aug 29 02:40:28 AM UTC 24 |
| Finished | Aug 29 02:53:20 AM UTC 24 |
| Peak memory | 384484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875720157 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_access_duri ng_key_req.1875720157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/44.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_alert_test.1713254660 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 41342444 ps |
| CPU time | 0.95 seconds |
| Started | Aug 29 02:42:02 AM UTC 24 |
| Finished | Aug 29 02:42:04 AM UTC 24 |
| Peak memory | 210876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713254660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_alert_test.1713254660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/44.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_bijection.3382925996 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 101050312690 ps |
| CPU time | 2413.8 seconds |
| Started | Aug 29 02:38:35 AM UTC 24 |
| Finished | Aug 29 03:19:19 AM UTC 24 |
| Peak memory | 213152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382925996 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection.3382925996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/44.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_executable.2769898410 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 1875728605 ps |
| CPU time | 163.15 seconds |
| Started | Aug 29 02:40:44 AM UTC 24 |
| Finished | Aug 29 02:43:30 AM UTC 24 |
| Peak memory | 382364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769898410 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executable.2769898410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/44.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.469706409 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 81027755675 ps |
| CPU time | 100.15 seconds |
| Started | Aug 29 02:40:25 AM UTC 24 |
| Finished | Aug 29 02:42:07 AM UTC 24 |
| Peak memory | 221740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469706409 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_escalation.469706409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/44.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.3149468962 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 3005034080 ps |
| CPU time | 33.79 seconds |
| Started | Aug 29 02:39:51 AM UTC 24 |
| Finished | Aug 29 02:40:26 AM UTC 24 |
| Peak memory | 298524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3149468962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ max_throughput.3149468962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/44.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.3411206743 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 1446013236 ps |
| CPU time | 98.21 seconds |
| Started | Aug 29 02:41:13 AM UTC 24 |
| Finished | Aug 29 02:42:54 AM UTC 24 |
| Peak memory | 221736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411206743 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_mem_partial_access.3411206743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/44.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.2295837557 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 13831784410 ps |
| CPU time | 219.41 seconds |
| Started | Aug 29 02:41:12 AM UTC 24 |
| Finished | Aug 29 02:44:55 AM UTC 24 |
| Peak memory | 222124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295837557 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_mem_walk.2295837557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/44.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.2678247934 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 57619587483 ps |
| CPU time | 1368.82 seconds |
| Started | Aug 29 02:38:26 AM UTC 24 |
| Finished | Aug 29 03:01:31 AM UTC 24 |
| Peak memory | 360124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678247934 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multiple_keys.2678247934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/44.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access.2563876155 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 10341636000 ps |
| CPU time | 36.75 seconds |
| Started | Aug 29 02:39:45 AM UTC 24 |
| Finished | Aug 29 02:40:23 AM UTC 24 |
| Peak memory | 211652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563876155 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_partial_access.2563876155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/44.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.1373278375 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 173462633943 ps |
| CPU time | 388.51 seconds |
| Started | Aug 29 02:39:50 AM UTC 24 |
| Finished | Aug 29 02:46:24 AM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373278375 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_partial_a ccess_b2b.1373278375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/44.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.3484575890 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 710911220 ps |
| CPU time | 6.31 seconds |
| Started | Aug 29 02:41:05 AM UTC 24 |
| Finished | Aug 29 02:41:12 AM UTC 24 |
| Peak memory | 211620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484575890 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.3484575890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/44.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_regwen.320803116 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 9629108821 ps |
| CPU time | 868.62 seconds |
| Started | Aug 29 02:40:54 AM UTC 24 |
| Finished | Aug 29 02:55:32 AM UTC 24 |
| Peak memory | 388820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320803116 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.320803116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/44.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_smoke.1008892232 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 3407927958 ps |
| CPU time | 80.33 seconds |
| Started | Aug 29 02:38:21 AM UTC 24 |
| Finished | Aug 29 02:39:43 AM UTC 24 |
| Peak memory | 349664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008892232 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.1008892232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/44.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all.3605305798 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 215990737236 ps |
| CPU time | 4624.36 seconds |
| Started | Aug 29 02:41:54 AM UTC 24 |
| Finished | Aug 29 03:59:49 AM UTC 24 |
| Peak memory | 386136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36053057 98 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_a ll.3605305798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/44.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2651491603 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 1642956483 ps |
| CPU time | 43.06 seconds |
| Started | Aug 29 02:41:16 AM UTC 24 |
| Finished | Aug 29 02:42:01 AM UTC 24 |
| Peak memory | 222072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651491603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.2651491603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/44.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.1440966414 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 3163483251 ps |
| CPU time | 272.65 seconds |
| Started | Aug 29 02:38:44 AM UTC 24 |
| Finished | Aug 29 02:43:21 AM UTC 24 |
| Peak memory | 211556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440966414 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_pipeline.1440966414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/44.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.1111693059 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 769932884 ps |
| CPU time | 51.93 seconds |
| Started | Aug 29 02:40:22 AM UTC 24 |
| Finished | Aug 29 02:41:16 AM UTC 24 |
| Peak memory | 341612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1111693059 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl _throughput_w_partial_write.1111693059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/44.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.2365617866 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 12629389616 ps |
| CPU time | 784.71 seconds |
| Started | Aug 29 02:42:52 AM UTC 24 |
| Finished | Aug 29 02:56:06 AM UTC 24 |
| Peak memory | 386496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365617866 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_access_duri ng_key_req.2365617866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/45.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_alert_test.2347687227 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 16216851 ps |
| CPU time | 1.06 seconds |
| Started | Aug 29 02:43:56 AM UTC 24 |
| Finished | Aug 29 02:43:58 AM UTC 24 |
| Peak memory | 210876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347687227 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_alert_test.2347687227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/45.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_bijection.1401404417 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 117744260026 ps |
| CPU time | 2430.82 seconds |
| Started | Aug 29 02:42:07 AM UTC 24 |
| Finished | Aug 29 03:23:07 AM UTC 24 |
| Peak memory | 213232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401404417 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection.1401404417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/45.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_executable.886286607 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 1254646655 ps |
| CPU time | 52.47 seconds |
| Started | Aug 29 02:42:54 AM UTC 24 |
| Finished | Aug 29 02:43:48 AM UTC 24 |
| Peak memory | 304524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886286607 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executable.886286607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/45.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.1589705997 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 29970458399 ps |
| CPU time | 73.14 seconds |
| Started | Aug 29 02:42:40 AM UTC 24 |
| Finished | Aug 29 02:43:55 AM UTC 24 |
| Peak memory | 211624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589705997 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_escalation.1589705997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/45.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.3494834713 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 2375399144 ps |
| CPU time | 8.35 seconds |
| Started | Aug 29 02:42:21 AM UTC 24 |
| Finished | Aug 29 02:42:30 AM UTC 24 |
| Peak memory | 211368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3494834713 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ max_throughput.3494834713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/45.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.3928666082 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 13789937590 ps |
| CPU time | 252.63 seconds |
| Started | Aug 29 02:43:31 AM UTC 24 |
| Finished | Aug 29 02:47:47 AM UTC 24 |
| Peak memory | 222080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928666082 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_mem_partial_access.3928666082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/45.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.1930056033 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 82825140489 ps |
| CPU time | 551.66 seconds |
| Started | Aug 29 02:43:30 AM UTC 24 |
| Finished | Aug 29 02:52:49 AM UTC 24 |
| Peak memory | 221936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930056033 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_mem_walk.1930056033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/45.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access.1930151155 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 6930684099 ps |
| CPU time | 28.37 seconds |
| Started | Aug 29 02:42:10 AM UTC 24 |
| Finished | Aug 29 02:42:39 AM UTC 24 |
| Peak memory | 211492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930151155 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_partial_access.1930151155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/45.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.1154079288 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 101782574120 ps |
| CPU time | 629.92 seconds |
| Started | Aug 29 02:42:10 AM UTC 24 |
| Finished | Aug 29 02:52:47 AM UTC 24 |
| Peak memory | 211552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154079288 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_partial_a ccess_b2b.1154079288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/45.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.4023972941 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 1034857063 ps |
| CPU time | 5.52 seconds |
| Started | Aug 29 02:43:22 AM UTC 24 |
| Finished | Aug 29 02:43:28 AM UTC 24 |
| Peak memory | 211628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023972941 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.4023972941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/45.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_regwen.430952521 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 11550292218 ps |
| CPU time | 444.8 seconds |
| Started | Aug 29 02:43:17 AM UTC 24 |
| Finished | Aug 29 02:50:48 AM UTC 24 |
| Peak memory | 378396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430952521 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.430952521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/45.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_smoke.528950459 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 12043336475 ps |
| CPU time | 115.84 seconds |
| Started | Aug 29 02:42:05 AM UTC 24 |
| Finished | Aug 29 02:44:03 AM UTC 24 |
| Peak memory | 366044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528950459 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.528950459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/45.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all.130706479 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 51935844043 ps |
| CPU time | 2799.62 seconds |
| Started | Aug 29 02:43:51 AM UTC 24 |
| Finished | Aug 29 03:31:02 AM UTC 24 |
| Peak memory | 392168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13070647 9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all.130706479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/45.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.4013911194 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 1688748314 ps |
| CPU time | 44.17 seconds |
| Started | Aug 29 02:43:49 AM UTC 24 |
| Finished | Aug 29 02:44:35 AM UTC 24 |
| Peak memory | 223936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013911194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.4013911194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/45.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.355363291 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 5927778331 ps |
| CPU time | 233.12 seconds |
| Started | Aug 29 02:42:07 AM UTC 24 |
| Finished | Aug 29 02:46:04 AM UTC 24 |
| Peak memory | 211576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355363291 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_pipeline.355363291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/45.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.773410795 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 1600943582 ps |
| CPU time | 105.61 seconds |
| Started | Aug 29 02:42:31 AM UTC 24 |
| Finished | Aug 29 02:44:19 AM UTC 24 |
| Peak memory | 382628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =773410795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ throughput_w_partial_write.773410795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/45.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.1434825022 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 15975233745 ps |
| CPU time | 639.26 seconds |
| Started | Aug 29 02:45:16 AM UTC 24 |
| Finished | Aug 29 02:56:03 AM UTC 24 |
| Peak memory | 378400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434825022 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_access_duri ng_key_req.1434825022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/46.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_alert_test.301893616 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 35850598 ps |
| CPU time | 1.03 seconds |
| Started | Aug 29 02:47:02 AM UTC 24 |
| Finished | Aug 29 02:47:04 AM UTC 24 |
| Peak memory | 210940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301893616 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_alert_test.301893616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/46.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_executable.2592489826 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 83697045407 ps |
| CPU time | 795.11 seconds |
| Started | Aug 29 02:45:19 AM UTC 24 |
| Finished | Aug 29 02:58:43 AM UTC 24 |
| Peak memory | 382404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592489826 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executable.2592489826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/46.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.1900325574 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 21395710856 ps |
| CPU time | 76.72 seconds |
| Started | Aug 29 02:45:15 AM UTC 24 |
| Finished | Aug 29 02:46:33 AM UTC 24 |
| Peak memory | 211564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900325574 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_escalation.1900325574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/46.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.1564854263 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 3103121523 ps |
| CPU time | 65 seconds |
| Started | Aug 29 02:44:46 AM UTC 24 |
| Finished | Aug 29 02:45:53 AM UTC 24 |
| Peak memory | 349724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1564854263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ max_throughput.1564854263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/46.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.4063691688 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 9944394868 ps |
| CPU time | 117.6 seconds |
| Started | Aug 29 02:46:06 AM UTC 24 |
| Finished | Aug 29 02:48:05 AM UTC 24 |
| Peak memory | 222072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063691688 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_mem_partial_access.4063691688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/46.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.3708769378 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 8231009859 ps |
| CPU time | 164.52 seconds |
| Started | Aug 29 02:46:02 AM UTC 24 |
| Finished | Aug 29 02:48:50 AM UTC 24 |
| Peak memory | 221816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708769378 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_mem_walk.3708769378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/46.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.3108649850 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 30535452447 ps |
| CPU time | 1012.3 seconds |
| Started | Aug 29 02:44:04 AM UTC 24 |
| Finished | Aug 29 03:01:09 AM UTC 24 |
| Peak memory | 382428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108649850 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multiple_keys.3108649850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/46.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access.1080421032 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 4612425053 ps |
| CPU time | 51.37 seconds |
| Started | Aug 29 02:44:20 AM UTC 24 |
| Finished | Aug 29 02:45:13 AM UTC 24 |
| Peak memory | 306844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080421032 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_partial_access.1080421032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/46.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.1639441612 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 6944919454 ps |
| CPU time | 256.25 seconds |
| Started | Aug 29 02:44:36 AM UTC 24 |
| Finished | Aug 29 02:48:55 AM UTC 24 |
| Peak memory | 211744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639441612 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_partial_a ccess_b2b.1639441612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/46.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.3379979282 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 1044034727 ps |
| CPU time | 6.09 seconds |
| Started | Aug 29 02:45:54 AM UTC 24 |
| Finished | Aug 29 02:46:01 AM UTC 24 |
| Peak memory | 211632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379979282 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.3379979282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/46.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_regwen.3255322717 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 5469940516 ps |
| CPU time | 167.4 seconds |
| Started | Aug 29 02:45:41 AM UTC 24 |
| Finished | Aug 29 02:48:31 AM UTC 24 |
| Peak memory | 368080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255322717 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.3255322717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/46.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_smoke.765315767 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 744902398 ps |
| CPU time | 12.03 seconds |
| Started | Aug 29 02:43:59 AM UTC 24 |
| Finished | Aug 29 02:44:12 AM UTC 24 |
| Peak memory | 211848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765315767 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.765315767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/46.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all.3935690666 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 60932704888 ps |
| CPU time | 3643.34 seconds |
| Started | Aug 29 02:46:34 AM UTC 24 |
| Finished | Aug 29 03:47:57 AM UTC 24 |
| Peak memory | 388184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39356906 66 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_a ll.3935690666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/46.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3724872332 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 612084794 ps |
| CPU time | 34.57 seconds |
| Started | Aug 29 02:46:25 AM UTC 24 |
| Finished | Aug 29 02:47:01 AM UTC 24 |
| Peak memory | 228932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724872332 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.3724872332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/46.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.3328663114 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 2683157681 ps |
| CPU time | 215.78 seconds |
| Started | Aug 29 02:44:15 AM UTC 24 |
| Finished | Aug 29 02:47:54 AM UTC 24 |
| Peak memory | 211748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328663114 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_pipeline.3328663114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/46.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.1478275706 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 3086998221 ps |
| CPU time | 41.93 seconds |
| Started | Aug 29 02:44:56 AM UTC 24 |
| Finished | Aug 29 02:45:40 AM UTC 24 |
| Peak memory | 312868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1478275706 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl _throughput_w_partial_write.1478275706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/46.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.2412359550 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 32801228547 ps |
| CPU time | 1111.03 seconds |
| Started | Aug 29 02:48:34 AM UTC 24 |
| Finished | Aug 29 03:07:16 AM UTC 24 |
| Peak memory | 388852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412359550 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_access_duri ng_key_req.2412359550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/47.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_alert_test.656526495 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 20311966 ps |
| CPU time | 1.05 seconds |
| Started | Aug 29 02:50:14 AM UTC 24 |
| Finished | Aug 29 02:50:16 AM UTC 24 |
| Peak memory | 210736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656526495 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_alert_test.656526495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/47.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_bijection.657258338 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 705512411843 ps |
| CPU time | 3028.05 seconds |
| Started | Aug 29 02:47:39 AM UTC 24 |
| Finished | Aug 29 03:38:41 AM UTC 24 |
| Peak memory | 213228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657258338 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection.657258338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/47.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_executable.2777776105 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 14332845477 ps |
| CPU time | 878.87 seconds |
| Started | Aug 29 02:48:51 AM UTC 24 |
| Finished | Aug 29 03:03:40 AM UTC 24 |
| Peak memory | 382624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777776105 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executable.2777776105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/47.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.499547514 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 4952047855 ps |
| CPU time | 56.86 seconds |
| Started | Aug 29 02:48:31 AM UTC 24 |
| Finished | Aug 29 02:49:30 AM UTC 24 |
| Peak memory | 221864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499547514 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_escalation.499547514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/47.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.4042262689 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 1500186811 ps |
| CPU time | 65.62 seconds |
| Started | Aug 29 02:48:05 AM UTC 24 |
| Finished | Aug 29 02:49:12 AM UTC 24 |
| Peak memory | 327136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4042262689 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ max_throughput.4042262689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/47.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.1186925601 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 2935942945 ps |
| CPU time | 109.43 seconds |
| Started | Aug 29 02:49:09 AM UTC 24 |
| Finished | Aug 29 02:51:00 AM UTC 24 |
| Peak memory | 221880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186925601 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_mem_partial_access.1186925601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/47.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.726536686 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 10958747406 ps |
| CPU time | 157.99 seconds |
| Started | Aug 29 02:49:07 AM UTC 24 |
| Finished | Aug 29 02:51:48 AM UTC 24 |
| Peak memory | 221816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726536686 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_mem_walk.726536686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/47.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_multiple_keys.1732935094 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 46291634150 ps |
| CPU time | 1246.43 seconds |
| Started | Aug 29 02:47:27 AM UTC 24 |
| Finished | Aug 29 03:08:27 AM UTC 24 |
| Peak memory | 386512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732935094 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multiple_keys.1732935094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/47.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access.2907640439 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 10178638930 ps |
| CPU time | 61.46 seconds |
| Started | Aug 29 02:47:54 AM UTC 24 |
| Finished | Aug 29 02:48:58 AM UTC 24 |
| Peak memory | 337568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907640439 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_partial_access.2907640439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/47.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.2863347522 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 80021117564 ps |
| CPU time | 526.6 seconds |
| Started | Aug 29 02:47:55 AM UTC 24 |
| Finished | Aug 29 02:56:49 AM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863347522 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_partial_a ccess_b2b.2863347522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/47.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.1303969488 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 1353422232 ps |
| CPU time | 5.89 seconds |
| Started | Aug 29 02:48:59 AM UTC 24 |
| Finished | Aug 29 02:49:06 AM UTC 24 |
| Peak memory | 211836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303969488 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.1303969488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/47.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_regwen.1345908010 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 111672708170 ps |
| CPU time | 814.27 seconds |
| Started | Aug 29 02:48:56 AM UTC 24 |
| Finished | Aug 29 03:02:41 AM UTC 24 |
| Peak memory | 384656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345908010 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.1345908010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/47.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_smoke.3337344127 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 508289071 ps |
| CPU time | 19.6 seconds |
| Started | Aug 29 02:47:05 AM UTC 24 |
| Finished | Aug 29 02:47:26 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337344127 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.3337344127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/47.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all.3565213735 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 347831502658 ps |
| CPU time | 3040.52 seconds |
| Started | Aug 29 02:49:31 AM UTC 24 |
| Finished | Aug 29 03:40:47 AM UTC 24 |
| Peak memory | 388260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35652137 35 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_a ll.3565213735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/47.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1219648335 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 1424485594 ps |
| CPU time | 100.83 seconds |
| Started | Aug 29 02:49:13 AM UTC 24 |
| Finished | Aug 29 02:50:56 AM UTC 24 |
| Peak memory | 331280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219648335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.1219648335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/47.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.522659469 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 8506771735 ps |
| CPU time | 383.4 seconds |
| Started | Aug 29 02:47:49 AM UTC 24 |
| Finished | Aug 29 02:54:18 AM UTC 24 |
| Peak memory | 211628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522659469 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_pipeline.522659469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/47.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.4087192109 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 757180359 ps |
| CPU time | 24.52 seconds |
| Started | Aug 29 02:48:06 AM UTC 24 |
| Finished | Aug 29 02:48:32 AM UTC 24 |
| Peak memory | 280232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =4087192109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl _throughput_w_partial_write.4087192109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/47.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.3329037116 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 14480655879 ps |
| CPU time | 718.64 seconds |
| Started | Aug 29 02:52:32 AM UTC 24 |
| Finished | Aug 29 03:04:39 AM UTC 24 |
| Peak memory | 386740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329037116 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_access_duri ng_key_req.3329037116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/48.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_alert_test.3449714373 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 38477302 ps |
| CPU time | 1.02 seconds |
| Started | Aug 29 02:53:45 AM UTC 24 |
| Finished | Aug 29 02:53:47 AM UTC 24 |
| Peak memory | 210728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449714373 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_alert_test.3449714373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/48.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_bijection.1983876323 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 14927015039 ps |
| CPU time | 1198.81 seconds |
| Started | Aug 29 02:50:49 AM UTC 24 |
| Finished | Aug 29 03:11:03 AM UTC 24 |
| Peak memory | 211568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983876323 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection.1983876323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/48.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_executable.1901658946 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 123832151493 ps |
| CPU time | 738.56 seconds |
| Started | Aug 29 02:52:45 AM UTC 24 |
| Finished | Aug 29 03:05:13 AM UTC 24 |
| Peak memory | 386656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901658946 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executable.1901658946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/48.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.3451446124 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 112198659677 ps |
| CPU time | 129.58 seconds |
| Started | Aug 29 02:52:27 AM UTC 24 |
| Finished | Aug 29 02:54:39 AM UTC 24 |
| Peak memory | 222004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451446124 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_escalation.3451446124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/48.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.2060906757 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 2652205649 ps |
| CPU time | 57.71 seconds |
| Started | Aug 29 02:51:49 AM UTC 24 |
| Finished | Aug 29 02:52:49 AM UTC 24 |
| Peak memory | 331292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2060906757 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ max_throughput.2060906757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/48.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.3482525825 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 4395555846 ps |
| CPU time | 180.02 seconds |
| Started | Aug 29 02:52:58 AM UTC 24 |
| Finished | Aug 29 02:56:01 AM UTC 24 |
| Peak memory | 221792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482525825 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_mem_partial_access.3482525825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/48.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.1939898955 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 5652191827 ps |
| CPU time | 318.26 seconds |
| Started | Aug 29 02:52:51 AM UTC 24 |
| Finished | Aug 29 02:58:13 AM UTC 24 |
| Peak memory | 221880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939898955 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_mem_walk.1939898955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/48.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.2212559772 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 1343754179 ps |
| CPU time | 109.5 seconds |
| Started | Aug 29 02:50:34 AM UTC 24 |
| Finished | Aug 29 02:52:26 AM UTC 24 |
| Peak memory | 298720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212559772 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multiple_keys.2212559772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/48.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access.556438883 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 801792235 ps |
| CPU time | 14.14 seconds |
| Started | Aug 29 02:51:01 AM UTC 24 |
| Finished | Aug 29 02:51:17 AM UTC 24 |
| Peak memory | 220540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556438883 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_partial_access.556438883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/48.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.3217931384 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 163510731432 ps |
| CPU time | 512.78 seconds |
| Started | Aug 29 02:51:18 AM UTC 24 |
| Finished | Aug 29 02:59:58 AM UTC 24 |
| Peak memory | 211740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217931384 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_partial_a ccess_b2b.3217931384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/48.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.68266477 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 366928279 ps |
| CPU time | 6.3 seconds |
| Started | Aug 29 02:52:49 AM UTC 24 |
| Finished | Aug 29 02:52:57 AM UTC 24 |
| Peak memory | 211832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68266477 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.68266477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/48.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_regwen.1328703100 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 12375187046 ps |
| CPU time | 711.78 seconds |
| Started | Aug 29 02:52:48 AM UTC 24 |
| Finished | Aug 29 03:04:48 AM UTC 24 |
| Peak memory | 382512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328703100 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.1328703100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/48.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_smoke.523293657 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 2942693891 ps |
| CPU time | 14.77 seconds |
| Started | Aug 29 02:50:17 AM UTC 24 |
| Finished | Aug 29 02:50:33 AM UTC 24 |
| Peak memory | 211496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523293657 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.523293657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/48.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all.4009368299 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 262468195319 ps |
| CPU time | 2447.1 seconds |
| Started | Aug 29 02:53:41 AM UTC 24 |
| Finished | Aug 29 03:34:55 AM UTC 24 |
| Peak memory | 390316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40093682 99 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_a ll.4009368299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/48.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3402391564 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 1613729742 ps |
| CPU time | 20.73 seconds |
| Started | Aug 29 02:53:21 AM UTC 24 |
| Finished | Aug 29 02:53:44 AM UTC 24 |
| Peak memory | 221936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402391564 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.3402391564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/48.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.3326198664 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 12859724785 ps |
| CPU time | 300.56 seconds |
| Started | Aug 29 02:50:57 AM UTC 24 |
| Finished | Aug 29 02:56:02 AM UTC 24 |
| Peak memory | 211624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326198664 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_pipeline.3326198664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/48.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.805906327 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 823824163 ps |
| CPU time | 88.71 seconds |
| Started | Aug 29 02:52:09 AM UTC 24 |
| Finished | Aug 29 02:53:39 AM UTC 24 |
| Peak memory | 357792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =805906327 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ throughput_w_partial_write.805906327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/48.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.3515475503 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 32345781162 ps |
| CPU time | 646.77 seconds |
| Started | Aug 29 02:56:04 AM UTC 24 |
| Finished | Aug 29 03:06:58 AM UTC 24 |
| Peak memory | 388564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515475503 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_access_duri ng_key_req.3515475503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/49.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_alert_test.2078333759 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 96591021 ps |
| CPU time | 0.98 seconds |
| Started | Aug 29 02:57:57 AM UTC 24 |
| Finished | Aug 29 02:57:59 AM UTC 24 |
| Peak memory | 210876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078333759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_alert_test.2078333759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/49.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_bijection.2876743994 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 57713980177 ps |
| CPU time | 1347.49 seconds |
| Started | Aug 29 02:54:20 AM UTC 24 |
| Finished | Aug 29 03:17:03 AM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876743994 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection.2876743994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/49.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_executable.360290217 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 10964388111 ps |
| CPU time | 826 seconds |
| Started | Aug 29 02:56:04 AM UTC 24 |
| Finished | Aug 29 03:10:01 AM UTC 24 |
| Peak memory | 388632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360290217 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executable.360290217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/49.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.1746212007 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 52004291514 ps |
| CPU time | 157.89 seconds |
| Started | Aug 29 02:56:02 AM UTC 24 |
| Finished | Aug 29 02:58:43 AM UTC 24 |
| Peak memory | 211572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746212007 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_escalation.1746212007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/49.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.1318638223 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 1548331085 ps |
| CPU time | 104.75 seconds |
| Started | Aug 29 02:55:34 AM UTC 24 |
| Finished | Aug 29 02:57:21 AM UTC 24 |
| Peak memory | 370068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1318638223 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ max_throughput.1318638223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/49.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.3368155175 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 2441153006 ps |
| CPU time | 113.33 seconds |
| Started | Aug 29 02:56:50 AM UTC 24 |
| Finished | Aug 29 02:58:46 AM UTC 24 |
| Peak memory | 221796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368155175 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_mem_partial_access.3368155175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/49.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.1366790086 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 7894879437 ps |
| CPU time | 167.96 seconds |
| Started | Aug 29 02:56:12 AM UTC 24 |
| Finished | Aug 29 02:59:04 AM UTC 24 |
| Peak memory | 221804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366790086 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_mem_walk.1366790086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/49.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.521911540 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 17141120517 ps |
| CPU time | 1024.47 seconds |
| Started | Aug 29 02:54:11 AM UTC 24 |
| Finished | Aug 29 03:11:27 AM UTC 24 |
| Peak memory | 370124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521911540 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multiple_keys.521911540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/49.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access.1716878387 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 2590115407 ps |
| CPU time | 12.44 seconds |
| Started | Aug 29 02:54:40 AM UTC 24 |
| Finished | Aug 29 02:54:54 AM UTC 24 |
| Peak memory | 211288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716878387 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_partial_access.1716878387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/49.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.4017999861 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 7995321555 ps |
| CPU time | 565.94 seconds |
| Started | Aug 29 02:54:56 AM UTC 24 |
| Finished | Aug 29 03:04:29 AM UTC 24 |
| Peak memory | 211636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017999861 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_partial_a ccess_b2b.4017999861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/49.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.786785882 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 346052357 ps |
| CPU time | 3.59 seconds |
| Started | Aug 29 02:56:07 AM UTC 24 |
| Finished | Aug 29 02:56:12 AM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786785882 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.786785882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/49.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_regwen.740059252 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 55834551602 ps |
| CPU time | 667.48 seconds |
| Started | Aug 29 02:56:06 AM UTC 24 |
| Finished | Aug 29 03:07:21 AM UTC 24 |
| Peak memory | 380372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740059252 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.740059252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/49.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_smoke.2411666128 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 3868073044 ps |
| CPU time | 103.4 seconds |
| Started | Aug 29 02:53:49 AM UTC 24 |
| Finished | Aug 29 02:55:34 AM UTC 24 |
| Peak memory | 380580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411666128 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.2411666128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/49.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3001296992 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 4751833477 ps |
| CPU time | 183.92 seconds |
| Started | Aug 29 02:56:52 AM UTC 24 |
| Finished | Aug 29 02:59:59 AM UTC 24 |
| Peak memory | 347816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001296992 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.3001296992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/49.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.2921831738 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 4802155298 ps |
| CPU time | 368.14 seconds |
| Started | Aug 29 02:54:28 AM UTC 24 |
| Finished | Aug 29 03:00:42 AM UTC 24 |
| Peak memory | 211568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921831738 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_pipeline.2921831738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/49.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.104053935 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 3049243926 ps |
| CPU time | 70.79 seconds |
| Started | Aug 29 02:55:36 AM UTC 24 |
| Finished | Aug 29 02:56:48 AM UTC 24 |
| Peak memory | 345556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =104053935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ throughput_w_partial_write.104053935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/49.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.2830032928 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 14157553005 ps |
| CPU time | 406.41 seconds |
| Started | Aug 29 12:33:16 AM UTC 24 |
| Finished | Aug 29 12:40:08 AM UTC 24 |
| Peak memory | 386500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830032928 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_access_durin g_key_req.2830032928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/5.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_alert_test.1473260400 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 15406670 ps |
| CPU time | 0.77 seconds |
| Started | Aug 29 12:34:07 AM UTC 24 |
| Finished | Aug 29 12:34:08 AM UTC 24 |
| Peak memory | 210872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473260400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_alert_test.1473260400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/5.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_bijection.970689572 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 603539467214 ps |
| CPU time | 2969.82 seconds |
| Started | Aug 29 12:32:05 AM UTC 24 |
| Finished | Aug 29 01:22:08 AM UTC 24 |
| Peak memory | 213212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970689572 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.970689572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/5.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_executable.3098243365 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 9458249602 ps |
| CPU time | 1290.65 seconds |
| Started | Aug 29 12:33:21 AM UTC 24 |
| Finished | Aug 29 12:55:06 AM UTC 24 |
| Peak memory | 388560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098243365 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executable.3098243365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/5.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.3908563625 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 126655657820 ps |
| CPU time | 127.76 seconds |
| Started | Aug 29 12:33:13 AM UTC 24 |
| Finished | Aug 29 12:35:23 AM UTC 24 |
| Peak memory | 211620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908563625 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_escalation.3908563625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/5.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.126101397 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 754931576 ps |
| CPU time | 35.57 seconds |
| Started | Aug 29 12:33:07 AM UTC 24 |
| Finished | Aug 29 12:33:44 AM UTC 24 |
| Peak memory | 300520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 126101397 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ma x_throughput.126101397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/5.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.1890802062 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 45779178986 ps |
| CPU time | 301.29 seconds |
| Started | Aug 29 12:34:02 AM UTC 24 |
| Finished | Aug 29 12:39:08 AM UTC 24 |
| Peak memory | 225972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890802062 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_mem_partial_access.1890802062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/5.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.2033607179 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 15768747492 ps |
| CPU time | 265.87 seconds |
| Started | Aug 29 12:33:53 AM UTC 24 |
| Finished | Aug 29 12:38:23 AM UTC 24 |
| Peak memory | 221892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033607179 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_mem_walk.2033607179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/5.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.870520788 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 16440813792 ps |
| CPU time | 1004.71 seconds |
| Started | Aug 29 12:31:56 AM UTC 24 |
| Finished | Aug 29 12:48:53 AM UTC 24 |
| Peak memory | 388568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870520788 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multiple_keys.870520788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/5.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access.3154675713 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 794509832 ps |
| CPU time | 39.28 seconds |
| Started | Aug 29 12:32:34 AM UTC 24 |
| Finished | Aug 29 12:33:15 AM UTC 24 |
| Peak memory | 296536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154675713 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_partial_access.3154675713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/5.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.2841818330 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 78821187793 ps |
| CPU time | 513.14 seconds |
| Started | Aug 29 12:32:41 AM UTC 24 |
| Finished | Aug 29 12:41:20 AM UTC 24 |
| Peak memory | 211572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841818330 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_partial_ac cess_b2b.2841818330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/5.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.1548226398 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 1403255141 ps |
| CPU time | 7.33 seconds |
| Started | Aug 29 12:33:44 AM UTC 24 |
| Finished | Aug 29 12:33:53 AM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548226398 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.1548226398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/5.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_smoke.3983235389 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 677255092 ps |
| CPU time | 41.35 seconds |
| Started | Aug 29 12:31:56 AM UTC 24 |
| Finished | Aug 29 12:32:39 AM UTC 24 |
| Peak memory | 298460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983235389 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.3983235389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/5.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all.3853713447 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 207900532957 ps |
| CPU time | 3585.84 seconds |
| Started | Aug 29 12:34:06 AM UTC 24 |
| Finished | Aug 29 01:34:32 AM UTC 24 |
| Peak memory | 398440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38537134 47 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all.3853713447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/5.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2348180501 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 1012566493 ps |
| CPU time | 21.46 seconds |
| Started | Aug 29 12:34:04 AM UTC 24 |
| Finished | Aug 29 12:34:26 AM UTC 24 |
| Peak memory | 224236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348180501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.2348180501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/5.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.1901713579 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 17357475142 ps |
| CPU time | 398.13 seconds |
| Started | Aug 29 12:32:29 AM UTC 24 |
| Finished | Aug 29 12:39:12 AM UTC 24 |
| Peak memory | 211772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901713579 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_pipeline.1901713579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/5.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.3129255627 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 776359800 ps |
| CPU time | 51.99 seconds |
| Started | Aug 29 12:33:11 AM UTC 24 |
| Finished | Aug 29 12:34:05 AM UTC 24 |
| Peak memory | 314844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3129255627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ throughput_w_partial_write.3129255627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/5.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.564919844 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 63940549178 ps |
| CPU time | 850.81 seconds |
| Started | Aug 29 12:35:26 AM UTC 24 |
| Finished | Aug 29 12:49:46 AM UTC 24 |
| Peak memory | 386576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564919844 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_access_during _key_req.564919844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/6.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_alert_test.1844714712 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 14598449 ps |
| CPU time | 1 seconds |
| Started | Aug 29 12:37:34 AM UTC 24 |
| Finished | Aug 29 12:37:36 AM UTC 24 |
| Peak memory | 210732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844714712 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_alert_test.1844714712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/6.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_bijection.102513357 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 146363433311 ps |
| CPU time | 2704.62 seconds |
| Started | Aug 29 12:34:27 AM UTC 24 |
| Finished | Aug 29 01:20:02 AM UTC 24 |
| Peak memory | 213232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102513357 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.102513357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/6.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_executable.4178552337 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 7287202083 ps |
| CPU time | 824.4 seconds |
| Started | Aug 29 12:35:36 AM UTC 24 |
| Finished | Aug 29 12:49:30 AM UTC 24 |
| Peak memory | 372368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178552337 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executable.4178552337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/6.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.1095398456 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5684887008 ps |
| CPU time | 80.93 seconds |
| Started | Aug 29 12:35:24 AM UTC 24 |
| Finished | Aug 29 12:36:46 AM UTC 24 |
| Peak memory | 225884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095398456 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_escalation.1095398456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/6.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.3714100106 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 758329564 ps |
| CPU time | 100.42 seconds |
| Started | Aug 29 12:34:59 AM UTC 24 |
| Finished | Aug 29 12:36:42 AM UTC 24 |
| Peak memory | 364136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3714100106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_m ax_throughput.3714100106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/6.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.2362576564 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 17351119319 ps |
| CPU time | 226.19 seconds |
| Started | Aug 29 12:36:43 AM UTC 24 |
| Finished | Aug 29 12:40:33 AM UTC 24 |
| Peak memory | 228864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362576564 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_mem_partial_access.2362576564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/6.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.3646496631 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 47047648533 ps |
| CPU time | 441.21 seconds |
| Started | Aug 29 12:36:40 AM UTC 24 |
| Finished | Aug 29 12:44:07 AM UTC 24 |
| Peak memory | 211616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646496631 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_mem_walk.3646496631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/6.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.2184198871 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 18661010258 ps |
| CPU time | 479.36 seconds |
| Started | Aug 29 12:34:09 AM UTC 24 |
| Finished | Aug 29 12:42:15 AM UTC 24 |
| Peak memory | 378400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184198871 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multiple_keys.2184198871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/6.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access.283861156 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 591437755 ps |
| CPU time | 26.16 seconds |
| Started | Aug 29 12:34:43 AM UTC 24 |
| Finished | Aug 29 12:35:11 AM UTC 24 |
| Peak memory | 211504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283861156 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_partial_access.283861156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/6.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.2869938038 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 13190805400 ps |
| CPU time | 207.76 seconds |
| Started | Aug 29 12:34:56 AM UTC 24 |
| Finished | Aug 29 12:38:27 AM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869938038 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_partial_ac cess_b2b.2869938038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/6.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.874943596 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 364955375 ps |
| CPU time | 5.95 seconds |
| Started | Aug 29 12:36:32 AM UTC 24 |
| Finished | Aug 29 12:36:40 AM UTC 24 |
| Peak memory | 211628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874943596 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.874943596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/6.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_regwen.1298447311 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 58859047807 ps |
| CPU time | 1139.99 seconds |
| Started | Aug 29 12:35:52 AM UTC 24 |
| Finished | Aug 29 12:55:04 AM UTC 24 |
| Peak memory | 388568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298447311 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.1298447311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/6.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_smoke.499728060 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 4316906123 ps |
| CPU time | 24.83 seconds |
| Started | Aug 29 12:34:08 AM UTC 24 |
| Finished | Aug 29 12:34:34 AM UTC 24 |
| Peak memory | 211616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499728060 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.499728060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/6.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all.1567991021 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 152866200443 ps |
| CPU time | 4442.12 seconds |
| Started | Aug 29 12:36:54 AM UTC 24 |
| Finished | Aug 29 01:51:42 AM UTC 24 |
| Peak memory | 388376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15679910 21 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all.1567991021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/6.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.648347958 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 1980125624 ps |
| CPU time | 43.78 seconds |
| Started | Aug 29 12:36:47 AM UTC 24 |
| Finished | Aug 29 12:37:33 AM UTC 24 |
| Peak memory | 221860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648347958 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.648347958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/6.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.2508739335 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 23072093154 ps |
| CPU time | 386.81 seconds |
| Started | Aug 29 12:34:35 AM UTC 24 |
| Finished | Aug 29 12:41:07 AM UTC 24 |
| Peak memory | 211568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508739335 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_pipeline.2508739335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/6.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.512817099 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 818653403 ps |
| CPU time | 77.88 seconds |
| Started | Aug 29 12:35:11 AM UTC 24 |
| Finished | Aug 29 12:36:31 AM UTC 24 |
| Peak memory | 380384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =512817099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_t hroughput_w_partial_write.512817099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/6.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.4044037483 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 33179225805 ps |
| CPU time | 947.67 seconds |
| Started | Aug 29 12:39:10 AM UTC 24 |
| Finished | Aug 29 12:55:08 AM UTC 24 |
| Peak memory | 388560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044037483 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_access_durin g_key_req.4044037483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/7.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_alert_test.2639142349 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 41691990 ps |
| CPU time | 1 seconds |
| Started | Aug 29 12:40:20 AM UTC 24 |
| Finished | Aug 29 12:40:22 AM UTC 24 |
| Peak memory | 210736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639142349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_alert_test.2639142349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/7.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_bijection.414243033 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 191812832826 ps |
| CPU time | 3004.46 seconds |
| Started | Aug 29 12:37:52 AM UTC 24 |
| Finished | Aug 29 01:28:33 AM UTC 24 |
| Peak memory | 213212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414243033 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.414243033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/7.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_executable.1682039924 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 17870064574 ps |
| CPU time | 752.31 seconds |
| Started | Aug 29 12:39:13 AM UTC 24 |
| Finished | Aug 29 12:51:55 AM UTC 24 |
| Peak memory | 386596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682039924 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executable.1682039924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/7.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.605997498 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 19718665081 ps |
| CPU time | 232.81 seconds |
| Started | Aug 29 12:39:09 AM UTC 24 |
| Finished | Aug 29 12:43:05 AM UTC 24 |
| Peak memory | 221752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605997498 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_escalation.605997498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/7.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.1840300701 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 755031378 ps |
| CPU time | 26.33 seconds |
| Started | Aug 29 12:38:32 AM UTC 24 |
| Finished | Aug 29 12:38:59 AM UTC 24 |
| Peak memory | 304612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1840300701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_m ax_throughput.1840300701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/7.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.1008665487 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 8781554369 ps |
| CPU time | 156.51 seconds |
| Started | Aug 29 12:39:47 AM UTC 24 |
| Finished | Aug 29 12:42:27 AM UTC 24 |
| Peak memory | 221880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008665487 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_mem_partial_access.1008665487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/7.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.3059474378 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 6989937848 ps |
| CPU time | 171 seconds |
| Started | Aug 29 12:39:47 AM UTC 24 |
| Finished | Aug 29 12:42:41 AM UTC 24 |
| Peak memory | 221864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059474378 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_mem_walk.3059474378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/7.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.1016359473 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 72443549346 ps |
| CPU time | 1072.05 seconds |
| Started | Aug 29 12:37:52 AM UTC 24 |
| Finished | Aug 29 12:55:55 AM UTC 24 |
| Peak memory | 386516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016359473 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multiple_keys.1016359473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/7.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access.2701627303 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 392492650 ps |
| CPU time | 6.04 seconds |
| Started | Aug 29 12:38:24 AM UTC 24 |
| Finished | Aug 29 12:38:31 AM UTC 24 |
| Peak memory | 211484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701627303 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_partial_access.2701627303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/7.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.1289776557 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 77600649881 ps |
| CPU time | 559.22 seconds |
| Started | Aug 29 12:38:28 AM UTC 24 |
| Finished | Aug 29 12:47:54 AM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289776557 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_partial_ac cess_b2b.1289776557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/7.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.3465760275 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 1406019156 ps |
| CPU time | 4.74 seconds |
| Started | Aug 29 12:39:40 AM UTC 24 |
| Finished | Aug 29 12:39:46 AM UTC 24 |
| Peak memory | 211624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465760275 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.3465760275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/7.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_regwen.2479033427 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 78401514798 ps |
| CPU time | 971.45 seconds |
| Started | Aug 29 12:39:39 AM UTC 24 |
| Finished | Aug 29 12:56:02 AM UTC 24 |
| Peak memory | 388560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479033427 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.2479033427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/7.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_smoke.2664369846 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 614129315 ps |
| CPU time | 13.07 seconds |
| Started | Aug 29 12:37:37 AM UTC 24 |
| Finished | Aug 29 12:37:51 AM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664369846 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.2664369846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/7.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all.1317757029 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 463323243970 ps |
| CPU time | 4611.2 seconds |
| Started | Aug 29 12:40:10 AM UTC 24 |
| Finished | Aug 29 01:57:49 AM UTC 24 |
| Peak memory | 392152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13177570 29 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all.1317757029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/7.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.928950630 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 2932391649 ps |
| CPU time | 42.36 seconds |
| Started | Aug 29 12:39:51 AM UTC 24 |
| Finished | Aug 29 12:40:35 AM UTC 24 |
| Peak memory | 221924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928950630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.928950630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/7.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.1792083633 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 5158382522 ps |
| CPU time | 191.74 seconds |
| Started | Aug 29 12:37:58 AM UTC 24 |
| Finished | Aug 29 12:41:12 AM UTC 24 |
| Peak memory | 211576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792083633 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_pipeline.1792083633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/7.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.266009322 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 10904199060 ps |
| CPU time | 77.23 seconds |
| Started | Aug 29 12:39:00 AM UTC 24 |
| Finished | Aug 29 12:40:19 AM UTC 24 |
| Peak memory | 355788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =266009322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_t hroughput_w_partial_write.266009322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/7.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.1571356082 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 3154928227 ps |
| CPU time | 153.07 seconds |
| Started | Aug 29 12:41:24 AM UTC 24 |
| Finished | Aug 29 12:44:00 AM UTC 24 |
| Peak memory | 337508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571356082 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_access_durin g_key_req.1571356082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/8.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_alert_test.3319639445 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 19866079 ps |
| CPU time | 0.96 seconds |
| Started | Aug 29 12:42:43 AM UTC 24 |
| Finished | Aug 29 12:42:45 AM UTC 24 |
| Peak memory | 210872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319639445 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_alert_test.3319639445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/8.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_bijection.471323189 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 45607806853 ps |
| CPU time | 609.28 seconds |
| Started | Aug 29 12:40:35 AM UTC 24 |
| Finished | Aug 29 12:50:52 AM UTC 24 |
| Peak memory | 211556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=471323189 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection.471323189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/8.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_executable.3204948360 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 108416588897 ps |
| CPU time | 1194.99 seconds |
| Started | Aug 29 12:41:53 AM UTC 24 |
| Finished | Aug 29 01:02:00 AM UTC 24 |
| Peak memory | 386708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204948360 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executable.3204948360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/8.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.700402393 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 7831964382 ps |
| CPU time | 115.32 seconds |
| Started | Aug 29 12:41:21 AM UTC 24 |
| Finished | Aug 29 12:43:18 AM UTC 24 |
| Peak memory | 211640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700402393 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_escalation.700402393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/8.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.3514655410 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 849838186 ps |
| CPU time | 65.28 seconds |
| Started | Aug 29 12:41:13 AM UTC 24 |
| Finished | Aug 29 12:42:21 AM UTC 24 |
| Peak memory | 327068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3514655410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_m ax_throughput.3514655410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/8.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.4280624686 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 2918135508 ps |
| CPU time | 86.76 seconds |
| Started | Aug 29 12:42:17 AM UTC 24 |
| Finished | Aug 29 12:43:46 AM UTC 24 |
| Peak memory | 228944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280624686 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_mem_partial_access.4280624686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/8.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.3439228697 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 43779720205 ps |
| CPU time | 333.04 seconds |
| Started | Aug 29 12:42:15 AM UTC 24 |
| Finished | Aug 29 12:47:53 AM UTC 24 |
| Peak memory | 221812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439228697 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_mem_walk.3439228697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/8.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.2710501703 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 73200985166 ps |
| CPU time | 1153.31 seconds |
| Started | Aug 29 12:40:34 AM UTC 24 |
| Finished | Aug 29 01:00:01 AM UTC 24 |
| Peak memory | 388588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710501703 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multiple_keys.2710501703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/8.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access.3428491558 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 6340364129 ps |
| CPU time | 22.59 seconds |
| Started | Aug 29 12:40:59 AM UTC 24 |
| Finished | Aug 29 12:41:23 AM UTC 24 |
| Peak memory | 211536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428491558 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_partial_access.3428491558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/8.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.3435570104 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 48266186929 ps |
| CPU time | 835.07 seconds |
| Started | Aug 29 12:41:07 AM UTC 24 |
| Finished | Aug 29 12:55:13 AM UTC 24 |
| Peak memory | 211632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435570104 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_partial_ac cess_b2b.3435570104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/8.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.3513279293 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 364077220 ps |
| CPU time | 5.47 seconds |
| Started | Aug 29 12:42:10 AM UTC 24 |
| Finished | Aug 29 12:42:17 AM UTC 24 |
| Peak memory | 211888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513279293 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.3513279293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/8.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_regwen.1917603313 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 14898076000 ps |
| CPU time | 389.97 seconds |
| Started | Aug 29 12:41:56 AM UTC 24 |
| Finished | Aug 29 12:48:30 AM UTC 24 |
| Peak memory | 378324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917603313 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.1917603313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/8.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_smoke.2569363250 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 3951337896 ps |
| CPU time | 21.73 seconds |
| Started | Aug 29 12:40:23 AM UTC 24 |
| Finished | Aug 29 12:40:46 AM UTC 24 |
| Peak memory | 211640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569363250 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.2569363250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/8.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all.1248368618 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 257758915469 ps |
| CPU time | 3640.82 seconds |
| Started | Aug 29 12:42:27 AM UTC 24 |
| Finished | Aug 29 01:43:46 AM UTC 24 |
| Peak memory | 392156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12483686 18 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all.1248368618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/8.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.4249767220 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 1157711770 ps |
| CPU time | 44.11 seconds |
| Started | Aug 29 12:42:21 AM UTC 24 |
| Finished | Aug 29 12:43:07 AM UTC 24 |
| Peak memory | 229016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249767220 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.4249767220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/8.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.4069181685 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 4989431083 ps |
| CPU time | 189.01 seconds |
| Started | Aug 29 12:40:47 AM UTC 24 |
| Finished | Aug 29 12:43:59 AM UTC 24 |
| Peak memory | 211576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069181685 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_pipeline.4069181685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/8.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.2218986242 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 767322911 ps |
| CPU time | 30.04 seconds |
| Started | Aug 29 12:41:21 AM UTC 24 |
| Finished | Aug 29 12:41:52 AM UTC 24 |
| Peak memory | 306568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2218986242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ throughput_w_partial_write.2218986242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/8.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.1169108563 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 9801850507 ps |
| CPU time | 249.59 seconds |
| Started | Aug 29 12:44:00 AM UTC 24 |
| Finished | Aug 29 12:48:14 AM UTC 24 |
| Peak memory | 384476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169108563 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_access_durin g_key_req.1169108563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/9.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_alert_test.979618451 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 28484844 ps |
| CPU time | 0.95 seconds |
| Started | Aug 29 12:45:31 AM UTC 24 |
| Finished | Aug 29 12:45:34 AM UTC 24 |
| Peak memory | 210880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979618451 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_alert_test.979618451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/9.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_bijection.3959690683 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 10947278119 ps |
| CPU time | 723.34 seconds |
| Started | Aug 29 12:43:08 AM UTC 24 |
| Finished | Aug 29 12:55:20 AM UTC 24 |
| Peak memory | 211656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959690683 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.3959690683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/9.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_executable.2567583351 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 14481838861 ps |
| CPU time | 298.62 seconds |
| Started | Aug 29 12:44:01 AM UTC 24 |
| Finished | Aug 29 12:49:03 AM UTC 24 |
| Peak memory | 378520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567583351 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executable.2567583351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/9.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.777364218 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 6334477675 ps |
| CPU time | 74.95 seconds |
| Started | Aug 29 12:43:58 AM UTC 24 |
| Finished | Aug 29 12:45:15 AM UTC 24 |
| Peak memory | 211556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777364218 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_escalation.777364218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/9.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.2957254431 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 1520722081 ps |
| CPU time | 16.24 seconds |
| Started | Aug 29 12:43:40 AM UTC 24 |
| Finished | Aug 29 12:43:58 AM UTC 24 |
| Peak memory | 261528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2957254431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_m ax_throughput.2957254431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/9.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.246769192 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 9567743732 ps |
| CPU time | 92.83 seconds |
| Started | Aug 29 12:44:32 AM UTC 24 |
| Finished | Aug 29 12:46:07 AM UTC 24 |
| Peak memory | 222180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246769192 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_mem_partial_access.246769192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/9.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.3245176217 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 55354007045 ps |
| CPU time | 352.61 seconds |
| Started | Aug 29 12:44:16 AM UTC 24 |
| Finished | Aug 29 12:50:13 AM UTC 24 |
| Peak memory | 221936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245176217 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_mem_walk.3245176217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/9.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.377707962 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 5987085779 ps |
| CPU time | 410.65 seconds |
| Started | Aug 29 12:43:07 AM UTC 24 |
| Finished | Aug 29 12:50:03 AM UTC 24 |
| Peak memory | 384544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377707962 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multiple_keys.377707962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/9.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access.555294468 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 1238866417 ps |
| CPU time | 14.01 seconds |
| Started | Aug 29 12:43:20 AM UTC 24 |
| Finished | Aug 29 12:43:35 AM UTC 24 |
| Peak memory | 211432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555294468 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_partial_access.555294468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/9.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.3251544313 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 31737017427 ps |
| CPU time | 482.63 seconds |
| Started | Aug 29 12:43:36 AM UTC 24 |
| Finished | Aug 29 12:51:45 AM UTC 24 |
| Peak memory | 211632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251544313 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_partial_ac cess_b2b.3251544313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/9.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.2954295598 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 350391360 ps |
| CPU time | 5.84 seconds |
| Started | Aug 29 12:44:08 AM UTC 24 |
| Finished | Aug 29 12:44:15 AM UTC 24 |
| Peak memory | 211696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954295598 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.2954295598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/9.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_regwen.3915465566 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 13980154217 ps |
| CPU time | 603.69 seconds |
| Started | Aug 29 12:44:07 AM UTC 24 |
| Finished | Aug 29 12:54:18 AM UTC 24 |
| Peak memory | 388756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915465566 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.3915465566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/9.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_smoke.2707039506 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 1600264484 ps |
| CPU time | 32.5 seconds |
| Started | Aug 29 12:42:46 AM UTC 24 |
| Finished | Aug 29 12:43:20 AM UTC 24 |
| Peak memory | 211696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707039506 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.2707039506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/9.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all.2550373552 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 80698284269 ps |
| CPU time | 1336.36 seconds |
| Started | Aug 29 12:45:20 AM UTC 24 |
| Finished | Aug 29 01:07:50 AM UTC 24 |
| Peak memory | 382428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25503735 52 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all.2550373552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/9.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1049641375 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 10415951814 ps |
| CPU time | 100.57 seconds |
| Started | Aug 29 12:45:16 AM UTC 24 |
| Finished | Aug 29 12:46:59 AM UTC 24 |
| Peak memory | 228948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049641375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.1049641375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/9.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.511385721 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 3591303907 ps |
| CPU time | 233.48 seconds |
| Started | Aug 29 12:43:19 AM UTC 24 |
| Finished | Aug 29 12:47:16 AM UTC 24 |
| Peak memory | 211624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511385721 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_pipeline.511385721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/9.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.1269578745 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 3050380342 ps |
| CPU time | 43.68 seconds |
| Started | Aug 29 12:43:46 AM UTC 24 |
| Finished | Aug 29 12:44:31 AM UTC 24 |
| Peak memory | 304596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1269578745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ throughput_w_partial_write.1269578745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/9.sram_ctrl_throughput_w_partial_write/latest |
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