| T798 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access.2563876155 |
|
|
Aug 29 02:39:45 AM UTC 24 |
Aug 29 02:40:23 AM UTC 24 |
10341636000 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.3149468962 |
|
|
Aug 29 02:39:51 AM UTC 24 |
Aug 29 02:40:26 AM UTC 24 |
3005034080 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_bijection.2014919391 |
|
|
Aug 29 02:24:20 AM UTC 24 |
Aug 29 02:40:43 AM UTC 24 |
129648341347 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.3106504741 |
|
|
Aug 29 02:37:36 AM UTC 24 |
Aug 29 02:40:53 AM UTC 24 |
9171002805 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.1973237080 |
|
|
Aug 29 02:23:13 AM UTC 24 |
Aug 29 02:41:05 AM UTC 24 |
10439031512 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.1017253123 |
|
|
Aug 29 02:33:06 AM UTC 24 |
Aug 29 02:41:12 AM UTC 24 |
5709363390 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.3484575890 |
|
|
Aug 29 02:41:05 AM UTC 24 |
Aug 29 02:41:12 AM UTC 24 |
710911220 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.1111693059 |
|
|
Aug 29 02:40:22 AM UTC 24 |
Aug 29 02:41:16 AM UTC 24 |
769932884 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_regwen.2871826965 |
|
|
Aug 29 02:25:52 AM UTC 24 |
Aug 29 02:41:52 AM UTC 24 |
111406998852 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2651491603 |
|
|
Aug 29 02:41:16 AM UTC 24 |
Aug 29 02:42:01 AM UTC 24 |
1642956483 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_alert_test.1713254660 |
|
|
Aug 29 02:42:02 AM UTC 24 |
Aug 29 02:42:04 AM UTC 24 |
41342444 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.1896753308 |
|
|
Aug 29 02:37:33 AM UTC 24 |
Aug 29 02:42:05 AM UTC 24 |
10547102828 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_regwen.2526367614 |
|
|
Aug 29 02:19:35 AM UTC 24 |
Aug 29 02:42:07 AM UTC 24 |
77103022167 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.469706409 |
|
|
Aug 29 02:40:25 AM UTC 24 |
Aug 29 02:42:07 AM UTC 24 |
81027755675 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.2757156642 |
|
|
Aug 29 02:32:36 AM UTC 24 |
Aug 29 02:42:08 AM UTC 24 |
154598504358 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all.4153034990 |
|
|
Aug 29 02:00:55 AM UTC 24 |
Aug 29 02:42:08 AM UTC 24 |
46901267432 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.4265446602 |
|
|
Aug 29 02:34:36 AM UTC 24 |
Aug 29 02:42:20 AM UTC 24 |
6609572072 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.3494834713 |
|
|
Aug 29 02:42:21 AM UTC 24 |
Aug 29 02:42:30 AM UTC 24 |
2375399144 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access.1930151155 |
|
|
Aug 29 02:42:10 AM UTC 24 |
Aug 29 02:42:39 AM UTC 24 |
6930684099 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_executable.2007120962 |
|
|
Aug 29 02:33:22 AM UTC 24 |
Aug 29 02:42:51 AM UTC 24 |
7300981799 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.3411206743 |
|
|
Aug 29 02:41:13 AM UTC 24 |
Aug 29 02:42:54 AM UTC 24 |
1446013236 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all.2243860146 |
|
|
Aug 29 01:27:02 AM UTC 24 |
Aug 29 02:43:17 AM UTC 24 |
138529984416 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.1440966414 |
|
|
Aug 29 02:38:44 AM UTC 24 |
Aug 29 02:43:21 AM UTC 24 |
3163483251 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.4023972941 |
|
|
Aug 29 02:43:22 AM UTC 24 |
Aug 29 02:43:28 AM UTC 24 |
1034857063 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_executable.2769898410 |
|
|
Aug 29 02:40:44 AM UTC 24 |
Aug 29 02:43:30 AM UTC 24 |
1875728605 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_executable.886286607 |
|
|
Aug 29 02:42:54 AM UTC 24 |
Aug 29 02:43:48 AM UTC 24 |
1254646655 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all.1929509955 |
|
|
Aug 29 12:28:08 AM UTC 24 |
Aug 29 02:43:51 AM UTC 24 |
1205295575748 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.1589705997 |
|
|
Aug 29 02:42:40 AM UTC 24 |
Aug 29 02:43:55 AM UTC 24 |
29970458399 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_alert_test.2347687227 |
|
|
Aug 29 02:43:56 AM UTC 24 |
Aug 29 02:43:58 AM UTC 24 |
16216851 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_smoke.528950459 |
|
|
Aug 29 02:42:05 AM UTC 24 |
Aug 29 02:44:03 AM UTC 24 |
12043336475 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_smoke.765315767 |
|
|
Aug 29 02:43:59 AM UTC 24 |
Aug 29 02:44:12 AM UTC 24 |
744902398 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all.2345196447 |
|
|
Aug 29 01:40:57 AM UTC 24 |
Aug 29 02:44:14 AM UTC 24 |
224472166273 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.773410795 |
|
|
Aug 29 02:42:31 AM UTC 24 |
Aug 29 02:44:19 AM UTC 24 |
1600943582 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.4013911194 |
|
|
Aug 29 02:43:49 AM UTC 24 |
Aug 29 02:44:35 AM UTC 24 |
1688748314 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.2135638232 |
|
|
Aug 29 02:35:27 AM UTC 24 |
Aug 29 02:44:45 AM UTC 24 |
13089267916 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.2295837557 |
|
|
Aug 29 02:41:12 AM UTC 24 |
Aug 29 02:44:55 AM UTC 24 |
13831784410 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access.1080421032 |
|
|
Aug 29 02:44:20 AM UTC 24 |
Aug 29 02:45:13 AM UTC 24 |
4612425053 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_bijection.3146067815 |
|
|
Aug 29 02:10:29 AM UTC 24 |
Aug 29 02:45:15 AM UTC 24 |
215337150934 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.1478275706 |
|
|
Aug 29 02:44:56 AM UTC 24 |
Aug 29 02:45:40 AM UTC 24 |
3086998221 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.1564854263 |
|
|
Aug 29 02:44:46 AM UTC 24 |
Aug 29 02:45:53 AM UTC 24 |
3103121523 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.3379979282 |
|
|
Aug 29 02:45:54 AM UTC 24 |
Aug 29 02:46:01 AM UTC 24 |
1044034727 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.355363291 |
|
|
Aug 29 02:42:07 AM UTC 24 |
Aug 29 02:46:04 AM UTC 24 |
5927778331 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.1373278375 |
|
|
Aug 29 02:39:50 AM UTC 24 |
Aug 29 02:46:24 AM UTC 24 |
173462633943 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.1900325574 |
|
|
Aug 29 02:45:15 AM UTC 24 |
Aug 29 02:46:33 AM UTC 24 |
21395710856 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3724872332 |
|
|
Aug 29 02:46:25 AM UTC 24 |
Aug 29 02:47:01 AM UTC 24 |
612084794 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_alert_test.301893616 |
|
|
Aug 29 02:47:02 AM UTC 24 |
Aug 29 02:47:04 AM UTC 24 |
35850598 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_smoke.3337344127 |
|
|
Aug 29 02:47:05 AM UTC 24 |
Aug 29 02:47:26 AM UTC 24 |
508289071 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_executable.1563290174 |
|
|
Aug 29 02:35:35 AM UTC 24 |
Aug 29 02:47:37 AM UTC 24 |
14053837404 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.3928666082 |
|
|
Aug 29 02:43:31 AM UTC 24 |
Aug 29 02:47:47 AM UTC 24 |
13789937590 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all.3056624319 |
|
|
Aug 29 01:44:28 AM UTC 24 |
Aug 29 02:47:53 AM UTC 24 |
246670000377 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.3328663114 |
|
|
Aug 29 02:44:15 AM UTC 24 |
Aug 29 02:47:54 AM UTC 24 |
2683157681 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all.4127889983 |
|
|
Aug 29 01:47:37 AM UTC 24 |
Aug 29 02:48:03 AM UTC 24 |
108408072957 ps |
| T97 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.4063691688 |
|
|
Aug 29 02:46:06 AM UTC 24 |
Aug 29 02:48:05 AM UTC 24 |
9944394868 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_regwen.3255322717 |
|
|
Aug 29 02:45:41 AM UTC 24 |
Aug 29 02:48:31 AM UTC 24 |
5469940516 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.4087192109 |
|
|
Aug 29 02:48:06 AM UTC 24 |
Aug 29 02:48:32 AM UTC 24 |
757180359 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.3708769378 |
|
|
Aug 29 02:46:02 AM UTC 24 |
Aug 29 02:48:50 AM UTC 24 |
8231009859 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.1639441612 |
|
|
Aug 29 02:44:36 AM UTC 24 |
Aug 29 02:48:55 AM UTC 24 |
6944919454 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access.2907640439 |
|
|
Aug 29 02:47:54 AM UTC 24 |
Aug 29 02:48:58 AM UTC 24 |
10178638930 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.1303969488 |
|
|
Aug 29 02:48:59 AM UTC 24 |
Aug 29 02:49:06 AM UTC 24 |
1353422232 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all.503788997 |
|
|
Aug 29 01:10:18 AM UTC 24 |
Aug 29 02:49:07 AM UTC 24 |
56715136554 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.4042262689 |
|
|
Aug 29 02:48:05 AM UTC 24 |
Aug 29 02:49:12 AM UTC 24 |
1500186811 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.499547514 |
|
|
Aug 29 02:48:31 AM UTC 24 |
Aug 29 02:49:30 AM UTC 24 |
4952047855 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_alert_test.656526495 |
|
|
Aug 29 02:50:14 AM UTC 24 |
Aug 29 02:50:16 AM UTC 24 |
20311966 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_smoke.523293657 |
|
|
Aug 29 02:50:17 AM UTC 24 |
Aug 29 02:50:33 AM UTC 24 |
2942693891 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_regwen.430952521 |
|
|
Aug 29 02:43:17 AM UTC 24 |
Aug 29 02:50:48 AM UTC 24 |
11550292218 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1219648335 |
|
|
Aug 29 02:49:13 AM UTC 24 |
Aug 29 02:50:56 AM UTC 24 |
1424485594 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.1186925601 |
|
|
Aug 29 02:49:09 AM UTC 24 |
Aug 29 02:51:00 AM UTC 24 |
2935942945 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access.556438883 |
|
|
Aug 29 02:51:01 AM UTC 24 |
Aug 29 02:51:17 AM UTC 24 |
801792235 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.726536686 |
|
|
Aug 29 02:49:07 AM UTC 24 |
Aug 29 02:51:48 AM UTC 24 |
10958747406 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_bijection.186487277 |
|
|
Aug 29 02:20:26 AM UTC 24 |
Aug 29 02:52:07 AM UTC 24 |
331789648006 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.2212559772 |
|
|
Aug 29 02:50:34 AM UTC 24 |
Aug 29 02:52:26 AM UTC 24 |
1343754179 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_regwen.1942136301 |
|
|
Aug 29 02:29:53 AM UTC 24 |
Aug 29 02:52:31 AM UTC 24 |
72714212989 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_bijection.1812670507 |
|
|
Aug 29 02:31:25 AM UTC 24 |
Aug 29 02:52:44 AM UTC 24 |
230829678212 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.1154079288 |
|
|
Aug 29 02:42:10 AM UTC 24 |
Aug 29 02:52:47 AM UTC 24 |
101782574120 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.2060906757 |
|
|
Aug 29 02:51:49 AM UTC 24 |
Aug 29 02:52:49 AM UTC 24 |
2652205649 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.1930056033 |
|
|
Aug 29 02:43:30 AM UTC 24 |
Aug 29 02:52:49 AM UTC 24 |
82825140489 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.68266477 |
|
|
Aug 29 02:52:49 AM UTC 24 |
Aug 29 02:52:57 AM UTC 24 |
366928279 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.1875720157 |
|
|
Aug 29 02:40:28 AM UTC 24 |
Aug 29 02:53:20 AM UTC 24 |
44852221780 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.805906327 |
|
|
Aug 29 02:52:09 AM UTC 24 |
Aug 29 02:53:39 AM UTC 24 |
823824163 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3402391564 |
|
|
Aug 29 02:53:21 AM UTC 24 |
Aug 29 02:53:44 AM UTC 24 |
1613729742 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_alert_test.3449714373 |
|
|
Aug 29 02:53:45 AM UTC 24 |
Aug 29 02:53:47 AM UTC 24 |
38477302 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.3440171584 |
|
|
Aug 29 02:29:42 AM UTC 24 |
Aug 29 02:54:10 AM UTC 24 |
70992442320 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.522659469 |
|
|
Aug 29 02:47:49 AM UTC 24 |
Aug 29 02:54:18 AM UTC 24 |
8506771735 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all.3007375217 |
|
|
Aug 29 02:09:52 AM UTC 24 |
Aug 29 02:54:27 AM UTC 24 |
156605916692 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.3451446124 |
|
|
Aug 29 02:52:27 AM UTC 24 |
Aug 29 02:54:39 AM UTC 24 |
112198659677 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access.1716878387 |
|
|
Aug 29 02:54:40 AM UTC 24 |
Aug 29 02:54:54 AM UTC 24 |
2590115407 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_regwen.320803116 |
|
|
Aug 29 02:40:54 AM UTC 24 |
Aug 29 02:55:32 AM UTC 24 |
9629108821 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_smoke.2411666128 |
|
|
Aug 29 02:53:49 AM UTC 24 |
Aug 29 02:55:34 AM UTC 24 |
3868073044 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.3482525825 |
|
|
Aug 29 02:52:58 AM UTC 24 |
Aug 29 02:56:01 AM UTC 24 |
4395555846 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.3326198664 |
|
|
Aug 29 02:50:57 AM UTC 24 |
Aug 29 02:56:02 AM UTC 24 |
12859724785 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.1434825022 |
|
|
Aug 29 02:45:16 AM UTC 24 |
Aug 29 02:56:03 AM UTC 24 |
15975233745 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_bijection.976410302 |
|
|
Aug 29 02:34:23 AM UTC 24 |
Aug 29 02:56:04 AM UTC 24 |
66976864404 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.2365617866 |
|
|
Aug 29 02:42:52 AM UTC 24 |
Aug 29 02:56:06 AM UTC 24 |
12629389616 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.786785882 |
|
|
Aug 29 02:56:07 AM UTC 24 |
Aug 29 02:56:12 AM UTC 24 |
346052357 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.104053935 |
|
|
Aug 29 02:55:36 AM UTC 24 |
Aug 29 02:56:48 AM UTC 24 |
3049243926 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.2863347522 |
|
|
Aug 29 02:47:55 AM UTC 24 |
Aug 29 02:56:49 AM UTC 24 |
80021117564 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.1318638223 |
|
|
Aug 29 02:55:34 AM UTC 24 |
Aug 29 02:57:21 AM UTC 24 |
1548331085 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.3450823779 |
|
|
Aug 29 02:34:14 AM UTC 24 |
Aug 29 02:57:55 AM UTC 24 |
9093699781 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_alert_test.2078333759 |
|
|
Aug 29 02:57:57 AM UTC 24 |
Aug 29 02:57:59 AM UTC 24 |
96591021 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_all.7255349 |
|
|
Aug 29 01:57:30 AM UTC 24 |
Aug 29 02:58:03 AM UTC 24 |
109767910559 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.1939898955 |
|
|
Aug 29 02:52:51 AM UTC 24 |
Aug 29 02:58:13 AM UTC 24 |
5652191827 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_bijection.3689297500 |
|
|
Aug 29 02:17:57 AM UTC 24 |
Aug 29 02:58:15 AM UTC 24 |
431409010004 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_bijection.3346970237 |
|
|
Aug 29 02:06:56 AM UTC 24 |
Aug 29 02:58:41 AM UTC 24 |
411005399171 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_executable.2592489826 |
|
|
Aug 29 02:45:19 AM UTC 24 |
Aug 29 02:58:43 AM UTC 24 |
83697045407 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.1746212007 |
|
|
Aug 29 02:56:02 AM UTC 24 |
Aug 29 02:58:43 AM UTC 24 |
52004291514 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.3368155175 |
|
|
Aug 29 02:56:50 AM UTC 24 |
Aug 29 02:58:46 AM UTC 24 |
2441153006 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.1366790086 |
|
|
Aug 29 02:56:12 AM UTC 24 |
Aug 29 02:59:04 AM UTC 24 |
7894879437 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.3217931384 |
|
|
Aug 29 02:51:18 AM UTC 24 |
Aug 29 02:59:58 AM UTC 24 |
163510731432 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3001296992 |
|
|
Aug 29 02:56:52 AM UTC 24 |
Aug 29 02:59:59 AM UTC 24 |
4751833477 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.2921831738 |
|
|
Aug 29 02:54:28 AM UTC 24 |
Aug 29 03:00:42 AM UTC 24 |
4802155298 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.3108649850 |
|
|
Aug 29 02:44:04 AM UTC 24 |
Aug 29 03:01:09 AM UTC 24 |
30535452447 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_bijection.21909297 |
|
|
Aug 29 02:13:38 AM UTC 24 |
Aug 29 03:01:28 AM UTC 24 |
965458386413 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.2678247934 |
|
|
Aug 29 02:38:26 AM UTC 24 |
Aug 29 03:01:31 AM UTC 24 |
57619587483 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_regwen.1345908010 |
|
|
Aug 29 02:48:56 AM UTC 24 |
Aug 29 03:02:41 AM UTC 24 |
111672708170 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_executable.2777776105 |
|
|
Aug 29 02:48:51 AM UTC 24 |
Aug 29 03:03:40 AM UTC 24 |
14332845477 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all.1805081364 |
|
|
Aug 29 02:20:07 AM UTC 24 |
Aug 29 03:03:48 AM UTC 24 |
35482142147 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.4017999861 |
|
|
Aug 29 02:54:56 AM UTC 24 |
Aug 29 03:04:29 AM UTC 24 |
7995321555 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.3329037116 |
|
|
Aug 29 02:52:32 AM UTC 24 |
Aug 29 03:04:39 AM UTC 24 |
14480655879 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_regwen.1328703100 |
|
|
Aug 29 02:52:48 AM UTC 24 |
Aug 29 03:04:48 AM UTC 24 |
12375187046 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_executable.1901658946 |
|
|
Aug 29 02:52:45 AM UTC 24 |
Aug 29 03:05:13 AM UTC 24 |
123832151493 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all.741549304 |
|
|
Aug 29 02:23:44 AM UTC 24 |
Aug 29 03:06:10 AM UTC 24 |
76380330398 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.3515475503 |
|
|
Aug 29 02:56:04 AM UTC 24 |
Aug 29 03:06:58 AM UTC 24 |
32345781162 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.2412359550 |
|
|
Aug 29 02:48:34 AM UTC 24 |
Aug 29 03:07:16 AM UTC 24 |
32801228547 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_regwen.740059252 |
|
|
Aug 29 02:56:06 AM UTC 24 |
Aug 29 03:07:21 AM UTC 24 |
55834551602 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all.635126400 |
|
|
Aug 29 02:06:25 AM UTC 24 |
Aug 29 03:08:24 AM UTC 24 |
267385875150 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_multiple_keys.1732935094 |
|
|
Aug 29 02:47:27 AM UTC 24 |
Aug 29 03:08:27 AM UTC 24 |
46291634150 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_executable.360290217 |
|
|
Aug 29 02:56:04 AM UTC 24 |
Aug 29 03:10:01 AM UTC 24 |
10964388111 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_bijection.1983876323 |
|
|
Aug 29 02:50:49 AM UTC 24 |
Aug 29 03:11:03 AM UTC 24 |
14927015039 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.521911540 |
|
|
Aug 29 02:54:11 AM UTC 24 |
Aug 29 03:11:27 AM UTC 24 |
17141120517 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all.140680098 |
|
|
Aug 29 02:26:39 AM UTC 24 |
Aug 29 03:14:10 AM UTC 24 |
27991081503 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all.455161255 |
|
|
Aug 29 01:19:47 AM UTC 24 |
Aug 29 03:17:02 AM UTC 24 |
3305888053630 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_bijection.2876743994 |
|
|
Aug 29 02:54:20 AM UTC 24 |
Aug 29 03:17:03 AM UTC 24 |
57713980177 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_bijection.3382925996 |
|
|
Aug 29 02:38:35 AM UTC 24 |
Aug 29 03:19:19 AM UTC 24 |
101050312690 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_bijection.1401404417 |
|
|
Aug 29 02:42:07 AM UTC 24 |
Aug 29 03:23:07 AM UTC 24 |
117744260026 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all.3549902777 |
|
|
Aug 29 02:16:23 AM UTC 24 |
Aug 29 03:25:27 AM UTC 24 |
650455270049 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all.1932057352 |
|
|
Aug 29 02:30:26 AM UTC 24 |
Aug 29 03:29:11 AM UTC 24 |
207408227272 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all.130706479 |
|
|
Aug 29 02:43:51 AM UTC 24 |
Aug 29 03:31:02 AM UTC 24 |
51935844043 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_all.359600658 |
|
|
Aug 29 01:54:29 AM UTC 24 |
Aug 29 03:33:58 AM UTC 24 |
200791897180 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all.4009368299 |
|
|
Aug 29 02:53:41 AM UTC 24 |
Aug 29 03:34:55 AM UTC 24 |
262468195319 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all.1106670835 |
|
|
Aug 29 02:12:58 AM UTC 24 |
Aug 29 03:38:21 AM UTC 24 |
252818412678 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_bijection.657258338 |
|
|
Aug 29 02:47:39 AM UTC 24 |
Aug 29 03:38:41 AM UTC 24 |
705512411843 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all.3565213735 |
|
|
Aug 29 02:49:31 AM UTC 24 |
Aug 29 03:40:47 AM UTC 24 |
347831502658 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all.3935690666 |
|
|
Aug 29 02:46:34 AM UTC 24 |
Aug 29 03:47:57 AM UTC 24 |
60932704888 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all.967526624 |
|
|
Aug 29 02:38:03 AM UTC 24 |
Aug 29 03:50:47 AM UTC 24 |
309234322958 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all.272989621 |
|
|
Aug 29 01:50:53 AM UTC 24 |
Aug 29 03:52:02 AM UTC 24 |
834309930644 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all.3605305798 |
|
|
Aug 29 02:41:54 AM UTC 24 |
Aug 29 03:59:49 AM UTC 24 |
215990737236 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all.3528044093 |
|
|
Aug 29 02:34:04 AM UTC 24 |
Aug 29 04:11:53 AM UTC 24 |
427940232587 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.72714082 |
|
|
Aug 29 12:11:18 AM UTC 24 |
Aug 29 12:11:20 AM UTC 24 |
25668000 ps |
| T72 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3342383663 |
|
|
Aug 29 12:11:18 AM UTC 24 |
Aug 29 12:11:20 AM UTC 24 |
17794874 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2350057702 |
|
|
Aug 29 12:11:18 AM UTC 24 |
Aug 29 12:11:20 AM UTC 24 |
32619791 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3719618276 |
|
|
Aug 29 12:11:18 AM UTC 24 |
Aug 29 12:11:20 AM UTC 24 |
60738653 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3108392480 |
|
|
Aug 29 12:11:18 AM UTC 24 |
Aug 29 12:11:20 AM UTC 24 |
42501803 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1430947785 |
|
|
Aug 29 12:11:18 AM UTC 24 |
Aug 29 12:11:20 AM UTC 24 |
23443825 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3532622116 |
|
|
Aug 29 12:11:18 AM UTC 24 |
Aug 29 12:11:20 AM UTC 24 |
18048698 ps |
| T104 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1752304790 |
|
|
Aug 29 12:11:18 AM UTC 24 |
Aug 29 12:11:20 AM UTC 24 |
11803867 ps |
| T67 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.431951382 |
|
|
Aug 29 12:11:18 AM UTC 24 |
Aug 29 12:11:21 AM UTC 24 |
367156070 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2859955934 |
|
|
Aug 29 12:11:16 AM UTC 24 |
Aug 29 12:11:21 AM UTC 24 |
173561743 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2781350068 |
|
|
Aug 29 12:11:18 AM UTC 24 |
Aug 29 12:11:22 AM UTC 24 |
184332749 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1916193891 |
|
|
Aug 29 12:11:18 AM UTC 24 |
Aug 29 12:11:22 AM UTC 24 |
469875019 ps |
| T68 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.920836552 |
|
|
Aug 29 12:11:18 AM UTC 24 |
Aug 29 12:11:23 AM UTC 24 |
191593918 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2538592462 |
|
|
Aug 29 12:11:18 AM UTC 24 |
Aug 29 12:11:23 AM UTC 24 |
84301858 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2515869833 |
|
|
Aug 29 12:11:22 AM UTC 24 |
Aug 29 12:11:24 AM UTC 24 |
22983509 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3082164175 |
|
|
Aug 29 12:11:22 AM UTC 24 |
Aug 29 12:11:24 AM UTC 24 |
16247215 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1092556084 |
|
|
Aug 29 12:11:22 AM UTC 24 |
Aug 29 12:11:24 AM UTC 24 |
45010555 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3072004176 |
|
|
Aug 29 12:11:22 AM UTC 24 |
Aug 29 12:11:24 AM UTC 24 |
28042939 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1572860883 |
|
|
Aug 29 12:11:18 AM UTC 24 |
Aug 29 12:11:24 AM UTC 24 |
1535191344 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1974508338 |
|
|
Aug 29 12:11:22 AM UTC 24 |
Aug 29 12:11:25 AM UTC 24 |
85461623 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.82590455 |
|
|
Aug 29 12:11:22 AM UTC 24 |
Aug 29 12:11:25 AM UTC 24 |
23471953 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2475217828 |
|
|
Aug 29 12:11:24 AM UTC 24 |
Aug 29 12:11:26 AM UTC 24 |
81592806 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.4251361532 |
|
|
Aug 29 12:11:24 AM UTC 24 |
Aug 29 12:11:26 AM UTC 24 |
18394422 ps |
| T69 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1439938289 |
|
|
Aug 29 12:11:22 AM UTC 24 |
Aug 29 12:11:26 AM UTC 24 |
167464495 ps |
| T86 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3870845823 |
|
|
Aug 29 12:11:25 AM UTC 24 |
Aug 29 12:11:27 AM UTC 24 |
63883436 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1366932411 |
|
|
Aug 29 12:11:20 AM UTC 24 |
Aug 29 12:11:27 AM UTC 24 |
727749484 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2729737474 |
|
|
Aug 29 12:11:24 AM UTC 24 |
Aug 29 12:11:28 AM UTC 24 |
384854041 ps |
| T87 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1491830324 |
|
|
Aug 29 12:11:24 AM UTC 24 |
Aug 29 12:11:28 AM UTC 24 |
187105394 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1950429040 |
|
|
Aug 29 12:11:27 AM UTC 24 |
Aug 29 12:11:29 AM UTC 24 |
86931374 ps |
| T88 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3160150298 |
|
|
Aug 29 12:11:27 AM UTC 24 |
Aug 29 12:11:29 AM UTC 24 |
42669075 ps |
| T89 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1841985005 |
|
|
Aug 29 12:11:27 AM UTC 24 |
Aug 29 12:11:29 AM UTC 24 |
19129479 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3866245991 |
|
|
Aug 29 12:11:22 AM UTC 24 |
Aug 29 12:11:29 AM UTC 24 |
355952032 ps |
| T90 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.362139108 |
|
|
Aug 29 12:11:29 AM UTC 24 |
Aug 29 12:11:31 AM UTC 24 |
37675501 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1754388174 |
|
|
Aug 29 12:11:29 AM UTC 24 |
Aug 29 12:11:31 AM UTC 24 |
14981033 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2842004234 |
|
|
Aug 29 12:11:24 AM UTC 24 |
Aug 29 12:11:32 AM UTC 24 |
440492911 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.289477318 |
|
|
Aug 29 12:11:29 AM UTC 24 |
Aug 29 12:11:32 AM UTC 24 |
80365742 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2683704035 |
|
|
Aug 29 12:11:29 AM UTC 24 |
Aug 29 12:11:33 AM UTC 24 |
1068590778 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2705059907 |
|
|
Aug 29 12:11:27 AM UTC 24 |
Aug 29 12:11:33 AM UTC 24 |
580745967 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.271216452 |
|
|
Aug 29 12:11:32 AM UTC 24 |
Aug 29 12:11:33 AM UTC 24 |
45575890 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3913425997 |
|
|
Aug 29 12:11:32 AM UTC 24 |
Aug 29 12:11:34 AM UTC 24 |
51114596 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.317189032 |
|
|
Aug 29 12:11:27 AM UTC 24 |
Aug 29 12:11:34 AM UTC 24 |
157501289 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.711717058 |
|
|
Aug 29 12:11:29 AM UTC 24 |
Aug 29 12:11:34 AM UTC 24 |
124004685 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1172230550 |
|
|
Aug 29 12:11:27 AM UTC 24 |
Aug 29 12:11:35 AM UTC 24 |
3770638047 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.492611761 |
|
|
Aug 29 12:11:34 AM UTC 24 |
Aug 29 12:11:36 AM UTC 24 |
10867865 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2653717546 |
|
|
Aug 29 12:11:34 AM UTC 24 |
Aug 29 12:11:36 AM UTC 24 |
68631625 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3168079304 |
|
|
Aug 29 12:11:29 AM UTC 24 |
Aug 29 12:11:37 AM UTC 24 |
664965373 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1143489715 |
|
|
Aug 29 12:11:32 AM UTC 24 |
Aug 29 12:11:38 AM UTC 24 |
1462042984 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1162586790 |
|
|
Aug 29 12:11:34 AM UTC 24 |
Aug 29 12:11:38 AM UTC 24 |
411499989 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.4238186343 |
|
|
Aug 29 12:11:36 AM UTC 24 |
Aug 29 12:11:38 AM UTC 24 |
12068677 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3407220098 |
|
|
Aug 29 12:11:36 AM UTC 24 |
Aug 29 12:11:38 AM UTC 24 |
75791188 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.379577120 |
|
|
Aug 29 12:11:36 AM UTC 24 |
Aug 29 12:11:40 AM UTC 24 |
307852105 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3365238470 |
|
|
Aug 29 12:11:34 AM UTC 24 |
Aug 29 12:11:40 AM UTC 24 |
386996315 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3471838887 |
|
|
Aug 29 12:11:34 AM UTC 24 |
Aug 29 12:11:40 AM UTC 24 |
725689932 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1021753791 |
|
|
Aug 29 12:11:36 AM UTC 24 |
Aug 29 12:11:41 AM UTC 24 |
31957134 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.4106845857 |
|
|
Aug 29 12:11:39 AM UTC 24 |
Aug 29 12:11:41 AM UTC 24 |
66148834 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3153663237 |
|
|
Aug 29 12:11:39 AM UTC 24 |
Aug 29 12:11:42 AM UTC 24 |
352220987 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.709456566 |
|
|
Aug 29 12:11:41 AM UTC 24 |
Aug 29 12:11:43 AM UTC 24 |
13594835 ps |
| T91 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.250919862 |
|
|
Aug 29 12:11:41 AM UTC 24 |
Aug 29 12:11:43 AM UTC 24 |
29073056 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.543077155 |
|
|
Aug 29 12:11:41 AM UTC 24 |
Aug 29 12:11:44 AM UTC 24 |
263312601 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.4218344903 |
|
|
Aug 29 12:11:39 AM UTC 24 |
Aug 29 12:11:45 AM UTC 24 |
357314103 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.732341366 |
|
|
Aug 29 12:11:43 AM UTC 24 |
Aug 29 12:11:45 AM UTC 24 |
76820233 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2171526272 |
|
|
Aug 29 12:11:39 AM UTC 24 |
Aug 29 12:11:47 AM UTC 24 |
158187147 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2673571973 |
|
|
Aug 29 12:11:41 AM UTC 24 |
Aug 29 12:11:48 AM UTC 24 |
1186451949 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.234635961 |
|
|
Aug 29 12:11:47 AM UTC 24 |
Aug 29 12:11:49 AM UTC 24 |
21757092 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.4181810602 |
|
|
Aug 29 12:11:47 AM UTC 24 |
Aug 29 12:11:49 AM UTC 24 |
54864713 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1690016066 |
|
|
Aug 29 12:11:46 AM UTC 24 |
Aug 29 12:11:49 AM UTC 24 |
91033529 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2265183990 |
|
|
Aug 29 12:11:41 AM UTC 24 |
Aug 29 12:11:50 AM UTC 24 |
506277343 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3168052554 |
|
|
Aug 29 12:11:43 AM UTC 24 |
Aug 29 12:11:50 AM UTC 24 |
365063270 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.436013383 |
|
|
Aug 29 12:11:46 AM UTC 24 |
Aug 29 12:11:50 AM UTC 24 |
37143435 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2152362598 |
|
|
Aug 29 12:11:50 AM UTC 24 |
Aug 29 12:11:53 AM UTC 24 |
43189862 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2256714241 |
|
|
Aug 29 12:11:50 AM UTC 24 |
Aug 29 12:11:53 AM UTC 24 |
79397743 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2119704165 |
|
|
Aug 29 12:11:49 AM UTC 24 |
Aug 29 12:11:53 AM UTC 24 |
708864812 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.4272442565 |
|
|
Aug 29 12:11:47 AM UTC 24 |
Aug 29 12:11:55 AM UTC 24 |
686037788 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3377340032 |
|
|
Aug 29 12:11:52 AM UTC 24 |
Aug 29 12:11:56 AM UTC 24 |
141781740 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2728427973 |
|
|
Aug 29 12:11:54 AM UTC 24 |
Aug 29 12:11:57 AM UTC 24 |
75267241 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.4096310769 |
|
|
Aug 29 12:11:52 AM UTC 24 |
Aug 29 12:11:57 AM UTC 24 |
649485823 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1467487671 |
|
|
Aug 29 12:11:49 AM UTC 24 |
Aug 29 12:11:57 AM UTC 24 |
125963597 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1623423652 |
|
|
Aug 29 12:11:54 AM UTC 24 |
Aug 29 12:11:57 AM UTC 24 |
14208390 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1165562968 |
|
|
Aug 29 12:11:50 AM UTC 24 |
Aug 29 12:11:58 AM UTC 24 |
719106206 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.444863085 |
|
|
Aug 29 12:11:57 AM UTC 24 |
Aug 29 12:11:59 AM UTC 24 |
24794754 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2212632272 |
|
|
Aug 29 12:11:57 AM UTC 24 |
Aug 29 12:11:59 AM UTC 24 |
14824459 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2231101448 |
|
|
Aug 29 12:12:01 AM UTC 24 |
Aug 29 12:12:03 AM UTC 24 |
18133130 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1636077276 |
|
|
Aug 29 12:11:57 AM UTC 24 |
Aug 29 12:12:03 AM UTC 24 |
368745830 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2445316119 |
|
|
Aug 29 12:11:54 AM UTC 24 |
Aug 29 12:12:03 AM UTC 24 |
677926323 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3920086132 |
|
|
Aug 29 12:11:55 AM UTC 24 |
Aug 29 12:12:04 AM UTC 24 |
1410468015 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.32763511 |
|
|
Aug 29 12:12:01 AM UTC 24 |
Aug 29 12:12:04 AM UTC 24 |
84308323 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2856285245 |
|
|
Aug 29 12:11:57 AM UTC 24 |
Aug 29 12:12:04 AM UTC 24 |
1809675981 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3006854650 |
|
|
Aug 29 12:11:59 AM UTC 24 |
Aug 29 12:12:06 AM UTC 24 |
216150864 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.4011025656 |
|
|
Aug 29 12:12:04 AM UTC 24 |
Aug 29 12:12:06 AM UTC 24 |
26884973 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2421701012 |
|
|
Aug 29 12:12:05 AM UTC 24 |
Aug 29 12:12:07 AM UTC 24 |
16241088 ps |
| T92 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2916835051 |
|
|
Aug 29 12:11:16 AM UTC 24 |
Aug 29 12:12:08 AM UTC 24 |
3841042004 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3044251223 |
|
|
Aug 29 12:12:06 AM UTC 24 |
Aug 29 12:12:08 AM UTC 24 |
18047930 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3701707979 |
|
|
Aug 29 12:12:05 AM UTC 24 |
Aug 29 12:12:08 AM UTC 24 |
139774823 ps |
| T93 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1899067056 |
|
|
Aug 29 12:11:32 AM UTC 24 |
Aug 29 12:12:09 AM UTC 24 |
73972912281 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2266854404 |
|
|
Aug 29 12:12:04 AM UTC 24 |
Aug 29 12:12:10 AM UTC 24 |
348479873 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2738415765 |
|
|
Aug 29 12:12:05 AM UTC 24 |
Aug 29 12:12:11 AM UTC 24 |
142907847 ps |
| T94 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1884379272 |
|
|
Aug 29 12:11:18 AM UTC 24 |
Aug 29 12:12:11 AM UTC 24 |
46080170479 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1391077973 |
|
|
Aug 29 12:12:10 AM UTC 24 |
Aug 29 12:12:12 AM UTC 24 |
44027365 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.4126070081 |
|
|
Aug 29 12:12:11 AM UTC 24 |
Aug 29 12:12:13 AM UTC 24 |
48757969 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3755711098 |
|
|
Aug 29 12:12:09 AM UTC 24 |
Aug 29 12:12:14 AM UTC 24 |
502106895 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2084321515 |
|
|
Aug 29 12:12:08 AM UTC 24 |
Aug 29 12:12:16 AM UTC 24 |
309261526 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3676707467 |
|
|
Aug 29 12:12:14 AM UTC 24 |
Aug 29 12:12:16 AM UTC 24 |
37020720 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_08_28/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1222219417 |
|
|
Aug 29 12:12:07 AM UTC 24 |
Aug 29 12:12:17 AM UTC 24 |
4950837818 ps |