| T311 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.4247335746 |
|
|
Sep 09 08:24:08 AM UTC 24 |
Sep 09 08:25:13 AM UTC 24 |
36643831489 ps |
| T312 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.1784255457 |
|
|
Sep 09 08:03:49 AM UTC 24 |
Sep 09 08:25:31 AM UTC 24 |
102098993570 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.3113419903 |
|
|
Sep 09 08:24:19 AM UTC 24 |
Sep 09 08:25:36 AM UTC 24 |
991198151 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access.2807507266 |
|
|
Sep 09 08:25:09 AM UTC 24 |
Sep 09 08:25:39 AM UTC 24 |
4537197481 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.2556960213 |
|
|
Sep 09 08:20:44 AM UTC 24 |
Sep 09 08:25:55 AM UTC 24 |
11023262598 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.2402794493 |
|
|
Sep 09 08:22:44 AM UTC 24 |
Sep 09 08:26:05 AM UTC 24 |
8532345293 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.2072652230 |
|
|
Sep 09 08:22:42 AM UTC 24 |
Sep 09 08:26:15 AM UTC 24 |
19215729780 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.2550619966 |
|
|
Sep 09 08:26:22 AM UTC 24 |
Sep 09 08:26:29 AM UTC 24 |
403957479 ps |
| T165 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_regwen.3244894247 |
|
|
Sep 09 08:17:33 AM UTC 24 |
Sep 09 08:26:31 AM UTC 24 |
4096970097 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.3308068797 |
|
|
Sep 09 08:23:05 AM UTC 24 |
Sep 09 08:26:34 AM UTC 24 |
68734729897 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.2676075222 |
|
|
Sep 09 08:23:46 AM UTC 24 |
Sep 09 08:26:40 AM UTC 24 |
8214694944 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.3286643821 |
|
|
Sep 09 08:20:23 AM UTC 24 |
Sep 09 08:26:42 AM UTC 24 |
4726922553 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_alert_test.2340056605 |
|
|
Sep 09 08:26:43 AM UTC 24 |
Sep 09 08:26:45 AM UTC 24 |
11206285 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_smoke.1027283576 |
|
|
Sep 09 08:26:46 AM UTC 24 |
Sep 09 08:27:07 AM UTC 24 |
3597813989 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.1428635913 |
|
|
Sep 09 08:25:31 AM UTC 24 |
Sep 09 08:27:11 AM UTC 24 |
1594768796 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.1373025755 |
|
|
Sep 09 08:25:40 AM UTC 24 |
Sep 09 08:27:13 AM UTC 24 |
9420631873 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.666594071 |
|
|
Sep 09 08:25:38 AM UTC 24 |
Sep 09 08:27:20 AM UTC 24 |
815364718 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.339234159 |
|
|
Sep 09 08:26:35 AM UTC 24 |
Sep 09 08:27:34 AM UTC 24 |
1050850618 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.3763562323 |
|
|
Sep 09 08:08:32 AM UTC 24 |
Sep 09 08:27:55 AM UTC 24 |
37200874071 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.605165934 |
|
|
Sep 09 08:21:30 AM UTC 24 |
Sep 09 08:27:57 AM UTC 24 |
61887017736 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.872933422 |
|
|
Sep 09 08:18:02 AM UTC 24 |
Sep 09 08:28:02 AM UTC 24 |
6833652875 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.1505358876 |
|
|
Sep 09 08:27:56 AM UTC 24 |
Sep 09 08:28:05 AM UTC 24 |
1389443279 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.2058044486 |
|
|
Sep 09 08:27:58 AM UTC 24 |
Sep 09 08:28:06 AM UTC 24 |
1441089620 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_bijection.851991054 |
|
|
Sep 09 08:03:49 AM UTC 24 |
Sep 09 08:28:10 AM UTC 24 |
20672824218 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_executable.324457568 |
|
|
Sep 09 08:26:06 AM UTC 24 |
Sep 09 08:28:23 AM UTC 24 |
15627515990 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.450838821 |
|
|
Sep 09 08:28:24 AM UTC 24 |
Sep 09 08:28:32 AM UTC 24 |
617732389 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access.2101853048 |
|
|
Sep 09 08:27:21 AM UTC 24 |
Sep 09 08:28:39 AM UTC 24 |
2312115169 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_bijection.3659220675 |
|
|
Sep 09 08:21:25 AM UTC 24 |
Sep 09 08:29:19 AM UTC 24 |
28717631314 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.3819829819 |
|
|
Sep 09 08:24:00 AM UTC 24 |
Sep 09 08:29:26 AM UTC 24 |
53399067733 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.1232976746 |
|
|
Sep 09 08:24:17 AM UTC 24 |
Sep 09 08:29:48 AM UTC 24 |
22837449580 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_alert_test.185854523 |
|
|
Sep 09 08:29:49 AM UTC 24 |
Sep 09 08:29:51 AM UTC 24 |
36235135 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.3083743235 |
|
|
Sep 09 08:24:43 AM UTC 24 |
Sep 09 08:29:57 AM UTC 24 |
18234818653 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.3348815258 |
|
|
Sep 09 08:22:02 AM UTC 24 |
Sep 09 08:29:57 AM UTC 24 |
275204274235 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.2370202361 |
|
|
Sep 09 08:29:21 AM UTC 24 |
Sep 09 08:29:59 AM UTC 24 |
677726507 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.1844985133 |
|
|
Sep 09 08:28:03 AM UTC 24 |
Sep 09 08:30:01 AM UTC 24 |
10298335987 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_regwen.1539452071 |
|
|
Sep 09 08:19:19 AM UTC 24 |
Sep 09 08:30:15 AM UTC 24 |
3455958311 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.386934981 |
|
|
Sep 09 08:26:32 AM UTC 24 |
Sep 09 08:30:19 AM UTC 24 |
20934189186 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.3689734554 |
|
|
Sep 09 08:24:56 AM UTC 24 |
Sep 09 08:30:30 AM UTC 24 |
17724548771 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.1108687468 |
|
|
Sep 09 08:28:40 AM UTC 24 |
Sep 09 08:30:32 AM UTC 24 |
5351011926 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access.3697449080 |
|
|
Sep 09 08:30:01 AM UTC 24 |
Sep 09 08:30:33 AM UTC 24 |
2744823504 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_regwen.3643806126 |
|
|
Sep 09 08:22:35 AM UTC 24 |
Sep 09 08:30:47 AM UTC 24 |
4892755712 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.2371703859 |
|
|
Sep 09 08:20:58 AM UTC 24 |
Sep 09 08:30:49 AM UTC 24 |
11440033844 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.4105798877 |
|
|
Sep 09 08:14:02 AM UTC 24 |
Sep 09 08:30:50 AM UTC 24 |
81386829462 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.1060375774 |
|
|
Sep 09 08:30:31 AM UTC 24 |
Sep 09 08:30:52 AM UTC 24 |
707299384 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.2550650185 |
|
|
Sep 09 08:30:51 AM UTC 24 |
Sep 09 08:30:57 AM UTC 24 |
916282143 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_smoke.3373551301 |
|
|
Sep 09 08:29:52 AM UTC 24 |
Sep 09 08:31:17 AM UTC 24 |
2370011017 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.2372954959 |
|
|
Sep 09 08:12:25 AM UTC 24 |
Sep 09 08:31:19 AM UTC 24 |
116451317712 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.3752143790 |
|
|
Sep 09 08:20:08 AM UTC 24 |
Sep 09 08:31:36 AM UTC 24 |
7621779501 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_alert_test.2072812288 |
|
|
Sep 09 08:31:37 AM UTC 24 |
Sep 09 08:31:39 AM UTC 24 |
23646058 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_regwen.1397169685 |
|
|
Sep 09 08:28:11 AM UTC 24 |
Sep 09 08:31:45 AM UTC 24 |
14445332202 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.409357295 |
|
|
Sep 09 08:30:21 AM UTC 24 |
Sep 09 08:31:54 AM UTC 24 |
3132653047 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_smoke.2971642996 |
|
|
Sep 09 08:31:40 AM UTC 24 |
Sep 09 08:32:06 AM UTC 24 |
2057695247 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_executable.3669949447 |
|
|
Sep 09 08:28:07 AM UTC 24 |
Sep 09 08:32:21 AM UTC 24 |
14265216419 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_smoke.791591983 |
|
|
Sep 09 08:33:54 AM UTC 24 |
Sep 09 08:34:34 AM UTC 24 |
5120502132 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.981256919 |
|
|
Sep 09 08:27:35 AM UTC 24 |
Sep 09 08:32:31 AM UTC 24 |
39997542984 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access.2005784611 |
|
|
Sep 09 08:32:21 AM UTC 24 |
Sep 09 08:32:34 AM UTC 24 |
448343800 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.3705783208 |
|
|
Sep 09 08:19:10 AM UTC 24 |
Sep 09 08:32:42 AM UTC 24 |
57768333598 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.61475279 |
|
|
Sep 09 08:32:35 AM UTC 24 |
Sep 09 08:32:49 AM UTC 24 |
2697509653 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_regwen.176325074 |
|
|
Sep 09 08:21:01 AM UTC 24 |
Sep 09 08:32:54 AM UTC 24 |
27861033085 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.1615711731 |
|
|
Sep 09 08:26:29 AM UTC 24 |
Sep 09 08:32:59 AM UTC 24 |
55282951087 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.3615986500 |
|
|
Sep 09 08:32:43 AM UTC 24 |
Sep 09 08:33:05 AM UTC 24 |
736678587 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.1154657172 |
|
|
Sep 09 08:25:56 AM UTC 24 |
Sep 09 08:33:09 AM UTC 24 |
11369342313 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.3373333271 |
|
|
Sep 09 08:31:18 AM UTC 24 |
Sep 09 08:33:09 AM UTC 24 |
1578458714 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.2836172588 |
|
|
Sep 09 08:33:10 AM UTC 24 |
Sep 09 08:33:17 AM UTC 24 |
356817056 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.2140285088 |
|
|
Sep 09 08:27:14 AM UTC 24 |
Sep 09 08:33:36 AM UTC 24 |
8753442577 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.729940951 |
|
|
Sep 09 08:32:50 AM UTC 24 |
Sep 09 08:33:40 AM UTC 24 |
8767838176 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_bijection.1235078819 |
|
|
Sep 09 08:04:16 AM UTC 24 |
Sep 09 08:33:50 AM UTC 24 |
89906765589 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_alert_test.2553356207 |
|
|
Sep 09 08:33:51 AM UTC 24 |
Sep 09 08:33:53 AM UTC 24 |
41445286 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.586002399 |
|
|
Sep 09 08:28:06 AM UTC 24 |
Sep 09 08:33:53 AM UTC 24 |
60863808878 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.1492234369 |
|
|
Sep 09 08:33:37 AM UTC 24 |
Sep 09 08:33:54 AM UTC 24 |
200139628 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.3953818620 |
|
|
Sep 09 08:24:09 AM UTC 24 |
Sep 09 08:34:06 AM UTC 24 |
33944451285 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.3330927235 |
|
|
Sep 09 08:30:33 AM UTC 24 |
Sep 09 08:34:38 AM UTC 24 |
133988493196 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.2304939763 |
|
|
Sep 09 08:30:00 AM UTC 24 |
Sep 09 08:34:40 AM UTC 24 |
5559390182 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access.629212123 |
|
|
Sep 09 08:34:35 AM UTC 24 |
Sep 09 08:34:49 AM UTC 24 |
2613552004 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.1008760293 |
|
|
Sep 09 08:30:53 AM UTC 24 |
Sep 09 08:34:50 AM UTC 24 |
45060562007 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.1842753099 |
|
|
Sep 09 08:30:58 AM UTC 24 |
Sep 09 08:34:54 AM UTC 24 |
10453853142 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_bijection.3666970065 |
|
|
Sep 09 08:18:13 AM UTC 24 |
Sep 09 08:35:00 AM UTC 24 |
14031622116 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.3805150269 |
|
|
Sep 09 08:34:41 AM UTC 24 |
Sep 09 08:35:10 AM UTC 24 |
754561994 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.3222006282 |
|
|
Sep 09 08:28:32 AM UTC 24 |
Sep 09 08:35:17 AM UTC 24 |
55271458439 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.1319861305 |
|
|
Sep 09 08:35:17 AM UTC 24 |
Sep 09 08:35:24 AM UTC 24 |
1409786697 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_executable.1218482450 |
|
|
Sep 09 08:30:47 AM UTC 24 |
Sep 09 08:35:27 AM UTC 24 |
5342191625 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_executable.2442574936 |
|
|
Sep 09 08:19:19 AM UTC 24 |
Sep 09 08:35:29 AM UTC 24 |
45385143532 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.489615600 |
|
|
Sep 09 08:25:14 AM UTC 24 |
Sep 09 08:35:35 AM UTC 24 |
15805045632 ps |
| T49 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.3768478288 |
|
|
Sep 09 08:35:31 AM UTC 24 |
Sep 09 08:35:58 AM UTC 24 |
4921893690 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_alert_test.1934833044 |
|
|
Sep 09 08:35:59 AM UTC 24 |
Sep 09 08:36:01 AM UTC 24 |
13650967 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.1821591055 |
|
|
Sep 09 08:34:50 AM UTC 24 |
Sep 09 08:36:13 AM UTC 24 |
777950280 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_smoke.124412370 |
|
|
Sep 09 08:36:02 AM UTC 24 |
Sep 09 08:36:14 AM UTC 24 |
3821837746 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.2498043542 |
|
|
Sep 09 08:21:23 AM UTC 24 |
Sep 09 08:36:16 AM UTC 24 |
36464270014 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.1849644674 |
|
|
Sep 09 08:30:16 AM UTC 24 |
Sep 09 08:36:23 AM UTC 24 |
62278459657 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_executable.1481960934 |
|
|
Sep 09 08:17:23 AM UTC 24 |
Sep 09 08:36:29 AM UTC 24 |
22339685213 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.1536196243 |
|
|
Sep 09 08:34:51 AM UTC 24 |
Sep 09 08:36:30 AM UTC 24 |
37765477010 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.3745318032 |
|
|
Sep 09 08:33:18 AM UTC 24 |
Sep 09 08:36:33 AM UTC 24 |
4994485594 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.32754984 |
|
|
Sep 09 08:36:31 AM UTC 24 |
Sep 09 08:36:42 AM UTC 24 |
691683770 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.3990007628 |
|
|
Sep 09 08:31:46 AM UTC 24 |
Sep 09 08:36:45 AM UTC 24 |
15166736781 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_executable.2798928505 |
|
|
Sep 09 08:21:01 AM UTC 24 |
Sep 09 08:36:46 AM UTC 24 |
20066297341 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.721053886 |
|
|
Sep 09 08:35:29 AM UTC 24 |
Sep 09 08:36:58 AM UTC 24 |
9486821710 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access.4126455180 |
|
|
Sep 09 08:36:23 AM UTC 24 |
Sep 09 08:36:59 AM UTC 24 |
6585263108 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.443080740 |
|
|
Sep 09 08:36:35 AM UTC 24 |
Sep 09 08:37:00 AM UTC 24 |
950215305 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.868851124 |
|
|
Sep 09 08:37:00 AM UTC 24 |
Sep 09 08:37:07 AM UTC 24 |
681804249 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all.1902957294 |
|
|
Sep 09 08:04:42 AM UTC 24 |
Sep 09 08:37:27 AM UTC 24 |
37177257824 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.205933558 |
|
|
Sep 09 08:32:06 AM UTC 24 |
Sep 09 08:38:03 AM UTC 24 |
21432457786 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.3009241809 |
|
|
Sep 09 08:37:28 AM UTC 24 |
Sep 09 08:38:09 AM UTC 24 |
972683364 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_alert_test.829733757 |
|
|
Sep 09 08:38:10 AM UTC 24 |
Sep 09 08:38:12 AM UTC 24 |
20576506 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.4202804145 |
|
|
Sep 09 08:33:10 AM UTC 24 |
Sep 09 08:38:15 AM UTC 24 |
18766822834 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_smoke.2373678466 |
|
|
Sep 09 08:38:13 AM UTC 24 |
Sep 09 08:38:19 AM UTC 24 |
769802214 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.3166817589 |
|
|
Sep 09 08:37:07 AM UTC 24 |
Sep 09 08:38:30 AM UTC 24 |
9854078385 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.2405356924 |
|
|
Sep 09 08:36:43 AM UTC 24 |
Sep 09 08:38:33 AM UTC 24 |
74984866785 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_executable.3593479228 |
|
|
Sep 09 08:24:12 AM UTC 24 |
Sep 09 08:38:43 AM UTC 24 |
15161689872 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access.2177361193 |
|
|
Sep 09 08:38:35 AM UTC 24 |
Sep 09 08:38:46 AM UTC 24 |
5660674848 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.4169268110 |
|
|
Sep 09 08:38:47 AM UTC 24 |
Sep 09 08:39:01 AM UTC 24 |
3968401213 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.4161371944 |
|
|
Sep 09 08:32:55 AM UTC 24 |
Sep 09 08:39:06 AM UTC 24 |
18662634153 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.49163361 |
|
|
Sep 09 08:34:07 AM UTC 24 |
Sep 09 08:39:17 AM UTC 24 |
8904165181 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_regwen.3443376033 |
|
|
Sep 09 08:26:16 AM UTC 24 |
Sep 09 08:39:19 AM UTC 24 |
11404922219 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.229356705 |
|
|
Sep 09 08:27:08 AM UTC 24 |
Sep 09 08:39:23 AM UTC 24 |
10615695198 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.4064596041 |
|
|
Sep 09 08:36:17 AM UTC 24 |
Sep 09 08:39:46 AM UTC 24 |
6728816178 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.530367391 |
|
|
Sep 09 08:39:47 AM UTC 24 |
Sep 09 08:39:53 AM UTC 24 |
364115173 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.3941755847 |
|
|
Sep 09 08:39:02 AM UTC 24 |
Sep 09 08:40:03 AM UTC 24 |
1602587987 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_bijection.371619619 |
|
|
Sep 09 08:11:20 AM UTC 24 |
Sep 09 08:40:32 AM UTC 24 |
110622473071 ps |
| T159 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_regwen.2360433228 |
|
|
Sep 09 08:24:13 AM UTC 24 |
Sep 09 08:40:34 AM UTC 24 |
15908288857 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.2252874030 |
|
|
Sep 09 08:39:07 AM UTC 24 |
Sep 09 08:40:37 AM UTC 24 |
10034382899 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_alert_test.1765299295 |
|
|
Sep 09 08:40:38 AM UTC 24 |
Sep 09 08:40:40 AM UTC 24 |
135961682 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_smoke.2816639337 |
|
|
Sep 09 08:40:41 AM UTC 24 |
Sep 09 08:40:48 AM UTC 24 |
1392565137 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.1360280087 |
|
|
Sep 09 08:37:01 AM UTC 24 |
Sep 09 08:41:01 AM UTC 24 |
4067788876 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.1005357363 |
|
|
Sep 09 08:40:33 AM UTC 24 |
Sep 09 08:41:09 AM UTC 24 |
3879675661 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.218109421 |
|
|
Sep 09 08:32:33 AM UTC 24 |
Sep 09 08:41:41 AM UTC 24 |
15477884248 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.533515180 |
|
|
Sep 09 08:40:04 AM UTC 24 |
Sep 09 08:41:56 AM UTC 24 |
2714390041 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access.4274573972 |
|
|
Sep 09 08:41:42 AM UTC 24 |
Sep 09 08:42:00 AM UTC 24 |
2622086621 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_bijection.3024885257 |
|
|
Sep 09 08:03:45 AM UTC 24 |
Sep 09 08:42:06 AM UTC 24 |
387030808840 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.3763439050 |
|
|
Sep 09 08:42:01 AM UTC 24 |
Sep 09 08:42:13 AM UTC 24 |
1376884740 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.1358415726 |
|
|
Sep 09 08:34:55 AM UTC 24 |
Sep 09 08:42:10 AM UTC 24 |
41895516996 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_executable.719560016 |
|
|
Sep 09 08:39:19 AM UTC 24 |
Sep 09 08:42:32 AM UTC 24 |
3712065830 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.837526956 |
|
|
Sep 09 08:35:24 AM UTC 24 |
Sep 09 08:42:37 AM UTC 24 |
78144948275 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.3214490106 |
|
|
Sep 09 08:42:06 AM UTC 24 |
Sep 09 08:42:52 AM UTC 24 |
1479339122 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.597105352 |
|
|
Sep 09 08:42:54 AM UTC 24 |
Sep 09 08:43:00 AM UTC 24 |
369716925 ps |
| T160 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_executable.4238058969 |
|
|
Sep 09 08:35:01 AM UTC 24 |
Sep 09 08:43:05 AM UTC 24 |
16463623213 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_bijection.1945749026 |
|
|
Sep 09 08:03:55 AM UTC 24 |
Sep 09 08:43:09 AM UTC 24 |
66224216972 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.3535355720 |
|
|
Sep 09 08:34:39 AM UTC 24 |
Sep 09 08:43:21 AM UTC 24 |
17226748791 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.2338235005 |
|
|
Sep 09 08:42:11 AM UTC 24 |
Sep 09 08:43:29 AM UTC 24 |
10500007143 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_alert_test.2565101136 |
|
|
Sep 09 08:43:30 AM UTC 24 |
Sep 09 08:43:32 AM UTC 24 |
24055252 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_regwen.4174092251 |
|
|
Sep 09 08:30:50 AM UTC 24 |
Sep 09 08:43:35 AM UTC 24 |
25727552940 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.1817354116 |
|
|
Sep 09 08:30:34 AM UTC 24 |
Sep 09 08:43:36 AM UTC 24 |
15787501686 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.1663408797 |
|
|
Sep 09 08:38:30 AM UTC 24 |
Sep 09 08:43:44 AM UTC 24 |
7990016922 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_smoke.1610447787 |
|
|
Sep 09 08:43:33 AM UTC 24 |
Sep 09 08:44:04 AM UTC 24 |
1684681921 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_bijection.3699422827 |
|
|
Sep 09 08:29:58 AM UTC 24 |
Sep 09 08:44:06 AM UTC 24 |
50067701809 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.2112685590 |
|
|
Sep 09 08:43:10 AM UTC 24 |
Sep 09 08:44:17 AM UTC 24 |
5330637563 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.1807217259 |
|
|
Sep 09 08:29:57 AM UTC 24 |
Sep 09 08:44:40 AM UTC 24 |
71800651862 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access.1991849371 |
|
|
Sep 09 08:44:05 AM UTC 24 |
Sep 09 08:44:44 AM UTC 24 |
463805023 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.853092319 |
|
|
Sep 09 08:44:18 AM UTC 24 |
Sep 09 08:45:00 AM UTC 24 |
763241280 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.216524267 |
|
|
Sep 09 08:39:54 AM UTC 24 |
Sep 09 08:45:15 AM UTC 24 |
18678468251 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_regwen.98720354 |
|
|
Sep 09 08:39:24 AM UTC 24 |
Sep 09 08:45:22 AM UTC 24 |
14047181888 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.2390549396 |
|
|
Sep 09 08:41:09 AM UTC 24 |
Sep 09 08:45:24 AM UTC 24 |
2801071605 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.224456286 |
|
|
Sep 09 08:36:29 AM UTC 24 |
Sep 09 08:45:28 AM UTC 24 |
19125583884 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.3636338680 |
|
|
Sep 09 08:44:40 AM UTC 24 |
Sep 09 08:45:30 AM UTC 24 |
766916150 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.3615369424 |
|
|
Sep 09 08:45:25 AM UTC 24 |
Sep 09 08:45:31 AM UTC 24 |
358960694 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.2278084596 |
|
|
Sep 09 08:43:06 AM UTC 24 |
Sep 09 08:45:46 AM UTC 24 |
24291538338 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.172284563 |
|
|
Sep 09 08:45:01 AM UTC 24 |
Sep 09 08:46:26 AM UTC 24 |
11412638618 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_alert_test.1088166065 |
|
|
Sep 09 08:46:26 AM UTC 24 |
Sep 09 08:46:28 AM UTC 24 |
12100484 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.4082896481 |
|
|
Sep 09 08:44:45 AM UTC 24 |
Sep 09 08:46:33 AM UTC 24 |
36286413888 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.200796419 |
|
|
Sep 09 08:38:45 AM UTC 24 |
Sep 09 08:46:42 AM UTC 24 |
25779092798 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_smoke.3370383552 |
|
|
Sep 09 08:46:29 AM UTC 24 |
Sep 09 08:46:49 AM UTC 24 |
819281516 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.4141733600 |
|
|
Sep 09 08:45:31 AM UTC 24 |
Sep 09 08:46:52 AM UTC 24 |
1021941430 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_regwen.4151667948 |
|
|
Sep 09 08:36:59 AM UTC 24 |
Sep 09 08:47:25 AM UTC 24 |
17533517485 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_regwen.2472592140 |
|
|
Sep 09 08:33:06 AM UTC 24 |
Sep 09 08:47:25 AM UTC 24 |
13952783530 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access.2554172753 |
|
|
Sep 09 08:46:53 AM UTC 24 |
Sep 09 08:47:25 AM UTC 24 |
5454981893 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.3529914354 |
|
|
Sep 09 08:45:32 AM UTC 24 |
Sep 09 08:47:34 AM UTC 24 |
1557296646 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.3694015566 |
|
|
Sep 09 08:41:57 AM UTC 24 |
Sep 09 08:48:17 AM UTC 24 |
6467603137 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.2645049040 |
|
|
Sep 09 08:47:26 AM UTC 24 |
Sep 09 08:48:22 AM UTC 24 |
1509560598 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_bijection.904192339 |
|
|
Sep 09 08:12:26 AM UTC 24 |
Sep 09 08:48:26 AM UTC 24 |
128049640916 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.3462978033 |
|
|
Sep 09 08:44:07 AM UTC 24 |
Sep 09 08:48:39 AM UTC 24 |
5866398118 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.2658327333 |
|
|
Sep 09 08:48:39 AM UTC 24 |
Sep 09 08:48:44 AM UTC 24 |
349376374 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.2064161984 |
|
|
Sep 09 08:45:29 AM UTC 24 |
Sep 09 08:48:52 AM UTC 24 |
5065079558 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.2643048965 |
|
|
Sep 09 08:47:26 AM UTC 24 |
Sep 09 08:49:09 AM UTC 24 |
1556918851 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.1540826949 |
|
|
Sep 09 08:46:34 AM UTC 24 |
Sep 09 08:49:15 AM UTC 24 |
2363350715 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.979694895 |
|
|
Sep 09 08:36:14 AM UTC 24 |
Sep 09 08:49:32 AM UTC 24 |
8176417850 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_alert_test.71673342 |
|
|
Sep 09 08:49:33 AM UTC 24 |
Sep 09 08:49:35 AM UTC 24 |
19345931 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.4197718861 |
|
|
Sep 09 08:43:01 AM UTC 24 |
Sep 09 08:49:48 AM UTC 24 |
5416841126 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.924585055 |
|
|
Sep 09 08:47:34 AM UTC 24 |
Sep 09 08:49:54 AM UTC 24 |
26711927856 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.3991020621 |
|
|
Sep 09 08:49:10 AM UTC 24 |
Sep 09 08:49:58 AM UTC 24 |
2866881394 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.4063838899 |
|
|
Sep 09 08:43:45 AM UTC 24 |
Sep 09 08:50:00 AM UTC 24 |
11864255860 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.2491177508 |
|
|
Sep 09 08:38:15 AM UTC 24 |
Sep 09 08:50:11 AM UTC 24 |
66893382285 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_bijection.2130303833 |
|
|
Sep 09 08:14:15 AM UTC 24 |
Sep 09 08:50:12 AM UTC 24 |
331632275228 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.2469851739 |
|
|
Sep 09 08:48:53 AM UTC 24 |
Sep 09 08:50:18 AM UTC 24 |
1015424225 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_smoke.2135502752 |
|
|
Sep 09 08:49:36 AM UTC 24 |
Sep 09 08:50:22 AM UTC 24 |
2995708543 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access.792747299 |
|
|
Sep 09 08:50:00 AM UTC 24 |
Sep 09 08:50:29 AM UTC 24 |
2940733048 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_regwen.86498721 |
|
|
Sep 09 08:42:38 AM UTC 24 |
Sep 09 08:50:29 AM UTC 24 |
14595172565 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.326882739 |
|
|
Sep 09 08:49:49 AM UTC 24 |
Sep 09 08:50:57 AM UTC 24 |
4621553110 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.685540150 |
|
|
Sep 09 08:50:12 AM UTC 24 |
Sep 09 08:51:10 AM UTC 24 |
756362887 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_executable.2771370353 |
|
|
Sep 09 08:36:47 AM UTC 24 |
Sep 09 08:51:19 AM UTC 24 |
22469264011 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.484485187 |
|
|
Sep 09 08:51:11 AM UTC 24 |
Sep 09 08:51:19 AM UTC 24 |
360470199 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.3867585495 |
|
|
Sep 09 08:50:30 AM UTC 24 |
Sep 09 08:51:28 AM UTC 24 |
1730095706 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.1315858383 |
|
|
Sep 09 08:48:44 AM UTC 24 |
Sep 09 08:51:40 AM UTC 24 |
2635859213 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all.888896352 |
|
|
Sep 09 08:03:52 AM UTC 24 |
Sep 09 08:51:58 AM UTC 24 |
59810735433 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.1303279681 |
|
|
Sep 09 08:46:50 AM UTC 24 |
Sep 09 08:52:00 AM UTC 24 |
28546346137 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_alert_test.1567359525 |
|
|
Sep 09 08:51:59 AM UTC 24 |
Sep 09 08:52:01 AM UTC 24 |
38149143 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_executable.2069462775 |
|
|
Sep 09 08:32:59 AM UTC 24 |
Sep 09 08:52:04 AM UTC 24 |
86219216074 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.2879164164 |
|
|
Sep 09 08:40:49 AM UTC 24 |
Sep 09 08:52:05 AM UTC 24 |
15397279040 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.2801966610 |
|
|
Sep 09 08:50:18 AM UTC 24 |
Sep 09 08:52:10 AM UTC 24 |
820261008 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_bijection.3606315561 |
|
|
Sep 09 08:16:38 AM UTC 24 |
Sep 09 08:52:20 AM UTC 24 |
29350519152 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.3856332639 |
|
|
Sep 09 08:50:24 AM UTC 24 |
Sep 09 08:52:22 AM UTC 24 |
12078091987 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access.494718891 |
|
|
Sep 09 08:52:11 AM UTC 24 |
Sep 09 08:52:26 AM UTC 24 |
2937148199 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.1698743989 |
|
|
Sep 09 08:51:28 AM UTC 24 |
Sep 09 08:52:27 AM UTC 24 |
8383079802 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_smoke.2827863905 |
|
|
Sep 09 08:52:01 AM UTC 24 |
Sep 09 08:52:30 AM UTC 24 |
5396833159 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_regwen.2197540819 |
|
|
Sep 09 08:45:23 AM UTC 24 |
Sep 09 08:52:53 AM UTC 24 |
33481665482 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.1038635984 |
|
|
Sep 09 08:51:20 AM UTC 24 |
Sep 09 08:53:07 AM UTC 24 |
2542052239 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.204172042 |
|
|
Sep 09 08:53:20 AM UTC 24 |
Sep 09 08:53:27 AM UTC 24 |
775051225 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.3369305634 |
|
|
Sep 09 08:49:59 AM UTC 24 |
Sep 09 08:53:19 AM UTC 24 |
8089469711 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.2005361474 |
|
|
Sep 09 08:52:22 AM UTC 24 |
Sep 09 08:53:32 AM UTC 24 |
1463977589 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.900634805 |
|
|
Sep 09 08:33:54 AM UTC 24 |
Sep 09 08:53:40 AM UTC 24 |
14109993869 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.2287480238 |
|
|
Sep 09 08:39:17 AM UTC 24 |
Sep 09 08:53:57 AM UTC 24 |
147369452397 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.2263723992 |
|
|
Sep 09 08:36:46 AM UTC 24 |
Sep 09 08:53:57 AM UTC 24 |
15023290302 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.2231202742 |
|
|
Sep 09 08:52:29 AM UTC 24 |
Sep 09 08:53:59 AM UTC 24 |
11948324619 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_alert_test.3134159662 |
|
|
Sep 09 08:53:59 AM UTC 24 |
Sep 09 08:54:01 AM UTC 24 |
22336151 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.1994008337 |
|
|
Sep 09 08:52:27 AM UTC 24 |
Sep 09 08:54:04 AM UTC 24 |
3723945262 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.1391818688 |
|
|
Sep 09 08:53:41 AM UTC 24 |
Sep 09 08:54:07 AM UTC 24 |
3064955983 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_regwen.2218073261 |
|
|
Sep 09 08:48:27 AM UTC 24 |
Sep 09 08:54:22 AM UTC 24 |
13614533847 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_regwen.3126016557 |
|
|
Sep 09 08:35:10 AM UTC 24 |
Sep 09 08:54:27 AM UTC 24 |
51001865785 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_executable.3062886768 |
|
|
Sep 09 08:42:33 AM UTC 24 |
Sep 09 08:54:35 AM UTC 24 |
69534120192 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_smoke.3355917715 |
|
|
Sep 09 08:54:00 AM UTC 24 |
Sep 09 08:54:46 AM UTC 24 |
4268267934 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access.1040987720 |
|
|
Sep 09 08:54:22 AM UTC 24 |
Sep 09 08:54:48 AM UTC 24 |
1586654562 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.1483176785 |
|
|
Sep 09 08:42:14 AM UTC 24 |
Sep 09 08:55:06 AM UTC 24 |
87925286238 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.1352235407 |
|
|
Sep 09 08:47:25 AM UTC 24 |
Sep 09 08:55:08 AM UTC 24 |
90845472285 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.1461911722 |
|
|
Sep 09 08:54:36 AM UTC 24 |
Sep 09 08:55:31 AM UTC 24 |
740467997 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all.3147750037 |
|
|
Sep 09 08:33:41 AM UTC 24 |
Sep 09 08:55:33 AM UTC 24 |
32896565371 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all.154462937 |
|
|
Sep 09 08:19:53 AM UTC 24 |
Sep 09 08:55:37 AM UTC 24 |
315301525486 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.4007790544 |
|
|
Sep 09 08:55:34 AM UTC 24 |
Sep 09 08:55:42 AM UTC 24 |
679051430 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.2076292969 |
|
|
Sep 09 08:54:46 AM UTC 24 |
Sep 09 08:55:47 AM UTC 24 |
2676093043 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.1315028230 |
|
|
Sep 09 08:52:06 AM UTC 24 |
Sep 09 08:56:14 AM UTC 24 |
3191124872 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all.1159154091 |
|
|
Sep 09 08:16:02 AM UTC 24 |
Sep 09 08:56:15 AM UTC 24 |
408475109735 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.3778776758 |
|
|
Sep 09 08:53:27 AM UTC 24 |
Sep 09 08:56:16 AM UTC 24 |
43123777993 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.1653374338 |
|
|
Sep 09 08:54:49 AM UTC 24 |
Sep 09 08:56:18 AM UTC 24 |
22871280240 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_alert_test.1894696815 |
|
|
Sep 09 08:56:16 AM UTC 24 |
Sep 09 08:56:19 AM UTC 24 |
13513379 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_regwen.3601120437 |
|
|
Sep 09 08:50:58 AM UTC 24 |
Sep 09 08:56:22 AM UTC 24 |
26116628869 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_smoke.3574568058 |
|
|
Sep 09 08:56:17 AM UTC 24 |
Sep 09 08:56:32 AM UTC 24 |
1814231862 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.4029352403 |
|
|
Sep 09 08:50:12 AM UTC 24 |
Sep 09 08:56:42 AM UTC 24 |
43808056721 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.1336135951 |
|
|
Sep 09 08:55:42 AM UTC 24 |
Sep 09 08:56:51 AM UTC 24 |
2849874282 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_bijection.1186498058 |
|
|
Sep 09 08:24:49 AM UTC 24 |
Sep 09 08:56:52 AM UTC 24 |
104750586934 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access.1944259933 |
|
|
Sep 09 08:56:33 AM UTC 24 |
Sep 09 08:56:52 AM UTC 24 |
1533617874 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.2019676441 |
|
|
Sep 09 08:51:19 AM UTC 24 |
Sep 09 08:56:56 AM UTC 24 |
19700175029 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.472000388 |
|
|
Sep 09 08:56:52 AM UTC 24 |
Sep 09 08:57:05 AM UTC 24 |
1375477271 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.619980504 |
|
|
Sep 09 08:53:33 AM UTC 24 |
Sep 09 08:57:07 AM UTC 24 |
20449774440 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.3088112633 |
|
|
Sep 09 08:52:02 AM UTC 24 |
Sep 09 08:57:16 AM UTC 24 |
21563650359 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.136746607 |
|
|
Sep 09 08:57:17 AM UTC 24 |
Sep 09 08:57:24 AM UTC 24 |
1408982461 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1385765913 |
|
|
Sep 09 08:55:47 AM UTC 24 |
Sep 09 08:57:31 AM UTC 24 |
9472312716 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.4286057200 |
|
|
Sep 09 08:56:52 AM UTC 24 |
Sep 09 08:58:22 AM UTC 24 |
788155931 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.297979620 |
|
|
Sep 09 08:56:52 AM UTC 24 |
Sep 09 08:58:28 AM UTC 24 |
8729738392 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.319659805 |
|
|
Sep 09 08:54:08 AM UTC 24 |
Sep 09 08:58:31 AM UTC 24 |
9409437876 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_regwen.2833819265 |
|
|
Sep 09 08:57:09 AM UTC 24 |
Sep 09 08:58:33 AM UTC 24 |
5707486299 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_alert_test.1386655849 |
|
|
Sep 09 08:58:31 AM UTC 24 |
Sep 09 08:58:34 AM UTC 24 |
28074619 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.4139534721 |
|
|
Sep 09 08:55:38 AM UTC 24 |
Sep 09 08:58:34 AM UTC 24 |
20686282081 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.4268467326 |
|
|
Sep 09 08:58:23 AM UTC 24 |
Sep 09 08:58:38 AM UTC 24 |
329650299 ps |