| T556 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_smoke.1322713030 |
|
|
Sep 09 08:58:35 AM UTC 24 |
Sep 09 08:59:00 AM UTC 24 |
2612469376 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.3260570205 |
|
|
Sep 09 08:56:23 AM UTC 24 |
Sep 09 08:59:23 AM UTC 24 |
3037957786 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access.130174071 |
|
|
Sep 09 08:59:01 AM UTC 24 |
Sep 09 09:00:13 AM UTC 24 |
2729420578 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_bijection.3286437881 |
|
|
Sep 09 08:20:13 AM UTC 24 |
Sep 09 09:00:34 AM UTC 24 |
133527573610 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.1746559105 |
|
|
Sep 09 09:00:14 AM UTC 24 |
Sep 09 09:00:53 AM UTC 24 |
2902390727 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.1595024537 |
|
|
Sep 09 08:57:32 AM UTC 24 |
Sep 09 09:01:02 AM UTC 24 |
4567216744 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.4099436776 |
|
|
Sep 09 08:55:08 AM UTC 24 |
Sep 09 09:01:05 AM UTC 24 |
21709843238 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.3903120321 |
|
|
Sep 09 08:52:31 AM UTC 24 |
Sep 09 09:01:30 AM UTC 24 |
28615890696 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.295398636 |
|
|
Sep 09 08:56:43 AM UTC 24 |
Sep 09 09:01:34 AM UTC 24 |
23206018326 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.1015817160 |
|
|
Sep 09 09:01:34 AM UTC 24 |
Sep 09 09:01:42 AM UTC 24 |
1873050534 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.1883573326 |
|
|
Sep 09 08:54:28 AM UTC 24 |
Sep 09 09:02:02 AM UTC 24 |
17734447193 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_regwen.1673867468 |
|
|
Sep 09 08:55:32 AM UTC 24 |
Sep 09 09:02:06 AM UTC 24 |
2686701878 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.128023749 |
|
|
Sep 09 09:00:54 AM UTC 24 |
Sep 09 09:02:07 AM UTC 24 |
41600599538 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.95192073 |
|
|
Sep 09 09:00:35 AM UTC 24 |
Sep 09 09:02:12 AM UTC 24 |
2839168805 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_alert_test.2933087887 |
|
|
Sep 09 09:02:13 AM UTC 24 |
Sep 09 09:02:15 AM UTC 24 |
13502295 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_smoke.1490589603 |
|
|
Sep 09 09:02:16 AM UTC 24 |
Sep 09 09:02:38 AM UTC 24 |
523282510 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.2035246862 |
|
|
Sep 09 08:52:21 AM UTC 24 |
Sep 09 09:02:39 AM UTC 24 |
98220571220 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_bijection.151067424 |
|
|
Sep 09 08:31:55 AM UTC 24 |
Sep 09 09:02:42 AM UTC 24 |
264147991013 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.197909020 |
|
|
Sep 09 08:54:02 AM UTC 24 |
Sep 09 09:02:54 AM UTC 24 |
10236089961 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.410303357 |
|
|
Sep 09 08:57:25 AM UTC 24 |
Sep 09 09:03:11 AM UTC 24 |
28245301396 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_executable.2499557800 |
|
|
Sep 09 08:45:15 AM UTC 24 |
Sep 09 09:03:19 AM UTC 24 |
19233857117 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access.3420727789 |
|
|
Sep 09 09:02:55 AM UTC 24 |
Sep 09 09:03:35 AM UTC 24 |
1663272802 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.3829263508 |
|
|
Sep 09 08:58:39 AM UTC 24 |
Sep 09 09:03:39 AM UTC 24 |
4028081326 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_executable.45445904 |
|
|
Sep 09 08:57:06 AM UTC 24 |
Sep 09 09:03:44 AM UTC 24 |
8537674364 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.137934318 |
|
|
Sep 09 09:02:07 AM UTC 24 |
Sep 09 09:03:59 AM UTC 24 |
4319679932 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all.3537194487 |
|
|
Sep 09 08:03:44 AM UTC 24 |
Sep 09 09:04:05 AM UTC 24 |
123559756157 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_bijection.3678663303 |
|
|
Sep 09 08:43:37 AM UTC 24 |
Sep 09 09:04:07 AM UTC 24 |
70574434073 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.164803511 |
|
|
Sep 09 09:03:20 AM UTC 24 |
Sep 09 09:04:13 AM UTC 24 |
756444287 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.1117189878 |
|
|
Sep 09 09:04:08 AM UTC 24 |
Sep 09 09:04:15 AM UTC 24 |
1880146477 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_executable.3954301576 |
|
|
Sep 09 08:52:54 AM UTC 24 |
Sep 09 09:04:27 AM UTC 24 |
8373285604 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.1565717028 |
|
|
Sep 09 09:03:36 AM UTC 24 |
Sep 09 09:04:42 AM UTC 24 |
794925940 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.506702908 |
|
|
Sep 09 09:02:03 AM UTC 24 |
Sep 09 09:04:58 AM UTC 24 |
5470426498 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_alert_test.2015333807 |
|
|
Sep 09 09:04:58 AM UTC 24 |
Sep 09 09:05:00 AM UTC 24 |
12459668 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.2151272700 |
|
|
Sep 09 09:03:40 AM UTC 24 |
Sep 09 09:05:16 AM UTC 24 |
38027882474 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_regwen.3671434135 |
|
|
Sep 09 09:01:31 AM UTC 24 |
Sep 09 09:05:22 AM UTC 24 |
6756810364 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.1946392605 |
|
|
Sep 09 09:04:29 AM UTC 24 |
Sep 09 09:05:27 AM UTC 24 |
991723254 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_smoke.3517903795 |
|
|
Sep 09 09:05:01 AM UTC 24 |
Sep 09 09:05:39 AM UTC 24 |
1119952631 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.3989497544 |
|
|
Sep 09 08:59:23 AM UTC 24 |
Sep 09 09:05:47 AM UTC 24 |
13594942732 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.4224804638 |
|
|
Sep 09 09:04:16 AM UTC 24 |
Sep 09 09:05:48 AM UTC 24 |
3816425393 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_executable.2213371978 |
|
|
Sep 09 08:48:23 AM UTC 24 |
Sep 09 09:05:56 AM UTC 24 |
16177662166 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access.1969065523 |
|
|
Sep 09 09:05:40 AM UTC 24 |
Sep 09 09:06:17 AM UTC 24 |
987991725 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.4265018459 |
|
|
Sep 09 09:05:49 AM UTC 24 |
Sep 09 09:06:39 AM UTC 24 |
14490885034 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_bijection.887505067 |
|
|
Sep 09 08:38:20 AM UTC 24 |
Sep 09 09:06:50 AM UTC 24 |
90505252281 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all.3740617569 |
|
|
Sep 09 08:17:47 AM UTC 24 |
Sep 09 09:07:01 AM UTC 24 |
400678071595 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.1063091894 |
|
|
Sep 09 09:05:57 AM UTC 24 |
Sep 09 09:07:20 AM UTC 24 |
3651980166 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.2535789644 |
|
|
Sep 09 08:56:56 AM UTC 24 |
Sep 09 09:07:26 AM UTC 24 |
23489915502 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.3869211840 |
|
|
Sep 09 09:07:21 AM UTC 24 |
Sep 09 09:07:28 AM UTC 24 |
1365487474 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.2533672184 |
|
|
Sep 09 09:06:18 AM UTC 24 |
Sep 09 09:07:36 AM UTC 24 |
34470927069 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all.3350000271 |
|
|
Sep 09 08:03:49 AM UTC 24 |
Sep 09 09:07:46 AM UTC 24 |
497811499203 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_regwen.3525914392 |
|
|
Sep 09 08:53:08 AM UTC 24 |
Sep 09 09:07:48 AM UTC 24 |
26649942406 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.1722880398 |
|
|
Sep 09 09:01:42 AM UTC 24 |
Sep 09 09:07:49 AM UTC 24 |
20920584025 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_alert_test.3006284262 |
|
|
Sep 09 09:07:49 AM UTC 24 |
Sep 09 09:07:51 AM UTC 24 |
12468279 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_smoke.2924926570 |
|
|
Sep 09 09:07:49 AM UTC 24 |
Sep 09 09:07:59 AM UTC 24 |
3264951086 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.3897404847 |
|
|
Sep 09 09:02:42 AM UTC 24 |
Sep 09 09:08:24 AM UTC 24 |
10555573099 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.321891078 |
|
|
Sep 09 09:04:14 AM UTC 24 |
Sep 09 09:08:24 AM UTC 24 |
41332996572 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3125826037 |
|
|
Sep 09 09:07:37 AM UTC 24 |
Sep 09 09:08:32 AM UTC 24 |
1608462020 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access.2794737644 |
|
|
Sep 09 09:08:25 AM UTC 24 |
Sep 09 09:08:40 AM UTC 24 |
2333922908 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.3186870136 |
|
|
Sep 09 09:08:41 AM UTC 24 |
Sep 09 09:08:54 AM UTC 24 |
5543298441 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.50623994 |
|
|
Sep 09 09:03:44 AM UTC 24 |
Sep 09 09:09:11 AM UTC 24 |
7104322516 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_executable.1629868834 |
|
|
Sep 09 08:50:30 AM UTC 24 |
Sep 09 09:09:51 AM UTC 24 |
38848858022 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all.1245771894 |
|
|
Sep 09 08:22:53 AM UTC 24 |
Sep 09 09:09:53 AM UTC 24 |
36037938883 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.3863321686 |
|
|
Sep 09 08:48:18 AM UTC 24 |
Sep 09 09:10:09 AM UTC 24 |
64556487134 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.1181887244 |
|
|
Sep 09 09:08:55 AM UTC 24 |
Sep 09 09:10:12 AM UTC 24 |
3109388879 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.638975515 |
|
|
Sep 09 09:05:29 AM UTC 24 |
Sep 09 09:10:13 AM UTC 24 |
22210242957 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.709406775 |
|
|
Sep 09 09:07:29 AM UTC 24 |
Sep 09 09:10:20 AM UTC 24 |
10036059124 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.3280014439 |
|
|
Sep 09 09:10:13 AM UTC 24 |
Sep 09 09:10:21 AM UTC 24 |
1343799080 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_bijection.3142836200 |
|
|
Sep 09 08:49:55 AM UTC 24 |
Sep 09 09:10:27 AM UTC 24 |
64300521063 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.2388737808 |
|
|
Sep 09 09:03:12 AM UTC 24 |
Sep 09 09:10:36 AM UTC 24 |
17567181824 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_alert_test.2769097883 |
|
|
Sep 09 09:10:37 AM UTC 24 |
Sep 09 09:10:40 AM UTC 24 |
15119029 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3059529619 |
|
|
Sep 09 09:10:22 AM UTC 24 |
Sep 09 09:10:40 AM UTC 24 |
384263376 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all.323637416 |
|
|
Sep 09 08:13:45 AM UTC 24 |
Sep 09 09:11:09 AM UTC 24 |
666936155438 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.121171711 |
|
|
Sep 09 09:09:11 AM UTC 24 |
Sep 09 09:11:14 AM UTC 24 |
9999996423 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_smoke.2644811520 |
|
|
Sep 09 09:10:40 AM UTC 24 |
Sep 09 09:11:20 AM UTC 24 |
18010176191 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.3777437433 |
|
|
Sep 09 09:06:40 AM UTC 24 |
Sep 09 09:11:42 AM UTC 24 |
34214740189 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_executable.2255445272 |
|
|
Sep 09 08:55:09 AM UTC 24 |
Sep 09 09:11:51 AM UTC 24 |
29122623879 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.2776301273 |
|
|
Sep 09 09:05:48 AM UTC 24 |
Sep 09 09:11:52 AM UTC 24 |
63577281342 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access.2579468904 |
|
|
Sep 09 09:11:21 AM UTC 24 |
Sep 09 09:11:55 AM UTC 24 |
1348252972 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.1234630323 |
|
|
Sep 09 09:11:51 AM UTC 24 |
Sep 09 09:12:19 AM UTC 24 |
747147963 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.1383280098 |
|
|
Sep 09 09:01:03 AM UTC 24 |
Sep 09 09:12:23 AM UTC 24 |
6460604240 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.4265315575 |
|
|
Sep 09 09:11:52 AM UTC 24 |
Sep 09 09:12:32 AM UTC 24 |
775105967 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_regwen.2283683548 |
|
|
Sep 09 09:04:06 AM UTC 24 |
Sep 09 09:12:37 AM UTC 24 |
9846808252 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.1336812217 |
|
|
Sep 09 09:12:38 AM UTC 24 |
Sep 09 09:12:44 AM UTC 24 |
1422036757 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all.2570086935 |
|
|
Sep 09 08:07:37 AM UTC 24 |
Sep 09 09:13:03 AM UTC 24 |
179053297134 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_executable.924515653 |
|
|
Sep 09 09:12:24 AM UTC 24 |
Sep 09 09:13:39 AM UTC 24 |
2714446299 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.1696299883 |
|
|
Sep 09 08:56:20 AM UTC 24 |
Sep 09 09:13:42 AM UTC 24 |
20502595740 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.3692419517 |
|
|
Sep 09 09:11:56 AM UTC 24 |
Sep 09 09:13:45 AM UTC 24 |
21818608258 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_alert_test.3240158493 |
|
|
Sep 09 09:13:46 AM UTC 24 |
Sep 09 09:13:48 AM UTC 24 |
79879643 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.610982566 |
|
|
Sep 09 09:07:27 AM UTC 24 |
Sep 09 09:13:48 AM UTC 24 |
23269492446 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.585696631 |
|
|
Sep 09 09:13:39 AM UTC 24 |
Sep 09 09:14:00 AM UTC 24 |
1862102629 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.1920812662 |
|
|
Sep 09 09:10:21 AM UTC 24 |
Sep 09 09:14:02 AM UTC 24 |
9843116909 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_smoke.55808048 |
|
|
Sep 09 09:13:49 AM UTC 24 |
Sep 09 09:14:13 AM UTC 24 |
1415045334 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_executable.2822966776 |
|
|
Sep 09 09:01:06 AM UTC 24 |
Sep 09 09:14:13 AM UTC 24 |
32238433848 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.2131384018 |
|
|
Sep 09 09:05:17 AM UTC 24 |
Sep 09 09:14:47 AM UTC 24 |
71550965073 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access.450805851 |
|
|
Sep 09 09:14:13 AM UTC 24 |
Sep 09 09:14:51 AM UTC 24 |
463268450 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_bijection.540818379 |
|
|
Sep 09 08:46:43 AM UTC 24 |
Sep 09 09:15:23 AM UTC 24 |
183224314365 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all.429758838 |
|
|
Sep 09 08:38:04 AM UTC 24 |
Sep 09 09:15:23 AM UTC 24 |
68991710995 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_bijection.4293368086 |
|
|
Sep 09 09:02:40 AM UTC 24 |
Sep 09 09:15:24 AM UTC 24 |
67624532311 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.1438480774 |
|
|
Sep 09 09:14:52 AM UTC 24 |
Sep 09 09:15:26 AM UTC 24 |
4178443495 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all.3367334041 |
|
|
Sep 09 08:04:04 AM UTC 24 |
Sep 09 09:15:32 AM UTC 24 |
264540408280 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.3987656674 |
|
|
Sep 09 09:11:15 AM UTC 24 |
Sep 09 09:15:33 AM UTC 24 |
4290148756 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.3664759502 |
|
|
Sep 09 09:15:33 AM UTC 24 |
Sep 09 09:15:39 AM UTC 24 |
344112330 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.89953366 |
|
|
Sep 09 09:08:25 AM UTC 24 |
Sep 09 09:15:45 AM UTC 24 |
24378100515 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.4093184306 |
|
|
Sep 09 09:14:47 AM UTC 24 |
Sep 09 09:15:52 AM UTC 24 |
4930631386 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_bijection.525132315 |
|
|
Sep 09 08:27:11 AM UTC 24 |
Sep 09 09:15:55 AM UTC 24 |
687587426621 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.249025513 |
|
|
Sep 09 08:58:35 AM UTC 24 |
Sep 09 09:15:58 AM UTC 24 |
103321668610 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_alert_test.1913986803 |
|
|
Sep 09 09:15:56 AM UTC 24 |
Sep 09 09:15:58 AM UTC 24 |
21763681 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.1740584437 |
|
|
Sep 09 09:10:14 AM UTC 24 |
Sep 09 09:16:02 AM UTC 24 |
3945340706 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.4270670523 |
|
|
Sep 09 09:13:04 AM UTC 24 |
Sep 09 09:16:04 AM UTC 24 |
25114131572 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.1521565527 |
|
|
Sep 09 09:15:25 AM UTC 24 |
Sep 09 09:16:05 AM UTC 24 |
13322495186 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_smoke.3778144847 |
|
|
Sep 09 09:15:58 AM UTC 24 |
Sep 09 09:16:08 AM UTC 24 |
1715225710 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access.3861940622 |
|
|
Sep 09 09:16:06 AM UTC 24 |
Sep 09 09:16:36 AM UTC 24 |
1616137843 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.3057036599 |
|
|
Sep 09 09:12:45 AM UTC 24 |
Sep 09 09:16:37 AM UTC 24 |
13857835152 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all.789801506 |
|
|
Sep 09 08:12:17 AM UTC 24 |
Sep 09 09:16:38 AM UTC 24 |
557921040831 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.4065281646 |
|
|
Sep 09 09:16:38 AM UTC 24 |
Sep 09 09:16:56 AM UTC 24 |
696132678 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all.815424339 |
|
|
Sep 09 08:35:36 AM UTC 24 |
Sep 09 09:16:57 AM UTC 24 |
299542216463 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.600756024 |
|
|
Sep 09 09:16:36 AM UTC 24 |
Sep 09 09:16:59 AM UTC 24 |
1423342031 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.1118599913 |
|
|
Sep 09 09:02:39 AM UTC 24 |
Sep 09 09:17:00 AM UTC 24 |
22435071188 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.2152469198 |
|
|
Sep 09 09:17:01 AM UTC 24 |
Sep 09 09:17:08 AM UTC 24 |
1609846762 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_regwen.3102154367 |
|
|
Sep 09 09:10:11 AM UTC 24 |
Sep 09 09:17:11 AM UTC 24 |
14899318418 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_regwen.1143242267 |
|
|
Sep 09 09:07:02 AM UTC 24 |
Sep 09 09:17:11 AM UTC 24 |
3662184774 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.565675583 |
|
|
Sep 09 09:17:12 AM UTC 24 |
Sep 09 09:17:25 AM UTC 24 |
876215610 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.3809659221 |
|
|
Sep 09 09:15:45 AM UTC 24 |
Sep 09 09:17:54 AM UTC 24 |
3004098099 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_alert_test.1750912152 |
|
|
Sep 09 09:17:55 AM UTC 24 |
Sep 09 09:17:58 AM UTC 24 |
44855580 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.1843334521 |
|
|
Sep 09 09:08:33 AM UTC 24 |
Sep 09 09:18:07 AM UTC 24 |
53176760225 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.3499262308 |
|
|
Sep 09 09:14:03 AM UTC 24 |
Sep 09 09:18:09 AM UTC 24 |
3945536745 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_smoke.2478498987 |
|
|
Sep 09 09:17:58 AM UTC 24 |
Sep 09 09:18:09 AM UTC 24 |
701633497 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.882225977 |
|
|
Sep 09 09:15:34 AM UTC 24 |
Sep 09 09:18:10 AM UTC 24 |
2018542095 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all.3455558572 |
|
|
Sep 09 08:10:02 AM UTC 24 |
Sep 09 09:18:17 AM UTC 24 |
731277053228 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.1928236202 |
|
|
Sep 09 09:11:43 AM UTC 24 |
Sep 09 09:18:25 AM UTC 24 |
13121860752 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.2396893325 |
|
|
Sep 09 09:15:40 AM UTC 24 |
Sep 09 09:18:30 AM UTC 24 |
10470734881 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access.2168580136 |
|
|
Sep 09 09:18:12 AM UTC 24 |
Sep 09 09:18:34 AM UTC 24 |
587386590 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.1237276991 |
|
|
Sep 09 09:16:05 AM UTC 24 |
Sep 09 09:18:34 AM UTC 24 |
2508285586 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.1855661523 |
|
|
Sep 09 09:14:14 AM UTC 24 |
Sep 09 09:18:36 AM UTC 24 |
24580895067 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.3799803213 |
|
|
Sep 09 09:12:20 AM UTC 24 |
Sep 09 09:24:10 AM UTC 24 |
13671565320 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.1505279636 |
|
|
Sep 09 08:43:36 AM UTC 24 |
Sep 09 09:18:37 AM UTC 24 |
29339166870 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.723555372 |
|
|
Sep 09 09:18:07 AM UTC 24 |
Sep 09 09:18:42 AM UTC 24 |
1377159556 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.2588933452 |
|
|
Sep 09 09:18:43 AM UTC 24 |
Sep 09 09:18:49 AM UTC 24 |
680762578 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.4184838484 |
|
|
Sep 09 09:16:39 AM UTC 24 |
Sep 09 09:18:54 AM UTC 24 |
54112772040 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.2323897540 |
|
|
Sep 09 09:18:26 AM UTC 24 |
Sep 09 09:19:07 AM UTC 24 |
754538697 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_executable.1255764005 |
|
|
Sep 09 09:06:51 AM UTC 24 |
Sep 09 09:19:08 AM UTC 24 |
86094835910 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.1462655284 |
|
|
Sep 09 09:16:09 AM UTC 24 |
Sep 09 09:19:12 AM UTC 24 |
4719239192 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_alert_test.1420077716 |
|
|
Sep 09 09:19:11 AM UTC 24 |
Sep 09 09:19:13 AM UTC 24 |
35535515 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.2166473636 |
|
|
Sep 09 09:18:31 AM UTC 24 |
Sep 09 09:19:16 AM UTC 24 |
7521264592 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3091186206 |
|
|
Sep 09 09:19:08 AM UTC 24 |
Sep 09 09:19:22 AM UTC 24 |
377653910 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.3316055793 |
|
|
Sep 09 09:17:09 AM UTC 24 |
Sep 09 09:19:52 AM UTC 24 |
3660425149 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.2325990755 |
|
|
Sep 09 09:22:02 AM UTC 24 |
Sep 09 09:24:10 AM UTC 24 |
10016244209 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_bijection.664182369 |
|
|
Sep 09 08:23:29 AM UTC 24 |
Sep 09 09:19:55 AM UTC 24 |
622594597153 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.801154762 |
|
|
Sep 09 09:18:35 AM UTC 24 |
Sep 09 09:20:01 AM UTC 24 |
10005028141 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_smoke.2432932572 |
|
|
Sep 09 09:19:13 AM UTC 24 |
Sep 09 09:20:01 AM UTC 24 |
4062056087 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access.1240299438 |
|
|
Sep 09 09:19:53 AM UTC 24 |
Sep 09 09:20:14 AM UTC 24 |
5334460622 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.3973224230 |
|
|
Sep 09 09:17:11 AM UTC 24 |
Sep 09 09:20:18 AM UTC 24 |
17568673013 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_executable.3637250129 |
|
|
Sep 09 09:04:00 AM UTC 24 |
Sep 09 09:20:29 AM UTC 24 |
81117018752 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.3831233107 |
|
|
Sep 09 09:20:15 AM UTC 24 |
Sep 09 09:20:35 AM UTC 24 |
6918148544 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.4283885842 |
|
|
Sep 09 09:10:41 AM UTC 24 |
Sep 09 09:20:36 AM UTC 24 |
74961411486 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_bijection.238992735 |
|
|
Sep 09 08:54:05 AM UTC 24 |
Sep 09 09:20:39 AM UTC 24 |
58006536159 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.1821972507 |
|
|
Sep 09 09:20:37 AM UTC 24 |
Sep 09 09:20:41 AM UTC 24 |
786503242 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_bijection.13456012 |
|
|
Sep 09 09:05:23 AM UTC 24 |
Sep 09 09:20:43 AM UTC 24 |
12518599616 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_regwen.1937200107 |
|
|
Sep 09 09:17:00 AM UTC 24 |
Sep 09 09:21:03 AM UTC 24 |
16431247217 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.681948987 |
|
|
Sep 09 09:09:51 AM UTC 24 |
Sep 09 09:21:07 AM UTC 24 |
51300018893 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_alert_test.268542940 |
|
|
Sep 09 09:21:08 AM UTC 24 |
Sep 09 09:21:11 AM UTC 24 |
50570617 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.29218038 |
|
|
Sep 09 09:15:25 AM UTC 24 |
Sep 09 09:21:15 AM UTC 24 |
32132718629 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_smoke.3309677816 |
|
|
Sep 09 09:21:11 AM UTC 24 |
Sep 09 09:21:19 AM UTC 24 |
381730223 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.115156058 |
|
|
Sep 09 09:20:02 AM UTC 24 |
Sep 09 09:21:21 AM UTC 24 |
3283723687 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.1963880408 |
|
|
Sep 09 09:20:02 AM UTC 24 |
Sep 09 09:21:30 AM UTC 24 |
1613709869 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_bijection.4027090839 |
|
|
Sep 09 08:52:05 AM UTC 24 |
Sep 09 09:21:31 AM UTC 24 |
159867822038 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_executable.3545970726 |
|
|
Sep 09 09:09:54 AM UTC 24 |
Sep 09 09:21:42 AM UTC 24 |
138548032189 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.293868261 |
|
|
Sep 09 09:18:55 AM UTC 24 |
Sep 09 09:21:57 AM UTC 24 |
27489478671 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.3180000978 |
|
|
Sep 09 09:18:51 AM UTC 24 |
Sep 09 09:22:02 AM UTC 24 |
59962239074 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access.3746469350 |
|
|
Sep 09 09:21:31 AM UTC 24 |
Sep 09 09:22:05 AM UTC 24 |
717824247 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.731892633 |
|
|
Sep 09 09:21:43 AM UTC 24 |
Sep 09 09:22:13 AM UTC 24 |
2865830546 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.388930063 |
|
|
Sep 09 09:21:58 AM UTC 24 |
Sep 09 09:22:17 AM UTC 24 |
1507698097 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all.713474485 |
|
|
Sep 09 09:07:47 AM UTC 24 |
Sep 09 09:22:58 AM UTC 24 |
65653787986 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.4275302981 |
|
|
Sep 09 09:22:59 AM UTC 24 |
Sep 09 09:23:06 AM UTC 24 |
1295930008 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.1157750052 |
|
|
Sep 09 09:20:44 AM UTC 24 |
Sep 09 09:23:07 AM UTC 24 |
4539789968 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.4124069408 |
|
|
Sep 09 09:20:40 AM UTC 24 |
Sep 09 09:23:46 AM UTC 24 |
41422327958 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_executable.252677569 |
|
|
Sep 09 09:15:25 AM UTC 24 |
Sep 09 09:23:47 AM UTC 24 |
19219339157 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.754683765 |
|
|
Sep 09 09:19:24 AM UTC 24 |
Sep 09 09:24:04 AM UTC 24 |
4184809809 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_alert_test.859087773 |
|
|
Sep 09 09:24:05 AM UTC 24 |
Sep 09 09:24:07 AM UTC 24 |
18990559 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.191807688 |
|
|
Sep 09 09:21:22 AM UTC 24 |
Sep 09 09:24:08 AM UTC 24 |
23716593749 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.4266105892 |
|
|
Sep 09 09:19:14 AM UTC 24 |
Sep 09 09:24:08 AM UTC 24 |
6220522892 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_executable.1926310457 |
|
|
Sep 09 09:22:14 AM UTC 24 |
Sep 09 09:24:13 AM UTC 24 |
4625977890 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access.2611601559 |
|
|
Sep 09 09:24:11 AM UTC 24 |
Sep 09 09:24:18 AM UTC 24 |
438073884 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.1512896303 |
|
|
Sep 09 09:18:35 AM UTC 24 |
Sep 09 09:24:24 AM UTC 24 |
6075365657 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.4009818366 |
|
|
Sep 09 09:20:42 AM UTC 24 |
Sep 09 09:24:24 AM UTC 24 |
20415588558 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_smoke.3744883477 |
|
|
Sep 09 09:24:08 AM UTC 24 |
Sep 09 09:24:34 AM UTC 24 |
6876215280 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_regwen.3802574486 |
|
|
Sep 09 09:12:34 AM UTC 24 |
Sep 09 09:24:38 AM UTC 24 |
6393613662 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.3896626724 |
|
|
Sep 09 09:24:25 AM UTC 24 |
Sep 09 09:24:49 AM UTC 24 |
1444071116 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.753627658 |
|
|
Sep 09 09:18:11 AM UTC 24 |
Sep 09 09:25:05 AM UTC 24 |
19200463025 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.3425890202 |
|
|
Sep 09 09:25:06 AM UTC 24 |
Sep 09 09:25:13 AM UTC 24 |
1351388677 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.3966385719 |
|
|
Sep 09 09:18:18 AM UTC 24 |
Sep 09 09:25:23 AM UTC 24 |
22175755038 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_bijection.504023680 |
|
|
Sep 09 08:41:02 AM UTC 24 |
Sep 09 09:25:38 AM UTC 24 |
423365461595 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.2122624899 |
|
|
Sep 09 09:23:48 AM UTC 24 |
Sep 09 09:25:45 AM UTC 24 |
17405081549 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.373313663 |
|
|
Sep 09 09:07:53 AM UTC 24 |
Sep 09 09:25:47 AM UTC 24 |
55345877705 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_alert_test.4231771778 |
|
|
Sep 09 09:25:49 AM UTC 24 |
Sep 09 09:25:51 AM UTC 24 |
46693527 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.4274561782 |
|
|
Sep 09 09:24:26 AM UTC 24 |
Sep 09 09:26:00 AM UTC 24 |
41382498328 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.1068617612 |
|
|
Sep 09 09:24:19 AM UTC 24 |
Sep 09 09:26:02 AM UTC 24 |
3083710108 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.3585303668 |
|
|
Sep 09 09:25:38 AM UTC 24 |
Sep 09 09:26:10 AM UTC 24 |
3894817078 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_smoke.4243739667 |
|
|
Sep 09 09:25:52 AM UTC 24 |
Sep 09 09:26:14 AM UTC 24 |
2768285910 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.4117433634 |
|
|
Sep 09 09:23:07 AM UTC 24 |
Sep 09 09:26:24 AM UTC 24 |
6930368545 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.1668407082 |
|
|
Sep 09 09:21:32 AM UTC 24 |
Sep 09 09:26:25 AM UTC 24 |
8353520452 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access.3066630427 |
|
|
Sep 09 09:26:15 AM UTC 24 |
Sep 09 09:26:27 AM UTC 24 |
1564721576 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all.3252228075 |
|
|
Sep 09 08:29:27 AM UTC 24 |
Sep 09 09:26:30 AM UTC 24 |
39059946128 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.2753987199 |
|
|
Sep 09 09:23:08 AM UTC 24 |
Sep 09 09:26:57 AM UTC 24 |
27479204377 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.835148132 |
|
|
Sep 09 09:25:24 AM UTC 24 |
Sep 09 09:27:03 AM UTC 24 |
5755507084 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all.2862607420 |
|
|
Sep 09 08:40:35 AM UTC 24 |
Sep 09 09:27:21 AM UTC 24 |
33140516073 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.739659858 |
|
|
Sep 09 09:26:28 AM UTC 24 |
Sep 09 09:27:24 AM UTC 24 |
1545627363 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_regwen.1470492672 |
|
|
Sep 09 09:22:18 AM UTC 24 |
Sep 09 09:27:25 AM UTC 24 |
2850078497 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.767266395 |
|
|
Sep 09 09:27:25 AM UTC 24 |
Sep 09 09:27:32 AM UTC 24 |
379487809 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.4213064718 |
|
|
Sep 09 09:19:56 AM UTC 24 |
Sep 09 09:27:40 AM UTC 24 |
31915165496 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.1807015838 |
|
|
Sep 09 09:26:26 AM UTC 24 |
Sep 09 09:27:49 AM UTC 24 |
1536482021 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.2246604127 |
|
|
Sep 09 09:25:14 AM UTC 24 |
Sep 09 09:28:05 AM UTC 24 |
14433484617 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.2801862276 |
|
|
Sep 09 09:27:40 AM UTC 24 |
Sep 09 09:28:07 AM UTC 24 |
688543074 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_alert_test.4097738294 |
|
|
Sep 09 09:28:06 AM UTC 24 |
Sep 09 09:28:08 AM UTC 24 |
148709926 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_bijection.3901148689 |
|
|
Sep 09 08:33:55 AM UTC 24 |
Sep 09 09:28:14 AM UTC 24 |
170560606409 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.1294920156 |
|
|
Sep 09 09:26:01 AM UTC 24 |
Sep 09 09:28:58 AM UTC 24 |
5770614148 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_bijection.3027292770 |
|
|
Sep 09 08:36:14 AM UTC 24 |
Sep 09 09:29:01 AM UTC 24 |
550089224675 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access.1172257276 |
|
|
Sep 09 09:29:01 AM UTC 24 |
Sep 09 09:29:09 AM UTC 24 |
782979010 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_smoke.3085936655 |
|
|
Sep 09 09:28:07 AM UTC 24 |
Sep 09 09:29:09 AM UTC 24 |
858020566 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.3032263409 |
|
|
Sep 09 09:26:30 AM UTC 24 |
Sep 09 09:29:13 AM UTC 24 |
75507200809 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.2216565661 |
|
|
Sep 09 09:16:56 AM UTC 24 |
Sep 09 09:29:22 AM UTC 24 |
16531737603 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.611707294 |
|
|
Sep 09 09:16:00 AM UTC 24 |
Sep 09 09:29:38 AM UTC 24 |
19714825088 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.2136611648 |
|
|
Sep 09 09:24:11 AM UTC 24 |
Sep 09 09:29:40 AM UTC 24 |
15890645371 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.732329771 |
|
|
Sep 09 09:27:33 AM UTC 24 |
Sep 09 09:30:06 AM UTC 24 |
20520251860 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.1015931478 |
|
|
Sep 09 09:27:26 AM UTC 24 |
Sep 09 09:30:21 AM UTC 24 |
43144691574 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.799812708 |
|
|
Sep 09 09:30:22 AM UTC 24 |
Sep 09 09:30:27 AM UTC 24 |
1400800446 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.3863718098 |
|
|
Sep 09 09:24:13 AM UTC 24 |
Sep 09 09:30:29 AM UTC 24 |
12800322371 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.1252961750 |
|
|
Sep 09 09:26:11 AM UTC 24 |
Sep 09 09:30:32 AM UTC 24 |
5093824589 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.3750242187 |
|
|
Sep 09 09:29:14 AM UTC 24 |
Sep 09 09:30:35 AM UTC 24 |
5953123302 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.191360988 |
|
|
Sep 09 09:29:23 AM UTC 24 |
Sep 09 09:30:36 AM UTC 24 |
49491058897 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all.2399535395 |
|
|
Sep 09 08:24:20 AM UTC 24 |
Sep 09 09:30:38 AM UTC 24 |
407166989869 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_alert_test.3251268151 |
|
|
Sep 09 09:30:37 AM UTC 24 |
Sep 09 09:30:39 AM UTC 24 |
37660812 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_bijection.3307694659 |
|
|
Sep 09 09:16:03 AM UTC 24 |
Sep 09 09:30:41 AM UTC 24 |
220556897235 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.3502034961 |
|
|
Sep 09 09:29:10 AM UTC 24 |
Sep 09 09:30:43 AM UTC 24 |
793418721 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.1166981360 |
|
|
Sep 09 09:26:58 AM UTC 24 |
Sep 09 09:30:50 AM UTC 24 |
35067898045 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_smoke.3721328647 |
|
|
Sep 09 09:30:39 AM UTC 24 |
Sep 09 09:31:06 AM UTC 24 |
7660566058 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_executable.4292267135 |
|
|
Sep 09 09:20:29 AM UTC 24 |
Sep 09 09:31:15 AM UTC 24 |
16887277117 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.3374799834 |
|
|
Sep 09 09:31:15 AM UTC 24 |
Sep 09 09:31:42 AM UTC 24 |
707076170 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access.2444955843 |
|
|
Sep 09 09:30:51 AM UTC 24 |
Sep 09 09:31:57 AM UTC 24 |
6662253227 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.1407571254 |
|
|
Sep 09 09:31:58 AM UTC 24 |
Sep 09 09:32:14 AM UTC 24 |
5058744791 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.338164237 |
|
|
Sep 09 09:30:29 AM UTC 24 |
Sep 09 09:32:17 AM UTC 24 |
10735191195 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.554937362 |
|
|
Sep 09 09:26:24 AM UTC 24 |
Sep 09 09:32:19 AM UTC 24 |
49346952907 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_all.3528759691 |
|
|
Sep 09 08:21:15 AM UTC 24 |
Sep 09 09:32:36 AM UTC 24 |
404409267473 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.1680300894 |
|
|
Sep 09 09:32:37 AM UTC 24 |
Sep 09 09:32:42 AM UTC 24 |
743822929 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.1075383928 |
|
|
Sep 09 09:31:44 AM UTC 24 |
Sep 09 09:32:44 AM UTC 24 |
14728460313 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_bijection.3060460245 |
|
|
Sep 09 09:19:16 AM UTC 24 |
Sep 09 09:32:54 AM UTC 24 |
13867497823 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_executable.2899992615 |
|
|
Sep 09 09:18:36 AM UTC 24 |
Sep 09 09:32:54 AM UTC 24 |
23681978992 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_bijection.3868121800 |
|
|
Sep 09 09:14:01 AM UTC 24 |
Sep 09 09:32:58 AM UTC 24 |
14787188771 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_alert_test.4255114764 |
|
|
Sep 09 09:32:59 AM UTC 24 |
Sep 09 09:33:01 AM UTC 24 |
43128079 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.1073226097 |
|
|
Sep 09 09:30:32 AM UTC 24 |
Sep 09 09:33:04 AM UTC 24 |
7280067798 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.808298950 |
|
|
Sep 09 09:32:54 AM UTC 24 |
Sep 09 09:33:06 AM UTC 24 |
248967564 ps |