| T801 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.4115418921 |
|
|
Sep 09 09:20:19 AM UTC 24 |
Sep 09 09:33:19 AM UTC 24 |
12176501265 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_regwen.1868425502 |
|
|
Sep 09 09:24:50 AM UTC 24 |
Sep 09 09:33:25 AM UTC 24 |
10678259222 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.2164970347 |
|
|
Sep 09 09:21:16 AM UTC 24 |
Sep 09 09:33:37 AM UTC 24 |
39827162634 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_smoke.48950302 |
|
|
Sep 09 09:33:02 AM UTC 24 |
Sep 09 09:33:38 AM UTC 24 |
2389147769 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access.2519561904 |
|
|
Sep 09 09:33:26 AM UTC 24 |
Sep 09 09:33:40 AM UTC 24 |
490070726 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.382844081 |
|
|
Sep 09 09:29:10 AM UTC 24 |
Sep 09 09:33:49 AM UTC 24 |
43430698350 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.203618974 |
|
|
Sep 09 09:22:06 AM UTC 24 |
Sep 09 09:34:06 AM UTC 24 |
13132375927 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.338180484 |
|
|
Sep 09 09:32:44 AM UTC 24 |
Sep 09 09:34:50 AM UTC 24 |
19132799950 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.2060908959 |
|
|
Sep 09 09:28:59 AM UTC 24 |
Sep 09 09:35:02 AM UTC 24 |
49842017532 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_executable.430096722 |
|
|
Sep 09 09:24:39 AM UTC 24 |
Sep 09 09:35:12 AM UTC 24 |
36020465770 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.1674580132 |
|
|
Sep 09 09:33:39 AM UTC 24 |
Sep 09 09:35:13 AM UTC 24 |
1587719399 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.326745331 |
|
|
Sep 09 09:35:13 AM UTC 24 |
Sep 09 09:35:20 AM UTC 24 |
1402836332 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.522749934 |
|
|
Sep 09 09:33:42 AM UTC 24 |
Sep 09 09:35:38 AM UTC 24 |
820438854 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.777216157 |
|
|
Sep 09 09:30:44 AM UTC 24 |
Sep 09 09:35:45 AM UTC 24 |
10377084587 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_bijection.2709193254 |
|
|
Sep 09 09:18:10 AM UTC 24 |
Sep 09 09:35:45 AM UTC 24 |
47670039854 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.504856565 |
|
|
Sep 09 09:30:27 AM UTC 24 |
Sep 09 09:35:46 AM UTC 24 |
62859049198 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_alert_test.528084871 |
|
|
Sep 09 09:35:46 AM UTC 24 |
Sep 09 09:35:48 AM UTC 24 |
14439819 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_smoke.3116318645 |
|
|
Sep 09 09:35:47 AM UTC 24 |
Sep 09 09:36:14 AM UTC 24 |
2510481913 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3798670730 |
|
|
Sep 09 09:35:39 AM UTC 24 |
Sep 09 09:36:35 AM UTC 24 |
2319791194 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.2136849973 |
|
|
Sep 09 09:24:35 AM UTC 24 |
Sep 09 09:36:46 AM UTC 24 |
22072791539 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.3521597351 |
|
|
Sep 09 09:33:51 AM UTC 24 |
Sep 09 09:37:00 AM UTC 24 |
70002390524 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access.3889882195 |
|
|
Sep 09 09:36:46 AM UTC 24 |
Sep 09 09:37:12 AM UTC 24 |
3727653172 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.3745665935 |
|
|
Sep 09 09:35:20 AM UTC 24 |
Sep 09 09:37:13 AM UTC 24 |
2381104717 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.3304446248 |
|
|
Sep 09 09:37:14 AM UTC 24 |
Sep 09 09:37:25 AM UTC 24 |
2568968292 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_regwen.1339760206 |
|
|
Sep 09 09:20:37 AM UTC 24 |
Sep 09 09:37:38 AM UTC 24 |
5230377305 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.113472186 |
|
|
Sep 09 09:31:06 AM UTC 24 |
Sep 09 09:37:39 AM UTC 24 |
6813773273 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.2919908435 |
|
|
Sep 09 09:35:13 AM UTC 24 |
Sep 09 09:38:00 AM UTC 24 |
5480760587 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_regwen.2279488285 |
|
|
Sep 09 09:27:22 AM UTC 24 |
Sep 09 09:38:15 AM UTC 24 |
46708631763 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.455645984 |
|
|
Sep 09 09:38:17 AM UTC 24 |
Sep 09 09:38:24 AM UTC 24 |
1209168341 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.521240831 |
|
|
Sep 09 09:37:13 AM UTC 24 |
Sep 09 09:38:25 AM UTC 24 |
760061444 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_bijection.2102032535 |
|
|
Sep 09 09:24:09 AM UTC 24 |
Sep 09 09:38:58 AM UTC 24 |
25283739844 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_regwen.816413196 |
|
|
Sep 09 09:18:37 AM UTC 24 |
Sep 09 09:39:03 AM UTC 24 |
38920779215 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.2944270971 |
|
|
Sep 09 09:29:39 AM UTC 24 |
Sep 09 09:39:07 AM UTC 24 |
22578734373 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_alert_test.4188821977 |
|
|
Sep 09 09:39:08 AM UTC 24 |
Sep 09 09:39:10 AM UTC 24 |
14174372 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2660602194 |
|
|
Sep 09 09:38:59 AM UTC 24 |
Sep 09 09:39:13 AM UTC 24 |
526199713 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.2296925361 |
|
|
Sep 09 09:32:42 AM UTC 24 |
Sep 09 09:39:45 AM UTC 24 |
103309046442 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.1078350142 |
|
|
Sep 09 09:38:26 AM UTC 24 |
Sep 09 09:39:48 AM UTC 24 |
1405423163 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.987462530 |
|
|
Sep 09 09:33:20 AM UTC 24 |
Sep 09 09:39:59 AM UTC 24 |
36115550347 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.1974522976 |
|
|
Sep 09 09:37:26 AM UTC 24 |
Sep 09 09:39:59 AM UTC 24 |
54530194049 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all.3954098617 |
|
|
Sep 09 08:31:20 AM UTC 24 |
Sep 09 09:40:20 AM UTC 24 |
125961622438 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access.3391918403 |
|
|
Sep 09 09:40:00 AM UTC 24 |
Sep 09 09:40:39 AM UTC 24 |
10038051795 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.1637906136 |
|
|
Sep 09 09:24:09 AM UTC 24 |
Sep 09 09:40:56 AM UTC 24 |
44562807575 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_smoke.3013006989 |
|
|
Sep 09 09:39:11 AM UTC 24 |
Sep 09 09:41:02 AM UTC 24 |
2614700961 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.3427764055 |
|
|
Sep 09 09:40:21 AM UTC 24 |
Sep 09 09:41:02 AM UTC 24 |
1508830079 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_executable.2355541617 |
|
|
Sep 09 09:16:58 AM UTC 24 |
Sep 09 09:41:30 AM UTC 24 |
29808872836 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.3301130527 |
|
|
Sep 09 09:33:38 AM UTC 24 |
Sep 09 09:41:31 AM UTC 24 |
239074951323 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.3094256307 |
|
|
Sep 09 09:41:31 AM UTC 24 |
Sep 09 09:41:37 AM UTC 24 |
348214101 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.2040178690 |
|
|
Sep 09 09:38:26 AM UTC 24 |
Sep 09 09:41:39 AM UTC 24 |
6928514330 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.566006441 |
|
|
Sep 09 09:13:49 AM UTC 24 |
Sep 09 09:41:50 AM UTC 24 |
55501378703 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.2306236992 |
|
|
Sep 09 09:40:56 AM UTC 24 |
Sep 09 09:41:57 AM UTC 24 |
12104580718 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_alert_test.2267950474 |
|
|
Sep 09 09:41:58 AM UTC 24 |
Sep 09 09:42:00 AM UTC 24 |
43730683 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_executable.3133019986 |
|
|
Sep 09 09:27:05 AM UTC 24 |
Sep 09 09:42:14 AM UTC 24 |
17926885382 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.512280452 |
|
|
Sep 09 09:40:40 AM UTC 24 |
Sep 09 09:42:14 AM UTC 24 |
2659865617 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.4084577727 |
|
|
Sep 09 09:30:40 AM UTC 24 |
Sep 09 09:42:43 AM UTC 24 |
9237323611 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_smoke.3503656142 |
|
|
Sep 09 09:42:01 AM UTC 24 |
Sep 09 09:42:47 AM UTC 24 |
1461104067 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.3954814107 |
|
|
Sep 09 09:37:01 AM UTC 24 |
Sep 09 09:43:05 AM UTC 24 |
6468763393 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.806705381 |
|
|
Sep 09 09:41:38 AM UTC 24 |
Sep 09 09:43:11 AM UTC 24 |
1927398888 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access.4214083997 |
|
|
Sep 09 09:42:48 AM UTC 24 |
Sep 09 09:43:15 AM UTC 24 |
5643734047 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.565830468 |
|
|
Sep 09 09:43:11 AM UTC 24 |
Sep 09 09:43:20 AM UTC 24 |
2807346664 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.4239094840 |
|
|
Sep 09 09:32:15 AM UTC 24 |
Sep 09 09:43:24 AM UTC 24 |
9727004150 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_regwen.1564975540 |
|
|
Sep 09 09:32:20 AM UTC 24 |
Sep 09 09:43:27 AM UTC 24 |
27385716792 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_all.503788914 |
|
|
Sep 09 08:58:28 AM UTC 24 |
Sep 09 09:43:29 AM UTC 24 |
50585875471 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.1694448238 |
|
|
Sep 09 09:43:16 AM UTC 24 |
Sep 09 09:43:33 AM UTC 24 |
1436184798 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.2286131678 |
|
|
Sep 09 09:43:34 AM UTC 24 |
Sep 09 09:43:40 AM UTC 24 |
1780210190 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_regwen.3585878141 |
|
|
Sep 09 09:41:15 AM UTC 24 |
Sep 09 09:43:41 AM UTC 24 |
9555743121 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_bijection.619104608 |
|
|
Sep 09 08:58:36 AM UTC 24 |
Sep 09 09:44:05 AM UTC 24 |
137943670077 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_multiple_keys.1958995400 |
|
|
Sep 09 09:39:14 AM UTC 24 |
Sep 09 09:44:08 AM UTC 24 |
12834979350 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3718516082 |
|
|
Sep 09 09:44:06 AM UTC 24 |
Sep 09 09:44:20 AM UTC 24 |
456093149 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_alert_test.3629879262 |
|
|
Sep 09 09:44:21 AM UTC 24 |
Sep 09 09:44:23 AM UTC 24 |
35100194 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all.37618731 |
|
|
Sep 09 08:45:46 AM UTC 24 |
Sep 09 09:44:34 AM UTC 24 |
508243395780 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_smoke.2979954553 |
|
|
Sep 09 09:44:25 AM UTC 24 |
Sep 09 09:44:36 AM UTC 24 |
909209916 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_executable.1403421269 |
|
|
Sep 09 09:41:02 AM UTC 24 |
Sep 09 09:44:41 AM UTC 24 |
11501653484 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_executable.693554195 |
|
|
Sep 09 09:29:41 AM UTC 24 |
Sep 09 09:44:44 AM UTC 24 |
38025309886 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2243453528 |
|
|
Sep 09 09:41:40 AM UTC 24 |
Sep 09 09:45:00 AM UTC 24 |
15659963680 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.3307316790 |
|
|
Sep 09 09:36:36 AM UTC 24 |
Sep 09 09:45:00 AM UTC 24 |
20640165140 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.183646405 |
|
|
Sep 09 09:43:42 AM UTC 24 |
Sep 09 09:45:01 AM UTC 24 |
5181535917 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.3696737507 |
|
|
Sep 09 09:43:21 AM UTC 24 |
Sep 09 09:45:07 AM UTC 24 |
43169095992 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access.1140811703 |
|
|
Sep 09 09:44:44 AM UTC 24 |
Sep 09 09:45:14 AM UTC 24 |
3464041044 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.707848850 |
|
|
Sep 09 09:45:02 AM UTC 24 |
Sep 09 09:45:17 AM UTC 24 |
754126458 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.886149522 |
|
|
Sep 09 09:28:10 AM UTC 24 |
Sep 09 09:45:39 AM UTC 24 |
20035854459 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_bijection.3217136943 |
|
|
Sep 09 08:56:20 AM UTC 24 |
Sep 09 09:45:43 AM UTC 24 |
165545227641 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.138399780 |
|
|
Sep 09 09:45:44 AM UTC 24 |
Sep 09 09:45:49 AM UTC 24 |
345585043 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.731419478 |
|
|
Sep 09 09:45:07 AM UTC 24 |
Sep 09 09:45:53 AM UTC 24 |
15610161487 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.3706607729 |
|
|
Sep 09 09:39:50 AM UTC 24 |
Sep 09 09:46:17 AM UTC 24 |
9024959208 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all.470184547 |
|
|
Sep 09 09:17:26 AM UTC 24 |
Sep 09 09:46:30 AM UTC 24 |
74546495209 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.2753129961 |
|
|
Sep 09 09:41:32 AM UTC 24 |
Sep 09 09:46:47 AM UTC 24 |
21871292556 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_regwen.3406066262 |
|
|
Sep 09 09:43:30 AM UTC 24 |
Sep 09 09:46:49 AM UTC 24 |
6470100755 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_alert_test.3864324878 |
|
|
Sep 09 09:46:48 AM UTC 24 |
Sep 09 09:46:50 AM UTC 24 |
14690365 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.670120510 |
|
|
Sep 09 09:45:01 AM UTC 24 |
Sep 09 09:46:50 AM UTC 24 |
798780755 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.1350527540 |
|
|
Sep 09 09:43:06 AM UTC 24 |
Sep 09 09:46:53 AM UTC 24 |
14528867995 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3610860077 |
|
|
Sep 09 09:46:18 AM UTC 24 |
Sep 09 09:47:02 AM UTC 24 |
2803399321 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.2716324579 |
|
|
Sep 09 09:40:00 AM UTC 24 |
Sep 09 09:47:03 AM UTC 24 |
78026529217 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_executable.1109386376 |
|
|
Sep 09 09:32:18 AM UTC 24 |
Sep 09 09:47:23 AM UTC 24 |
65260768322 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_bijection.502498665 |
|
|
Sep 09 09:26:03 AM UTC 24 |
Sep 09 09:47:26 AM UTC 24 |
373712651976 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_regwen.1240164867 |
|
|
Sep 09 09:35:02 AM UTC 24 |
Sep 09 09:48:23 AM UTC 24 |
10899044000 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.2980291539 |
|
|
Sep 09 09:43:41 AM UTC 24 |
Sep 09 09:48:49 AM UTC 24 |
16418477229 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_executable.3060700541 |
|
|
Sep 09 09:34:51 AM UTC 24 |
Sep 09 09:48:58 AM UTC 24 |
73171795831 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.4010940515 |
|
|
Sep 09 09:45:53 AM UTC 24 |
Sep 09 09:48:58 AM UTC 24 |
5201354781 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.2558446096 |
|
|
Sep 09 09:34:08 AM UTC 24 |
Sep 09 09:49:15 AM UTC 24 |
29852204678 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.1346786086 |
|
|
Sep 09 09:45:01 AM UTC 24 |
Sep 09 09:49:15 AM UTC 24 |
3471950846 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.3225773954 |
|
|
Sep 09 09:44:41 AM UTC 24 |
Sep 09 09:49:23 AM UTC 24 |
4225918589 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all.3506037682 |
|
|
Sep 09 08:43:22 AM UTC 24 |
Sep 09 09:49:39 AM UTC 24 |
736618625519 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_executable.2007603016 |
|
|
Sep 09 09:43:28 AM UTC 24 |
Sep 09 09:50:34 AM UTC 24 |
9559112134 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.2151451884 |
|
|
Sep 09 09:33:05 AM UTC 24 |
Sep 09 09:50:37 AM UTC 24 |
51824401200 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.2334920315 |
|
|
Sep 09 09:42:44 AM UTC 24 |
Sep 09 09:50:50 AM UTC 24 |
18689679037 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_regwen.2979678121 |
|
|
Sep 09 09:45:40 AM UTC 24 |
Sep 09 09:51:14 AM UTC 24 |
15107299943 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all.3035126371 |
|
|
Sep 09 09:04:43 AM UTC 24 |
Sep 09 09:51:21 AM UTC 24 |
203217217830 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_regwen.2428185987 |
|
|
Sep 09 09:38:01 AM UTC 24 |
Sep 09 09:51:44 AM UTC 24 |
19328178588 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_executable.3939306905 |
|
|
Sep 09 09:45:18 AM UTC 24 |
Sep 09 09:52:31 AM UTC 24 |
14069442761 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.3755300000 |
|
|
Sep 09 09:37:38 AM UTC 24 |
Sep 09 09:52:40 AM UTC 24 |
14301134493 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all.766459683 |
|
|
Sep 09 08:11:00 AM UTC 24 |
Sep 09 09:52:57 AM UTC 24 |
270942742137 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_regwen.4029095511 |
|
|
Sep 09 09:30:07 AM UTC 24 |
Sep 09 09:53:01 AM UTC 24 |
60623681796 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.866603785 |
|
|
Sep 09 09:45:50 AM UTC 24 |
Sep 09 09:53:02 AM UTC 24 |
37453537986 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.4281778496 |
|
|
Sep 09 09:44:35 AM UTC 24 |
Sep 09 09:53:23 AM UTC 24 |
11706081304 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.1973639300 |
|
|
Sep 09 09:41:02 AM UTC 24 |
Sep 09 09:54:22 AM UTC 24 |
13290148034 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all.2563012590 |
|
|
Sep 09 09:21:04 AM UTC 24 |
Sep 09 09:55:17 AM UTC 24 |
84769548574 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.446672071 |
|
|
Sep 09 09:43:25 AM UTC 24 |
Sep 09 09:55:54 AM UTC 24 |
26893665142 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.821165191 |
|
|
Sep 09 09:42:14 AM UTC 24 |
Sep 09 09:56:04 AM UTC 24 |
19055508283 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_bijection.3443954857 |
|
|
Sep 09 09:28:15 AM UTC 24 |
Sep 09 09:56:51 AM UTC 24 |
25206013397 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_executable.818259151 |
|
|
Sep 09 09:37:40 AM UTC 24 |
Sep 09 09:57:14 AM UTC 24 |
25126072435 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_bijection.319518944 |
|
|
Sep 09 09:44:37 AM UTC 24 |
Sep 09 09:58:19 AM UTC 24 |
129749876753 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.3704999083 |
|
|
Sep 09 09:45:15 AM UTC 24 |
Sep 09 10:01:50 AM UTC 24 |
16762644512 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_bijection.3821329183 |
|
|
Sep 09 09:42:16 AM UTC 24 |
Sep 09 10:03:33 AM UTC 24 |
76035170117 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all.108462086 |
|
|
Sep 09 09:19:09 AM UTC 24 |
Sep 09 10:04:40 AM UTC 24 |
109358425517 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all.2536823492 |
|
|
Sep 09 09:30:37 AM UTC 24 |
Sep 09 10:05:27 AM UTC 24 |
52147237721 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.2221025235 |
|
|
Sep 09 09:35:48 AM UTC 24 |
Sep 09 10:05:52 AM UTC 24 |
36320958990 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_bijection.625645811 |
|
|
Sep 09 09:36:15 AM UTC 24 |
Sep 09 10:05:52 AM UTC 24 |
230722001745 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_bijection.477209104 |
|
|
Sep 09 09:11:10 AM UTC 24 |
Sep 09 10:07:46 AM UTC 24 |
304911144887 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all.2827803435 |
|
|
Sep 09 09:41:51 AM UTC 24 |
Sep 09 10:08:39 AM UTC 24 |
125431899771 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_bijection.497192067 |
|
|
Sep 09 09:21:20 AM UTC 24 |
Sep 09 10:10:55 AM UTC 24 |
718163102088 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all.1874110667 |
|
|
Sep 09 08:26:41 AM UTC 24 |
Sep 09 10:11:06 AM UTC 24 |
296041488161 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_bijection.2208340613 |
|
|
Sep 09 09:33:07 AM UTC 24 |
Sep 09 10:11:56 AM UTC 24 |
30470207404 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all.1081213043 |
|
|
Sep 09 09:44:09 AM UTC 24 |
Sep 09 10:15:39 AM UTC 24 |
104133884018 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all.2730802694 |
|
|
Sep 09 09:35:46 AM UTC 24 |
Sep 09 10:15:51 AM UTC 24 |
279024867815 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_bijection.1460810229 |
|
|
Sep 09 09:30:42 AM UTC 24 |
Sep 09 10:16:06 AM UTC 24 |
172708864350 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all.794485295 |
|
|
Sep 09 09:25:46 AM UTC 24 |
Sep 09 10:16:33 AM UTC 24 |
221444110557 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all.1401441797 |
|
|
Sep 09 09:15:52 AM UTC 24 |
Sep 09 10:16:41 AM UTC 24 |
55363314744 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all.913869009 |
|
|
Sep 09 09:13:42 AM UTC 24 |
Sep 09 10:17:07 AM UTC 24 |
27106215885 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all.384995046 |
|
|
Sep 09 09:10:27 AM UTC 24 |
Sep 09 10:17:54 AM UTC 24 |
1048409841406 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_bijection.4126379037 |
|
|
Sep 09 09:39:45 AM UTC 24 |
Sep 09 10:19:07 AM UTC 24 |
300125928404 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all.3573004643 |
|
|
Sep 09 09:39:04 AM UTC 24 |
Sep 09 10:21:32 AM UTC 24 |
193856897981 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all.273169254 |
|
|
Sep 09 08:49:17 AM UTC 24 |
Sep 09 10:22:21 AM UTC 24 |
216009328076 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all.1447055729 |
|
|
Sep 09 08:53:58 AM UTC 24 |
Sep 09 10:23:10 AM UTC 24 |
2852094193856 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all.1664852663 |
|
|
Sep 09 09:27:49 AM UTC 24 |
Sep 09 10:23:18 AM UTC 24 |
244388594630 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_all.3357457457 |
|
|
Sep 09 09:02:08 AM UTC 24 |
Sep 09 10:29:56 AM UTC 24 |
85645532438 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all.4030694778 |
|
|
Sep 09 08:56:14 AM UTC 24 |
Sep 09 10:35:31 AM UTC 24 |
181423013550 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all.2758002401 |
|
|
Sep 09 09:23:48 AM UTC 24 |
Sep 09 10:52:08 AM UTC 24 |
643607481007 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all.3024996293 |
|
|
Sep 09 09:46:31 AM UTC 24 |
Sep 09 11:03:43 AM UTC 24 |
255250855253 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all.3519724607 |
|
|
Sep 09 09:32:56 AM UTC 24 |
Sep 09 11:11:41 AM UTC 24 |
334189422431 ps |
| T68 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3398847282 |
|
|
Sep 09 09:46:51 AM UTC 24 |
Sep 09 09:46:55 AM UTC 24 |
679029296 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1278456786 |
|
|
Sep 09 09:46:54 AM UTC 24 |
Sep 09 09:46:56 AM UTC 24 |
53761347 ps |
| T72 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.326656827 |
|
|
Sep 09 09:46:56 AM UTC 24 |
Sep 09 09:46:58 AM UTC 24 |
100991121 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2153090999 |
|
|
Sep 09 09:46:51 AM UTC 24 |
Sep 09 09:46:58 AM UTC 24 |
136655409 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2306030330 |
|
|
Sep 09 09:46:57 AM UTC 24 |
Sep 09 09:47:01 AM UTC 24 |
280595400 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3753620047 |
|
|
Sep 09 09:46:59 AM UTC 24 |
Sep 09 09:47:01 AM UTC 24 |
19191761 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.779782087 |
|
|
Sep 09 09:46:59 AM UTC 24 |
Sep 09 09:47:01 AM UTC 24 |
30271778 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.4205872414 |
|
|
Sep 09 09:47:04 AM UTC 24 |
Sep 09 09:47:06 AM UTC 24 |
74540210 ps |
| T69 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.962079567 |
|
|
Sep 09 09:47:04 AM UTC 24 |
Sep 09 09:47:07 AM UTC 24 |
304255560 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2223699099 |
|
|
Sep 09 09:47:01 AM UTC 24 |
Sep 09 09:47:09 AM UTC 24 |
1332160153 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2766551116 |
|
|
Sep 09 09:47:07 AM UTC 24 |
Sep 09 09:47:09 AM UTC 24 |
39667272 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1298845910 |
|
|
Sep 09 09:47:03 AM UTC 24 |
Sep 09 09:47:10 AM UTC 24 |
161570757 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.796959038 |
|
|
Sep 09 09:47:08 AM UTC 24 |
Sep 09 09:47:11 AM UTC 24 |
67740580 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.450527380 |
|
|
Sep 09 09:47:09 AM UTC 24 |
Sep 09 09:47:11 AM UTC 24 |
44503080 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.61107819 |
|
|
Sep 09 09:47:10 AM UTC 24 |
Sep 09 09:47:12 AM UTC 24 |
20742048 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.622369848 |
|
|
Sep 09 09:47:12 AM UTC 24 |
Sep 09 09:47:17 AM UTC 24 |
340953430 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.567221264 |
|
|
Sep 09 09:47:13 AM UTC 24 |
Sep 09 09:47:18 AM UTC 24 |
173579108 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2553478592 |
|
|
Sep 09 09:47:17 AM UTC 24 |
Sep 09 09:47:19 AM UTC 24 |
23864704 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.4158012526 |
|
|
Sep 09 09:47:10 AM UTC 24 |
Sep 09 09:47:20 AM UTC 24 |
374601821 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1265302495 |
|
|
Sep 09 09:47:19 AM UTC 24 |
Sep 09 09:47:21 AM UTC 24 |
26437727 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.748282670 |
|
|
Sep 09 09:47:21 AM UTC 24 |
Sep 09 09:47:23 AM UTC 24 |
34436864 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3820336260 |
|
|
Sep 09 09:47:23 AM UTC 24 |
Sep 09 09:47:25 AM UTC 24 |
47348215 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2549364997 |
|
|
Sep 09 09:47:21 AM UTC 24 |
Sep 09 09:47:25 AM UTC 24 |
446139698 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.252197075 |
|
|
Sep 09 09:47:27 AM UTC 24 |
Sep 09 09:47:29 AM UTC 24 |
19309654 ps |
| T151 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2752365856 |
|
|
Sep 09 09:47:26 AM UTC 24 |
Sep 09 09:47:30 AM UTC 24 |
682523356 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.4290462407 |
|
|
Sep 09 09:47:30 AM UTC 24 |
Sep 09 09:47:32 AM UTC 24 |
13984503 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.380920192 |
|
|
Sep 09 09:47:26 AM UTC 24 |
Sep 09 09:47:34 AM UTC 24 |
301327271 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3687578577 |
|
|
Sep 09 09:47:31 AM UTC 24 |
Sep 09 09:47:34 AM UTC 24 |
36129197 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3379709561 |
|
|
Sep 09 09:47:24 AM UTC 24 |
Sep 09 09:47:34 AM UTC 24 |
4898858440 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3999353506 |
|
|
Sep 09 09:47:33 AM UTC 24 |
Sep 09 09:47:36 AM UTC 24 |
23803194 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1117367173 |
|
|
Sep 09 09:47:35 AM UTC 24 |
Sep 09 09:47:38 AM UTC 24 |
18217629 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1338908667 |
|
|
Sep 09 09:47:39 AM UTC 24 |
Sep 09 09:47:43 AM UTC 24 |
513290736 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3102882227 |
|
|
Sep 09 09:47:36 AM UTC 24 |
Sep 09 09:47:44 AM UTC 24 |
749310161 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.270011213 |
|
|
Sep 09 09:47:37 AM UTC 24 |
Sep 09 09:47:44 AM UTC 24 |
358507067 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2934053289 |
|
|
Sep 09 09:47:44 AM UTC 24 |
Sep 09 09:47:46 AM UTC 24 |
16246945 ps |
| T86 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1591996807 |
|
|
Sep 09 09:47:45 AM UTC 24 |
Sep 09 09:47:47 AM UTC 24 |
51728530 ps |
| T87 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3236973876 |
|
|
Sep 09 09:47:45 AM UTC 24 |
Sep 09 09:47:49 AM UTC 24 |
99035321 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1431041913 |
|
|
Sep 09 09:47:47 AM UTC 24 |
Sep 09 09:47:49 AM UTC 24 |
43494607 ps |
| T88 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1239964770 |
|
|
Sep 09 09:47:48 AM UTC 24 |
Sep 09 09:47:51 AM UTC 24 |
86140761 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1517073748 |
|
|
Sep 09 09:47:52 AM UTC 24 |
Sep 09 09:47:56 AM UTC 24 |
80958791 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3600834163 |
|
|
Sep 09 09:47:49 AM UTC 24 |
Sep 09 09:47:59 AM UTC 24 |
2929083067 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2766588561 |
|
|
Sep 09 09:47:57 AM UTC 24 |
Sep 09 09:48:00 AM UTC 24 |
153481402 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.4074459146 |
|
|
Sep 09 09:48:00 AM UTC 24 |
Sep 09 09:48:02 AM UTC 24 |
59978442 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3301115381 |
|
|
Sep 09 09:48:01 AM UTC 24 |
Sep 09 09:48:03 AM UTC 24 |
58890882 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2908235678 |
|
|
Sep 09 09:48:03 AM UTC 24 |
Sep 09 09:48:09 AM UTC 24 |
361454780 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1736450766 |
|
|
Sep 09 09:48:09 AM UTC 24 |
Sep 09 09:48:13 AM UTC 24 |
36706264 ps |
| T97 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2516530198 |
|
|
Sep 09 09:47:24 AM UTC 24 |
Sep 09 09:48:13 AM UTC 24 |
7176631633 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2512742899 |
|
|
Sep 09 09:48:14 AM UTC 24 |
Sep 09 09:48:16 AM UTC 24 |
11331577 ps |
| T149 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1358168419 |
|
|
Sep 09 09:48:13 AM UTC 24 |
Sep 09 09:48:17 AM UTC 24 |
176545907 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3968264716 |
|
|
Sep 09 09:48:17 AM UTC 24 |
Sep 09 09:48:19 AM UTC 24 |
22605372 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.816664740 |
|
|
Sep 09 09:47:02 AM UTC 24 |
Sep 09 09:48:22 AM UTC 24 |
117569664581 ps |
| T98 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3268890178 |
|
|
Sep 09 09:46:50 AM UTC 24 |
Sep 09 09:48:23 AM UTC 24 |
7264241129 ps |
| T99 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3920737204 |
|
|
Sep 09 09:47:11 AM UTC 24 |
Sep 09 09:48:23 AM UTC 24 |
7894605973 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1785441480 |
|
|
Sep 09 09:48:17 AM UTC 24 |
Sep 09 09:48:25 AM UTC 24 |
730359936 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3439416979 |
|
|
Sep 09 09:48:24 AM UTC 24 |
Sep 09 09:48:26 AM UTC 24 |
40367958 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2917335084 |
|
|
Sep 09 09:48:24 AM UTC 24 |
Sep 09 09:48:27 AM UTC 24 |
96833531 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1270914001 |
|
|
Sep 09 09:48:25 AM UTC 24 |
Sep 09 09:48:27 AM UTC 24 |
23604740 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.939011170 |
|
|
Sep 09 09:48:24 AM UTC 24 |
Sep 09 09:48:29 AM UTC 24 |
72642698 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1343340875 |
|
|
Sep 09 09:48:28 AM UTC 24 |
Sep 09 09:48:32 AM UTC 24 |
786574215 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3001345541 |
|
|
Sep 09 09:48:31 AM UTC 24 |
Sep 09 09:48:33 AM UTC 24 |
10874417 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.861661355 |
|
|
Sep 09 09:48:26 AM UTC 24 |
Sep 09 09:48:33 AM UTC 24 |
721349535 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3616221054 |
|
|
Sep 09 09:48:28 AM UTC 24 |
Sep 09 09:48:34 AM UTC 24 |
72088634 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.814709857 |
|
|
Sep 09 09:48:33 AM UTC 24 |
Sep 09 09:48:35 AM UTC 24 |
50239572 ps |
| T150 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3406739442 |
|
|
Sep 09 09:48:36 AM UTC 24 |
Sep 09 09:48:41 AM UTC 24 |
616833800 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1091146166 |
|
|
Sep 09 09:48:34 AM UTC 24 |
Sep 09 09:48:41 AM UTC 24 |
366984634 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3096486494 |
|
|
Sep 09 09:48:35 AM UTC 24 |
Sep 09 09:48:43 AM UTC 24 |
42516306 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1354180109 |
|
|
Sep 09 09:48:41 AM UTC 24 |
Sep 09 09:48:43 AM UTC 24 |
28641141 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.211169779 |
|
|
Sep 09 09:48:42 AM UTC 24 |
Sep 09 09:48:45 AM UTC 24 |
22019934 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2393116725 |
|
|
Sep 09 09:48:58 AM UTC 24 |
Sep 09 09:49:00 AM UTC 24 |
13033868 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.118471559 |
|
|
Sep 09 09:48:44 AM UTC 24 |
Sep 09 09:48:52 AM UTC 24 |
359263031 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1937168217 |
|
|
Sep 09 09:48:46 AM UTC 24 |
Sep 09 09:48:52 AM UTC 24 |
1714302546 ps |
| T146 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3741624309 |
|
|
Sep 09 09:48:50 AM UTC 24 |
Sep 09 09:48:54 AM UTC 24 |
207708703 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2064118992 |
|
|
Sep 09 09:48:52 AM UTC 24 |
Sep 09 09:48:54 AM UTC 24 |
31885168 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2550068932 |
|
|
Sep 09 09:47:36 AM UTC 24 |
Sep 09 09:48:55 AM UTC 24 |
7085455683 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.152054983 |
|
|
Sep 09 09:48:53 AM UTC 24 |
Sep 09 09:48:55 AM UTC 24 |
58629633 ps |
| T147 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3595310330 |
|
|
Sep 09 09:48:56 AM UTC 24 |
Sep 09 09:48:59 AM UTC 24 |
115714297 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.714746564 |
|
|
Sep 09 09:48:58 AM UTC 24 |
Sep 09 09:49:00 AM UTC 24 |
21238952 ps |
| T100 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1908049152 |
|
|
Sep 09 09:48:27 AM UTC 24 |
Sep 09 09:49:01 AM UTC 24 |
8019127423 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2257344710 |
|
|
Sep 09 09:48:55 AM UTC 24 |
Sep 09 09:49:02 AM UTC 24 |
1462321649 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3316091639 |
|
|
Sep 09 09:48:56 AM UTC 24 |
Sep 09 09:49:04 AM UTC 24 |
141576990 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1696871599 |
|
|
Sep 09 09:49:03 AM UTC 24 |
Sep 09 09:49:05 AM UTC 24 |
13446401 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2165211593 |
|
|
Sep 09 09:49:02 AM UTC 24 |
Sep 09 09:49:06 AM UTC 24 |
158732317 ps |
| T153 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3065585998 |
|
|
Sep 09 09:49:02 AM UTC 24 |
Sep 09 09:49:06 AM UTC 24 |
224280854 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.928710998 |
|
|
Sep 09 09:49:05 AM UTC 24 |
Sep 09 09:49:08 AM UTC 24 |
21340633 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3434589720 |
|
|
Sep 09 09:48:20 AM UTC 24 |
Sep 09 09:49:08 AM UTC 24 |
3870537502 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3517336145 |
|
|
Sep 09 09:49:01 AM UTC 24 |
Sep 09 09:49:08 AM UTC 24 |
377324649 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.4113846924 |
|
|
Sep 09 09:49:09 AM UTC 24 |
Sep 09 09:49:11 AM UTC 24 |
17652662 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2308227210 |
|
|
Sep 09 09:49:09 AM UTC 24 |
Sep 09 09:49:11 AM UTC 24 |
19040439 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.920155578 |
|
|
Sep 09 09:49:08 AM UTC 24 |
Sep 09 09:49:12 AM UTC 24 |
82652570 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3176042476 |
|
|
Sep 09 09:49:08 AM UTC 24 |
Sep 09 09:49:12 AM UTC 24 |
463726983 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3197810961 |
|
|
Sep 09 09:48:34 AM UTC 24 |
Sep 09 09:49:14 AM UTC 24 |
15408779706 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3192778756 |
|
|
Sep 09 09:49:07 AM UTC 24 |
Sep 09 09:49:14 AM UTC 24 |
356744971 ps |
| T145 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2803788174 |
|
|
Sep 09 09:49:14 AM UTC 24 |
Sep 09 09:49:17 AM UTC 24 |
119747212 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1387852168 |
|
|
Sep 09 09:49:15 AM UTC 24 |
Sep 09 09:49:18 AM UTC 24 |
38220510 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2154646461 |
|
|
Sep 09 09:49:15 AM UTC 24 |
Sep 09 09:49:18 AM UTC 24 |
17964900 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2514694958 |
|
|
Sep 09 09:49:14 AM UTC 24 |
Sep 09 09:49:20 AM UTC 24 |
493037691 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.343888688 |
|
|
Sep 09 09:49:13 AM UTC 24 |
Sep 09 09:49:21 AM UTC 24 |
1377529982 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.948965705 |
|
|
Sep 09 09:49:18 AM UTC 24 |
Sep 09 09:49:21 AM UTC 24 |
57248934 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2115888729 |
|
|
Sep 09 09:49:19 AM UTC 24 |
Sep 09 09:49:21 AM UTC 24 |
49727231 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3741474874 |
|
|
Sep 09 09:49:21 AM UTC 24 |
Sep 09 09:49:24 AM UTC 24 |
68924393 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.781047248 |
|
|
Sep 09 09:49:16 AM UTC 24 |
Sep 09 09:49:24 AM UTC 24 |
373476258 ps |