| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.94 | 99.19 | 94.27 | 99.72 | 100.00 | 96.03 | 99.12 | 97.26 |
| T1011 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.730244314 | Sep 09 09:49:19 AM UTC 24 | Sep 09 09:49:24 AM UTC 24 | 237517944 ps | ||
| T101 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2008458932 | Sep 09 09:49:25 AM UTC 24 | Sep 09 09:49:27 AM UTC 24 | 93117616 ps | ||
| T1012 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1130249595 | Sep 09 09:49:25 AM UTC 24 | Sep 09 09:49:27 AM UTC 24 | 21302439 ps | ||
| T102 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1575206583 | Sep 09 09:47:50 AM UTC 24 | Sep 09 09:49:27 AM UTC 24 | 14402721774 ps | ||
| T103 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2168635177 | Sep 09 09:48:45 AM UTC 24 | Sep 09 09:49:28 AM UTC 24 | 3720199333 ps | ||
| T148 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2110102541 | Sep 09 09:49:25 AM UTC 24 | Sep 09 09:49:29 AM UTC 24 | 361719100 ps | ||
| T1013 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.408350002 | Sep 09 09:49:22 AM UTC 24 | Sep 09 09:49:30 AM UTC 24 | 472634638 ps | ||
| T1014 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2326938022 | Sep 09 09:49:22 AM UTC 24 | Sep 09 09:49:30 AM UTC 24 | 379943114 ps | ||
| T1015 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2944493440 | Sep 09 09:49:30 AM UTC 24 | Sep 09 09:49:32 AM UTC 24 | 18810065 ps | ||
| T1016 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.147888327 | Sep 09 09:49:30 AM UTC 24 | Sep 09 09:49:32 AM UTC 24 | 16407407 ps | ||
| T1017 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2207535632 | Sep 09 09:49:28 AM UTC 24 | Sep 09 09:49:32 AM UTC 24 | 119470953 ps | ||
| T109 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1583069599 | Sep 09 09:48:56 AM UTC 24 | Sep 09 09:49:32 AM UTC 24 | 7543909346 ps | ||
| T1018 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.414602708 | Sep 09 09:49:25 AM UTC 24 | Sep 09 09:49:33 AM UTC 24 | 902693740 ps | ||
| T110 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2779187689 | Sep 09 09:48:04 AM UTC 24 | Sep 09 09:49:34 AM UTC 24 | 29440320877 ps | ||
| T1019 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2100792613 | Sep 09 09:49:28 AM UTC 24 | Sep 09 09:49:35 AM UTC 24 | 836653401 ps | ||
| T1020 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3449193498 | Sep 09 09:49:34 AM UTC 24 | Sep 09 09:49:36 AM UTC 24 | 15970851 ps | ||
| T1021 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3042070500 | Sep 09 09:49:32 AM UTC 24 | Sep 09 09:49:36 AM UTC 24 | 329305516 ps | ||
| T1022 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3784477556 | Sep 09 09:49:34 AM UTC 24 | Sep 09 09:49:36 AM UTC 24 | 38744697 ps | ||
| T1023 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.114630325 | Sep 09 09:49:31 AM UTC 24 | Sep 09 09:49:36 AM UTC 24 | 368591557 ps | ||
| T1024 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1882678657 | Sep 09 09:49:32 AM UTC 24 | Sep 09 09:49:37 AM UTC 24 | 78371927 ps | ||
| T111 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.220746348 | Sep 09 09:49:38 AM UTC 24 | Sep 09 09:49:40 AM UTC 24 | 14535324 ps | ||
| T1025 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2328550734 | Sep 09 09:49:38 AM UTC 24 | Sep 09 09:49:40 AM UTC 24 | 18289546 ps | ||
| T1026 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3306959132 | Sep 09 09:49:36 AM UTC 24 | Sep 09 09:49:40 AM UTC 24 | 24304890 ps | ||
| T1027 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1026607163 | Sep 09 09:49:34 AM UTC 24 | Sep 09 09:49:40 AM UTC 24 | 384554932 ps | ||
| T152 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3739927501 | Sep 09 09:49:38 AM UTC 24 | Sep 09 09:49:42 AM UTC 24 | 165019416 ps | ||
| T1028 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.673749070 | Sep 09 09:49:38 AM UTC 24 | Sep 09 09:49:46 AM UTC 24 | 371332438 ps | ||
| T1029 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3669046291 | Sep 09 09:49:16 AM UTC 24 | Sep 09 09:49:53 AM UTC 24 | 14791385722 ps | ||
| T112 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1634216345 | Sep 09 09:49:02 AM UTC 24 | Sep 09 09:49:59 AM UTC 24 | 7251030211 ps | ||
| T113 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.943839782 | Sep 09 09:49:35 AM UTC 24 | Sep 09 09:50:06 AM UTC 24 | 6839635554 ps | ||
| T1030 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3887949007 | Sep 09 09:49:22 AM UTC 24 | Sep 09 09:50:09 AM UTC 24 | 15427549845 ps | ||
| T1031 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.452299235 | Sep 09 09:49:07 AM UTC 24 | Sep 09 09:50:09 AM UTC 24 | 28124585488 ps | ||
| T1032 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1847548202 | Sep 09 09:49:13 AM UTC 24 | Sep 09 09:50:12 AM UTC 24 | 23533360506 ps | ||
| T1033 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.670932546 | Sep 09 09:49:31 AM UTC 24 | Sep 09 09:50:16 AM UTC 24 | 16981901320 ps | ||
| T1034 | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2848766194 | Sep 09 09:49:28 AM UTC 24 | Sep 09 09:50:32 AM UTC 24 | 7507904607 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.2477497330 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 7929445292 ps |
| CPU time | 33.08 seconds |
| Started | Sep 09 08:03:15 AM UTC 24 |
| Finished | Sep 09 08:03:50 AM UTC 24 |
| Peak memory | 222180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477497330 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_escalation.2477497330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.2360895490 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 1898331432 ps |
| CPU time | 34.24 seconds |
| Started | Sep 09 08:04:04 AM UTC 24 |
| Finished | Sep 09 08:04:40 AM UTC 24 |
| Peak memory | 221132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360895490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.2360895490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.2950486138 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 538811499 ps |
| CPU time | 3.59 seconds |
| Started | Sep 09 08:03:44 AM UTC 24 |
| Finished | Sep 09 08:03:49 AM UTC 24 |
| Peak memory | 247756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950486138 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_sec_cm.2950486138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.1984847046 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 11139537997 ps |
| CPU time | 90.89 seconds |
| Started | Sep 09 08:03:49 AM UTC 24 |
| Finished | Sep 09 08:05:22 AM UTC 24 |
| Peak memory | 221236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984847046 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_mem_partial_access.1984847046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_regwen.843331399 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 24065023351 ps |
| CPU time | 188.06 seconds |
| Started | Sep 09 08:03:48 AM UTC 24 |
| Finished | Sep 09 08:06:59 AM UTC 24 |
| Peak memory | 348004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843331399 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.843331399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_smoke.1360666597 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 7323795046 ps |
| CPU time | 15.41 seconds |
| Started | Sep 09 08:03:45 AM UTC 24 |
| Finished | Sep 09 08:04:02 AM UTC 24 |
| Peak memory | 241704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360666597 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.1360666597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1343340875 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 786574215 ps |
| CPU time | 2.69 seconds |
| Started | Sep 09 09:48:28 AM UTC 24 |
| Finished | Sep 09 09:48:32 AM UTC 24 |
| Peak memory | 213348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343 340875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_ intg_err.1343340875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.2654665920 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 36396042668 ps |
| CPU time | 244.59 seconds |
| Started | Sep 09 08:03:51 AM UTC 24 |
| Finished | Sep 09 08:07:59 AM UTC 24 |
| Peak memory | 212036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654665920 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_partial_ac cess_b2b.2654665920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_executable.2278368496 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 11288475350 ps |
| CPU time | 939.27 seconds |
| Started | Sep 09 08:03:32 AM UTC 24 |
| Finished | Sep 09 08:19:21 AM UTC 24 |
| Peak memory | 390648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278368496 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executable.2278368496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.2522949501 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 2387570671 ps |
| CPU time | 4 seconds |
| Started | Sep 09 08:03:48 AM UTC 24 |
| Finished | Sep 09 08:03:53 AM UTC 24 |
| Peak memory | 212012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522949501 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.2522949501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3268890178 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 7264241129 ps |
| CPU time | 91.17 seconds |
| Started | Sep 09 09:46:50 AM UTC 24 |
| Finished | Sep 09 09:48:23 AM UTC 24 |
| Peak memory | 213392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 268890178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ passthru_mem_tl_intg_err.3268890178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_regwen.3335543092 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1199498890 ps |
| CPU time | 212.12 seconds |
| Started | Sep 09 08:03:42 AM UTC 24 |
| Finished | Sep 09 08:07:17 AM UTC 24 |
| Peak memory | 386848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335543092 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.3335543092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3398847282 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 679029296 ps |
| CPU time | 3.08 seconds |
| Started | Sep 09 09:46:51 AM UTC 24 |
| Finished | Sep 09 09:46:55 AM UTC 24 |
| Peak memory | 223524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398 847282 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_tl_ intg_err.3398847282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_regwen.1839283014 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 65959401149 ps |
| CPU time | 800.82 seconds |
| Started | Sep 09 08:03:51 AM UTC 24 |
| Finished | Sep 09 08:17:21 AM UTC 24 |
| Peak memory | 388988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839283014 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.1839283014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_alert_test.1729250817 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 16499453 ps |
| CPU time | 0.89 seconds |
| Started | Sep 09 08:03:44 AM UTC 24 |
| Finished | Sep 09 08:03:46 AM UTC 24 |
| Peak memory | 210996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729250817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_alert_test.1729250817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.3768478288 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 4921893690 ps |
| CPU time | 26.21 seconds |
| Started | Sep 09 08:35:31 AM UTC 24 |
| Finished | Sep 09 08:35:58 AM UTC 24 |
| Peak memory | 222248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768478288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.3768478288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/21.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3595310330 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 115714297 ps |
| CPU time | 2.19 seconds |
| Started | Sep 09 09:48:56 AM UTC 24 |
| Finished | Sep 09 09:48:59 AM UTC 24 |
| Peak memory | 223600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595 310330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl _intg_err.3595310330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all.323181055 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 79390436687 ps |
| CPU time | 417.19 seconds |
| Started | Sep 09 08:05:23 AM UTC 24 |
| Finished | Sep 09 08:12:26 AM UTC 24 |
| Peak memory | 354428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32318105 5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all.323181055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3753620047 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 19191761 ps |
| CPU time | 1.02 seconds |
| Started | Sep 09 09:46:59 AM UTC 24 |
| Finished | Sep 09 09:47:01 AM UTC 24 |
| Peak memory | 212476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3753620047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram _ctrl_same_csr_outstanding.3753620047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.4136666043 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 26112462122 ps |
| CPU time | 394.84 seconds |
| Started | Sep 09 08:03:47 AM UTC 24 |
| Finished | Sep 09 08:10:27 AM UTC 24 |
| Peak memory | 211920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136666043 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_partial_ac cess_b2b.4136666043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3065585998 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 224280854 ps |
| CPU time | 3.19 seconds |
| Started | Sep 09 09:49:02 AM UTC 24 |
| Finished | Sep 09 09:49:06 AM UTC 24 |
| Peak memory | 223528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065 585998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl _intg_err.3065585998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access.1014568472 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 3894018177 ps |
| CPU time | 13.04 seconds |
| Started | Sep 09 08:02:58 AM UTC 24 |
| Finished | Sep 09 08:03:13 AM UTC 24 |
| Peak memory | 212096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014568472 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_partial_access.1014568472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_executable.3481780082 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 5360648361 ps |
| CPU time | 373.85 seconds |
| Started | Sep 09 08:15:24 AM UTC 24 |
| Finished | Sep 09 08:21:42 AM UTC 24 |
| Peak memory | 356380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481780082 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executable.3481780082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all.1159154091 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 408475109735 ps |
| CPU time | 2386.95 seconds |
| Started | Sep 09 08:16:02 AM UTC 24 |
| Finished | Sep 09 08:56:15 AM UTC 24 |
| Peak memory | 392700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11591540 91 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_a ll.1159154091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.779782087 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 30271778 ps |
| CPU time | 1.13 seconds |
| Started | Sep 09 09:46:59 AM UTC 24 |
| Finished | Sep 09 09:47:01 AM UTC 24 |
| Peak memory | 212520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7797820 87 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_ali asing.779782087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2306030330 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 280595400 ps |
| CPU time | 2.81 seconds |
| Started | Sep 09 09:46:57 AM UTC 24 |
| Finished | Sep 09 09:47:01 AM UTC 24 |
| Peak memory | 213296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306030 330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_bi t_bash.2306030330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1278456786 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 53761347 ps |
| CPU time | 0.98 seconds |
| Started | Sep 09 09:46:54 AM UTC 24 |
| Finished | Sep 09 09:46:56 AM UTC 24 |
| Peak memory | 212988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278456 786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_hw _reset.1278456786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2223699099 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 1332160153 ps |
| CPU time | 6.21 seconds |
| Started | Sep 09 09:47:01 AM UTC 24 |
| Finished | Sep 09 09:47:09 AM UTC 24 |
| Peak memory | 223440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=2223699099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.2223699099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.326656827 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 100991121 ps |
| CPU time | 1.06 seconds |
| Started | Sep 09 09:46:56 AM UTC 24 |
| Finished | Sep 09 09:46:58 AM UTC 24 |
| Peak memory | 212932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326656827 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_rw.326656827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2153090999 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 136655409 ps |
| CPU time | 6.23 seconds |
| Started | Sep 09 09:46:51 AM UTC 24 |
| Finished | Sep 09 09:46:58 AM UTC 24 |
| Peak memory | 223560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153090999 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_tl_errors.2153090999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.450527380 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 44503080 ps |
| CPU time | 1.04 seconds |
| Started | Sep 09 09:47:09 AM UTC 24 |
| Finished | Sep 09 09:47:11 AM UTC 24 |
| Peak memory | 212408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4505273 80 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_ali asing.450527380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.796959038 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 67740580 ps |
| CPU time | 1.98 seconds |
| Started | Sep 09 09:47:08 AM UTC 24 |
| Finished | Sep 09 09:47:11 AM UTC 24 |
| Peak memory | 212892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7969590 38 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_bit _bash.796959038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.4205872414 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 74540210 ps |
| CPU time | 1.05 seconds |
| Started | Sep 09 09:47:04 AM UTC 24 |
| Finished | Sep 09 09:47:06 AM UTC 24 |
| Peak memory | 212420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205872 414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_hw _reset.4205872414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.4158012526 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 374601821 ps |
| CPU time | 9 seconds |
| Started | Sep 09 09:47:10 AM UTC 24 |
| Finished | Sep 09 09:47:20 AM UTC 24 |
| Peak memory | 223588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=4158012526 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.4158012526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2766551116 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 39667272 ps |
| CPU time | 0.94 seconds |
| Started | Sep 09 09:47:07 AM UTC 24 |
| Finished | Sep 09 09:47:09 AM UTC 24 |
| Peak memory | 212408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766551116 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_rw.2766551116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.816664740 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 117569664581 ps |
| CPU time | 77.88 seconds |
| Started | Sep 09 09:47:02 AM UTC 24 |
| Finished | Sep 09 09:48:22 AM UTC 24 |
| Peak memory | 213344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8 16664740 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_p assthru_mem_tl_intg_err.816664740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.61107819 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 20742048 ps |
| CPU time | 1.19 seconds |
| Started | Sep 09 09:47:10 AM UTC 24 |
| Finished | Sep 09 09:47:12 AM UTC 24 |
| Peak memory | 212472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=61107819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_c trl_same_csr_outstanding.61107819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1298845910 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 161570757 ps |
| CPU time | 6.1 seconds |
| Started | Sep 09 09:47:03 AM UTC 24 |
| Finished | Sep 09 09:47:10 AM UTC 24 |
| Peak memory | 223644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298845910 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_errors.1298845910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.962079567 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 304255560 ps |
| CPU time | 2.11 seconds |
| Started | Sep 09 09:47:04 AM UTC 24 |
| Finished | Sep 09 09:47:07 AM UTC 24 |
| Peak memory | 223592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9620 79567 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_i ntg_err.962079567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2257344710 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 1462321649 ps |
| CPU time | 6.05 seconds |
| Started | Sep 09 09:48:55 AM UTC 24 |
| Finished | Sep 09 09:49:02 AM UTC 24 |
| Peak memory | 223568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=2257344710 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.2257344710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2064118992 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 31885168 ps |
| CPU time | 0.95 seconds |
| Started | Sep 09 09:48:52 AM UTC 24 |
| Finished | Sep 09 09:48:54 AM UTC 24 |
| Peak memory | 212752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064118992 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_rw.2064118992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2168635177 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 3720199333 ps |
| CPU time | 41.81 seconds |
| Started | Sep 09 09:48:45 AM UTC 24 |
| Finished | Sep 09 09:49:28 AM UTC 24 |
| Peak memory | 213328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 168635177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl _passthru_mem_tl_intg_err.2168635177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.152054983 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 58629633 ps |
| CPU time | 0.92 seconds |
| Started | Sep 09 09:48:53 AM UTC 24 |
| Finished | Sep 09 09:48:55 AM UTC 24 |
| Peak memory | 212752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=152054983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram _ctrl_same_csr_outstanding.152054983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1937168217 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 1714302546 ps |
| CPU time | 5.54 seconds |
| Started | Sep 09 09:48:46 AM UTC 24 |
| Finished | Sep 09 09:48:52 AM UTC 24 |
| Peak memory | 223580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937168217 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl_errors.1937168217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3741624309 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 207708703 ps |
| CPU time | 2.88 seconds |
| Started | Sep 09 09:48:50 AM UTC 24 |
| Finished | Sep 09 09:48:54 AM UTC 24 |
| Peak memory | 223504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741 624309 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl _intg_err.3741624309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3517336145 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 377324649 ps |
| CPU time | 6.05 seconds |
| Started | Sep 09 09:49:01 AM UTC 24 |
| Finished | Sep 09 09:49:08 AM UTC 24 |
| Peak memory | 223432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=3517336145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.3517336145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2393116725 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 13033868 ps |
| CPU time | 0.96 seconds |
| Started | Sep 09 09:48:58 AM UTC 24 |
| Finished | Sep 09 09:49:00 AM UTC 24 |
| Peak memory | 212692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393116725 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_rw.2393116725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.1583069599 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 7543909346 ps |
| CPU time | 34.84 seconds |
| Started | Sep 09 09:48:56 AM UTC 24 |
| Finished | Sep 09 09:49:32 AM UTC 24 |
| Peak memory | 213328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 583069599 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl _passthru_mem_tl_intg_err.1583069599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.714746564 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 21238952 ps |
| CPU time | 1.11 seconds |
| Started | Sep 09 09:48:58 AM UTC 24 |
| Finished | Sep 09 09:49:00 AM UTC 24 |
| Peak memory | 212752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=714746564 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram _ctrl_same_csr_outstanding.714746564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3316091639 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 141576990 ps |
| CPU time | 6.92 seconds |
| Started | Sep 09 09:48:56 AM UTC 24 |
| Finished | Sep 09 09:49:04 AM UTC 24 |
| Peak memory | 223780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316091639 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl_errors.3316091639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3192778756 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 356744971 ps |
| CPU time | 6.15 seconds |
| Started | Sep 09 09:49:07 AM UTC 24 |
| Finished | Sep 09 09:49:14 AM UTC 24 |
| Peak memory | 223592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=3192778756 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.3192778756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1696871599 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 13446401 ps |
| CPU time | 0.98 seconds |
| Started | Sep 09 09:49:03 AM UTC 24 |
| Finished | Sep 09 09:49:05 AM UTC 24 |
| Peak memory | 212408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696871599 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_rw.1696871599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1634216345 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 7251030211 ps |
| CPU time | 55.12 seconds |
| Started | Sep 09 09:49:02 AM UTC 24 |
| Finished | Sep 09 09:49:59 AM UTC 24 |
| Peak memory | 213404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 634216345 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl _passthru_mem_tl_intg_err.1634216345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.928710998 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 21340633 ps |
| CPU time | 1.16 seconds |
| Started | Sep 09 09:49:05 AM UTC 24 |
| Finished | Sep 09 09:49:08 AM UTC 24 |
| Peak memory | 212476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=928710998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram _ctrl_same_csr_outstanding.928710998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2165211593 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 158732317 ps |
| CPU time | 3.01 seconds |
| Started | Sep 09 09:49:02 AM UTC 24 |
| Finished | Sep 09 09:49:06 AM UTC 24 |
| Peak memory | 213348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165211593 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl_errors.2165211593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.343888688 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 1377529982 ps |
| CPU time | 7.02 seconds |
| Started | Sep 09 09:49:13 AM UTC 24 |
| Finished | Sep 09 09:49:21 AM UTC 24 |
| Peak memory | 223644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=343888688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.343888688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.4113846924 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 17652662 ps |
| CPU time | 0.95 seconds |
| Started | Sep 09 09:49:09 AM UTC 24 |
| Finished | Sep 09 09:49:11 AM UTC 24 |
| Peak memory | 212408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113846924 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_rw.4113846924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.452299235 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 28124585488 ps |
| CPU time | 60.82 seconds |
| Started | Sep 09 09:49:07 AM UTC 24 |
| Finished | Sep 09 09:50:09 AM UTC 24 |
| Peak memory | 213384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4 52299235 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ passthru_mem_tl_intg_err.452299235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2308227210 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 19040439 ps |
| CPU time | 1.12 seconds |
| Started | Sep 09 09:49:09 AM UTC 24 |
| Finished | Sep 09 09:49:11 AM UTC 24 |
| Peak memory | 212584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2308227210 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sra m_ctrl_same_csr_outstanding.2308227210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.920155578 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 82652570 ps |
| CPU time | 3.38 seconds |
| Started | Sep 09 09:49:08 AM UTC 24 |
| Finished | Sep 09 09:49:12 AM UTC 24 |
| Peak memory | 213544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920155578 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl_errors.920155578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3176042476 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 463726983 ps |
| CPU time | 3.37 seconds |
| Started | Sep 09 09:49:08 AM UTC 24 |
| Finished | Sep 09 09:49:12 AM UTC 24 |
| Peak memory | 223456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176 042476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl _intg_err.3176042476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.781047248 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 373476258 ps |
| CPU time | 6.5 seconds |
| Started | Sep 09 09:49:16 AM UTC 24 |
| Finished | Sep 09 09:49:24 AM UTC 24 |
| Peak memory | 225492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=781047248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.781047248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1387852168 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 38220510 ps |
| CPU time | 1.05 seconds |
| Started | Sep 09 09:49:15 AM UTC 24 |
| Finished | Sep 09 09:49:18 AM UTC 24 |
| Peak memory | 212408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387852168 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_rw.1387852168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1847548202 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 23533360506 ps |
| CPU time | 57.84 seconds |
| Started | Sep 09 09:49:13 AM UTC 24 |
| Finished | Sep 09 09:50:12 AM UTC 24 |
| Peak memory | 213456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 847548202 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl _passthru_mem_tl_intg_err.1847548202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2154646461 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 17964900 ps |
| CPU time | 1.18 seconds |
| Started | Sep 09 09:49:15 AM UTC 24 |
| Finished | Sep 09 09:49:18 AM UTC 24 |
| Peak memory | 212472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2154646461 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sra m_ctrl_same_csr_outstanding.2154646461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2514694958 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 493037691 ps |
| CPU time | 4.87 seconds |
| Started | Sep 09 09:49:14 AM UTC 24 |
| Finished | Sep 09 09:49:20 AM UTC 24 |
| Peak memory | 223652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514694958 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_tl_errors.2514694958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2803788174 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 119747212 ps |
| CPU time | 1.93 seconds |
| Started | Sep 09 09:49:14 AM UTC 24 |
| Finished | Sep 09 09:49:17 AM UTC 24 |
| Peak memory | 222716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803 788174 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_tl _intg_err.2803788174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2326938022 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 379943114 ps |
| CPU time | 5.58 seconds |
| Started | Sep 09 09:49:22 AM UTC 24 |
| Finished | Sep 09 09:49:30 AM UTC 24 |
| Peak memory | 223512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=2326938022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.2326938022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2115888729 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 49727231 ps |
| CPU time | 0.99 seconds |
| Started | Sep 09 09:49:19 AM UTC 24 |
| Finished | Sep 09 09:49:21 AM UTC 24 |
| Peak memory | 212408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115888729 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_rw.2115888729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3669046291 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 14791385722 ps |
| CPU time | 34.81 seconds |
| Started | Sep 09 09:49:16 AM UTC 24 |
| Finished | Sep 09 09:49:53 AM UTC 24 |
| Peak memory | 213244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 669046291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl _passthru_mem_tl_intg_err.3669046291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3741474874 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 68924393 ps |
| CPU time | 1.14 seconds |
| Started | Sep 09 09:49:21 AM UTC 24 |
| Finished | Sep 09 09:49:24 AM UTC 24 |
| Peak memory | 212472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3741474874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sra m_ctrl_same_csr_outstanding.3741474874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.948965705 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 57248934 ps |
| CPU time | 2.61 seconds |
| Started | Sep 09 09:49:18 AM UTC 24 |
| Finished | Sep 09 09:49:21 AM UTC 24 |
| Peak memory | 213536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948965705 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl_errors.948965705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.730244314 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 237517944 ps |
| CPU time | 4.01 seconds |
| Started | Sep 09 09:49:19 AM UTC 24 |
| Finished | Sep 09 09:49:24 AM UTC 24 |
| Peak memory | 223532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7302 44314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl_ intg_err.730244314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.414602708 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 902693740 ps |
| CPU time | 6.3 seconds |
| Started | Sep 09 09:49:25 AM UTC 24 |
| Finished | Sep 09 09:49:33 AM UTC 24 |
| Peak memory | 223520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=414602708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.414602708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2008458932 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 93117616 ps |
| CPU time | 0.99 seconds |
| Started | Sep 09 09:49:25 AM UTC 24 |
| Finished | Sep 09 09:49:27 AM UTC 24 |
| Peak memory | 212692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008458932 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_rw.2008458932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3887949007 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 15427549845 ps |
| CPU time | 44.26 seconds |
| Started | Sep 09 09:49:22 AM UTC 24 |
| Finished | Sep 09 09:50:09 AM UTC 24 |
| Peak memory | 213260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 887949007 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl _passthru_mem_tl_intg_err.3887949007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1130249595 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 21302439 ps |
| CPU time | 1.03 seconds |
| Started | Sep 09 09:49:25 AM UTC 24 |
| Finished | Sep 09 09:49:27 AM UTC 24 |
| Peak memory | 212472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1130249595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sra m_ctrl_same_csr_outstanding.1130249595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.408350002 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 472634638 ps |
| CPU time | 5.21 seconds |
| Started | Sep 09 09:49:22 AM UTC 24 |
| Finished | Sep 09 09:49:30 AM UTC 24 |
| Peak memory | 223580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408350002 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl_errors.408350002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2110102541 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 361719100 ps |
| CPU time | 2.66 seconds |
| Started | Sep 09 09:49:25 AM UTC 24 |
| Finished | Sep 09 09:49:29 AM UTC 24 |
| Peak memory | 223532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110 102541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl _intg_err.2110102541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.114630325 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 368591557 ps |
| CPU time | 4.29 seconds |
| Started | Sep 09 09:49:31 AM UTC 24 |
| Finished | Sep 09 09:49:36 AM UTC 24 |
| Peak memory | 223516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=114630325 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.114630325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2944493440 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 18810065 ps |
| CPU time | 1 seconds |
| Started | Sep 09 09:49:30 AM UTC 24 |
| Finished | Sep 09 09:49:32 AM UTC 24 |
| Peak memory | 212408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944493440 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_rw.2944493440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2848766194 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 7507904607 ps |
| CPU time | 61.99 seconds |
| Started | Sep 09 09:49:28 AM UTC 24 |
| Finished | Sep 09 09:50:32 AM UTC 24 |
| Peak memory | 213380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 848766194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl _passthru_mem_tl_intg_err.2848766194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.147888327 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 16407407 ps |
| CPU time | 1.1 seconds |
| Started | Sep 09 09:49:30 AM UTC 24 |
| Finished | Sep 09 09:49:32 AM UTC 24 |
| Peak memory | 212752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=147888327 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram _ctrl_same_csr_outstanding.147888327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2100792613 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 836653401 ps |
| CPU time | 5.93 seconds |
| Started | Sep 09 09:49:28 AM UTC 24 |
| Finished | Sep 09 09:49:35 AM UTC 24 |
| Peak memory | 225636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100792613 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_errors.2100792613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2207535632 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 119470953 ps |
| CPU time | 2.55 seconds |
| Started | Sep 09 09:49:28 AM UTC 24 |
| Finished | Sep 09 09:49:32 AM UTC 24 |
| Peak memory | 213348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207 535632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl _intg_err.2207535632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1026607163 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 384554932 ps |
| CPU time | 5.34 seconds |
| Started | Sep 09 09:49:34 AM UTC 24 |
| Finished | Sep 09 09:49:40 AM UTC 24 |
| Peak memory | 223444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=1026607163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.1026607163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3449193498 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 15970851 ps |
| CPU time | 1.07 seconds |
| Started | Sep 09 09:49:34 AM UTC 24 |
| Finished | Sep 09 09:49:36 AM UTC 24 |
| Peak memory | 212752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449193498 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_rw.3449193498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.670932546 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 16981901320 ps |
| CPU time | 43.42 seconds |
| Started | Sep 09 09:49:31 AM UTC 24 |
| Finished | Sep 09 09:50:16 AM UTC 24 |
| Peak memory | 213328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6 70932546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ passthru_mem_tl_intg_err.670932546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3784477556 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 38744697 ps |
| CPU time | 1.03 seconds |
| Started | Sep 09 09:49:34 AM UTC 24 |
| Finished | Sep 09 09:49:36 AM UTC 24 |
| Peak memory | 212472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3784477556 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sra m_ctrl_same_csr_outstanding.3784477556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1882678657 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 78371927 ps |
| CPU time | 4.07 seconds |
| Started | Sep 09 09:49:32 AM UTC 24 |
| Finished | Sep 09 09:49:37 AM UTC 24 |
| Peak memory | 213412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882678657 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_tl_errors.1882678657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3042070500 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 329305516 ps |
| CPU time | 2.89 seconds |
| Started | Sep 09 09:49:32 AM UTC 24 |
| Finished | Sep 09 09:49:36 AM UTC 24 |
| Peak memory | 223532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042 070500 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_tl _intg_err.3042070500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.673749070 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 371332438 ps |
| CPU time | 7.49 seconds |
| Started | Sep 09 09:49:38 AM UTC 24 |
| Finished | Sep 09 09:49:46 AM UTC 24 |
| Peak memory | 223568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=673749070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.673749070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.220746348 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 14535324 ps |
| CPU time | 0.91 seconds |
| Started | Sep 09 09:49:38 AM UTC 24 |
| Finished | Sep 09 09:49:40 AM UTC 24 |
| Peak memory | 212408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220746348 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_rw.220746348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.943839782 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 6839635554 ps |
| CPU time | 30.01 seconds |
| Started | Sep 09 09:49:35 AM UTC 24 |
| Finished | Sep 09 09:50:06 AM UTC 24 |
| Peak memory | 213248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9 43839782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ passthru_mem_tl_intg_err.943839782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2328550734 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 18289546 ps |
| CPU time | 1.06 seconds |
| Started | Sep 09 09:49:38 AM UTC 24 |
| Finished | Sep 09 09:49:40 AM UTC 24 |
| Peak memory | 212472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2328550734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sra m_ctrl_same_csr_outstanding.2328550734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3306959132 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 24304890 ps |
| CPU time | 2.69 seconds |
| Started | Sep 09 09:49:36 AM UTC 24 |
| Finished | Sep 09 09:49:40 AM UTC 24 |
| Peak memory | 213336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306959132 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl_errors.3306959132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3739927501 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 165019416 ps |
| CPU time | 3.31 seconds |
| Started | Sep 09 09:49:38 AM UTC 24 |
| Finished | Sep 09 09:49:42 AM UTC 24 |
| Peak memory | 223544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739 927501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl _intg_err.3739927501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.748282670 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 34436864 ps |
| CPU time | 1.02 seconds |
| Started | Sep 09 09:47:21 AM UTC 24 |
| Finished | Sep 09 09:47:23 AM UTC 24 |
| Peak memory | 212988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7482826 70 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_ali asing.748282670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2549364997 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 446139698 ps |
| CPU time | 3.21 seconds |
| Started | Sep 09 09:47:21 AM UTC 24 |
| Finished | Sep 09 09:47:25 AM UTC 24 |
| Peak memory | 213296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549364 997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_bi t_bash.2549364997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2553478592 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 23864704 ps |
| CPU time | 0.85 seconds |
| Started | Sep 09 09:47:17 AM UTC 24 |
| Finished | Sep 09 09:47:19 AM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553478 592 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_hw _reset.2553478592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3379709561 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 4898858440 ps |
| CPU time | 9.44 seconds |
| Started | Sep 09 09:47:24 AM UTC 24 |
| Finished | Sep 09 09:47:34 AM UTC 24 |
| Peak memory | 223768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=3379709561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.3379709561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1265302495 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 26437727 ps |
| CPU time | 1.02 seconds |
| Started | Sep 09 09:47:19 AM UTC 24 |
| Finished | Sep 09 09:47:21 AM UTC 24 |
| Peak memory | 212988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265302495 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_rw.1265302495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3920737204 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 7894605973 ps |
| CPU time | 70.11 seconds |
| Started | Sep 09 09:47:11 AM UTC 24 |
| Finished | Sep 09 09:48:23 AM UTC 24 |
| Peak memory | 213452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 920737204 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ passthru_mem_tl_intg_err.3920737204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3820336260 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 47348215 ps |
| CPU time | 1.03 seconds |
| Started | Sep 09 09:47:23 AM UTC 24 |
| Finished | Sep 09 09:47:25 AM UTC 24 |
| Peak memory | 212752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3820336260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram _ctrl_same_csr_outstanding.3820336260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.622369848 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 340953430 ps |
| CPU time | 3.86 seconds |
| Started | Sep 09 09:47:12 AM UTC 24 |
| Finished | Sep 09 09:47:17 AM UTC 24 |
| Peak memory | 213352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622369848 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_errors.622369848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.567221264 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 173579108 ps |
| CPU time | 3.99 seconds |
| Started | Sep 09 09:47:13 AM UTC 24 |
| Finished | Sep 09 09:47:18 AM UTC 24 |
| Peak memory | 223536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5672 21264 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_i ntg_err.567221264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3999353506 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 23803194 ps |
| CPU time | 1.18 seconds |
| Started | Sep 09 09:47:33 AM UTC 24 |
| Finished | Sep 09 09:47:36 AM UTC 24 |
| Peak memory | 212988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999353 506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_al iasing.3999353506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3687578577 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 36129197 ps |
| CPU time | 1.92 seconds |
| Started | Sep 09 09:47:31 AM UTC 24 |
| Finished | Sep 09 09:47:34 AM UTC 24 |
| Peak memory | 212880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687578 577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_bi t_bash.3687578577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.252197075 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 19309654 ps |
| CPU time | 1.06 seconds |
| Started | Sep 09 09:47:27 AM UTC 24 |
| Finished | Sep 09 09:47:29 AM UTC 24 |
| Peak memory | 212408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521970 75 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_hw_ reset.252197075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3102882227 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 749310161 ps |
| CPU time | 7.13 seconds |
| Started | Sep 09 09:47:36 AM UTC 24 |
| Finished | Sep 09 09:47:44 AM UTC 24 |
| Peak memory | 225548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=3102882227 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.3102882227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.4290462407 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 13984503 ps |
| CPU time | 1 seconds |
| Started | Sep 09 09:47:30 AM UTC 24 |
| Finished | Sep 09 09:47:32 AM UTC 24 |
| Peak memory | 212408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290462407 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_rw.4290462407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2516530198 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 7176631633 ps |
| CPU time | 48.23 seconds |
| Started | Sep 09 09:47:24 AM UTC 24 |
| Finished | Sep 09 09:48:13 AM UTC 24 |
| Peak memory | 213388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 516530198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ passthru_mem_tl_intg_err.2516530198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1117367173 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 18217629 ps |
| CPU time | 1.05 seconds |
| Started | Sep 09 09:47:35 AM UTC 24 |
| Finished | Sep 09 09:47:38 AM UTC 24 |
| Peak memory | 212476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1117367173 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram _ctrl_same_csr_outstanding.1117367173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.380920192 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 301327271 ps |
| CPU time | 7.09 seconds |
| Started | Sep 09 09:47:26 AM UTC 24 |
| Finished | Sep 09 09:47:34 AM UTC 24 |
| Peak memory | 225708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380920192 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_errors.380920192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2752365856 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 682523356 ps |
| CPU time | 2.98 seconds |
| Started | Sep 09 09:47:26 AM UTC 24 |
| Finished | Sep 09 09:47:30 AM UTC 24 |
| Peak memory | 223712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752 365856 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_ intg_err.2752365856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1431041913 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 43494607 ps |
| CPU time | 1.08 seconds |
| Started | Sep 09 09:47:47 AM UTC 24 |
| Finished | Sep 09 09:47:49 AM UTC 24 |
| Peak memory | 212752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431041 913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_al iasing.1431041913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3236973876 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 99035321 ps |
| CPU time | 2.37 seconds |
| Started | Sep 09 09:47:45 AM UTC 24 |
| Finished | Sep 09 09:47:49 AM UTC 24 |
| Peak memory | 213220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236973 876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_bi t_bash.3236973876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2934053289 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 16246945 ps |
| CPU time | 1.03 seconds |
| Started | Sep 09 09:47:44 AM UTC 24 |
| Finished | Sep 09 09:47:46 AM UTC 24 |
| Peak memory | 212416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934053 289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_hw _reset.2934053289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3600834163 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 2929083067 ps |
| CPU time | 8.25 seconds |
| Started | Sep 09 09:47:49 AM UTC 24 |
| Finished | Sep 09 09:47:59 AM UTC 24 |
| Peak memory | 223564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=3600834163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.3600834163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1591996807 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 51728530 ps |
| CPU time | 1.1 seconds |
| Started | Sep 09 09:47:45 AM UTC 24 |
| Finished | Sep 09 09:47:47 AM UTC 24 |
| Peak memory | 212752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591996807 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_rw.1591996807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2550068932 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 7085455683 ps |
| CPU time | 77.29 seconds |
| Started | Sep 09 09:47:36 AM UTC 24 |
| Finished | Sep 09 09:48:55 AM UTC 24 |
| Peak memory | 213404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 550068932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ passthru_mem_tl_intg_err.2550068932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1239964770 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 86140761 ps |
| CPU time | 1.24 seconds |
| Started | Sep 09 09:47:48 AM UTC 24 |
| Finished | Sep 09 09:47:51 AM UTC 24 |
| Peak memory | 212476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1239964770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram _ctrl_same_csr_outstanding.1239964770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.270011213 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 358507067 ps |
| CPU time | 5.93 seconds |
| Started | Sep 09 09:47:37 AM UTC 24 |
| Finished | Sep 09 09:47:44 AM UTC 24 |
| Peak memory | 223660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270011213 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_errors.270011213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1338908667 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 513290736 ps |
| CPU time | 2.56 seconds |
| Started | Sep 09 09:47:39 AM UTC 24 |
| Finished | Sep 09 09:47:43 AM UTC 24 |
| Peak memory | 223540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338 908667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_ intg_err.1338908667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2908235678 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 361454780 ps |
| CPU time | 4.71 seconds |
| Started | Sep 09 09:48:03 AM UTC 24 |
| Finished | Sep 09 09:48:09 AM UTC 24 |
| Peak memory | 223624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=2908235678 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.2908235678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.4074459146 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 59978442 ps |
| CPU time | 0.93 seconds |
| Started | Sep 09 09:48:00 AM UTC 24 |
| Finished | Sep 09 09:48:02 AM UTC 24 |
| Peak memory | 212408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074459146 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_rw.4074459146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1575206583 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 14402721774 ps |
| CPU time | 94.85 seconds |
| Started | Sep 09 09:47:50 AM UTC 24 |
| Finished | Sep 09 09:49:27 AM UTC 24 |
| Peak memory | 213580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 575206583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ passthru_mem_tl_intg_err.1575206583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3301115381 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 58890882 ps |
| CPU time | 1.11 seconds |
| Started | Sep 09 09:48:01 AM UTC 24 |
| Finished | Sep 09 09:48:03 AM UTC 24 |
| Peak memory | 212476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3301115381 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram _ctrl_same_csr_outstanding.3301115381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1517073748 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 80958791 ps |
| CPU time | 3.49 seconds |
| Started | Sep 09 09:47:52 AM UTC 24 |
| Finished | Sep 09 09:47:56 AM UTC 24 |
| Peak memory | 223664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517073748 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_errors.1517073748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2766588561 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 153481402 ps |
| CPU time | 2.28 seconds |
| Started | Sep 09 09:47:57 AM UTC 24 |
| Finished | Sep 09 09:48:00 AM UTC 24 |
| Peak memory | 213276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766 588561 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_ intg_err.2766588561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1785441480 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 730359936 ps |
| CPU time | 6.81 seconds |
| Started | Sep 09 09:48:17 AM UTC 24 |
| Finished | Sep 09 09:48:25 AM UTC 24 |
| Peak memory | 223648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=1785441480 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.1785441480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2512742899 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 11331577 ps |
| CPU time | 0.87 seconds |
| Started | Sep 09 09:48:14 AM UTC 24 |
| Finished | Sep 09 09:48:16 AM UTC 24 |
| Peak memory | 212408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512742899 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_rw.2512742899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2779187689 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 29440320877 ps |
| CPU time | 88.22 seconds |
| Started | Sep 09 09:48:04 AM UTC 24 |
| Finished | Sep 09 09:49:34 AM UTC 24 |
| Peak memory | 213344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2 779187689 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ passthru_mem_tl_intg_err.2779187689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3968264716 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 22605372 ps |
| CPU time | 1.09 seconds |
| Started | Sep 09 09:48:17 AM UTC 24 |
| Finished | Sep 09 09:48:19 AM UTC 24 |
| Peak memory | 212472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3968264716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram _ctrl_same_csr_outstanding.3968264716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1736450766 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 36706264 ps |
| CPU time | 2.49 seconds |
| Started | Sep 09 09:48:09 AM UTC 24 |
| Finished | Sep 09 09:48:13 AM UTC 24 |
| Peak memory | 213332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736450766 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_errors.1736450766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1358168419 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 176545907 ps |
| CPU time | 2.5 seconds |
| Started | Sep 09 09:48:13 AM UTC 24 |
| Finished | Sep 09 09:48:17 AM UTC 24 |
| Peak memory | 213240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358 168419 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_ intg_err.1358168419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.861661355 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 721349535 ps |
| CPU time | 5.88 seconds |
| Started | Sep 09 09:48:26 AM UTC 24 |
| Finished | Sep 09 09:48:33 AM UTC 24 |
| Peak memory | 223768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=861661355 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.861661355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3439416979 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 40367958 ps |
| CPU time | 0.95 seconds |
| Started | Sep 09 09:48:24 AM UTC 24 |
| Finished | Sep 09 09:48:26 AM UTC 24 |
| Peak memory | 212408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439416979 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_rw.3439416979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3434589720 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 3870537502 ps |
| CPU time | 45.63 seconds |
| Started | Sep 09 09:48:20 AM UTC 24 |
| Finished | Sep 09 09:49:08 AM UTC 24 |
| Peak memory | 213524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 434589720 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ passthru_mem_tl_intg_err.3434589720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1270914001 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 23604740 ps |
| CPU time | 0.99 seconds |
| Started | Sep 09 09:48:25 AM UTC 24 |
| Finished | Sep 09 09:48:27 AM UTC 24 |
| Peak memory | 212476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1270914001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram _ctrl_same_csr_outstanding.1270914001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.939011170 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 72642698 ps |
| CPU time | 4.57 seconds |
| Started | Sep 09 09:48:24 AM UTC 24 |
| Finished | Sep 09 09:48:29 AM UTC 24 |
| Peak memory | 213556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939011170 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_tl_errors.939011170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2917335084 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 96833531 ps |
| CPU time | 2.19 seconds |
| Started | Sep 09 09:48:24 AM UTC 24 |
| Finished | Sep 09 09:48:27 AM UTC 24 |
| Peak memory | 223540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917 335084 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_tl_ intg_err.2917335084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1091146166 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 366984634 ps |
| CPU time | 6.55 seconds |
| Started | Sep 09 09:48:34 AM UTC 24 |
| Finished | Sep 09 09:48:41 AM UTC 24 |
| Peak memory | 225688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=1091146166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd b -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.1091146166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3001345541 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 10874417 ps |
| CPU time | 1.03 seconds |
| Started | Sep 09 09:48:31 AM UTC 24 |
| Finished | Sep 09 09:48:33 AM UTC 24 |
| Peak memory | 212408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001345541 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_rw.3001345541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1908049152 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 8019127423 ps |
| CPU time | 32.41 seconds |
| Started | Sep 09 09:48:27 AM UTC 24 |
| Finished | Sep 09 09:49:01 AM UTC 24 |
| Peak memory | 213320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1 908049152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ passthru_mem_tl_intg_err.1908049152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.814709857 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 50239572 ps |
| CPU time | 1.17 seconds |
| Started | Sep 09 09:48:33 AM UTC 24 |
| Finished | Sep 09 09:48:35 AM UTC 24 |
| Peak memory | 212760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=814709857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ ctrl_same_csr_outstanding.814709857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3616221054 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 72088634 ps |
| CPU time | 4.17 seconds |
| Started | Sep 09 09:48:28 AM UTC 24 |
| Finished | Sep 09 09:48:34 AM UTC 24 |
| Peak memory | 223580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616221054 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_errors.3616221054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.118471559 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 359263031 ps |
| CPU time | 7.14 seconds |
| Started | Sep 09 09:48:44 AM UTC 24 |
| Finished | Sep 09 09:48:52 AM UTC 24 |
| Peak memory | 223776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000 00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re po/hw/dv/tools/sim.tcl +ntb_random_seed=118471559 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.118471559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1354180109 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 28641141 ps |
| CPU time | 1.08 seconds |
| Started | Sep 09 09:48:41 AM UTC 24 |
| Finished | Sep 09 09:48:43 AM UTC 24 |
| Peak memory | 212408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354180109 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_rw.1354180109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3197810961 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 15408779706 ps |
| CPU time | 38.5 seconds |
| Started | Sep 09 09:48:34 AM UTC 24 |
| Finished | Sep 09 09:49:14 AM UTC 24 |
| Peak memory | 213340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3 197810961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ passthru_mem_tl_intg_err.3197810961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.211169779 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 22019934 ps |
| CPU time | 1.07 seconds |
| Started | Sep 09 09:48:42 AM UTC 24 |
| Finished | Sep 09 09:48:45 AM UTC 24 |
| Peak memory | 212476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000 00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=211169779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ ctrl_same_csr_outstanding.211169779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3096486494 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 42516306 ps |
| CPU time | 6.47 seconds |
| Started | Sep 09 09:48:35 AM UTC 24 |
| Finished | Sep 09 09:48:43 AM UTC 24 |
| Peak memory | 213284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096486494 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_errors.3096486494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3406739442 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 616833800 ps |
| CPU time | 3.63 seconds |
| Started | Sep 09 09:48:36 AM UTC 24 |
| Finished | Sep 09 09:48:41 AM UTC 24 |
| Peak memory | 223660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406 739442 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_ intg_err.3406739442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.1193304196 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 13193284715 ps |
| CPU time | 597.68 seconds |
| Started | Sep 09 08:03:16 AM UTC 24 |
| Finished | Sep 09 08:13:21 AM UTC 24 |
| Peak memory | 390652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193304196 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_access_durin g_key_req.1193304196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_bijection.3180145993 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 22092896706 ps |
| CPU time | 680.48 seconds |
| Started | Sep 09 08:02:45 AM UTC 24 |
| Finished | Sep 09 08:14:13 AM UTC 24 |
| Peak memory | 213620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180145993 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.3180145993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.1828843793 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 2562511511 ps |
| CPU time | 11.78 seconds |
| Started | Sep 09 08:03:02 AM UTC 24 |
| Finished | Sep 09 08:03:15 AM UTC 24 |
| Peak memory | 247728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1828843793 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_m ax_throughput.1828843793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.3471559393 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 8435276562 ps |
| CPU time | 158.2 seconds |
| Started | Sep 09 08:03:44 AM UTC 24 |
| Finished | Sep 09 08:06:25 AM UTC 24 |
| Peak memory | 229308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471559393 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_mem_partial_access.3471559393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.3908435718 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 13276649799 ps |
| CPU time | 175.56 seconds |
| Started | Sep 09 08:03:43 AM UTC 24 |
| Finished | Sep 09 08:06:42 AM UTC 24 |
| Peak memory | 222180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908435718 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_mem_walk.3908435718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.2707502035 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 59638820500 ps |
| CPU time | 788.66 seconds |
| Started | Sep 09 08:02:43 AM UTC 24 |
| Finished | Sep 09 08:16:00 AM UTC 24 |
| Peak memory | 390652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707502035 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multiple_keys.2707502035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.3344526823 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 24813990156 ps |
| CPU time | 565.1 seconds |
| Started | Sep 09 08:03:00 AM UTC 24 |
| Finished | Sep 09 08:12:32 AM UTC 24 |
| Peak memory | 213704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344526823 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_partial_ac cess_b2b.3344526823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.3574540870 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 361114044 ps |
| CPU time | 4.02 seconds |
| Started | Sep 09 08:03:43 AM UTC 24 |
| Finished | Sep 09 08:03:48 AM UTC 24 |
| Peak memory | 211940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574540870 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.3574540870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_smoke.3389530582 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 740556555 ps |
| CPU time | 13.11 seconds |
| Started | Sep 09 08:02:43 AM UTC 24 |
| Finished | Sep 09 08:02:57 AM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389530582 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.3389530582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all.3537194487 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 123559756157 ps |
| CPU time | 3582.38 seconds |
| Started | Sep 09 08:03:44 AM UTC 24 |
| Finished | Sep 09 09:04:05 AM UTC 24 |
| Peak memory | 388616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35371944 87 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all.3537194487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2463732049 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 1001721717 ps |
| CPU time | 8.59 seconds |
| Started | Sep 09 08:03:44 AM UTC 24 |
| Finished | Sep 09 08:03:54 AM UTC 24 |
| Peak memory | 222396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463732049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.2463732049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.306013334 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 20028093445 ps |
| CPU time | 420.88 seconds |
| Started | Sep 09 08:02:57 AM UTC 24 |
| Finished | Sep 09 08:10:04 AM UTC 24 |
| Peak memory | 213644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306013334 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_pipeline.306013334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.1299199677 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 1566456394 ps |
| CPU time | 61.9 seconds |
| Started | Sep 09 08:03:14 AM UTC 24 |
| Finished | Sep 09 08:04:17 AM UTC 24 |
| Peak memory | 382828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1299199677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ throughput_w_partial_write.1299199677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.3758140137 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 10846547294 ps |
| CPU time | 554.05 seconds |
| Started | Sep 09 08:03:47 AM UTC 24 |
| Finished | Sep 09 08:13:07 AM UTC 24 |
| Peak memory | 386996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758140137 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_access_durin g_key_req.3758140137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_alert_test.4152120281 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 25340910 ps |
| CPU time | 0.98 seconds |
| Started | Sep 09 08:03:49 AM UTC 24 |
| Finished | Sep 09 08:03:51 AM UTC 24 |
| Peak memory | 210996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152120281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_alert_test.4152120281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_bijection.3024885257 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 387030808840 ps |
| CPU time | 2275.22 seconds |
| Started | Sep 09 08:03:45 AM UTC 24 |
| Finished | Sep 09 08:42:06 AM UTC 24 |
| Peak memory | 213640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024885257 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection.3024885257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_executable.110634896 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1934822523 ps |
| CPU time | 309.05 seconds |
| Started | Sep 09 08:03:48 AM UTC 24 |
| Finished | Sep 09 08:09:01 AM UTC 24 |
| Peak memory | 386920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110634896 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executable.110634896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.3507314864 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 48129296682 ps |
| CPU time | 90.33 seconds |
| Started | Sep 09 08:03:47 AM UTC 24 |
| Finished | Sep 09 08:05:19 AM UTC 24 |
| Peak memory | 212112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507314864 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_escalation.3507314864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.2095776742 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 2715769056 ps |
| CPU time | 53.13 seconds |
| Started | Sep 09 08:03:47 AM UTC 24 |
| Finished | Sep 09 08:04:41 AM UTC 24 |
| Peak memory | 329660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2095776742 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_m ax_throughput.2095776742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.1033225595 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 86150882576 ps |
| CPU time | 444.96 seconds |
| Started | Sep 09 08:03:48 AM UTC 24 |
| Finished | Sep 09 08:11:19 AM UTC 24 |
| Peak memory | 222196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033225595 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_mem_walk.1033225595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.1769118820 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 10276310240 ps |
| CPU time | 565.88 seconds |
| Started | Sep 09 08:03:45 AM UTC 24 |
| Finished | Sep 09 08:13:18 AM UTC 24 |
| Peak memory | 388944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769118820 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multiple_keys.1769118820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access.2018987034 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 2130320617 ps |
| CPU time | 40.3 seconds |
| Started | Sep 09 08:03:46 AM UTC 24 |
| Finished | Sep 09 08:04:27 AM UTC 24 |
| Peak memory | 325492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018987034 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_partial_access.2018987034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.44858776 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 392290646 ps |
| CPU time | 3.7 seconds |
| Started | Sep 09 08:03:49 AM UTC 24 |
| Finished | Sep 09 08:03:54 AM UTC 24 |
| Peak memory | 247816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44858776 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_sec_cm.44858776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all.3350000271 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 497811499203 ps |
| CPU time | 3798.98 seconds |
| Started | Sep 09 08:03:49 AM UTC 24 |
| Finished | Sep 09 09:07:46 AM UTC 24 |
| Peak memory | 390632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33500002 71 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all.3350000271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3347682005 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 13912268389 ps |
| CPU time | 42.17 seconds |
| Started | Sep 09 08:03:49 AM UTC 24 |
| Finished | Sep 09 08:04:33 AM UTC 24 |
| Peak memory | 223472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347682005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.3347682005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.4094749027 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 5785142986 ps |
| CPU time | 432.25 seconds |
| Started | Sep 09 08:03:46 AM UTC 24 |
| Finished | Sep 09 08:11:04 AM UTC 24 |
| Peak memory | 211924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094749027 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_pipeline.4094749027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.3406798706 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 2930268467 ps |
| CPU time | 14.87 seconds |
| Started | Sep 09 08:03:47 AM UTC 24 |
| Finished | Sep 09 08:04:03 AM UTC 24 |
| Peak memory | 261988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3406798706 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ throughput_w_partial_write.3406798706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.3177440272 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 10809805827 ps |
| CPU time | 452.28 seconds |
| Started | Sep 09 08:13:08 AM UTC 24 |
| Finished | Sep 09 08:20:46 AM UTC 24 |
| Peak memory | 386916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177440272 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_access_duri ng_key_req.3177440272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_alert_test.1732622809 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 29788752 ps |
| CPU time | 0.97 seconds |
| Started | Sep 09 08:13:53 AM UTC 24 |
| Finished | Sep 09 08:13:55 AM UTC 24 |
| Peak memory | 210996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732622809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_alert_test.1732622809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_bijection.904192339 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 128049640916 ps |
| CPU time | 2136.32 seconds |
| Started | Sep 09 08:12:26 AM UTC 24 |
| Finished | Sep 09 08:48:26 AM UTC 24 |
| Peak memory | 213496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904192339 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection.904192339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_executable.2589247472 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 4476379687 ps |
| CPU time | 297.75 seconds |
| Started | Sep 09 08:13:20 AM UTC 24 |
| Finished | Sep 09 08:18:22 AM UTC 24 |
| Peak memory | 380780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589247472 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executable.2589247472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.2594746971 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 84137240044 ps |
| CPU time | 110.19 seconds |
| Started | Sep 09 08:13:07 AM UTC 24 |
| Finished | Sep 09 08:14:59 AM UTC 24 |
| Peak memory | 212024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594746971 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_escalation.2594746971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.2751229789 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 828135283 ps |
| CPU time | 63.98 seconds |
| Started | Sep 09 08:12:47 AM UTC 24 |
| Finished | Sep 09 08:13:53 AM UTC 24 |
| Peak memory | 378864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2751229789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ max_throughput.2751229789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.83593616 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 5799135574 ps |
| CPU time | 176.66 seconds |
| Started | Sep 09 08:13:41 AM UTC 24 |
| Finished | Sep 09 08:16:41 AM UTC 24 |
| Peak memory | 222324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83593616 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_mem_partial_access.83593616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.3465473786 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 27724227252 ps |
| CPU time | 217.9 seconds |
| Started | Sep 09 08:13:39 AM UTC 24 |
| Finished | Sep 09 08:17:20 AM UTC 24 |
| Peak memory | 222392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465473786 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_mem_walk.3465473786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.2372954959 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 116451317712 ps |
| CPU time | 1121.34 seconds |
| Started | Sep 09 08:12:25 AM UTC 24 |
| Finished | Sep 09 08:31:19 AM UTC 24 |
| Peak memory | 382820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372954959 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multiple_keys.2372954959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access.1162756851 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 2149973545 ps |
| CPU time | 26.53 seconds |
| Started | Sep 09 08:12:33 AM UTC 24 |
| Finished | Sep 09 08:13:01 AM UTC 24 |
| Peak memory | 212144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162756851 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_partial_access.1162756851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.2133902633 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 29105077414 ps |
| CPU time | 370.87 seconds |
| Started | Sep 09 08:12:34 AM UTC 24 |
| Finished | Sep 09 08:18:50 AM UTC 24 |
| Peak memory | 211876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133902633 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_partial_a ccess_b2b.2133902633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.1159426286 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 697122836 ps |
| CPU time | 5.63 seconds |
| Started | Sep 09 08:13:32 AM UTC 24 |
| Finished | Sep 09 08:13:39 AM UTC 24 |
| Peak memory | 211944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159426286 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.1159426286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_smoke.3190544597 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 1481199404 ps |
| CPU time | 7.8 seconds |
| Started | Sep 09 08:12:24 AM UTC 24 |
| Finished | Sep 09 08:12:33 AM UTC 24 |
| Peak memory | 223084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190544597 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.3190544597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all.323637416 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 666936155438 ps |
| CPU time | 3408.19 seconds |
| Started | Sep 09 08:13:45 AM UTC 24 |
| Finished | Sep 09 09:11:09 AM UTC 24 |
| Peak memory | 392788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32363741 6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all.323637416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.1150746653 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 610376113 ps |
| CPU time | 14.79 seconds |
| Started | Sep 09 08:13:45 AM UTC 24 |
| Finished | Sep 09 08:14:01 AM UTC 24 |
| Peak memory | 222384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150746653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.1150746653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.2208569828 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 5035867553 ps |
| CPU time | 296.3 seconds |
| Started | Sep 09 08:12:33 AM UTC 24 |
| Finished | Sep 09 08:17:33 AM UTC 24 |
| Peak memory | 211956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208569828 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_pipeline.2208569828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.3065377947 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 1463463833 ps |
| CPU time | 37.77 seconds |
| Started | Sep 09 08:13:01 AM UTC 24 |
| Finished | Sep 09 08:13:41 AM UTC 24 |
| Peak memory | 298788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3065377947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl _throughput_w_partial_write.3065377947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.2682597683 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 8647997363 ps |
| CPU time | 349.54 seconds |
| Started | Sep 09 08:15:20 AM UTC 24 |
| Finished | Sep 09 08:21:14 AM UTC 24 |
| Peak memory | 372608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682597683 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_access_duri ng_key_req.2682597683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_alert_test.1067317893 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 19511519 ps |
| CPU time | 1.04 seconds |
| Started | Sep 09 08:16:20 AM UTC 24 |
| Finished | Sep 09 08:16:23 AM UTC 24 |
| Peak memory | 210996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067317893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_alert_test.1067317893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_bijection.2130303833 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 331632275228 ps |
| CPU time | 2133.08 seconds |
| Started | Sep 09 08:14:15 AM UTC 24 |
| Finished | Sep 09 08:50:12 AM UTC 24 |
| Peak memory | 213568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130303833 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection.2130303833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.463194262 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 14297394106 ps |
| CPU time | 132.35 seconds |
| Started | Sep 09 08:15:17 AM UTC 24 |
| Finished | Sep 09 08:17:31 AM UTC 24 |
| Peak memory | 222392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463194262 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_escalation.463194262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.4153424089 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 743146291 ps |
| CPU time | 21.62 seconds |
| Started | Sep 09 08:15:03 AM UTC 24 |
| Finished | Sep 09 08:15:26 AM UTC 24 |
| Peak memory | 274288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4153424089 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ max_throughput.4153424089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.3267960598 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 2895174498 ps |
| CPU time | 75.09 seconds |
| Started | Sep 09 08:16:00 AM UTC 24 |
| Finished | Sep 09 08:17:17 AM UTC 24 |
| Peak memory | 229216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267960598 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_mem_partial_access.3267960598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.3675364201 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 6929459538 ps |
| CPU time | 221.58 seconds |
| Started | Sep 09 08:15:33 AM UTC 24 |
| Finished | Sep 09 08:19:18 AM UTC 24 |
| Peak memory | 222128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675364201 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_mem_walk.3675364201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.4105798877 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 81386829462 ps |
| CPU time | 997.16 seconds |
| Started | Sep 09 08:14:02 AM UTC 24 |
| Finished | Sep 09 08:30:50 AM UTC 24 |
| Peak memory | 386936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105798877 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multiple_keys.4105798877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access.2699909711 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 15897418772 ps |
| CPU time | 26.41 seconds |
| Started | Sep 09 08:14:51 AM UTC 24 |
| Finished | Sep 09 08:15:19 AM UTC 24 |
| Peak memory | 284572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699909711 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_partial_access.2699909711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.3779059369 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 26583581648 ps |
| CPU time | 355.39 seconds |
| Started | Sep 09 08:15:00 AM UTC 24 |
| Finished | Sep 09 08:21:01 AM UTC 24 |
| Peak memory | 211976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779059369 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_partial_a ccess_b2b.3779059369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.3986742944 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 3372059085 ps |
| CPU time | 3.72 seconds |
| Started | Sep 09 08:15:28 AM UTC 24 |
| Finished | Sep 09 08:15:33 AM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986742944 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.3986742944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_regwen.592085933 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 1925980466 ps |
| CPU time | 311.64 seconds |
| Started | Sep 09 08:15:27 AM UTC 24 |
| Finished | Sep 09 08:20:42 AM UTC 24 |
| Peak memory | 362284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592085933 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.592085933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_smoke.3792960676 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 444245124 ps |
| CPU time | 84.44 seconds |
| Started | Sep 09 08:13:56 AM UTC 24 |
| Finished | Sep 09 08:15:23 AM UTC 24 |
| Peak memory | 364328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792960676 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.3792960676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.4056664939 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 402595977 ps |
| CPU time | 16.8 seconds |
| Started | Sep 09 08:16:01 AM UTC 24 |
| Finished | Sep 09 08:16:19 AM UTC 24 |
| Peak memory | 222456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056664939 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.4056664939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.779268850 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 2258414150 ps |
| CPU time | 115.24 seconds |
| Started | Sep 09 08:14:51 AM UTC 24 |
| Finished | Sep 09 08:16:49 AM UTC 24 |
| Peak memory | 212152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779268850 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_pipeline.779268850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.1652196189 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 2667761340 ps |
| CPU time | 11.69 seconds |
| Started | Sep 09 08:15:14 AM UTC 24 |
| Finished | Sep 09 08:15:27 AM UTC 24 |
| Peak memory | 211676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1652196189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl _throughput_w_partial_write.1652196189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.1142826303 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 7466303065 ps |
| CPU time | 379.03 seconds |
| Started | Sep 09 08:17:21 AM UTC 24 |
| Finished | Sep 09 08:23:46 AM UTC 24 |
| Peak memory | 382820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142826303 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_access_duri ng_key_req.1142826303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_alert_test.1566547411 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 24046825 ps |
| CPU time | 0.96 seconds |
| Started | Sep 09 08:17:56 AM UTC 24 |
| Finished | Sep 09 08:17:58 AM UTC 24 |
| Peak memory | 211116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566547411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_alert_test.1566547411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_bijection.3606315561 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 29350519152 ps |
| CPU time | 2117.65 seconds |
| Started | Sep 09 08:16:38 AM UTC 24 |
| Finished | Sep 09 08:52:20 AM UTC 24 |
| Peak memory | 213620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606315561 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection.3606315561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_executable.1481960934 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 22339685213 ps |
| CPU time | 1133.03 seconds |
| Started | Sep 09 08:17:23 AM UTC 24 |
| Finished | Sep 09 08:36:29 AM UTC 24 |
| Peak memory | 389024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481960934 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executable.1481960934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.775160611 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 9943124545 ps |
| CPU time | 68.57 seconds |
| Started | Sep 09 08:17:21 AM UTC 24 |
| Finished | Sep 09 08:18:31 AM UTC 24 |
| Peak memory | 222320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775160611 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_escalation.775160611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.3733023290 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 2667502702 ps |
| CPU time | 102.9 seconds |
| Started | Sep 09 08:17:07 AM UTC 24 |
| Finished | Sep 09 08:18:52 AM UTC 24 |
| Peak memory | 380976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3733023290 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ max_throughput.3733023290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.2303266365 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 12270592548 ps |
| CPU time | 94.45 seconds |
| Started | Sep 09 08:17:42 AM UTC 24 |
| Finished | Sep 09 08:19:18 AM UTC 24 |
| Peak memory | 222184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303266365 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_mem_partial_access.2303266365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.2674670455 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 21003079044 ps |
| CPU time | 306.63 seconds |
| Started | Sep 09 08:17:41 AM UTC 24 |
| Finished | Sep 09 08:22:52 AM UTC 24 |
| Peak memory | 222200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674670455 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_mem_walk.2674670455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access.793127706 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 4280268829 ps |
| CPU time | 49.13 seconds |
| Started | Sep 09 08:16:50 AM UTC 24 |
| Finished | Sep 09 08:17:41 AM UTC 24 |
| Peak memory | 304912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793127706 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_partial_access.793127706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.1106211710 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 5275756217 ps |
| CPU time | 252.93 seconds |
| Started | Sep 09 08:16:55 AM UTC 24 |
| Finished | Sep 09 08:21:11 AM UTC 24 |
| Peak memory | 211948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106211710 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_partial_a ccess_b2b.1106211710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.482197179 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 5599749646 ps |
| CPU time | 4.24 seconds |
| Started | Sep 09 08:17:35 AM UTC 24 |
| Finished | Sep 09 08:17:40 AM UTC 24 |
| Peak memory | 212216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482197179 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.482197179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_regwen.3244894247 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 4096970097 ps |
| CPU time | 532.34 seconds |
| Started | Sep 09 08:17:33 AM UTC 24 |
| Finished | Sep 09 08:26:31 AM UTC 24 |
| Peak memory | 386936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244894247 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.3244894247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_smoke.2699922161 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 930972903 ps |
| CPU time | 10.06 seconds |
| Started | Sep 09 08:16:24 AM UTC 24 |
| Finished | Sep 09 08:16:36 AM UTC 24 |
| Peak memory | 211944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699922161 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.2699922161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all.3740617569 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 400678071595 ps |
| CPU time | 2923.56 seconds |
| Started | Sep 09 08:17:47 AM UTC 24 |
| Finished | Sep 09 09:07:01 AM UTC 24 |
| Peak memory | 392720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37406175 69 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_a ll.3740617569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.2105075487 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 4324884899 ps |
| CPU time | 141.69 seconds |
| Started | Sep 09 08:17:43 AM UTC 24 |
| Finished | Sep 09 08:20:07 AM UTC 24 |
| Peak memory | 385136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105075487 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.2105075487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.1663137938 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 12175669699 ps |
| CPU time | 207.31 seconds |
| Started | Sep 09 08:16:42 AM UTC 24 |
| Finished | Sep 09 08:20:12 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663137938 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_pipeline.1663137938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.3466821170 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 764157294 ps |
| CPU time | 52.8 seconds |
| Started | Sep 09 08:17:18 AM UTC 24 |
| Finished | Sep 09 08:18:13 AM UTC 24 |
| Peak memory | 345960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3466821170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl _throughput_w_partial_write.3466821170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.3705783208 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 57768333598 ps |
| CPU time | 802.96 seconds |
| Started | Sep 09 08:19:10 AM UTC 24 |
| Finished | Sep 09 08:32:42 AM UTC 24 |
| Peak memory | 386984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705783208 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_access_duri ng_key_req.3705783208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_alert_test.1548971805 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 20610029 ps |
| CPU time | 1.08 seconds |
| Started | Sep 09 08:20:02 AM UTC 24 |
| Finished | Sep 09 08:20:04 AM UTC 24 |
| Peak memory | 211028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548971805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_alert_test.1548971805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_bijection.3666970065 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 14031622116 ps |
| CPU time | 994.31 seconds |
| Started | Sep 09 08:18:13 AM UTC 24 |
| Finished | Sep 09 08:35:00 AM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666970065 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection.3666970065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_executable.2442574936 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 45385143532 ps |
| CPU time | 958.44 seconds |
| Started | Sep 09 08:19:19 AM UTC 24 |
| Finished | Sep 09 08:35:29 AM UTC 24 |
| Peak memory | 382836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442574936 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executable.2442574936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.428255524 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 46568759558 ps |
| CPU time | 138.14 seconds |
| Started | Sep 09 08:18:53 AM UTC 24 |
| Finished | Sep 09 08:21:14 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428255524 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_escalation.428255524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.1468116826 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 731920341 ps |
| CPU time | 33.9 seconds |
| Started | Sep 09 08:18:51 AM UTC 24 |
| Finished | Sep 09 08:19:26 AM UTC 24 |
| Peak memory | 305140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1468116826 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ max_throughput.1468116826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.2255419620 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 5485742115 ps |
| CPU time | 98.12 seconds |
| Started | Sep 09 08:19:27 AM UTC 24 |
| Finished | Sep 09 08:21:07 AM UTC 24 |
| Peak memory | 229404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255419620 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_mem_partial_access.2255419620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.75953749 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 21877737839 ps |
| CPU time | 289.97 seconds |
| Started | Sep 09 08:19:25 AM UTC 24 |
| Finished | Sep 09 08:24:18 AM UTC 24 |
| Peak memory | 222200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75953749 -assert nopost proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_mem_walk.75953749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.872933422 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 6833652875 ps |
| CPU time | 592.57 seconds |
| Started | Sep 09 08:18:02 AM UTC 24 |
| Finished | Sep 09 08:28:02 AM UTC 24 |
| Peak memory | 386992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872933422 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multiple_keys.872933422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access.2163423527 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 6465950854 ps |
| CPU time | 77.75 seconds |
| Started | Sep 09 08:18:33 AM UTC 24 |
| Finished | Sep 09 08:19:52 AM UTC 24 |
| Peak memory | 376744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163423527 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_partial_access.2163423527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.2062379302 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 44159251560 ps |
| CPU time | 326.63 seconds |
| Started | Sep 09 08:18:40 AM UTC 24 |
| Finished | Sep 09 08:24:11 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062379302 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_partial_a ccess_b2b.2062379302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.3493414352 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 1470211917 ps |
| CPU time | 4.48 seconds |
| Started | Sep 09 08:19:22 AM UTC 24 |
| Finished | Sep 09 08:19:28 AM UTC 24 |
| Peak memory | 211952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493414352 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.3493414352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_regwen.1539452071 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 3455958311 ps |
| CPU time | 648.91 seconds |
| Started | Sep 09 08:19:19 AM UTC 24 |
| Finished | Sep 09 08:30:15 AM UTC 24 |
| Peak memory | 386928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539452071 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.1539452071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_smoke.3602964608 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 750940174 ps |
| CPU time | 49.47 seconds |
| Started | Sep 09 08:17:59 AM UTC 24 |
| Finished | Sep 09 08:18:50 AM UTC 24 |
| Peak memory | 331756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602964608 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.3602964608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all.154462937 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 315301525486 ps |
| CPU time | 2121.11 seconds |
| Started | Sep 09 08:19:53 AM UTC 24 |
| Finished | Sep 09 08:55:37 AM UTC 24 |
| Peak memory | 392716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15446293 7 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all.154462937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.932196942 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 2295442147 ps |
| CPU time | 30.98 seconds |
| Started | Sep 09 08:19:29 AM UTC 24 |
| Finished | Sep 09 08:20:01 AM UTC 24 |
| Peak memory | 222320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932196942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.932196942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.2280842956 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 4347181990 ps |
| CPU time | 323.08 seconds |
| Started | Sep 09 08:18:22 AM UTC 24 |
| Finished | Sep 09 08:23:50 AM UTC 24 |
| Peak memory | 211940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280842956 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_pipeline.2280842956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.1381719672 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 769062033 ps |
| CPU time | 31.38 seconds |
| Started | Sep 09 08:18:51 AM UTC 24 |
| Finished | Sep 09 08:19:24 AM UTC 24 |
| Peak memory | 311076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1381719672 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl _throughput_w_partial_write.1381719672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.2371703859 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 11440033844 ps |
| CPU time | 584.01 seconds |
| Started | Sep 09 08:20:58 AM UTC 24 |
| Finished | Sep 09 08:30:49 AM UTC 24 |
| Peak memory | 386924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371703859 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_access_duri ng_key_req.2371703859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_alert_test.2175482575 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 32635961 ps |
| CPU time | 0.91 seconds |
| Started | Sep 09 08:21:15 AM UTC 24 |
| Finished | Sep 09 08:21:17 AM UTC 24 |
| Peak memory | 211060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175482575 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_alert_test.2175482575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_bijection.3286437881 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 133527573610 ps |
| CPU time | 2392.68 seconds |
| Started | Sep 09 08:20:13 AM UTC 24 |
| Finished | Sep 09 09:00:34 AM UTC 24 |
| Peak memory | 213692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286437881 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection.3286437881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_executable.2798928505 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 20066297341 ps |
| CPU time | 933.47 seconds |
| Started | Sep 09 08:21:01 AM UTC 24 |
| Finished | Sep 09 08:36:46 AM UTC 24 |
| Peak memory | 378984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798928505 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executable.2798928505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.3868478981 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 26933891544 ps |
| CPU time | 79.96 seconds |
| Started | Sep 09 08:20:51 AM UTC 24 |
| Finished | Sep 09 08:22:13 AM UTC 24 |
| Peak memory | 222372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868478981 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_escalation.3868478981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.2054580750 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 2813178465 ps |
| CPU time | 12.09 seconds |
| Started | Sep 09 08:20:47 AM UTC 24 |
| Finished | Sep 09 08:21:00 AM UTC 24 |
| Peak memory | 229224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2054580750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ max_throughput.2054580750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.3178913853 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 5105375309 ps |
| CPU time | 164.57 seconds |
| Started | Sep 09 08:21:12 AM UTC 24 |
| Finished | Sep 09 08:24:00 AM UTC 24 |
| Peak memory | 229204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178913853 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_mem_partial_access.3178913853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.2255725563 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 8221412721 ps |
| CPU time | 167.91 seconds |
| Started | Sep 09 08:21:07 AM UTC 24 |
| Finished | Sep 09 08:23:59 AM UTC 24 |
| Peak memory | 222336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255725563 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_mem_walk.2255725563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.3752143790 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 7621779501 ps |
| CPU time | 680.69 seconds |
| Started | Sep 09 08:20:08 AM UTC 24 |
| Finished | Sep 09 08:31:36 AM UTC 24 |
| Peak memory | 387120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752143790 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multiple_keys.3752143790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access.1409148013 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 1054335148 ps |
| CPU time | 42.09 seconds |
| Started | Sep 09 08:20:39 AM UTC 24 |
| Finished | Sep 09 08:21:23 AM UTC 24 |
| Peak memory | 292916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409148013 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_partial_access.1409148013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.2556960213 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 11023262598 ps |
| CPU time | 307.19 seconds |
| Started | Sep 09 08:20:44 AM UTC 24 |
| Finished | Sep 09 08:25:55 AM UTC 24 |
| Peak memory | 212016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556960213 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_partial_a ccess_b2b.2556960213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.2325654633 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 353942027 ps |
| CPU time | 5.23 seconds |
| Started | Sep 09 08:21:07 AM UTC 24 |
| Finished | Sep 09 08:21:14 AM UTC 24 |
| Peak memory | 211944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325654633 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.2325654633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_regwen.176325074 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 27861033085 ps |
| CPU time | 704.94 seconds |
| Started | Sep 09 08:21:01 AM UTC 24 |
| Finished | Sep 09 08:32:54 AM UTC 24 |
| Peak memory | 386920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176325074 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.176325074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_smoke.374263767 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 6326833872 ps |
| CPU time | 31.43 seconds |
| Started | Sep 09 08:20:05 AM UTC 24 |
| Finished | Sep 09 08:20:38 AM UTC 24 |
| Peak memory | 211940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374263767 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.374263767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_all.3528759691 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 404409267473 ps |
| CPU time | 4235.44 seconds |
| Started | Sep 09 08:21:15 AM UTC 24 |
| Finished | Sep 09 09:32:36 AM UTC 24 |
| Peak memory | 390732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35287596 91 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_a ll.3528759691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.791701498 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 1002520256 ps |
| CPU time | 47.1 seconds |
| Started | Sep 09 08:21:15 AM UTC 24 |
| Finished | Sep 09 08:22:04 AM UTC 24 |
| Peak memory | 229240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791701498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.791701498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.3286643821 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 4726922553 ps |
| CPU time | 372.68 seconds |
| Started | Sep 09 08:20:23 AM UTC 24 |
| Finished | Sep 09 08:26:42 AM UTC 24 |
| Peak memory | 211944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286643821 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_pipeline.3286643821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.453284975 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 3338156359 ps |
| CPU time | 9.51 seconds |
| Started | Sep 09 08:20:47 AM UTC 24 |
| Finished | Sep 09 08:20:57 AM UTC 24 |
| Peak memory | 222188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =453284975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ throughput_w_partial_write.453284975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.1692350893 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 8780238039 ps |
| CPU time | 135.5 seconds |
| Started | Sep 09 08:22:19 AM UTC 24 |
| Finished | Sep 09 08:24:37 AM UTC 24 |
| Peak memory | 378816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692350893 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_access_duri ng_key_req.1692350893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_alert_test.1812444271 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 15437628 ps |
| CPU time | 1.02 seconds |
| Started | Sep 09 08:22:53 AM UTC 24 |
| Finished | Sep 09 08:22:55 AM UTC 24 |
| Peak memory | 210996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812444271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_alert_test.1812444271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_bijection.3659220675 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 28717631314 ps |
| CPU time | 468.34 seconds |
| Started | Sep 09 08:21:25 AM UTC 24 |
| Finished | Sep 09 08:29:19 AM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659220675 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection.3659220675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.1505040727 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 60361025437 ps |
| CPU time | 151.48 seconds |
| Started | Sep 09 08:22:14 AM UTC 24 |
| Finished | Sep 09 08:24:48 AM UTC 24 |
| Peak memory | 211888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505040727 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_escalation.1505040727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.3455854331 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 1638301531 ps |
| CPU time | 81.65 seconds |
| Started | Sep 09 08:22:05 AM UTC 24 |
| Finished | Sep 09 08:23:28 AM UTC 24 |
| Peak memory | 362280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3455854331 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ max_throughput.3455854331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.2402794493 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 8532345293 ps |
| CPU time | 197.44 seconds |
| Started | Sep 09 08:22:44 AM UTC 24 |
| Finished | Sep 09 08:26:05 AM UTC 24 |
| Peak memory | 222240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402794493 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_mem_partial_access.2402794493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.2072652230 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 19215729780 ps |
| CPU time | 209.56 seconds |
| Started | Sep 09 08:22:42 AM UTC 24 |
| Finished | Sep 09 08:26:15 AM UTC 24 |
| Peak memory | 222260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072652230 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_mem_walk.2072652230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.2498043542 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 36464270014 ps |
| CPU time | 883.16 seconds |
| Started | Sep 09 08:21:23 AM UTC 24 |
| Finished | Sep 09 08:36:16 AM UTC 24 |
| Peak memory | 380948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498043542 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multiple_keys.2498043542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access.361201658 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 1937907815 ps |
| CPU time | 38.73 seconds |
| Started | Sep 09 08:21:43 AM UTC 24 |
| Finished | Sep 09 08:22:23 AM UTC 24 |
| Peak memory | 284660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361201658 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_partial_access.361201658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.3348815258 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 275204274235 ps |
| CPU time | 468.73 seconds |
| Started | Sep 09 08:22:02 AM UTC 24 |
| Finished | Sep 09 08:29:57 AM UTC 24 |
| Peak memory | 212028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348815258 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_partial_a ccess_b2b.3348815258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.600466378 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 5578366653 ps |
| CPU time | 6.45 seconds |
| Started | Sep 09 08:22:40 AM UTC 24 |
| Finished | Sep 09 08:22:48 AM UTC 24 |
| Peak memory | 212020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600466378 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.600466378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_regwen.3643806126 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 4892755712 ps |
| CPU time | 485.69 seconds |
| Started | Sep 09 08:22:35 AM UTC 24 |
| Finished | Sep 09 08:30:47 AM UTC 24 |
| Peak memory | 380868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643806126 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.3643806126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_smoke.2797206904 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 413258483 ps |
| CPU time | 10.28 seconds |
| Started | Sep 09 08:21:18 AM UTC 24 |
| Finished | Sep 09 08:21:29 AM UTC 24 |
| Peak memory | 211900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797206904 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.2797206904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all.1245771894 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 36037938883 ps |
| CPU time | 2792.42 seconds |
| Started | Sep 09 08:22:53 AM UTC 24 |
| Finished | Sep 09 09:09:53 AM UTC 24 |
| Peak memory | 401156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12457718 94 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_a ll.1245771894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.251621600 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 3933759596 ps |
| CPU time | 76.74 seconds |
| Started | Sep 09 08:22:49 AM UTC 24 |
| Finished | Sep 09 08:24:07 AM UTC 24 |
| Peak memory | 243688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251621600 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.251621600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.605165934 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 61887017736 ps |
| CPU time | 381.65 seconds |
| Started | Sep 09 08:21:30 AM UTC 24 |
| Finished | Sep 09 08:27:57 AM UTC 24 |
| Peak memory | 212016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605165934 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_pipeline.605165934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.2138982123 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 5795409642 ps |
| CPU time | 19.85 seconds |
| Started | Sep 09 08:22:14 AM UTC 24 |
| Finished | Sep 09 08:22:35 AM UTC 24 |
| Peak memory | 247648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2138982123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl _throughput_w_partial_write.2138982123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.3953818620 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 33944451285 ps |
| CPU time | 590.25 seconds |
| Started | Sep 09 08:24:09 AM UTC 24 |
| Finished | Sep 09 08:34:06 AM UTC 24 |
| Peak memory | 384884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953818620 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_access_duri ng_key_req.3953818620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_alert_test.2975614805 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 33318344 ps |
| CPU time | 0.97 seconds |
| Started | Sep 09 08:24:38 AM UTC 24 |
| Finished | Sep 09 08:24:40 AM UTC 24 |
| Peak memory | 210996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975614805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_alert_test.2975614805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_bijection.664182369 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 622594597153 ps |
| CPU time | 3344.13 seconds |
| Started | Sep 09 08:23:29 AM UTC 24 |
| Finished | Sep 09 09:19:55 AM UTC 24 |
| Peak memory | 213640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664182369 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection.664182369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_executable.3593479228 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 15161689872 ps |
| CPU time | 862.62 seconds |
| Started | Sep 09 08:24:12 AM UTC 24 |
| Finished | Sep 09 08:38:43 AM UTC 24 |
| Peak memory | 382912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593479228 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executable.3593479228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.4247335746 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 36643831489 ps |
| CPU time | 63.69 seconds |
| Started | Sep 09 08:24:08 AM UTC 24 |
| Finished | Sep 09 08:25:13 AM UTC 24 |
| Peak memory | 222184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247335746 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_escalation.4247335746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.3752803913 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 754914071 ps |
| CPU time | 39.38 seconds |
| Started | Sep 09 08:24:01 AM UTC 24 |
| Finished | Sep 09 08:24:42 AM UTC 24 |
| Peak memory | 298792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3752803913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ max_throughput.3752803913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.3113419903 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 991198151 ps |
| CPU time | 74.95 seconds |
| Started | Sep 09 08:24:19 AM UTC 24 |
| Finished | Sep 09 08:25:36 AM UTC 24 |
| Peak memory | 229208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113419903 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_mem_partial_access.3113419903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.1232976746 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 22837449580 ps |
| CPU time | 325.81 seconds |
| Started | Sep 09 08:24:17 AM UTC 24 |
| Finished | Sep 09 08:29:48 AM UTC 24 |
| Peak memory | 222208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232976746 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_mem_walk.1232976746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.3308068797 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 68734729897 ps |
| CPU time | 205.82 seconds |
| Started | Sep 09 08:23:05 AM UTC 24 |
| Finished | Sep 09 08:26:34 AM UTC 24 |
| Peak memory | 329580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308068797 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multiple_keys.3308068797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access.2609355914 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 813583484 ps |
| CPU time | 20.1 seconds |
| Started | Sep 09 08:23:51 AM UTC 24 |
| Finished | Sep 09 08:24:13 AM UTC 24 |
| Peak memory | 211956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609355914 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_partial_access.2609355914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.3819829819 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 53399067733 ps |
| CPU time | 322.06 seconds |
| Started | Sep 09 08:24:00 AM UTC 24 |
| Finished | Sep 09 08:29:26 AM UTC 24 |
| Peak memory | 212016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819829819 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_partial_a ccess_b2b.3819829819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.102934987 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 394249608 ps |
| CPU time | 4.78 seconds |
| Started | Sep 09 08:24:13 AM UTC 24 |
| Finished | Sep 09 08:24:19 AM UTC 24 |
| Peak memory | 212028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102934987 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.102934987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_regwen.2360433228 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 15908288857 ps |
| CPU time | 970.16 seconds |
| Started | Sep 09 08:24:13 AM UTC 24 |
| Finished | Sep 09 08:40:34 AM UTC 24 |
| Peak memory | 376768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360433228 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.2360433228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_smoke.2127068643 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 937904653 ps |
| CPU time | 74.69 seconds |
| Started | Sep 09 08:22:56 AM UTC 24 |
| Finished | Sep 09 08:24:12 AM UTC 24 |
| Peak memory | 358164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127068643 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.2127068643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all.2399535395 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 407166989869 ps |
| CPU time | 3934.74 seconds |
| Started | Sep 09 08:24:20 AM UTC 24 |
| Finished | Sep 09 09:30:38 AM UTC 24 |
| Peak memory | 388600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23995353 95 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_a ll.2399535395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.2874736750 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 4060967277 ps |
| CPU time | 33.62 seconds |
| Started | Sep 09 08:24:20 AM UTC 24 |
| Finished | Sep 09 08:24:56 AM UTC 24 |
| Peak memory | 222192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874736750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.2874736750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.2676075222 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 8214694944 ps |
| CPU time | 170.98 seconds |
| Started | Sep 09 08:23:46 AM UTC 24 |
| Finished | Sep 09 08:26:40 AM UTC 24 |
| Peak memory | 212168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676075222 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_pipeline.2676075222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.1058411391 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 721254916 ps |
| CPU time | 12.83 seconds |
| Started | Sep 09 08:24:05 AM UTC 24 |
| Finished | Sep 09 08:24:19 AM UTC 24 |
| Peak memory | 245540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1058411391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl _throughput_w_partial_write.1058411391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.1154657172 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 11369342313 ps |
| CPU time | 427.68 seconds |
| Started | Sep 09 08:25:56 AM UTC 24 |
| Finished | Sep 09 08:33:09 AM UTC 24 |
| Peak memory | 341948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154657172 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_access_duri ng_key_req.1154657172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_alert_test.2340056605 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 11206285 ps |
| CPU time | 1.03 seconds |
| Started | Sep 09 08:26:43 AM UTC 24 |
| Finished | Sep 09 08:26:45 AM UTC 24 |
| Peak memory | 211028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340056605 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_alert_test.2340056605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_bijection.1186498058 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 104750586934 ps |
| CPU time | 1900.91 seconds |
| Started | Sep 09 08:24:49 AM UTC 24 |
| Finished | Sep 09 08:56:52 AM UTC 24 |
| Peak memory | 213640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186498058 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection.1186498058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_executable.324457568 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 15627515990 ps |
| CPU time | 135.12 seconds |
| Started | Sep 09 08:26:06 AM UTC 24 |
| Finished | Sep 09 08:28:23 AM UTC 24 |
| Peak memory | 352120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324457568 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executable.324457568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.1373025755 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 9420631873 ps |
| CPU time | 91.63 seconds |
| Started | Sep 09 08:25:40 AM UTC 24 |
| Finished | Sep 09 08:27:13 AM UTC 24 |
| Peak memory | 222244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373025755 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_escalation.1373025755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.1428635913 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 1594768796 ps |
| CPU time | 96.51 seconds |
| Started | Sep 09 08:25:31 AM UTC 24 |
| Finished | Sep 09 08:27:11 AM UTC 24 |
| Peak memory | 376616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1428635913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ max_throughput.1428635913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.386934981 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 20934189186 ps |
| CPU time | 224.26 seconds |
| Started | Sep 09 08:26:32 AM UTC 24 |
| Finished | Sep 09 08:30:19 AM UTC 24 |
| Peak memory | 222172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386934981 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_mem_partial_access.386934981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.1615711731 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 55282951087 ps |
| CPU time | 384.17 seconds |
| Started | Sep 09 08:26:29 AM UTC 24 |
| Finished | Sep 09 08:32:59 AM UTC 24 |
| Peak memory | 222184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615711731 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_mem_walk.1615711731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.3083743235 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 18234818653 ps |
| CPU time | 309.68 seconds |
| Started | Sep 09 08:24:43 AM UTC 24 |
| Finished | Sep 09 08:29:57 AM UTC 24 |
| Peak memory | 380840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083743235 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multiple_keys.3083743235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access.2807507266 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 4537197481 ps |
| CPU time | 28.47 seconds |
| Started | Sep 09 08:25:09 AM UTC 24 |
| Finished | Sep 09 08:25:39 AM UTC 24 |
| Peak memory | 211884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807507266 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_partial_access.2807507266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.489615600 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 15805045632 ps |
| CPU time | 612.27 seconds |
| Started | Sep 09 08:25:14 AM UTC 24 |
| Finished | Sep 09 08:35:35 AM UTC 24 |
| Peak memory | 211876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489615600 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_partial_ac cess_b2b.489615600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.2550619966 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 403957479 ps |
| CPU time | 5.67 seconds |
| Started | Sep 09 08:26:22 AM UTC 24 |
| Finished | Sep 09 08:26:29 AM UTC 24 |
| Peak memory | 212024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550619966 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.2550619966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_regwen.3443376033 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 11404922219 ps |
| CPU time | 773.29 seconds |
| Started | Sep 09 08:26:16 AM UTC 24 |
| Finished | Sep 09 08:39:19 AM UTC 24 |
| Peak memory | 362424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443376033 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.3443376033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_smoke.4189920954 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 3548820025 ps |
| CPU time | 26.38 seconds |
| Started | Sep 09 08:24:41 AM UTC 24 |
| Finished | Sep 09 08:25:08 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189920954 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.4189920954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all.1874110667 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 296041488161 ps |
| CPU time | 6198.71 seconds |
| Started | Sep 09 08:26:41 AM UTC 24 |
| Finished | Sep 09 10:11:06 AM UTC 24 |
| Peak memory | 392784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18741106 67 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_a ll.1874110667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.339234159 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 1050850618 ps |
| CPU time | 57.27 seconds |
| Started | Sep 09 08:26:35 AM UTC 24 |
| Finished | Sep 09 08:27:34 AM UTC 24 |
| Peak memory | 222184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339234159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.339234159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.3689734554 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 17724548771 ps |
| CPU time | 329.26 seconds |
| Started | Sep 09 08:24:56 AM UTC 24 |
| Finished | Sep 09 08:30:30 AM UTC 24 |
| Peak memory | 211964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689734554 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_pipeline.3689734554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.666594071 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 815364718 ps |
| CPU time | 100.51 seconds |
| Started | Sep 09 08:25:38 AM UTC 24 |
| Finished | Sep 09 08:27:20 AM UTC 24 |
| Peak memory | 376872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =666594071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ throughput_w_partial_write.666594071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.586002399 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 60863808878 ps |
| CPU time | 343.02 seconds |
| Started | Sep 09 08:28:06 AM UTC 24 |
| Finished | Sep 09 08:33:53 AM UTC 24 |
| Peak memory | 368696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586002399 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_access_durin g_key_req.586002399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_alert_test.185854523 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 36235135 ps |
| CPU time | 0.91 seconds |
| Started | Sep 09 08:29:49 AM UTC 24 |
| Finished | Sep 09 08:29:51 AM UTC 24 |
| Peak memory | 211096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185854523 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_alert_test.185854523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_bijection.525132315 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 687587426621 ps |
| CPU time | 2892.1 seconds |
| Started | Sep 09 08:27:11 AM UTC 24 |
| Finished | Sep 09 09:15:55 AM UTC 24 |
| Peak memory | 213580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525132315 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection.525132315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_executable.3669949447 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 14265216419 ps |
| CPU time | 250.58 seconds |
| Started | Sep 09 08:28:07 AM UTC 24 |
| Finished | Sep 09 08:32:21 AM UTC 24 |
| Peak memory | 364464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669949447 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executable.3669949447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.1844985133 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 10298335987 ps |
| CPU time | 115.89 seconds |
| Started | Sep 09 08:28:03 AM UTC 24 |
| Finished | Sep 09 08:30:01 AM UTC 24 |
| Peak memory | 212024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844985133 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_escalation.1844985133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.1505358876 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 1389443279 ps |
| CPU time | 8.36 seconds |
| Started | Sep 09 08:27:56 AM UTC 24 |
| Finished | Sep 09 08:28:05 AM UTC 24 |
| Peak memory | 211692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1505358876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ max_throughput.1505358876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.1108687468 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 5351011926 ps |
| CPU time | 109.87 seconds |
| Started | Sep 09 08:28:40 AM UTC 24 |
| Finished | Sep 09 08:30:32 AM UTC 24 |
| Peak memory | 229208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108687468 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_mem_partial_access.1108687468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.3222006282 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 55271458439 ps |
| CPU time | 398.46 seconds |
| Started | Sep 09 08:28:32 AM UTC 24 |
| Finished | Sep 09 08:35:17 AM UTC 24 |
| Peak memory | 222328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222006282 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_mem_walk.3222006282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.229356705 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 10615695198 ps |
| CPU time | 725.91 seconds |
| Started | Sep 09 08:27:08 AM UTC 24 |
| Finished | Sep 09 08:39:23 AM UTC 24 |
| Peak memory | 389044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229356705 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multiple_keys.229356705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access.2101853048 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 2312115169 ps |
| CPU time | 75.5 seconds |
| Started | Sep 09 08:27:21 AM UTC 24 |
| Finished | Sep 09 08:28:39 AM UTC 24 |
| Peak memory | 343980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101853048 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_partial_access.2101853048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.981256919 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 39997542984 ps |
| CPU time | 292.38 seconds |
| Started | Sep 09 08:27:35 AM UTC 24 |
| Finished | Sep 09 08:32:31 AM UTC 24 |
| Peak memory | 211964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981256919 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_partial_ac cess_b2b.981256919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.450838821 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 617732389 ps |
| CPU time | 6.2 seconds |
| Started | Sep 09 08:28:24 AM UTC 24 |
| Finished | Sep 09 08:28:32 AM UTC 24 |
| Peak memory | 211948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450838821 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.450838821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_regwen.1397169685 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 14445332202 ps |
| CPU time | 209.91 seconds |
| Started | Sep 09 08:28:11 AM UTC 24 |
| Finished | Sep 09 08:31:45 AM UTC 24 |
| Peak memory | 333876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397169685 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.1397169685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_smoke.1027283576 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 3597813989 ps |
| CPU time | 20.36 seconds |
| Started | Sep 09 08:26:46 AM UTC 24 |
| Finished | Sep 09 08:27:07 AM UTC 24 |
| Peak memory | 212152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1027283576 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.1027283576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all.3252228075 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 39059946128 ps |
| CPU time | 3388 seconds |
| Started | Sep 09 08:29:27 AM UTC 24 |
| Finished | Sep 09 09:26:30 AM UTC 24 |
| Peak memory | 400904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32522280 75 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_a ll.3252228075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.2370202361 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 677726507 ps |
| CPU time | 37.38 seconds |
| Started | Sep 09 08:29:21 AM UTC 24 |
| Finished | Sep 09 08:29:59 AM UTC 24 |
| Peak memory | 222196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370202361 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.2370202361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.2140285088 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 8753442577 ps |
| CPU time | 376.06 seconds |
| Started | Sep 09 08:27:14 AM UTC 24 |
| Finished | Sep 09 08:33:36 AM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140285088 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_pipeline.2140285088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.2058044486 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 1441089620 ps |
| CPU time | 7.14 seconds |
| Started | Sep 09 08:27:58 AM UTC 24 |
| Finished | Sep 09 08:28:06 AM UTC 24 |
| Peak memory | 228944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2058044486 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl _throughput_w_partial_write.2058044486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.1817354116 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 15787501686 ps |
| CPU time | 773.38 seconds |
| Started | Sep 09 08:30:34 AM UTC 24 |
| Finished | Sep 09 08:43:36 AM UTC 24 |
| Peak memory | 386900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817354116 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_access_duri ng_key_req.1817354116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_alert_test.2072812288 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 23646058 ps |
| CPU time | 0.97 seconds |
| Started | Sep 09 08:31:37 AM UTC 24 |
| Finished | Sep 09 08:31:39 AM UTC 24 |
| Peak memory | 211028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072812288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_alert_test.2072812288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_bijection.3699422827 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 50067701809 ps |
| CPU time | 836.98 seconds |
| Started | Sep 09 08:29:58 AM UTC 24 |
| Finished | Sep 09 08:44:06 AM UTC 24 |
| Peak memory | 211896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699422827 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection.3699422827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_executable.1218482450 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 5342191625 ps |
| CPU time | 276.57 seconds |
| Started | Sep 09 08:30:47 AM UTC 24 |
| Finished | Sep 09 08:35:27 AM UTC 24 |
| Peak memory | 374900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218482450 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executable.1218482450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.3330927235 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 133988493196 ps |
| CPU time | 240.99 seconds |
| Started | Sep 09 08:30:33 AM UTC 24 |
| Finished | Sep 09 08:34:38 AM UTC 24 |
| Peak memory | 212144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330927235 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_escalation.3330927235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.409357295 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 3132653047 ps |
| CPU time | 91.44 seconds |
| Started | Sep 09 08:30:21 AM UTC 24 |
| Finished | Sep 09 08:31:54 AM UTC 24 |
| Peak memory | 360496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 409357295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_m ax_throughput.409357295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.1842753099 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 10453853142 ps |
| CPU time | 232.73 seconds |
| Started | Sep 09 08:30:58 AM UTC 24 |
| Finished | Sep 09 08:34:54 AM UTC 24 |
| Peak memory | 222236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842753099 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_mem_partial_access.1842753099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.1008760293 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 45060562007 ps |
| CPU time | 233.03 seconds |
| Started | Sep 09 08:30:53 AM UTC 24 |
| Finished | Sep 09 08:34:50 AM UTC 24 |
| Peak memory | 222208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008760293 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_mem_walk.1008760293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.1807217259 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 71800651862 ps |
| CPU time | 872.26 seconds |
| Started | Sep 09 08:29:57 AM UTC 24 |
| Finished | Sep 09 08:44:40 AM UTC 24 |
| Peak memory | 391084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807217259 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multiple_keys.1807217259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access.3697449080 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 2744823504 ps |
| CPU time | 29.87 seconds |
| Started | Sep 09 08:30:01 AM UTC 24 |
| Finished | Sep 09 08:30:33 AM UTC 24 |
| Peak memory | 212220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697449080 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_partial_access.3697449080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.1849644674 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 62278459657 ps |
| CPU time | 362.17 seconds |
| Started | Sep 09 08:30:16 AM UTC 24 |
| Finished | Sep 09 08:36:23 AM UTC 24 |
| Peak memory | 211908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849644674 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_partial_a ccess_b2b.1849644674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.2550650185 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 916282143 ps |
| CPU time | 4.28 seconds |
| Started | Sep 09 08:30:51 AM UTC 24 |
| Finished | Sep 09 08:30:57 AM UTC 24 |
| Peak memory | 212152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550650185 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.2550650185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_regwen.4174092251 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 25727552940 ps |
| CPU time | 755.83 seconds |
| Started | Sep 09 08:30:50 AM UTC 24 |
| Finished | Sep 09 08:43:35 AM UTC 24 |
| Peak memory | 376680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174092251 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.4174092251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_smoke.3373551301 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 2370011017 ps |
| CPU time | 82.65 seconds |
| Started | Sep 09 08:29:52 AM UTC 24 |
| Finished | Sep 09 08:31:17 AM UTC 24 |
| Peak memory | 354152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373551301 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.3373551301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all.3954098617 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 125961622438 ps |
| CPU time | 4097.63 seconds |
| Started | Sep 09 08:31:20 AM UTC 24 |
| Finished | Sep 09 09:40:20 AM UTC 24 |
| Peak memory | 390744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39540986 17 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_a ll.3954098617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.3373333271 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 1578458714 ps |
| CPU time | 109.24 seconds |
| Started | Sep 09 08:31:18 AM UTC 24 |
| Finished | Sep 09 08:33:09 AM UTC 24 |
| Peak memory | 226284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373333271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.3373333271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.2304939763 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 5559390182 ps |
| CPU time | 275.71 seconds |
| Started | Sep 09 08:30:00 AM UTC 24 |
| Finished | Sep 09 08:34:40 AM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304939763 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_pipeline.2304939763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.1060375774 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 707299384 ps |
| CPU time | 20.12 seconds |
| Started | Sep 09 08:30:31 AM UTC 24 |
| Finished | Sep 09 08:30:52 AM UTC 24 |
| Peak memory | 261996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1060375774 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl _throughput_w_partial_write.1060375774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.1094856094 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 99619431533 ps |
| CPU time | 1025.37 seconds |
| Started | Sep 09 08:03:51 AM UTC 24 |
| Finished | Sep 09 08:21:07 AM UTC 24 |
| Peak memory | 387080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094856094 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_access_durin g_key_req.1094856094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_alert_test.1181491619 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 19563763 ps |
| CPU time | 0.81 seconds |
| Started | Sep 09 08:03:53 AM UTC 24 |
| Finished | Sep 09 08:03:55 AM UTC 24 |
| Peak memory | 211056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181491619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_alert_test.1181491619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_bijection.851991054 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 20672824218 ps |
| CPU time | 1444.2 seconds |
| Started | Sep 09 08:03:49 AM UTC 24 |
| Finished | Sep 09 08:28:10 AM UTC 24 |
| Peak memory | 213644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851991054 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection.851991054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_executable.3902436750 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 69841389664 ps |
| CPU time | 1078.39 seconds |
| Started | Sep 09 08:03:51 AM UTC 24 |
| Finished | Sep 09 08:22:02 AM UTC 24 |
| Peak memory | 389200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902436750 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executable.3902436750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.4275591732 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 34849462587 ps |
| CPU time | 77.42 seconds |
| Started | Sep 09 08:03:51 AM UTC 24 |
| Finished | Sep 09 08:05:10 AM UTC 24 |
| Peak memory | 222200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275591732 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_escalation.4275591732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.3078074156 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 3433357760 ps |
| CPU time | 77.18 seconds |
| Started | Sep 09 08:03:51 AM UTC 24 |
| Finished | Sep 09 08:05:10 AM UTC 24 |
| Peak memory | 364408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3078074156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_m ax_throughput.3078074156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.3626089826 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 24344423233 ps |
| CPU time | 193 seconds |
| Started | Sep 09 08:03:51 AM UTC 24 |
| Finished | Sep 09 08:07:07 AM UTC 24 |
| Peak memory | 222264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626089826 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_mem_partial_access.3626089826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.259432941 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 19134591040 ps |
| CPU time | 211.97 seconds |
| Started | Sep 09 08:03:51 AM UTC 24 |
| Finished | Sep 09 08:07:27 AM UTC 24 |
| Peak memory | 211940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259432941 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_mem_walk.259432941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.1784255457 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 102098993570 ps |
| CPU time | 1287.82 seconds |
| Started | Sep 09 08:03:49 AM UTC 24 |
| Finished | Sep 09 08:25:31 AM UTC 24 |
| Peak memory | 386508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784255457 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multiple_keys.1784255457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access.252503001 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 1537014846 ps |
| CPU time | 24.33 seconds |
| Started | Sep 09 08:03:49 AM UTC 24 |
| Finished | Sep 09 08:04:15 AM UTC 24 |
| Peak memory | 211888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252503001 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_partial_access.252503001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.1370613547 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 354492836 ps |
| CPU time | 6.39 seconds |
| Started | Sep 09 08:03:51 AM UTC 24 |
| Finished | Sep 09 08:03:58 AM UTC 24 |
| Peak memory | 212032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370613547 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.1370613547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.2830307980 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 494697764 ps |
| CPU time | 2.44 seconds |
| Started | Sep 09 08:03:53 AM UTC 24 |
| Finished | Sep 09 08:03:57 AM UTC 24 |
| Peak memory | 247752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830307980 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_sec_cm.2830307980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_smoke.2283954331 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1335152009 ps |
| CPU time | 55.36 seconds |
| Started | Sep 09 08:03:49 AM UTC 24 |
| Finished | Sep 09 08:04:46 AM UTC 24 |
| Peak memory | 339816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283954331 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.2283954331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all.888896352 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 59810735433 ps |
| CPU time | 2856.73 seconds |
| Started | Sep 09 08:03:52 AM UTC 24 |
| Finished | Sep 09 08:51:58 AM UTC 24 |
| Peak memory | 390916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88889635 2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all.888896352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.3617126759 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 6474219323 ps |
| CPU time | 20.53 seconds |
| Started | Sep 09 08:03:52 AM UTC 24 |
| Finished | Sep 09 08:04:14 AM UTC 24 |
| Peak memory | 222456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617126759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.3617126759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.636564896 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 10870121085 ps |
| CPU time | 295.18 seconds |
| Started | Sep 09 08:03:49 AM UTC 24 |
| Finished | Sep 09 08:08:49 AM UTC 24 |
| Peak memory | 211936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636564896 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_pipeline.636564896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.3528349720 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 2969245123 ps |
| CPU time | 24.89 seconds |
| Started | Sep 09 08:03:51 AM UTC 24 |
| Finished | Sep 09 08:04:17 AM UTC 24 |
| Peak memory | 280452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3528349720 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ throughput_w_partial_write.3528349720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.4161371944 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 18662634153 ps |
| CPU time | 366.88 seconds |
| Started | Sep 09 08:32:55 AM UTC 24 |
| Finished | Sep 09 08:39:06 AM UTC 24 |
| Peak memory | 364408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161371944 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_access_duri ng_key_req.4161371944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/20.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_alert_test.2553356207 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 41445286 ps |
| CPU time | 0.96 seconds |
| Started | Sep 09 08:33:51 AM UTC 24 |
| Finished | Sep 09 08:33:53 AM UTC 24 |
| Peak memory | 211056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553356207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_alert_test.2553356207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/20.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_bijection.151067424 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 264147991013 ps |
| CPU time | 1825.5 seconds |
| Started | Sep 09 08:31:55 AM UTC 24 |
| Finished | Sep 09 09:02:42 AM UTC 24 |
| Peak memory | 213564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151067424 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection.151067424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/20.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_executable.2069462775 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 86219216074 ps |
| CPU time | 1133.62 seconds |
| Started | Sep 09 08:32:59 AM UTC 24 |
| Finished | Sep 09 08:52:04 AM UTC 24 |
| Peak memory | 389044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069462775 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executable.2069462775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/20.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.729940951 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 8767838176 ps |
| CPU time | 49.07 seconds |
| Started | Sep 09 08:32:50 AM UTC 24 |
| Finished | Sep 09 08:33:40 AM UTC 24 |
| Peak memory | 211936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729940951 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_escalation.729940951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/20.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.61475279 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 2697509653 ps |
| CPU time | 12.98 seconds |
| Started | Sep 09 08:32:35 AM UTC 24 |
| Finished | Sep 09 08:32:49 AM UTC 24 |
| Peak memory | 228280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 61475279 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ma x_throughput.61475279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/20.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.3745318032 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 4994485594 ps |
| CPU time | 192.52 seconds |
| Started | Sep 09 08:33:18 AM UTC 24 |
| Finished | Sep 09 08:36:33 AM UTC 24 |
| Peak memory | 222324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745318032 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_mem_partial_access.3745318032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/20.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.4202804145 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 18766822834 ps |
| CPU time | 299.78 seconds |
| Started | Sep 09 08:33:10 AM UTC 24 |
| Finished | Sep 09 08:38:15 AM UTC 24 |
| Peak memory | 222372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202804145 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_mem_walk.4202804145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/20.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.3990007628 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 15166736781 ps |
| CPU time | 294.85 seconds |
| Started | Sep 09 08:31:46 AM UTC 24 |
| Finished | Sep 09 08:36:45 AM UTC 24 |
| Peak memory | 385068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990007628 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multiple_keys.3990007628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/20.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access.2005784611 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 448343800 ps |
| CPU time | 11.47 seconds |
| Started | Sep 09 08:32:21 AM UTC 24 |
| Finished | Sep 09 08:32:34 AM UTC 24 |
| Peak memory | 231200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005784611 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_partial_access.2005784611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/20.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.218109421 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 15477884248 ps |
| CPU time | 541.16 seconds |
| Started | Sep 09 08:32:33 AM UTC 24 |
| Finished | Sep 09 08:41:41 AM UTC 24 |
| Peak memory | 211928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218109421 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_partial_ac cess_b2b.218109421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/20.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.2836172588 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 356817056 ps |
| CPU time | 5.44 seconds |
| Started | Sep 09 08:33:10 AM UTC 24 |
| Finished | Sep 09 08:33:17 AM UTC 24 |
| Peak memory | 212024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836172588 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.2836172588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/20.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_regwen.2472592140 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 13952783530 ps |
| CPU time | 849.94 seconds |
| Started | Sep 09 08:33:06 AM UTC 24 |
| Finished | Sep 09 08:47:25 AM UTC 24 |
| Peak memory | 389052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472592140 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.2472592140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/20.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_smoke.2971642996 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 2057695247 ps |
| CPU time | 24.16 seconds |
| Started | Sep 09 08:31:40 AM UTC 24 |
| Finished | Sep 09 08:32:06 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971642996 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.2971642996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/20.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all.3147750037 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 32896565371 ps |
| CPU time | 1297.99 seconds |
| Started | Sep 09 08:33:41 AM UTC 24 |
| Finished | Sep 09 08:55:33 AM UTC 24 |
| Peak memory | 386908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31477500 37 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_a ll.3147750037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/20.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.1492234369 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 200139628 ps |
| CPU time | 15.65 seconds |
| Started | Sep 09 08:33:37 AM UTC 24 |
| Finished | Sep 09 08:33:54 AM UTC 24 |
| Peak memory | 222192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492234369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.1492234369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/20.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.205933558 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 21432457786 ps |
| CPU time | 352.29 seconds |
| Started | Sep 09 08:32:06 AM UTC 24 |
| Finished | Sep 09 08:38:03 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205933558 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_pipeline.205933558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/20.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.3615986500 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 736678587 ps |
| CPU time | 21.16 seconds |
| Started | Sep 09 08:32:43 AM UTC 24 |
| Finished | Sep 09 08:33:05 AM UTC 24 |
| Peak memory | 262132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3615986500 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl _throughput_w_partial_write.3615986500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/20.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.1358415726 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 41895516996 ps |
| CPU time | 430.69 seconds |
| Started | Sep 09 08:34:55 AM UTC 24 |
| Finished | Sep 09 08:42:10 AM UTC 24 |
| Peak memory | 386920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358415726 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_access_duri ng_key_req.1358415726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/21.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_alert_test.1934833044 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 13650967 ps |
| CPU time | 0.94 seconds |
| Started | Sep 09 08:35:59 AM UTC 24 |
| Finished | Sep 09 08:36:01 AM UTC 24 |
| Peak memory | 210996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934833044 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_alert_test.1934833044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/21.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_bijection.3901148689 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 170560606409 ps |
| CPU time | 3221.88 seconds |
| Started | Sep 09 08:33:55 AM UTC 24 |
| Finished | Sep 09 09:28:14 AM UTC 24 |
| Peak memory | 213648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901148689 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection.3901148689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/21.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_executable.4238058969 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 16463623213 ps |
| CPU time | 478.73 seconds |
| Started | Sep 09 08:35:01 AM UTC 24 |
| Finished | Sep 09 08:43:05 AM UTC 24 |
| Peak memory | 382816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238058969 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executable.4238058969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/21.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.1536196243 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 37765477010 ps |
| CPU time | 96.73 seconds |
| Started | Sep 09 08:34:51 AM UTC 24 |
| Finished | Sep 09 08:36:30 AM UTC 24 |
| Peak memory | 211884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536196243 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_escalation.1536196243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/21.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.3805150269 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 754561994 ps |
| CPU time | 27.88 seconds |
| Started | Sep 09 08:34:41 AM UTC 24 |
| Finished | Sep 09 08:35:10 AM UTC 24 |
| Peak memory | 300848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3805150269 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ max_throughput.3805150269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/21.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.721053886 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 9486821710 ps |
| CPU time | 87.66 seconds |
| Started | Sep 09 08:35:29 AM UTC 24 |
| Finished | Sep 09 08:36:58 AM UTC 24 |
| Peak memory | 229432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721053886 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_mem_partial_access.721053886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/21.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.837526956 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 78144948275 ps |
| CPU time | 426.91 seconds |
| Started | Sep 09 08:35:24 AM UTC 24 |
| Finished | Sep 09 08:42:37 AM UTC 24 |
| Peak memory | 222372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837526956 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_mem_walk.837526956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/21.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.900634805 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 14109993869 ps |
| CPU time | 1172.2 seconds |
| Started | Sep 09 08:33:54 AM UTC 24 |
| Finished | Sep 09 08:53:40 AM UTC 24 |
| Peak memory | 388968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900634805 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multiple_keys.900634805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/21.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access.629212123 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 2613552004 ps |
| CPU time | 13.3 seconds |
| Started | Sep 09 08:34:35 AM UTC 24 |
| Finished | Sep 09 08:34:49 AM UTC 24 |
| Peak memory | 212028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629212123 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_partial_access.629212123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/21.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.3535355720 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 17226748791 ps |
| CPU time | 515.69 seconds |
| Started | Sep 09 08:34:39 AM UTC 24 |
| Finished | Sep 09 08:43:21 AM UTC 24 |
| Peak memory | 211964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535355720 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_partial_a ccess_b2b.3535355720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/21.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.1319861305 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 1409786697 ps |
| CPU time | 5.34 seconds |
| Started | Sep 09 08:35:17 AM UTC 24 |
| Finished | Sep 09 08:35:24 AM UTC 24 |
| Peak memory | 212024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319861305 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.1319861305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/21.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_regwen.3126016557 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 51001865785 ps |
| CPU time | 1144.04 seconds |
| Started | Sep 09 08:35:10 AM UTC 24 |
| Finished | Sep 09 08:54:27 AM UTC 24 |
| Peak memory | 380776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126016557 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.3126016557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/21.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_smoke.791591983 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 5120502132 ps |
| CPU time | 38.09 seconds |
| Started | Sep 09 08:33:54 AM UTC 24 |
| Finished | Sep 09 08:34:34 AM UTC 24 |
| Peak memory | 323620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791591983 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.791591983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/21.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all.815424339 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 299542216463 ps |
| CPU time | 2456.66 seconds |
| Started | Sep 09 08:35:36 AM UTC 24 |
| Finished | Sep 09 09:16:57 AM UTC 24 |
| Peak memory | 384512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81542433 9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all.815424339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/21.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.49163361 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 8904165181 ps |
| CPU time | 304.9 seconds |
| Started | Sep 09 08:34:07 AM UTC 24 |
| Finished | Sep 09 08:39:17 AM UTC 24 |
| Peak memory | 211924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49163361 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_pipeline.49163361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/21.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.1821591055 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 777950280 ps |
| CPU time | 81.12 seconds |
| Started | Sep 09 08:34:50 AM UTC 24 |
| Finished | Sep 09 08:36:13 AM UTC 24 |
| Peak memory | 354084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1821591055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl _throughput_w_partial_write.1821591055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/21.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.2263723992 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 15023290302 ps |
| CPU time | 1019.02 seconds |
| Started | Sep 09 08:36:46 AM UTC 24 |
| Finished | Sep 09 08:53:57 AM UTC 24 |
| Peak memory | 378732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263723992 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_access_duri ng_key_req.2263723992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/22.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_alert_test.829733757 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 20576506 ps |
| CPU time | 0.85 seconds |
| Started | Sep 09 08:38:10 AM UTC 24 |
| Finished | Sep 09 08:38:12 AM UTC 24 |
| Peak memory | 210996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829733757 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_alert_test.829733757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/22.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_bijection.3027292770 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 550089224675 ps |
| CPU time | 3131.53 seconds |
| Started | Sep 09 08:36:14 AM UTC 24 |
| Finished | Sep 09 09:29:01 AM UTC 24 |
| Peak memory | 213496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027292770 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection.3027292770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/22.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_executable.2771370353 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 22469264011 ps |
| CPU time | 861.65 seconds |
| Started | Sep 09 08:36:47 AM UTC 24 |
| Finished | Sep 09 08:51:19 AM UTC 24 |
| Peak memory | 380836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771370353 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executable.2771370353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/22.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.2405356924 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 74984866785 ps |
| CPU time | 108.23 seconds |
| Started | Sep 09 08:36:43 AM UTC 24 |
| Finished | Sep 09 08:38:33 AM UTC 24 |
| Peak memory | 211952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405356924 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_escalation.2405356924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/22.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.32754984 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 691683770 ps |
| CPU time | 9.93 seconds |
| Started | Sep 09 08:36:31 AM UTC 24 |
| Finished | Sep 09 08:36:42 AM UTC 24 |
| Peak memory | 211628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 32754984 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ma x_throughput.32754984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/22.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.3166817589 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 9854078385 ps |
| CPU time | 80.55 seconds |
| Started | Sep 09 08:37:07 AM UTC 24 |
| Finished | Sep 09 08:38:30 AM UTC 24 |
| Peak memory | 222240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166817589 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_mem_partial_access.3166817589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/22.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.1360280087 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 4067788876 ps |
| CPU time | 236.83 seconds |
| Started | Sep 09 08:37:01 AM UTC 24 |
| Finished | Sep 09 08:41:01 AM UTC 24 |
| Peak memory | 222204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360280087 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_mem_walk.1360280087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/22.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.979694895 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 8176417850 ps |
| CPU time | 788.4 seconds |
| Started | Sep 09 08:36:14 AM UTC 24 |
| Finished | Sep 09 08:49:32 AM UTC 24 |
| Peak memory | 387196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979694895 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multiple_keys.979694895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/22.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access.4126455180 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 6585263108 ps |
| CPU time | 34.5 seconds |
| Started | Sep 09 08:36:23 AM UTC 24 |
| Finished | Sep 09 08:36:59 AM UTC 24 |
| Peak memory | 212120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126455180 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_partial_access.4126455180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/22.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.224456286 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 19125583884 ps |
| CPU time | 531.57 seconds |
| Started | Sep 09 08:36:29 AM UTC 24 |
| Finished | Sep 09 08:45:28 AM UTC 24 |
| Peak memory | 212080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224456286 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_partial_ac cess_b2b.224456286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/22.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.868851124 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 681804249 ps |
| CPU time | 5.47 seconds |
| Started | Sep 09 08:37:00 AM UTC 24 |
| Finished | Sep 09 08:37:07 AM UTC 24 |
| Peak memory | 211948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868851124 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.868851124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/22.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_regwen.4151667948 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 17533517485 ps |
| CPU time | 618.79 seconds |
| Started | Sep 09 08:36:59 AM UTC 24 |
| Finished | Sep 09 08:47:25 AM UTC 24 |
| Peak memory | 384948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151667948 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.4151667948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/22.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_smoke.124412370 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 3821837746 ps |
| CPU time | 10.46 seconds |
| Started | Sep 09 08:36:02 AM UTC 24 |
| Finished | Sep 09 08:36:14 AM UTC 24 |
| Peak memory | 225316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124412370 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.124412370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/22.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all.429758838 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 68991710995 ps |
| CPU time | 2217.33 seconds |
| Started | Sep 09 08:38:04 AM UTC 24 |
| Finished | Sep 09 09:15:23 AM UTC 24 |
| Peak memory | 390640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42975883 8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all.429758838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/22.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.3009241809 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 972683364 ps |
| CPU time | 38.86 seconds |
| Started | Sep 09 08:37:28 AM UTC 24 |
| Finished | Sep 09 08:38:09 AM UTC 24 |
| Peak memory | 222320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009241809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.3009241809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/22.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.4064596041 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 6728816178 ps |
| CPU time | 205.84 seconds |
| Started | Sep 09 08:36:17 AM UTC 24 |
| Finished | Sep 09 08:39:46 AM UTC 24 |
| Peak memory | 211936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064596041 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_pipeline.4064596041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/22.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.443080740 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 950215305 ps |
| CPU time | 23.67 seconds |
| Started | Sep 09 08:36:35 AM UTC 24 |
| Finished | Sep 09 08:37:00 AM UTC 24 |
| Peak memory | 278396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =443080740 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ throughput_w_partial_write.443080740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/22.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.2287480238 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 147369452397 ps |
| CPU time | 869.69 seconds |
| Started | Sep 09 08:39:17 AM UTC 24 |
| Finished | Sep 09 08:53:57 AM UTC 24 |
| Peak memory | 386916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287480238 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_access_duri ng_key_req.2287480238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/23.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_alert_test.1765299295 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 135961682 ps |
| CPU time | 0.85 seconds |
| Started | Sep 09 08:40:38 AM UTC 24 |
| Finished | Sep 09 08:40:40 AM UTC 24 |
| Peak memory | 210996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765299295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_alert_test.1765299295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/23.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_bijection.887505067 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 90505252281 ps |
| CPU time | 1689.86 seconds |
| Started | Sep 09 08:38:20 AM UTC 24 |
| Finished | Sep 09 09:06:50 AM UTC 24 |
| Peak memory | 212116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887505067 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection.887505067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/23.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_executable.719560016 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 3712065830 ps |
| CPU time | 189.76 seconds |
| Started | Sep 09 08:39:19 AM UTC 24 |
| Finished | Sep 09 08:42:32 AM UTC 24 |
| Peak memory | 350128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719560016 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executable.719560016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/23.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.2252874030 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 10034382899 ps |
| CPU time | 88.2 seconds |
| Started | Sep 09 08:39:07 AM UTC 24 |
| Finished | Sep 09 08:40:37 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252874030 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_escalation.2252874030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/23.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.4169268110 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 3968401213 ps |
| CPU time | 13.5 seconds |
| Started | Sep 09 08:38:47 AM UTC 24 |
| Finished | Sep 09 08:39:01 AM UTC 24 |
| Peak memory | 229224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4169268110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ max_throughput.4169268110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/23.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.533515180 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 2714390041 ps |
| CPU time | 110.16 seconds |
| Started | Sep 09 08:40:04 AM UTC 24 |
| Finished | Sep 09 08:41:56 AM UTC 24 |
| Peak memory | 222192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533515180 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_mem_partial_access.533515180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/23.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.216524267 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 18678468251 ps |
| CPU time | 316.73 seconds |
| Started | Sep 09 08:39:54 AM UTC 24 |
| Finished | Sep 09 08:45:15 AM UTC 24 |
| Peak memory | 222384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216524267 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_mem_walk.216524267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/23.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.2491177508 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 66893382285 ps |
| CPU time | 707.9 seconds |
| Started | Sep 09 08:38:15 AM UTC 24 |
| Finished | Sep 09 08:50:11 AM UTC 24 |
| Peak memory | 389164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491177508 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multiple_keys.2491177508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/23.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access.2177361193 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 5660674848 ps |
| CPU time | 10.39 seconds |
| Started | Sep 09 08:38:35 AM UTC 24 |
| Finished | Sep 09 08:38:46 AM UTC 24 |
| Peak memory | 212212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177361193 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_partial_access.2177361193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/23.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.200796419 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 25779092798 ps |
| CPU time | 471.3 seconds |
| Started | Sep 09 08:38:45 AM UTC 24 |
| Finished | Sep 09 08:46:42 AM UTC 24 |
| Peak memory | 212128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200796419 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_partial_ac cess_b2b.200796419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/23.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.530367391 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 364115173 ps |
| CPU time | 4.46 seconds |
| Started | Sep 09 08:39:47 AM UTC 24 |
| Finished | Sep 09 08:39:53 AM UTC 24 |
| Peak memory | 212156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530367391 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.530367391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/23.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_regwen.98720354 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 14047181888 ps |
| CPU time | 353.22 seconds |
| Started | Sep 09 08:39:24 AM UTC 24 |
| Finished | Sep 09 08:45:22 AM UTC 24 |
| Peak memory | 388972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98720354 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.98720354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/23.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_smoke.2373678466 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 769802214 ps |
| CPU time | 5.14 seconds |
| Started | Sep 09 08:38:13 AM UTC 24 |
| Finished | Sep 09 08:38:19 AM UTC 24 |
| Peak memory | 211616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373678466 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.2373678466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/23.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all.2862607420 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 33140516073 ps |
| CPU time | 2779.21 seconds |
| Started | Sep 09 08:40:35 AM UTC 24 |
| Finished | Sep 09 09:27:21 AM UTC 24 |
| Peak memory | 392712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28626074 20 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_a ll.2862607420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/23.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.1005357363 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 3879675661 ps |
| CPU time | 34.68 seconds |
| Started | Sep 09 08:40:33 AM UTC 24 |
| Finished | Sep 09 08:41:09 AM UTC 24 |
| Peak memory | 222344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005357363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.1005357363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/23.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.1663408797 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 7990016922 ps |
| CPU time | 308.73 seconds |
| Started | Sep 09 08:38:30 AM UTC 24 |
| Finished | Sep 09 08:43:44 AM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663408797 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_pipeline.1663408797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/23.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.3941755847 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 1602587987 ps |
| CPU time | 59.62 seconds |
| Started | Sep 09 08:39:02 AM UTC 24 |
| Finished | Sep 09 08:40:03 AM UTC 24 |
| Peak memory | 382756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3941755847 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl _throughput_w_partial_write.3941755847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/23.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.1483176785 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 87925286238 ps |
| CPU time | 764.07 seconds |
| Started | Sep 09 08:42:14 AM UTC 24 |
| Finished | Sep 09 08:55:06 AM UTC 24 |
| Peak memory | 386932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483176785 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_access_duri ng_key_req.1483176785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/24.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_alert_test.2565101136 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 24055252 ps |
| CPU time | 0.92 seconds |
| Started | Sep 09 08:43:30 AM UTC 24 |
| Finished | Sep 09 08:43:32 AM UTC 24 |
| Peak memory | 211056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565101136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_alert_test.2565101136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/24.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_bijection.504023680 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 423365461595 ps |
| CPU time | 2646.35 seconds |
| Started | Sep 09 08:41:02 AM UTC 24 |
| Finished | Sep 09 09:25:38 AM UTC 24 |
| Peak memory | 213636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504023680 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection.504023680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/24.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_executable.3062886768 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 69534120192 ps |
| CPU time | 713.22 seconds |
| Started | Sep 09 08:42:33 AM UTC 24 |
| Finished | Sep 09 08:54:35 AM UTC 24 |
| Peak memory | 385120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062886768 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executable.3062886768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/24.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.2338235005 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 10500007143 ps |
| CPU time | 75.97 seconds |
| Started | Sep 09 08:42:11 AM UTC 24 |
| Finished | Sep 09 08:43:29 AM UTC 24 |
| Peak memory | 222168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338235005 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_escalation.2338235005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/24.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.3763439050 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 1376884740 ps |
| CPU time | 10.81 seconds |
| Started | Sep 09 08:42:01 AM UTC 24 |
| Finished | Sep 09 08:42:13 AM UTC 24 |
| Peak memory | 229008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3763439050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ max_throughput.3763439050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/24.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.2278084596 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 24291538338 ps |
| CPU time | 157.2 seconds |
| Started | Sep 09 08:43:06 AM UTC 24 |
| Finished | Sep 09 08:45:46 AM UTC 24 |
| Peak memory | 222460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278084596 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_mem_partial_access.2278084596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/24.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.4197718861 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 5416841126 ps |
| CPU time | 401.94 seconds |
| Started | Sep 09 08:43:01 AM UTC 24 |
| Finished | Sep 09 08:49:48 AM UTC 24 |
| Peak memory | 222132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197718861 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_mem_walk.4197718861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/24.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.2879164164 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 15397279040 ps |
| CPU time | 668.25 seconds |
| Started | Sep 09 08:40:49 AM UTC 24 |
| Finished | Sep 09 08:52:05 AM UTC 24 |
| Peak memory | 380848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879164164 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multiple_keys.2879164164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/24.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access.4274573972 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 2622086621 ps |
| CPU time | 17.41 seconds |
| Started | Sep 09 08:41:42 AM UTC 24 |
| Finished | Sep 09 08:42:00 AM UTC 24 |
| Peak memory | 274464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274573972 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_partial_access.4274573972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/24.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.3694015566 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 6467603137 ps |
| CPU time | 375.19 seconds |
| Started | Sep 09 08:41:57 AM UTC 24 |
| Finished | Sep 09 08:48:17 AM UTC 24 |
| Peak memory | 212036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694015566 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_partial_a ccess_b2b.3694015566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/24.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.597105352 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 369716925 ps |
| CPU time | 5.6 seconds |
| Started | Sep 09 08:42:54 AM UTC 24 |
| Finished | Sep 09 08:43:00 AM UTC 24 |
| Peak memory | 211940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597105352 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.597105352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/24.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_regwen.86498721 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 14595172565 ps |
| CPU time | 464.6 seconds |
| Started | Sep 09 08:42:38 AM UTC 24 |
| Finished | Sep 09 08:50:29 AM UTC 24 |
| Peak memory | 378744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86498721 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.86498721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/24.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_smoke.2816639337 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 1392565137 ps |
| CPU time | 6.4 seconds |
| Started | Sep 09 08:40:41 AM UTC 24 |
| Finished | Sep 09 08:40:48 AM UTC 24 |
| Peak memory | 211696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816639337 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.2816639337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/24.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all.3506037682 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 736618625519 ps |
| CPU time | 3934.53 seconds |
| Started | Sep 09 08:43:22 AM UTC 24 |
| Finished | Sep 09 09:49:39 AM UTC 24 |
| Peak memory | 386628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35060376 82 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_a ll.3506037682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/24.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.2112685590 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 5330637563 ps |
| CPU time | 65.19 seconds |
| Started | Sep 09 08:43:10 AM UTC 24 |
| Finished | Sep 09 08:44:17 AM UTC 24 |
| Peak memory | 245664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112685590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.2112685590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/24.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.2390549396 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 2801071605 ps |
| CPU time | 251.13 seconds |
| Started | Sep 09 08:41:09 AM UTC 24 |
| Finished | Sep 09 08:45:24 AM UTC 24 |
| Peak memory | 211956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390549396 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_pipeline.2390549396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/24.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.3214490106 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 1479339122 ps |
| CPU time | 45.02 seconds |
| Started | Sep 09 08:42:06 AM UTC 24 |
| Finished | Sep 09 08:42:52 AM UTC 24 |
| Peak memory | 337768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3214490106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl _throughput_w_partial_write.3214490106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/24.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.172284563 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 11412638618 ps |
| CPU time | 82.82 seconds |
| Started | Sep 09 08:45:01 AM UTC 24 |
| Finished | Sep 09 08:46:26 AM UTC 24 |
| Peak memory | 311212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172284563 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_access_durin g_key_req.172284563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/25.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_alert_test.1088166065 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 12100484 ps |
| CPU time | 0.97 seconds |
| Started | Sep 09 08:46:26 AM UTC 24 |
| Finished | Sep 09 08:46:28 AM UTC 24 |
| Peak memory | 211056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088166065 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_alert_test.1088166065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/25.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_bijection.3678663303 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 70574434073 ps |
| CPU time | 1215.74 seconds |
| Started | Sep 09 08:43:37 AM UTC 24 |
| Finished | Sep 09 09:04:07 AM UTC 24 |
| Peak memory | 211960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678663303 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection.3678663303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/25.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_executable.2499557800 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 19233857117 ps |
| CPU time | 1072.32 seconds |
| Started | Sep 09 08:45:15 AM UTC 24 |
| Finished | Sep 09 09:03:19 AM UTC 24 |
| Peak memory | 384836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499557800 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executable.2499557800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/25.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.4082896481 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 36286413888 ps |
| CPU time | 105.58 seconds |
| Started | Sep 09 08:44:45 AM UTC 24 |
| Finished | Sep 09 08:46:33 AM UTC 24 |
| Peak memory | 211892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082896481 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_escalation.4082896481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/25.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.853092319 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 763241280 ps |
| CPU time | 41 seconds |
| Started | Sep 09 08:44:18 AM UTC 24 |
| Finished | Sep 09 08:45:00 AM UTC 24 |
| Peak memory | 311216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 853092319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_m ax_throughput.853092319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/25.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.4141733600 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 1021941430 ps |
| CPU time | 78.88 seconds |
| Started | Sep 09 08:45:31 AM UTC 24 |
| Finished | Sep 09 08:46:52 AM UTC 24 |
| Peak memory | 229360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141733600 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_mem_partial_access.4141733600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/25.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.2064161984 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 5065079558 ps |
| CPU time | 200.08 seconds |
| Started | Sep 09 08:45:29 AM UTC 24 |
| Finished | Sep 09 08:48:52 AM UTC 24 |
| Peak memory | 222208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064161984 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_mem_walk.2064161984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/25.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.1505279636 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 29339166870 ps |
| CPU time | 2078.4 seconds |
| Started | Sep 09 08:43:36 AM UTC 24 |
| Finished | Sep 09 09:18:37 AM UTC 24 |
| Peak memory | 388588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505279636 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multiple_keys.1505279636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/25.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access.1991849371 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 463805023 ps |
| CPU time | 37.76 seconds |
| Started | Sep 09 08:44:05 AM UTC 24 |
| Finished | Sep 09 08:44:44 AM UTC 24 |
| Peak memory | 294756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991849371 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_partial_access.1991849371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/25.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.3462978033 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 5866398118 ps |
| CPU time | 266.49 seconds |
| Started | Sep 09 08:44:07 AM UTC 24 |
| Finished | Sep 09 08:48:39 AM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462978033 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_partial_a ccess_b2b.3462978033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/25.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.3615369424 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 358960694 ps |
| CPU time | 5.64 seconds |
| Started | Sep 09 08:45:25 AM UTC 24 |
| Finished | Sep 09 08:45:31 AM UTC 24 |
| Peak memory | 211944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615369424 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.3615369424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/25.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_regwen.2197540819 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 33481665482 ps |
| CPU time | 445.59 seconds |
| Started | Sep 09 08:45:23 AM UTC 24 |
| Finished | Sep 09 08:52:53 AM UTC 24 |
| Peak memory | 384888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197540819 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.2197540819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/25.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_smoke.1610447787 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 1684681921 ps |
| CPU time | 29.82 seconds |
| Started | Sep 09 08:43:33 AM UTC 24 |
| Finished | Sep 09 08:44:04 AM UTC 24 |
| Peak memory | 211864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610447787 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.1610447787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/25.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all.37618731 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 508243395780 ps |
| CPU time | 3493.67 seconds |
| Started | Sep 09 08:45:46 AM UTC 24 |
| Finished | Sep 09 09:44:34 AM UTC 24 |
| Peak memory | 392772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37618731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all.37618731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/25.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.3529914354 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 1557296646 ps |
| CPU time | 119.26 seconds |
| Started | Sep 09 08:45:32 AM UTC 24 |
| Finished | Sep 09 08:47:34 AM UTC 24 |
| Peak memory | 366456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529914354 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.3529914354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/25.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.4063838899 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 11864255860 ps |
| CPU time | 369.98 seconds |
| Started | Sep 09 08:43:45 AM UTC 24 |
| Finished | Sep 09 08:50:00 AM UTC 24 |
| Peak memory | 212028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063838899 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_pipeline.4063838899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/25.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.3636338680 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 766916150 ps |
| CPU time | 48.34 seconds |
| Started | Sep 09 08:44:40 AM UTC 24 |
| Finished | Sep 09 08:45:30 AM UTC 24 |
| Peak memory | 311156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3636338680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl _throughput_w_partial_write.3636338680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/25.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.3863321686 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 64556487134 ps |
| CPU time | 1297.85 seconds |
| Started | Sep 09 08:48:18 AM UTC 24 |
| Finished | Sep 09 09:10:09 AM UTC 24 |
| Peak memory | 389188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863321686 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_access_duri ng_key_req.3863321686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/26.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_alert_test.71673342 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 19345931 ps |
| CPU time | 1.01 seconds |
| Started | Sep 09 08:49:33 AM UTC 24 |
| Finished | Sep 09 08:49:35 AM UTC 24 |
| Peak memory | 210968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71673342 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_alert_test.71673342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/26.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_bijection.540818379 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 183224314365 ps |
| CPU time | 1701.67 seconds |
| Started | Sep 09 08:46:43 AM UTC 24 |
| Finished | Sep 09 09:15:23 AM UTC 24 |
| Peak memory | 211952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540818379 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection.540818379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/26.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_executable.2213371978 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 16177662166 ps |
| CPU time | 1041.73 seconds |
| Started | Sep 09 08:48:23 AM UTC 24 |
| Finished | Sep 09 09:05:56 AM UTC 24 |
| Peak memory | 389160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213371978 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executable.2213371978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/26.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.924585055 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 26711927856 ps |
| CPU time | 137.12 seconds |
| Started | Sep 09 08:47:34 AM UTC 24 |
| Finished | Sep 09 08:49:54 AM UTC 24 |
| Peak memory | 222276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924585055 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_escalation.924585055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/26.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.2643048965 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 1556918851 ps |
| CPU time | 101.05 seconds |
| Started | Sep 09 08:47:26 AM UTC 24 |
| Finished | Sep 09 08:49:09 AM UTC 24 |
| Peak memory | 372520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2643048965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ max_throughput.2643048965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/26.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.2469851739 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 1015424225 ps |
| CPU time | 82.34 seconds |
| Started | Sep 09 08:48:53 AM UTC 24 |
| Finished | Sep 09 08:50:18 AM UTC 24 |
| Peak memory | 229136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469851739 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_mem_partial_access.2469851739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/26.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.1315858383 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 2635859213 ps |
| CPU time | 172.88 seconds |
| Started | Sep 09 08:48:44 AM UTC 24 |
| Finished | Sep 09 08:51:40 AM UTC 24 |
| Peak memory | 222132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315858383 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_mem_walk.1315858383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/26.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.1540826949 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 2363350715 ps |
| CPU time | 158.92 seconds |
| Started | Sep 09 08:46:34 AM UTC 24 |
| Finished | Sep 09 08:49:15 AM UTC 24 |
| Peak memory | 344168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540826949 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multiple_keys.1540826949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/26.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access.2554172753 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 5454981893 ps |
| CPU time | 31.31 seconds |
| Started | Sep 09 08:46:53 AM UTC 24 |
| Finished | Sep 09 08:47:25 AM UTC 24 |
| Peak memory | 212068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554172753 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_partial_access.2554172753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/26.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.1352235407 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 90845472285 ps |
| CPU time | 457.08 seconds |
| Started | Sep 09 08:47:25 AM UTC 24 |
| Finished | Sep 09 08:55:08 AM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352235407 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_partial_a ccess_b2b.1352235407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/26.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.2658327333 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 349376374 ps |
| CPU time | 3.55 seconds |
| Started | Sep 09 08:48:39 AM UTC 24 |
| Finished | Sep 09 08:48:44 AM UTC 24 |
| Peak memory | 212016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658327333 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.2658327333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/26.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_regwen.2218073261 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 13614533847 ps |
| CPU time | 349.57 seconds |
| Started | Sep 09 08:48:27 AM UTC 24 |
| Finished | Sep 09 08:54:22 AM UTC 24 |
| Peak memory | 380784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218073261 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.2218073261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/26.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_smoke.3370383552 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 819281516 ps |
| CPU time | 17.46 seconds |
| Started | Sep 09 08:46:29 AM UTC 24 |
| Finished | Sep 09 08:46:49 AM UTC 24 |
| Peak memory | 237284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370383552 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.3370383552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/26.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all.273169254 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 216009328076 ps |
| CPU time | 5524.48 seconds |
| Started | Sep 09 08:49:17 AM UTC 24 |
| Finished | Sep 09 10:22:21 AM UTC 24 |
| Peak memory | 382472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27316925 4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all.273169254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/26.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.3991020621 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 2866881394 ps |
| CPU time | 46.21 seconds |
| Started | Sep 09 08:49:10 AM UTC 24 |
| Finished | Sep 09 08:49:58 AM UTC 24 |
| Peak memory | 229284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991020621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.3991020621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/26.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.1303279681 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 28546346137 ps |
| CPU time | 305.75 seconds |
| Started | Sep 09 08:46:50 AM UTC 24 |
| Finished | Sep 09 08:52:00 AM UTC 24 |
| Peak memory | 211952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303279681 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_pipeline.1303279681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/26.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.2645049040 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 1509560598 ps |
| CPU time | 53.86 seconds |
| Started | Sep 09 08:47:26 AM UTC 24 |
| Finished | Sep 09 08:48:22 AM UTC 24 |
| Peak memory | 311144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2645049040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl _throughput_w_partial_write.2645049040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/26.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.3867585495 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 1730095706 ps |
| CPU time | 55.84 seconds |
| Started | Sep 09 08:50:30 AM UTC 24 |
| Finished | Sep 09 08:51:28 AM UTC 24 |
| Peak memory | 212028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867585495 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_access_duri ng_key_req.3867585495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/27.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_alert_test.1567359525 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 38149143 ps |
| CPU time | 1.02 seconds |
| Started | Sep 09 08:51:59 AM UTC 24 |
| Finished | Sep 09 08:52:01 AM UTC 24 |
| Peak memory | 210996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567359525 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_alert_test.1567359525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/27.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_bijection.3142836200 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 64300521063 ps |
| CPU time | 1217.31 seconds |
| Started | Sep 09 08:49:55 AM UTC 24 |
| Finished | Sep 09 09:10:27 AM UTC 24 |
| Peak memory | 212156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142836200 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection.3142836200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/27.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_executable.1629868834 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 38848858022 ps |
| CPU time | 1147.61 seconds |
| Started | Sep 09 08:50:30 AM UTC 24 |
| Finished | Sep 09 09:09:51 AM UTC 24 |
| Peak memory | 389052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629868834 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executable.1629868834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/27.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.3856332639 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 12078091987 ps |
| CPU time | 115.48 seconds |
| Started | Sep 09 08:50:24 AM UTC 24 |
| Finished | Sep 09 08:52:22 AM UTC 24 |
| Peak memory | 211952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856332639 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_escalation.3856332639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/27.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.685540150 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 756362887 ps |
| CPU time | 55.48 seconds |
| Started | Sep 09 08:50:12 AM UTC 24 |
| Finished | Sep 09 08:51:10 AM UTC 24 |
| Peak memory | 358252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 685540150 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_m ax_throughput.685540150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/27.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.1038635984 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 2542052239 ps |
| CPU time | 104.62 seconds |
| Started | Sep 09 08:51:20 AM UTC 24 |
| Finished | Sep 09 08:53:07 AM UTC 24 |
| Peak memory | 222400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038635984 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_mem_partial_access.1038635984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/27.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.2019676441 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 19700175029 ps |
| CPU time | 331.7 seconds |
| Started | Sep 09 08:51:19 AM UTC 24 |
| Finished | Sep 09 08:56:56 AM UTC 24 |
| Peak memory | 222212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019676441 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_mem_walk.2019676441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/27.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.326882739 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 4621553110 ps |
| CPU time | 66.52 seconds |
| Started | Sep 09 08:49:49 AM UTC 24 |
| Finished | Sep 09 08:50:57 AM UTC 24 |
| Peak memory | 268204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326882739 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multiple_keys.326882739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/27.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access.792747299 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 2940733048 ps |
| CPU time | 26.99 seconds |
| Started | Sep 09 08:50:00 AM UTC 24 |
| Finished | Sep 09 08:50:29 AM UTC 24 |
| Peak memory | 211960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792747299 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_partial_access.792747299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/27.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.4029352403 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 43808056721 ps |
| CPU time | 383.74 seconds |
| Started | Sep 09 08:50:12 AM UTC 24 |
| Finished | Sep 09 08:56:42 AM UTC 24 |
| Peak memory | 211960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029352403 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_partial_a ccess_b2b.4029352403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/27.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.484485187 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 360470199 ps |
| CPU time | 5.82 seconds |
| Started | Sep 09 08:51:11 AM UTC 24 |
| Finished | Sep 09 08:51:19 AM UTC 24 |
| Peak memory | 211940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484485187 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.484485187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/27.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_regwen.3601120437 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 26116628869 ps |
| CPU time | 319.77 seconds |
| Started | Sep 09 08:50:58 AM UTC 24 |
| Finished | Sep 09 08:56:22 AM UTC 24 |
| Peak memory | 382888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601120437 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.3601120437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/27.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_smoke.2135502752 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 2995708543 ps |
| CPU time | 45.14 seconds |
| Started | Sep 09 08:49:36 AM UTC 24 |
| Finished | Sep 09 08:50:22 AM UTC 24 |
| Peak memory | 313264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135502752 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.2135502752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/27.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.1698743989 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 8383079802 ps |
| CPU time | 57.28 seconds |
| Started | Sep 09 08:51:28 AM UTC 24 |
| Finished | Sep 09 08:52:27 AM UTC 24 |
| Peak memory | 224440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698743989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.1698743989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/27.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.3369305634 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 8089469711 ps |
| CPU time | 197.16 seconds |
| Started | Sep 09 08:49:59 AM UTC 24 |
| Finished | Sep 09 08:53:19 AM UTC 24 |
| Peak memory | 212156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369305634 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_pipeline.3369305634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/27.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.2801966610 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 820261008 ps |
| CPU time | 109.2 seconds |
| Started | Sep 09 08:50:18 AM UTC 24 |
| Finished | Sep 09 08:52:10 AM UTC 24 |
| Peak memory | 380908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2801966610 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl _throughput_w_partial_write.2801966610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/27.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.3903120321 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 28615890696 ps |
| CPU time | 532.97 seconds |
| Started | Sep 09 08:52:31 AM UTC 24 |
| Finished | Sep 09 09:01:30 AM UTC 24 |
| Peak memory | 386996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903120321 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_access_duri ng_key_req.3903120321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/28.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_alert_test.3134159662 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 22336151 ps |
| CPU time | 0.94 seconds |
| Started | Sep 09 08:53:59 AM UTC 24 |
| Finished | Sep 09 08:54:01 AM UTC 24 |
| Peak memory | 211028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134159662 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_alert_test.3134159662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/28.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_bijection.4027090839 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 159867822038 ps |
| CPU time | 1747.17 seconds |
| Started | Sep 09 08:52:05 AM UTC 24 |
| Finished | Sep 09 09:21:31 AM UTC 24 |
| Peak memory | 212120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027090839 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection.4027090839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/28.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_executable.3954301576 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 8373285604 ps |
| CPU time | 685.94 seconds |
| Started | Sep 09 08:52:54 AM UTC 24 |
| Finished | Sep 09 09:04:27 AM UTC 24 |
| Peak memory | 389240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954301576 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executable.3954301576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/28.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.2231202742 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 11948324619 ps |
| CPU time | 88.09 seconds |
| Started | Sep 09 08:52:29 AM UTC 24 |
| Finished | Sep 09 08:53:59 AM UTC 24 |
| Peak memory | 226224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231202742 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_escalation.2231202742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/28.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.2005361474 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 1463977589 ps |
| CPU time | 67.89 seconds |
| Started | Sep 09 08:52:22 AM UTC 24 |
| Finished | Sep 09 08:53:32 AM UTC 24 |
| Peak memory | 346096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2005361474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ max_throughput.2005361474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/28.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.619980504 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 20449774440 ps |
| CPU time | 210.7 seconds |
| Started | Sep 09 08:53:33 AM UTC 24 |
| Finished | Sep 09 08:57:07 AM UTC 24 |
| Peak memory | 229212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619980504 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_mem_partial_access.619980504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/28.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.3778776758 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 43123777993 ps |
| CPU time | 165.99 seconds |
| Started | Sep 09 08:53:27 AM UTC 24 |
| Finished | Sep 09 08:56:16 AM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778776758 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_mem_walk.3778776758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/28.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.3088112633 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 21563650359 ps |
| CPU time | 310.06 seconds |
| Started | Sep 09 08:52:02 AM UTC 24 |
| Finished | Sep 09 08:57:16 AM UTC 24 |
| Peak memory | 384872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088112633 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multiple_keys.3088112633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/28.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access.494718891 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 2937148199 ps |
| CPU time | 12.72 seconds |
| Started | Sep 09 08:52:11 AM UTC 24 |
| Finished | Sep 09 08:52:26 AM UTC 24 |
| Peak memory | 212020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494718891 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_partial_access.494718891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/28.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.2035246862 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 98220571220 ps |
| CPU time | 609.92 seconds |
| Started | Sep 09 08:52:21 AM UTC 24 |
| Finished | Sep 09 09:02:39 AM UTC 24 |
| Peak memory | 212152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035246862 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_partial_a ccess_b2b.2035246862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/28.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.204172042 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 775051225 ps |
| CPU time | 5.58 seconds |
| Started | Sep 09 08:53:20 AM UTC 24 |
| Finished | Sep 09 08:53:27 AM UTC 24 |
| Peak memory | 211948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204172042 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.204172042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/28.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_regwen.3525914392 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 26649942406 ps |
| CPU time | 870.36 seconds |
| Started | Sep 09 08:53:08 AM UTC 24 |
| Finished | Sep 09 09:07:48 AM UTC 24 |
| Peak memory | 386928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525914392 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.3525914392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/28.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_smoke.2827863905 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 5396833159 ps |
| CPU time | 27.44 seconds |
| Started | Sep 09 08:52:01 AM UTC 24 |
| Finished | Sep 09 08:52:30 AM UTC 24 |
| Peak memory | 211960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827863905 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.2827863905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/28.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all.1447055729 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 2852094193856 ps |
| CPU time | 5295.05 seconds |
| Started | Sep 09 08:53:58 AM UTC 24 |
| Finished | Sep 09 10:23:10 AM UTC 24 |
| Peak memory | 400904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14470557 29 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_a ll.1447055729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/28.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.1391818688 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 3064955983 ps |
| CPU time | 24.02 seconds |
| Started | Sep 09 08:53:41 AM UTC 24 |
| Finished | Sep 09 08:54:07 AM UTC 24 |
| Peak memory | 222328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391818688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.1391818688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/28.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.1315028230 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 3191124872 ps |
| CPU time | 243.9 seconds |
| Started | Sep 09 08:52:06 AM UTC 24 |
| Finished | Sep 09 08:56:14 AM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315028230 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_pipeline.1315028230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/28.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.1994008337 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 3723945262 ps |
| CPU time | 95.53 seconds |
| Started | Sep 09 08:52:27 AM UTC 24 |
| Finished | Sep 09 08:54:04 AM UTC 24 |
| Peak memory | 382888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1994008337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl _throughput_w_partial_write.1994008337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/28.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.4099436776 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 21709843238 ps |
| CPU time | 353.59 seconds |
| Started | Sep 09 08:55:08 AM UTC 24 |
| Finished | Sep 09 09:01:05 AM UTC 24 |
| Peak memory | 387124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099436776 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_access_duri ng_key_req.4099436776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/29.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_alert_test.1894696815 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 13513379 ps |
| CPU time | 1.03 seconds |
| Started | Sep 09 08:56:16 AM UTC 24 |
| Finished | Sep 09 08:56:19 AM UTC 24 |
| Peak memory | 211028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894696815 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_alert_test.1894696815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/29.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_bijection.238992735 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 58006536159 ps |
| CPU time | 1576.39 seconds |
| Started | Sep 09 08:54:05 AM UTC 24 |
| Finished | Sep 09 09:20:39 AM UTC 24 |
| Peak memory | 211956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238992735 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection.238992735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/29.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_executable.2255445272 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 29122623879 ps |
| CPU time | 990.45 seconds |
| Started | Sep 09 08:55:09 AM UTC 24 |
| Finished | Sep 09 09:11:51 AM UTC 24 |
| Peak memory | 381032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255445272 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executable.2255445272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/29.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.1653374338 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 22871280240 ps |
| CPU time | 87.09 seconds |
| Started | Sep 09 08:54:49 AM UTC 24 |
| Finished | Sep 09 08:56:18 AM UTC 24 |
| Peak memory | 212144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653374338 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_escalation.1653374338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/29.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.1461911722 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 740467997 ps |
| CPU time | 53.25 seconds |
| Started | Sep 09 08:54:36 AM UTC 24 |
| Finished | Sep 09 08:55:31 AM UTC 24 |
| Peak memory | 329712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1461911722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ max_throughput.1461911722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/29.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.1336135951 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 2849874282 ps |
| CPU time | 67.41 seconds |
| Started | Sep 09 08:55:42 AM UTC 24 |
| Finished | Sep 09 08:56:51 AM UTC 24 |
| Peak memory | 229144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336135951 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_mem_partial_access.1336135951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/29.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.4139534721 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 20686282081 ps |
| CPU time | 173.11 seconds |
| Started | Sep 09 08:55:38 AM UTC 24 |
| Finished | Sep 09 08:58:34 AM UTC 24 |
| Peak memory | 211968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139534721 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_mem_walk.4139534721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/29.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.197909020 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 10236089961 ps |
| CPU time | 525.98 seconds |
| Started | Sep 09 08:54:02 AM UTC 24 |
| Finished | Sep 09 09:02:54 AM UTC 24 |
| Peak memory | 384844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197909020 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multiple_keys.197909020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/29.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access.1040987720 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 1586654562 ps |
| CPU time | 25.01 seconds |
| Started | Sep 09 08:54:22 AM UTC 24 |
| Finished | Sep 09 08:54:48 AM UTC 24 |
| Peak memory | 211940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040987720 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_partial_access.1040987720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/29.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.1883573326 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 17734447193 ps |
| CPU time | 447.86 seconds |
| Started | Sep 09 08:54:28 AM UTC 24 |
| Finished | Sep 09 09:02:02 AM UTC 24 |
| Peak memory | 211964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883573326 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_partial_a ccess_b2b.1883573326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/29.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.4007790544 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 679051430 ps |
| CPU time | 6.16 seconds |
| Started | Sep 09 08:55:34 AM UTC 24 |
| Finished | Sep 09 08:55:42 AM UTC 24 |
| Peak memory | 211952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007790544 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.4007790544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/29.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_regwen.1673867468 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 2686701878 ps |
| CPU time | 389.18 seconds |
| Started | Sep 09 08:55:32 AM UTC 24 |
| Finished | Sep 09 09:02:06 AM UTC 24 |
| Peak memory | 382884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673867468 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.1673867468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/29.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_smoke.3355917715 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 4268267934 ps |
| CPU time | 44.29 seconds |
| Started | Sep 09 08:54:00 AM UTC 24 |
| Finished | Sep 09 08:54:46 AM UTC 24 |
| Peak memory | 292792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355917715 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.3355917715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/29.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all.4030694778 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 181423013550 ps |
| CPU time | 5893.02 seconds |
| Started | Sep 09 08:56:14 AM UTC 24 |
| Finished | Sep 09 10:35:31 AM UTC 24 |
| Peak memory | 392656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40306947 78 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_a ll.4030694778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/29.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1385765913 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 9472312716 ps |
| CPU time | 101.95 seconds |
| Started | Sep 09 08:55:47 AM UTC 24 |
| Finished | Sep 09 08:57:31 AM UTC 24 |
| Peak memory | 229352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385765913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.1385765913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/29.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.319659805 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 9409437876 ps |
| CPU time | 259.41 seconds |
| Started | Sep 09 08:54:08 AM UTC 24 |
| Finished | Sep 09 08:58:31 AM UTC 24 |
| Peak memory | 211928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319659805 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_pipeline.319659805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/29.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.2076292969 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 2676093043 ps |
| CPU time | 58.82 seconds |
| Started | Sep 09 08:54:46 AM UTC 24 |
| Finished | Sep 09 08:55:47 AM UTC 24 |
| Peak memory | 335928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2076292969 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl _throughput_w_partial_write.2076292969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/29.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.2827324604 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 25990709668 ps |
| CPU time | 403.92 seconds |
| Started | Sep 09 08:03:58 AM UTC 24 |
| Finished | Sep 09 08:10:47 AM UTC 24 |
| Peak memory | 378724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827324604 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_access_durin g_key_req.2827324604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_alert_test.2462828288 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 77690293 ps |
| CPU time | 0.96 seconds |
| Started | Sep 09 08:04:09 AM UTC 24 |
| Finished | Sep 09 08:04:11 AM UTC 24 |
| Peak memory | 211056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462828288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_alert_test.2462828288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_bijection.1945749026 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 66224216972 ps |
| CPU time | 2329.34 seconds |
| Started | Sep 09 08:03:55 AM UTC 24 |
| Finished | Sep 09 08:43:09 AM UTC 24 |
| Peak memory | 213652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945749026 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.1945749026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_executable.1386717389 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 4806441404 ps |
| CPU time | 414.47 seconds |
| Started | Sep 09 08:04:00 AM UTC 24 |
| Finished | Sep 09 08:10:59 AM UTC 24 |
| Peak memory | 378796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386717389 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executable.1386717389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.1418619687 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 93466507434 ps |
| CPU time | 55.16 seconds |
| Started | Sep 09 08:03:58 AM UTC 24 |
| Finished | Sep 09 08:04:55 AM UTC 24 |
| Peak memory | 226288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418619687 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_escalation.1418619687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.1587564728 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 736818417 ps |
| CPU time | 39.63 seconds |
| Started | Sep 09 08:03:57 AM UTC 24 |
| Finished | Sep 09 08:04:38 AM UTC 24 |
| Peak memory | 323372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1587564728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_m ax_throughput.1587564728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.1666350431 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 5018562823 ps |
| CPU time | 214.05 seconds |
| Started | Sep 09 08:04:04 AM UTC 24 |
| Finished | Sep 09 08:07:42 AM UTC 24 |
| Peak memory | 229288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666350431 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_mem_partial_access.1666350431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.1786054221 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 3945714695 ps |
| CPU time | 266.28 seconds |
| Started | Sep 09 08:04:01 AM UTC 24 |
| Finished | Sep 09 08:08:31 AM UTC 24 |
| Peak memory | 222264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786054221 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_mem_walk.1786054221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.2386539427 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 12401035483 ps |
| CPU time | 798.22 seconds |
| Started | Sep 09 08:03:54 AM UTC 24 |
| Finished | Sep 09 08:17:23 AM UTC 24 |
| Peak memory | 382892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386539427 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multiple_keys.2386539427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access.250755236 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 4027052325 ps |
| CPU time | 79.59 seconds |
| Started | Sep 09 08:03:56 AM UTC 24 |
| Finished | Sep 09 08:05:17 AM UTC 24 |
| Peak memory | 366436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250755236 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_partial_access.250755236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.43711425 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 6573933688 ps |
| CPU time | 211.44 seconds |
| Started | Sep 09 08:03:56 AM UTC 24 |
| Finished | Sep 09 08:07:30 AM UTC 24 |
| Peak memory | 212220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43711425 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_partial_acce ss_b2b.43711425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.2628677004 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 1399153583 ps |
| CPU time | 5.8 seconds |
| Started | Sep 09 08:04:01 AM UTC 24 |
| Finished | Sep 09 08:04:08 AM UTC 24 |
| Peak memory | 212016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628677004 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.2628677004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_regwen.436386961 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 10978890577 ps |
| CPU time | 826.07 seconds |
| Started | Sep 09 08:04:00 AM UTC 24 |
| Finished | Sep 09 08:17:55 AM UTC 24 |
| Peak memory | 376760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436386961 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.436386961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.3282509353 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 838559041 ps |
| CPU time | 6.23 seconds |
| Started | Sep 09 08:04:09 AM UTC 24 |
| Finished | Sep 09 08:04:16 AM UTC 24 |
| Peak memory | 247616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282509353 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_sec_cm.3282509353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_smoke.1935446486 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 1337057387 ps |
| CPU time | 26.69 seconds |
| Started | Sep 09 08:03:53 AM UTC 24 |
| Finished | Sep 09 08:04:21 AM UTC 24 |
| Peak memory | 211940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935446486 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.1935446486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all.3367334041 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 264540408280 ps |
| CPU time | 4243.08 seconds |
| Started | Sep 09 08:04:04 AM UTC 24 |
| Finished | Sep 09 09:15:32 AM UTC 24 |
| Peak memory | 388632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33673340 41 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all.3367334041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.3856756271 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 5845036483 ps |
| CPU time | 265.14 seconds |
| Started | Sep 09 08:03:56 AM UTC 24 |
| Finished | Sep 09 08:08:25 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856756271 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_pipeline.3856756271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.1739859713 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 760327565 ps |
| CPU time | 48.61 seconds |
| Started | Sep 09 08:03:57 AM UTC 24 |
| Finished | Sep 09 08:04:47 AM UTC 24 |
| Peak memory | 327528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1739859713 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ throughput_w_partial_write.1739859713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.2535789644 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 23489915502 ps |
| CPU time | 621.68 seconds |
| Started | Sep 09 08:56:56 AM UTC 24 |
| Finished | Sep 09 09:07:26 AM UTC 24 |
| Peak memory | 372580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535789644 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_access_duri ng_key_req.2535789644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/30.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_alert_test.1386655849 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 28074619 ps |
| CPU time | 0.97 seconds |
| Started | Sep 09 08:58:31 AM UTC 24 |
| Finished | Sep 09 08:58:34 AM UTC 24 |
| Peak memory | 211028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386655849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_alert_test.1386655849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/30.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_bijection.3217136943 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 165545227641 ps |
| CPU time | 2930.87 seconds |
| Started | Sep 09 08:56:20 AM UTC 24 |
| Finished | Sep 09 09:45:43 AM UTC 24 |
| Peak memory | 213572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217136943 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection.3217136943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/30.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_executable.45445904 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 8537674364 ps |
| CPU time | 392.1 seconds |
| Started | Sep 09 08:57:06 AM UTC 24 |
| Finished | Sep 09 09:03:44 AM UTC 24 |
| Peak memory | 366440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45445904 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executable.45445904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/30.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.297979620 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 8729738392 ps |
| CPU time | 93.66 seconds |
| Started | Sep 09 08:56:52 AM UTC 24 |
| Finished | Sep 09 08:58:28 AM UTC 24 |
| Peak memory | 211944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297979620 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_escalation.297979620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/30.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.4286057200 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 788155931 ps |
| CPU time | 87.91 seconds |
| Started | Sep 09 08:56:52 AM UTC 24 |
| Finished | Sep 09 08:58:22 AM UTC 24 |
| Peak memory | 382832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4286057200 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ max_throughput.4286057200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/30.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.1595024537 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 4567216744 ps |
| CPU time | 206.7 seconds |
| Started | Sep 09 08:57:32 AM UTC 24 |
| Finished | Sep 09 09:01:02 AM UTC 24 |
| Peak memory | 229228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595024537 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_mem_partial_access.1595024537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/30.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.410303357 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 28245301396 ps |
| CPU time | 341.44 seconds |
| Started | Sep 09 08:57:25 AM UTC 24 |
| Finished | Sep 09 09:03:11 AM UTC 24 |
| Peak memory | 222256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410303357 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_mem_walk.410303357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/30.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.1696299883 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 20502595740 ps |
| CPU time | 1029.41 seconds |
| Started | Sep 09 08:56:20 AM UTC 24 |
| Finished | Sep 09 09:13:42 AM UTC 24 |
| Peak memory | 386908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696299883 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multiple_keys.1696299883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/30.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access.1944259933 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 1533617874 ps |
| CPU time | 17.71 seconds |
| Started | Sep 09 08:56:33 AM UTC 24 |
| Finished | Sep 09 08:56:52 AM UTC 24 |
| Peak memory | 263964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944259933 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_partial_access.1944259933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/30.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.295398636 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 23206018326 ps |
| CPU time | 286.78 seconds |
| Started | Sep 09 08:56:43 AM UTC 24 |
| Finished | Sep 09 09:01:34 AM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295398636 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_partial_ac cess_b2b.295398636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/30.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.136746607 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 1408982461 ps |
| CPU time | 5.85 seconds |
| Started | Sep 09 08:57:17 AM UTC 24 |
| Finished | Sep 09 08:57:24 AM UTC 24 |
| Peak memory | 211948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136746607 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.136746607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/30.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_regwen.2833819265 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 5707486299 ps |
| CPU time | 82.87 seconds |
| Started | Sep 09 08:57:09 AM UTC 24 |
| Finished | Sep 09 08:58:33 AM UTC 24 |
| Peak memory | 300984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833819265 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.2833819265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/30.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_smoke.3574568058 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 1814231862 ps |
| CPU time | 14.12 seconds |
| Started | Sep 09 08:56:17 AM UTC 24 |
| Finished | Sep 09 08:56:32 AM UTC 24 |
| Peak memory | 212068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574568058 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.3574568058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/30.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_all.503788914 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 50585875471 ps |
| CPU time | 2673.28 seconds |
| Started | Sep 09 08:58:28 AM UTC 24 |
| Finished | Sep 09 09:43:29 AM UTC 24 |
| Peak memory | 390652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50378891 4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all.503788914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/30.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.4268467326 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 329650299 ps |
| CPU time | 13.7 seconds |
| Started | Sep 09 08:58:23 AM UTC 24 |
| Finished | Sep 09 08:58:38 AM UTC 24 |
| Peak memory | 222328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268467326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.4268467326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/30.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.3260570205 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 3037957786 ps |
| CPU time | 177.01 seconds |
| Started | Sep 09 08:56:23 AM UTC 24 |
| Finished | Sep 09 08:59:23 AM UTC 24 |
| Peak memory | 211956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260570205 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_pipeline.3260570205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/30.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.472000388 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 1375477271 ps |
| CPU time | 11.97 seconds |
| Started | Sep 09 08:56:52 AM UTC 24 |
| Finished | Sep 09 08:57:05 AM UTC 24 |
| Peak memory | 245532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =472000388 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ throughput_w_partial_write.472000388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/30.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.1383280098 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 6460604240 ps |
| CPU time | 671.05 seconds |
| Started | Sep 09 09:01:03 AM UTC 24 |
| Finished | Sep 09 09:12:23 AM UTC 24 |
| Peak memory | 386912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383280098 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_access_duri ng_key_req.1383280098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/31.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_alert_test.2933087887 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 13502295 ps |
| CPU time | 1.02 seconds |
| Started | Sep 09 09:02:13 AM UTC 24 |
| Finished | Sep 09 09:02:15 AM UTC 24 |
| Peak memory | 211056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933087887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_alert_test.2933087887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/31.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_bijection.619104608 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 137943670077 ps |
| CPU time | 2697.85 seconds |
| Started | Sep 09 08:58:36 AM UTC 24 |
| Finished | Sep 09 09:44:05 AM UTC 24 |
| Peak memory | 213616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619104608 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection.619104608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/31.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_executable.2822966776 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 32238433848 ps |
| CPU time | 778.33 seconds |
| Started | Sep 09 09:01:06 AM UTC 24 |
| Finished | Sep 09 09:14:13 AM UTC 24 |
| Peak memory | 387188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822966776 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executable.2822966776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/31.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.128023749 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 41600599538 ps |
| CPU time | 71.21 seconds |
| Started | Sep 09 09:00:54 AM UTC 24 |
| Finished | Sep 09 09:02:07 AM UTC 24 |
| Peak memory | 226284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128023749 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_escalation.128023749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/31.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.1746559105 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 2902390727 ps |
| CPU time | 38.13 seconds |
| Started | Sep 09 09:00:14 AM UTC 24 |
| Finished | Sep 09 09:00:53 AM UTC 24 |
| Peak memory | 311232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1746559105 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ max_throughput.1746559105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/31.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.506702908 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 5470426498 ps |
| CPU time | 171.98 seconds |
| Started | Sep 09 09:02:03 AM UTC 24 |
| Finished | Sep 09 09:04:58 AM UTC 24 |
| Peak memory | 222244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506702908 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_mem_partial_access.506702908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/31.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.1722880398 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 20920584025 ps |
| CPU time | 361.31 seconds |
| Started | Sep 09 09:01:42 AM UTC 24 |
| Finished | Sep 09 09:07:49 AM UTC 24 |
| Peak memory | 222188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722880398 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_mem_walk.1722880398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/31.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.249025513 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 103321668610 ps |
| CPU time | 1032.25 seconds |
| Started | Sep 09 08:58:35 AM UTC 24 |
| Finished | Sep 09 09:15:58 AM UTC 24 |
| Peak memory | 389116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249025513 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multiple_keys.249025513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/31.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access.130174071 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 2729420578 ps |
| CPU time | 69.99 seconds |
| Started | Sep 09 08:59:01 AM UTC 24 |
| Finished | Sep 09 09:00:13 AM UTC 24 |
| Peak memory | 346040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130174071 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_partial_access.130174071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/31.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.3989497544 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 13594942732 ps |
| CPU time | 378.9 seconds |
| Started | Sep 09 08:59:23 AM UTC 24 |
| Finished | Sep 09 09:05:47 AM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989497544 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_partial_a ccess_b2b.3989497544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/31.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.1015817160 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 1873050534 ps |
| CPU time | 6.28 seconds |
| Started | Sep 09 09:01:34 AM UTC 24 |
| Finished | Sep 09 09:01:42 AM UTC 24 |
| Peak memory | 211952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015817160 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.1015817160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/31.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_regwen.3671434135 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 6756810364 ps |
| CPU time | 227.27 seconds |
| Started | Sep 09 09:01:31 AM UTC 24 |
| Finished | Sep 09 09:05:22 AM UTC 24 |
| Peak memory | 383040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671434135 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.3671434135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/31.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_smoke.1322713030 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 2612469376 ps |
| CPU time | 23.85 seconds |
| Started | Sep 09 08:58:35 AM UTC 24 |
| Finished | Sep 09 08:59:00 AM UTC 24 |
| Peak memory | 211932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322713030 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.1322713030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/31.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_all.3357457457 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 85645532438 ps |
| CPU time | 5211.56 seconds |
| Started | Sep 09 09:02:08 AM UTC 24 |
| Finished | Sep 09 10:29:56 AM UTC 24 |
| Peak memory | 390748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33574574 57 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_a ll.3357457457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/31.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.137934318 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 4319679932 ps |
| CPU time | 109.9 seconds |
| Started | Sep 09 09:02:07 AM UTC 24 |
| Finished | Sep 09 09:03:59 AM UTC 24 |
| Peak memory | 356264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137934318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.137934318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/31.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.3829263508 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 4028081326 ps |
| CPU time | 295.9 seconds |
| Started | Sep 09 08:58:39 AM UTC 24 |
| Finished | Sep 09 09:03:39 AM UTC 24 |
| Peak memory | 212000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829263508 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_pipeline.3829263508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/31.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.95192073 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 2839168805 ps |
| CPU time | 95.35 seconds |
| Started | Sep 09 09:00:35 AM UTC 24 |
| Finished | Sep 09 09:02:12 AM UTC 24 |
| Peak memory | 362548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =95192073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_t hroughput_w_partial_write.95192073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/31.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.50623994 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 7104322516 ps |
| CPU time | 322.31 seconds |
| Started | Sep 09 09:03:44 AM UTC 24 |
| Finished | Sep 09 09:09:11 AM UTC 24 |
| Peak memory | 370520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50623994 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_access_during _key_req.50623994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/32.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_alert_test.2015333807 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 12459668 ps |
| CPU time | 1.07 seconds |
| Started | Sep 09 09:04:58 AM UTC 24 |
| Finished | Sep 09 09:05:00 AM UTC 24 |
| Peak memory | 210996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015333807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_alert_test.2015333807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/32.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_bijection.4293368086 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 67624532311 ps |
| CPU time | 754.65 seconds |
| Started | Sep 09 09:02:40 AM UTC 24 |
| Finished | Sep 09 09:15:24 AM UTC 24 |
| Peak memory | 211932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293368086 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection.4293368086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/32.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_executable.3637250129 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 81117018752 ps |
| CPU time | 977.12 seconds |
| Started | Sep 09 09:04:00 AM UTC 24 |
| Finished | Sep 09 09:20:29 AM UTC 24 |
| Peak memory | 386912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637250129 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executable.3637250129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/32.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.2151272700 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 38027882474 ps |
| CPU time | 93.34 seconds |
| Started | Sep 09 09:03:40 AM UTC 24 |
| Finished | Sep 09 09:05:16 AM UTC 24 |
| Peak memory | 212144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151272700 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_escalation.2151272700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/32.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.164803511 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 756444287 ps |
| CPU time | 51.32 seconds |
| Started | Sep 09 09:03:20 AM UTC 24 |
| Finished | Sep 09 09:04:13 AM UTC 24 |
| Peak memory | 352036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 164803511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_m ax_throughput.164803511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/32.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.4224804638 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 3816425393 ps |
| CPU time | 90.21 seconds |
| Started | Sep 09 09:04:16 AM UTC 24 |
| Finished | Sep 09 09:05:48 AM UTC 24 |
| Peak memory | 229160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224804638 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_mem_partial_access.4224804638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/32.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.321891078 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 41332996572 ps |
| CPU time | 246.93 seconds |
| Started | Sep 09 09:04:14 AM UTC 24 |
| Finished | Sep 09 09:08:24 AM UTC 24 |
| Peak memory | 222212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321891078 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_mem_walk.321891078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/32.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.1118599913 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 22435071188 ps |
| CPU time | 850.49 seconds |
| Started | Sep 09 09:02:39 AM UTC 24 |
| Finished | Sep 09 09:17:00 AM UTC 24 |
| Peak memory | 384880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118599913 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multiple_keys.1118599913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/32.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access.3420727789 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 1663272802 ps |
| CPU time | 39.27 seconds |
| Started | Sep 09 09:02:55 AM UTC 24 |
| Finished | Sep 09 09:03:35 AM UTC 24 |
| Peak memory | 212120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420727789 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_partial_access.3420727789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/32.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.2388737808 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 17567181824 ps |
| CPU time | 438.87 seconds |
| Started | Sep 09 09:03:12 AM UTC 24 |
| Finished | Sep 09 09:10:36 AM UTC 24 |
| Peak memory | 212072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388737808 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_partial_a ccess_b2b.2388737808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/32.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.1117189878 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 1880146477 ps |
| CPU time | 6.38 seconds |
| Started | Sep 09 09:04:08 AM UTC 24 |
| Finished | Sep 09 09:04:15 AM UTC 24 |
| Peak memory | 212152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117189878 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.1117189878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/32.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_regwen.2283683548 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 9846808252 ps |
| CPU time | 504.63 seconds |
| Started | Sep 09 09:04:06 AM UTC 24 |
| Finished | Sep 09 09:12:37 AM UTC 24 |
| Peak memory | 380856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283683548 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.2283683548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/32.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_smoke.1490589603 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 523282510 ps |
| CPU time | 20.53 seconds |
| Started | Sep 09 09:02:16 AM UTC 24 |
| Finished | Sep 09 09:02:38 AM UTC 24 |
| Peak memory | 211896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490589603 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.1490589603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/32.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all.3035126371 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 203217217830 ps |
| CPU time | 2769.07 seconds |
| Started | Sep 09 09:04:43 AM UTC 24 |
| Finished | Sep 09 09:51:21 AM UTC 24 |
| Peak memory | 392780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30351263 71 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_a ll.3035126371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/32.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.1946392605 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 991723254 ps |
| CPU time | 56.85 seconds |
| Started | Sep 09 09:04:29 AM UTC 24 |
| Finished | Sep 09 09:05:27 AM UTC 24 |
| Peak memory | 222184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946392605 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.1946392605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/32.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.3897404847 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 10555573099 ps |
| CPU time | 336.67 seconds |
| Started | Sep 09 09:02:42 AM UTC 24 |
| Finished | Sep 09 09:08:24 AM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897404847 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_pipeline.3897404847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/32.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.1565717028 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 794925940 ps |
| CPU time | 64.46 seconds |
| Started | Sep 09 09:03:36 AM UTC 24 |
| Finished | Sep 09 09:04:42 AM UTC 24 |
| Peak memory | 360296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1565717028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl _throughput_w_partial_write.1565717028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/32.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.3777437433 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 34214740189 ps |
| CPU time | 297.04 seconds |
| Started | Sep 09 09:06:40 AM UTC 24 |
| Finished | Sep 09 09:11:42 AM UTC 24 |
| Peak memory | 362424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777437433 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_access_duri ng_key_req.3777437433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/33.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_alert_test.3006284262 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 12468279 ps |
| CPU time | 0.97 seconds |
| Started | Sep 09 09:07:49 AM UTC 24 |
| Finished | Sep 09 09:07:51 AM UTC 24 |
| Peak memory | 211116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006284262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_alert_test.3006284262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/33.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_bijection.13456012 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 12518599616 ps |
| CPU time | 909.82 seconds |
| Started | Sep 09 09:05:23 AM UTC 24 |
| Finished | Sep 09 09:20:43 AM UTC 24 |
| Peak memory | 211956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13456012 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection.13456012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/33.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_executable.1255764005 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 86094835910 ps |
| CPU time | 728.8 seconds |
| Started | Sep 09 09:06:51 AM UTC 24 |
| Finished | Sep 09 09:19:08 AM UTC 24 |
| Peak memory | 383036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255764005 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executable.1255764005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/33.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.2533672184 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 34470927069 ps |
| CPU time | 76.3 seconds |
| Started | Sep 09 09:06:18 AM UTC 24 |
| Finished | Sep 09 09:07:36 AM UTC 24 |
| Peak memory | 226220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533672184 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_escalation.2533672184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/33.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.4265018459 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 14490885034 ps |
| CPU time | 48.75 seconds |
| Started | Sep 09 09:05:49 AM UTC 24 |
| Finished | Sep 09 09:06:39 AM UTC 24 |
| Peak memory | 311220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4265018459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ max_throughput.4265018459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/33.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.709406775 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 10036059124 ps |
| CPU time | 168.47 seconds |
| Started | Sep 09 09:07:29 AM UTC 24 |
| Finished | Sep 09 09:10:20 AM UTC 24 |
| Peak memory | 229240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709406775 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_mem_partial_access.709406775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/33.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.610982566 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 23269492446 ps |
| CPU time | 375.7 seconds |
| Started | Sep 09 09:07:27 AM UTC 24 |
| Finished | Sep 09 09:13:48 AM UTC 24 |
| Peak memory | 222332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610982566 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_mem_walk.610982566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/33.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.2131384018 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 71550965073 ps |
| CPU time | 563.78 seconds |
| Started | Sep 09 09:05:17 AM UTC 24 |
| Finished | Sep 09 09:14:47 AM UTC 24 |
| Peak memory | 389048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131384018 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multiple_keys.2131384018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/33.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access.1969065523 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 987991725 ps |
| CPU time | 35.67 seconds |
| Started | Sep 09 09:05:40 AM UTC 24 |
| Finished | Sep 09 09:06:17 AM UTC 24 |
| Peak memory | 282408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969065523 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_partial_access.1969065523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/33.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.2776301273 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 63577281342 ps |
| CPU time | 359.26 seconds |
| Started | Sep 09 09:05:48 AM UTC 24 |
| Finished | Sep 09 09:11:52 AM UTC 24 |
| Peak memory | 211936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776301273 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_partial_a ccess_b2b.2776301273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/33.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.3869211840 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 1365487474 ps |
| CPU time | 5.58 seconds |
| Started | Sep 09 09:07:21 AM UTC 24 |
| Finished | Sep 09 09:07:28 AM UTC 24 |
| Peak memory | 211952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869211840 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.3869211840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/33.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_regwen.1143242267 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 3662184774 ps |
| CPU time | 602.49 seconds |
| Started | Sep 09 09:07:02 AM UTC 24 |
| Finished | Sep 09 09:17:11 AM UTC 24 |
| Peak memory | 389056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143242267 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.1143242267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/33.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_smoke.3517903795 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 1119952631 ps |
| CPU time | 36.49 seconds |
| Started | Sep 09 09:05:01 AM UTC 24 |
| Finished | Sep 09 09:05:39 AM UTC 24 |
| Peak memory | 317304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517903795 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.3517903795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/33.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all.713474485 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 65653787986 ps |
| CPU time | 900.73 seconds |
| Started | Sep 09 09:07:47 AM UTC 24 |
| Finished | Sep 09 09:22:58 AM UTC 24 |
| Peak memory | 382840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71347448 5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all.713474485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/33.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3125826037 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 1608462020 ps |
| CPU time | 53.42 seconds |
| Started | Sep 09 09:07:37 AM UTC 24 |
| Finished | Sep 09 09:08:32 AM UTC 24 |
| Peak memory | 224236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125826037 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.3125826037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/33.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.638975515 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 22210242957 ps |
| CPU time | 280.89 seconds |
| Started | Sep 09 09:05:29 AM UTC 24 |
| Finished | Sep 09 09:10:13 AM UTC 24 |
| Peak memory | 211928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638975515 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_pipeline.638975515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/33.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.1063091894 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 3651980166 ps |
| CPU time | 81.27 seconds |
| Started | Sep 09 09:05:57 AM UTC 24 |
| Finished | Sep 09 09:07:20 AM UTC 24 |
| Peak memory | 360372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1063091894 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl _throughput_w_partial_write.1063091894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/33.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.681948987 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 51300018893 ps |
| CPU time | 667.45 seconds |
| Started | Sep 09 09:09:51 AM UTC 24 |
| Finished | Sep 09 09:21:07 AM UTC 24 |
| Peak memory | 378868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681948987 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_access_durin g_key_req.681948987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/34.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_alert_test.2769097883 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 15119029 ps |
| CPU time | 1.08 seconds |
| Started | Sep 09 09:10:37 AM UTC 24 |
| Finished | Sep 09 09:10:40 AM UTC 24 |
| Peak memory | 210996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769097883 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_alert_test.2769097883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/34.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_executable.3545970726 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 138548032189 ps |
| CPU time | 699.51 seconds |
| Started | Sep 09 09:09:54 AM UTC 24 |
| Finished | Sep 09 09:21:42 AM UTC 24 |
| Peak memory | 388964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545970726 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executable.3545970726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/34.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.121171711 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 9999996423 ps |
| CPU time | 120.22 seconds |
| Started | Sep 09 09:09:11 AM UTC 24 |
| Finished | Sep 09 09:11:14 AM UTC 24 |
| Peak memory | 212152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121171711 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_escalation.121171711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/34.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.3186870136 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 5543298441 ps |
| CPU time | 11.68 seconds |
| Started | Sep 09 09:08:41 AM UTC 24 |
| Finished | Sep 09 09:08:54 AM UTC 24 |
| Peak memory | 211756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3186870136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ max_throughput.3186870136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/34.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.1920812662 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 9843116909 ps |
| CPU time | 217.95 seconds |
| Started | Sep 09 09:10:21 AM UTC 24 |
| Finished | Sep 09 09:14:02 AM UTC 24 |
| Peak memory | 222464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920812662 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_mem_partial_access.1920812662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/34.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.1740584437 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 3945340706 ps |
| CPU time | 342.92 seconds |
| Started | Sep 09 09:10:14 AM UTC 24 |
| Finished | Sep 09 09:16:02 AM UTC 24 |
| Peak memory | 222244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740584437 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_mem_walk.1740584437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/34.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.373313663 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 55345877705 ps |
| CPU time | 1063.45 seconds |
| Started | Sep 09 09:07:53 AM UTC 24 |
| Finished | Sep 09 09:25:47 AM UTC 24 |
| Peak memory | 384868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373313663 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multiple_keys.373313663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/34.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access.2794737644 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 2333922908 ps |
| CPU time | 14.11 seconds |
| Started | Sep 09 09:08:25 AM UTC 24 |
| Finished | Sep 09 09:08:40 AM UTC 24 |
| Peak memory | 212152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794737644 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_partial_access.2794737644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/34.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.1843334521 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 53176760225 ps |
| CPU time | 566.34 seconds |
| Started | Sep 09 09:08:33 AM UTC 24 |
| Finished | Sep 09 09:18:07 AM UTC 24 |
| Peak memory | 211936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843334521 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_partial_a ccess_b2b.1843334521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/34.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.3280014439 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 1343799080 ps |
| CPU time | 6.49 seconds |
| Started | Sep 09 09:10:13 AM UTC 24 |
| Finished | Sep 09 09:10:21 AM UTC 24 |
| Peak memory | 211948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280014439 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.3280014439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/34.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_regwen.3102154367 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 14899318418 ps |
| CPU time | 414.84 seconds |
| Started | Sep 09 09:10:11 AM UTC 24 |
| Finished | Sep 09 09:17:11 AM UTC 24 |
| Peak memory | 384892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102154367 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.3102154367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/34.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_smoke.2924926570 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 3264951086 ps |
| CPU time | 8.47 seconds |
| Started | Sep 09 09:07:49 AM UTC 24 |
| Finished | Sep 09 09:07:59 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924926570 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.2924926570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/34.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all.384995046 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 1048409841406 ps |
| CPU time | 4006.83 seconds |
| Started | Sep 09 09:10:27 AM UTC 24 |
| Finished | Sep 09 10:17:54 AM UTC 24 |
| Peak memory | 392700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38499504 6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all.384995046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/34.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3059529619 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 384263376 ps |
| CPU time | 16.76 seconds |
| Started | Sep 09 09:10:22 AM UTC 24 |
| Finished | Sep 09 09:10:40 AM UTC 24 |
| Peak memory | 224236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059529619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.3059529619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/34.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.89953366 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 24378100515 ps |
| CPU time | 434.25 seconds |
| Started | Sep 09 09:08:25 AM UTC 24 |
| Finished | Sep 09 09:15:45 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89953366 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_pipeline.89953366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/34.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.1181887244 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 3109388879 ps |
| CPU time | 74.78 seconds |
| Started | Sep 09 09:08:55 AM UTC 24 |
| Finished | Sep 09 09:10:12 AM UTC 24 |
| Peak memory | 374628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1181887244 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl _throughput_w_partial_write.1181887244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/34.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.3799803213 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 13671565320 ps |
| CPU time | 701.96 seconds |
| Started | Sep 09 09:12:20 AM UTC 24 |
| Finished | Sep 09 09:24:10 AM UTC 24 |
| Peak memory | 389220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799803213 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_access_duri ng_key_req.3799803213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/35.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_alert_test.3240158493 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 79879643 ps |
| CPU time | 1.05 seconds |
| Started | Sep 09 09:13:46 AM UTC 24 |
| Finished | Sep 09 09:13:48 AM UTC 24 |
| Peak memory | 211056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240158493 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_alert_test.3240158493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/35.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_bijection.477209104 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 304911144887 ps |
| CPU time | 3357.9 seconds |
| Started | Sep 09 09:11:10 AM UTC 24 |
| Finished | Sep 09 10:07:46 AM UTC 24 |
| Peak memory | 213572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477209104 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection.477209104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/35.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_executable.924515653 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 2714446299 ps |
| CPU time | 73.25 seconds |
| Started | Sep 09 09:12:24 AM UTC 24 |
| Finished | Sep 09 09:13:39 AM UTC 24 |
| Peak memory | 259936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924515653 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executable.924515653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/35.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.3692419517 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 21818608258 ps |
| CPU time | 106.25 seconds |
| Started | Sep 09 09:11:56 AM UTC 24 |
| Finished | Sep 09 09:13:45 AM UTC 24 |
| Peak memory | 212164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692419517 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_escalation.3692419517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/35.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.1234630323 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 747147963 ps |
| CPU time | 26.71 seconds |
| Started | Sep 09 09:11:51 AM UTC 24 |
| Finished | Sep 09 09:12:19 AM UTC 24 |
| Peak memory | 278320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1234630323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ max_throughput.1234630323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/35.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.4270670523 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 25114131572 ps |
| CPU time | 176.82 seconds |
| Started | Sep 09 09:13:04 AM UTC 24 |
| Finished | Sep 09 09:16:04 AM UTC 24 |
| Peak memory | 222108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270670523 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_mem_partial_access.4270670523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/35.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.3057036599 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 13857835152 ps |
| CPU time | 228.36 seconds |
| Started | Sep 09 09:12:45 AM UTC 24 |
| Finished | Sep 09 09:16:37 AM UTC 24 |
| Peak memory | 222200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057036599 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_mem_walk.3057036599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/35.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.4283885842 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 74961411486 ps |
| CPU time | 587.21 seconds |
| Started | Sep 09 09:10:41 AM UTC 24 |
| Finished | Sep 09 09:20:36 AM UTC 24 |
| Peak memory | 380772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283885842 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multiple_keys.4283885842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/35.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access.2579468904 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 1348252972 ps |
| CPU time | 33.06 seconds |
| Started | Sep 09 09:11:21 AM UTC 24 |
| Finished | Sep 09 09:11:55 AM UTC 24 |
| Peak memory | 211884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579468904 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_partial_access.2579468904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/35.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.1928236202 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 13121860752 ps |
| CPU time | 396.25 seconds |
| Started | Sep 09 09:11:43 AM UTC 24 |
| Finished | Sep 09 09:18:25 AM UTC 24 |
| Peak memory | 211960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928236202 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_partial_a ccess_b2b.1928236202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/35.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.1336812217 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 1422036757 ps |
| CPU time | 4.89 seconds |
| Started | Sep 09 09:12:38 AM UTC 24 |
| Finished | Sep 09 09:12:44 AM UTC 24 |
| Peak memory | 211952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336812217 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.1336812217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/35.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_regwen.3802574486 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 6393613662 ps |
| CPU time | 716.63 seconds |
| Started | Sep 09 09:12:34 AM UTC 24 |
| Finished | Sep 09 09:24:38 AM UTC 24 |
| Peak memory | 386920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802574486 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.3802574486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/35.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_smoke.2644811520 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 18010176191 ps |
| CPU time | 38.44 seconds |
| Started | Sep 09 09:10:40 AM UTC 24 |
| Finished | Sep 09 09:11:20 AM UTC 24 |
| Peak memory | 211932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644811520 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.2644811520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/35.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all.913869009 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 27106215885 ps |
| CPU time | 3767.85 seconds |
| Started | Sep 09 09:13:42 AM UTC 24 |
| Finished | Sep 09 10:17:07 AM UTC 24 |
| Peak memory | 392720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91386900 9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all.913869009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/35.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.585696631 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 1862102629 ps |
| CPU time | 18.88 seconds |
| Started | Sep 09 09:13:39 AM UTC 24 |
| Finished | Sep 09 09:14:00 AM UTC 24 |
| Peak memory | 222252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585696631 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.585696631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/35.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.3987656674 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 4290148756 ps |
| CPU time | 254.55 seconds |
| Started | Sep 09 09:11:15 AM UTC 24 |
| Finished | Sep 09 09:15:33 AM UTC 24 |
| Peak memory | 211964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987656674 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_pipeline.3987656674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/35.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.4265315575 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 775105967 ps |
| CPU time | 38.74 seconds |
| Started | Sep 09 09:11:52 AM UTC 24 |
| Finished | Sep 09 09:12:32 AM UTC 24 |
| Peak memory | 311144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =4265315575 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl _throughput_w_partial_write.4265315575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/35.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.29218038 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 32132718629 ps |
| CPU time | 346.38 seconds |
| Started | Sep 09 09:15:25 AM UTC 24 |
| Finished | Sep 09 09:21:15 AM UTC 24 |
| Peak memory | 389056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29218038 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_access_during _key_req.29218038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/36.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_alert_test.1913986803 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 21763681 ps |
| CPU time | 1.01 seconds |
| Started | Sep 09 09:15:56 AM UTC 24 |
| Finished | Sep 09 09:15:58 AM UTC 24 |
| Peak memory | 210996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913986803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_alert_test.1913986803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/36.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_bijection.3868121800 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 14787188771 ps |
| CPU time | 1122.37 seconds |
| Started | Sep 09 09:14:01 AM UTC 24 |
| Finished | Sep 09 09:32:58 AM UTC 24 |
| Peak memory | 212152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868121800 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection.3868121800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/36.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_executable.252677569 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 19219339157 ps |
| CPU time | 496.15 seconds |
| Started | Sep 09 09:15:25 AM UTC 24 |
| Finished | Sep 09 09:23:47 AM UTC 24 |
| Peak memory | 386932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252677569 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executable.252677569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/36.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.1521565527 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 13322495186 ps |
| CPU time | 38.5 seconds |
| Started | Sep 09 09:15:25 AM UTC 24 |
| Finished | Sep 09 09:16:05 AM UTC 24 |
| Peak memory | 211948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521565527 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_escalation.1521565527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/36.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.4093184306 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 4930631386 ps |
| CPU time | 62.39 seconds |
| Started | Sep 09 09:14:47 AM UTC 24 |
| Finished | Sep 09 09:15:52 AM UTC 24 |
| Peak memory | 343912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4093184306 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ max_throughput.4093184306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/36.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.2396893325 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 10470734881 ps |
| CPU time | 167.27 seconds |
| Started | Sep 09 09:15:40 AM UTC 24 |
| Finished | Sep 09 09:18:30 AM UTC 24 |
| Peak memory | 222168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396893325 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_mem_partial_access.2396893325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/36.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.882225977 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 2018542095 ps |
| CPU time | 153.56 seconds |
| Started | Sep 09 09:15:34 AM UTC 24 |
| Finished | Sep 09 09:18:10 AM UTC 24 |
| Peak memory | 222144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882225977 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_mem_walk.882225977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/36.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.566006441 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 55501378703 ps |
| CPU time | 1663.94 seconds |
| Started | Sep 09 09:13:49 AM UTC 24 |
| Finished | Sep 09 09:41:50 AM UTC 24 |
| Peak memory | 389212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566006441 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multiple_keys.566006441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/36.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access.450805851 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 463268450 ps |
| CPU time | 37.09 seconds |
| Started | Sep 09 09:14:13 AM UTC 24 |
| Finished | Sep 09 09:14:51 AM UTC 24 |
| Peak memory | 300860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450805851 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_partial_access.450805851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/36.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.1855661523 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 24580895067 ps |
| CPU time | 258.27 seconds |
| Started | Sep 09 09:14:14 AM UTC 24 |
| Finished | Sep 09 09:18:36 AM UTC 24 |
| Peak memory | 211956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855661523 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_partial_a ccess_b2b.1855661523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/36.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.3664759502 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 344112330 ps |
| CPU time | 5.5 seconds |
| Started | Sep 09 09:15:33 AM UTC 24 |
| Finished | Sep 09 09:15:39 AM UTC 24 |
| Peak memory | 211944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664759502 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.3664759502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/36.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_smoke.55808048 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 1415045334 ps |
| CPU time | 22.76 seconds |
| Started | Sep 09 09:13:49 AM UTC 24 |
| Finished | Sep 09 09:14:13 AM UTC 24 |
| Peak memory | 211964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55808048 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.55808048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/36.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all.1401441797 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 55363314744 ps |
| CPU time | 3608.1 seconds |
| Started | Sep 09 09:15:52 AM UTC 24 |
| Finished | Sep 09 10:16:41 AM UTC 24 |
| Peak memory | 390672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14014417 97 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_a ll.1401441797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/36.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.3809659221 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 3004098099 ps |
| CPU time | 126.69 seconds |
| Started | Sep 09 09:15:45 AM UTC 24 |
| Finished | Sep 09 09:17:54 AM UTC 24 |
| Peak memory | 327596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809659221 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.3809659221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/36.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.3499262308 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 3945536745 ps |
| CPU time | 242.51 seconds |
| Started | Sep 09 09:14:03 AM UTC 24 |
| Finished | Sep 09 09:18:09 AM UTC 24 |
| Peak memory | 212020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499262308 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_pipeline.3499262308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/36.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.1438480774 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 4178443495 ps |
| CPU time | 32.12 seconds |
| Started | Sep 09 09:14:52 AM UTC 24 |
| Finished | Sep 09 09:15:26 AM UTC 24 |
| Peak memory | 297004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1438480774 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl _throughput_w_partial_write.1438480774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/36.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.2216565661 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 16531737603 ps |
| CPU time | 736.01 seconds |
| Started | Sep 09 09:16:56 AM UTC 24 |
| Finished | Sep 09 09:29:22 AM UTC 24 |
| Peak memory | 386936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216565661 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_access_duri ng_key_req.2216565661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/37.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_alert_test.1750912152 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 44855580 ps |
| CPU time | 1.04 seconds |
| Started | Sep 09 09:17:55 AM UTC 24 |
| Finished | Sep 09 09:17:58 AM UTC 24 |
| Peak memory | 211028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750912152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_alert_test.1750912152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/37.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_bijection.3307694659 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 220556897235 ps |
| CPU time | 868.49 seconds |
| Started | Sep 09 09:16:03 AM UTC 24 |
| Finished | Sep 09 09:30:41 AM UTC 24 |
| Peak memory | 212012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307694659 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection.3307694659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/37.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_executable.2355541617 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 29808872836 ps |
| CPU time | 1456.13 seconds |
| Started | Sep 09 09:16:58 AM UTC 24 |
| Finished | Sep 09 09:41:30 AM UTC 24 |
| Peak memory | 389096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355541617 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executable.2355541617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/37.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.4184838484 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 54112772040 ps |
| CPU time | 132.78 seconds |
| Started | Sep 09 09:16:39 AM UTC 24 |
| Finished | Sep 09 09:18:54 AM UTC 24 |
| Peak memory | 211896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184838484 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_escalation.4184838484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/37.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.600756024 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 1423342031 ps |
| CPU time | 21.78 seconds |
| Started | Sep 09 09:16:36 AM UTC 24 |
| Finished | Sep 09 09:16:59 AM UTC 24 |
| Peak memory | 262012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 600756024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_m ax_throughput.600756024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/37.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.3973224230 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 17568673013 ps |
| CPU time | 184.33 seconds |
| Started | Sep 09 09:17:11 AM UTC 24 |
| Finished | Sep 09 09:20:18 AM UTC 24 |
| Peak memory | 222380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973224230 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_mem_partial_access.3973224230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/37.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.3316055793 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 3660425149 ps |
| CPU time | 160.33 seconds |
| Started | Sep 09 09:17:09 AM UTC 24 |
| Finished | Sep 09 09:19:52 AM UTC 24 |
| Peak memory | 222264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316055793 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_mem_walk.3316055793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/37.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.611707294 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 19714825088 ps |
| CPU time | 809.38 seconds |
| Started | Sep 09 09:16:00 AM UTC 24 |
| Finished | Sep 09 09:29:38 AM UTC 24 |
| Peak memory | 380980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611707294 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multiple_keys.611707294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/37.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access.3861940622 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 1616137843 ps |
| CPU time | 28.1 seconds |
| Started | Sep 09 09:16:06 AM UTC 24 |
| Finished | Sep 09 09:16:36 AM UTC 24 |
| Peak memory | 211952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861940622 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_partial_access.3861940622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/37.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.1462655284 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 4719239192 ps |
| CPU time | 179.94 seconds |
| Started | Sep 09 09:16:09 AM UTC 24 |
| Finished | Sep 09 09:19:12 AM UTC 24 |
| Peak memory | 211888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462655284 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_partial_a ccess_b2b.1462655284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/37.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.2152469198 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 1609846762 ps |
| CPU time | 5.81 seconds |
| Started | Sep 09 09:17:01 AM UTC 24 |
| Finished | Sep 09 09:17:08 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152469198 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.2152469198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/37.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_regwen.1937200107 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 16431247217 ps |
| CPU time | 239.75 seconds |
| Started | Sep 09 09:17:00 AM UTC 24 |
| Finished | Sep 09 09:21:03 AM UTC 24 |
| Peak memory | 350060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937200107 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.1937200107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/37.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_smoke.3778144847 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 1715225710 ps |
| CPU time | 8.95 seconds |
| Started | Sep 09 09:15:58 AM UTC 24 |
| Finished | Sep 09 09:16:08 AM UTC 24 |
| Peak memory | 211952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778144847 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.3778144847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/37.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all.470184547 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 74546495209 ps |
| CPU time | 1726.53 seconds |
| Started | Sep 09 09:17:26 AM UTC 24 |
| Finished | Sep 09 09:46:30 AM UTC 24 |
| Peak memory | 394820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47018454 7 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all.470184547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/37.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.565675583 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 876215610 ps |
| CPU time | 11.95 seconds |
| Started | Sep 09 09:17:12 AM UTC 24 |
| Finished | Sep 09 09:17:25 AM UTC 24 |
| Peak memory | 228396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565675583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.565675583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/37.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.1237276991 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 2508285586 ps |
| CPU time | 147.11 seconds |
| Started | Sep 09 09:16:05 AM UTC 24 |
| Finished | Sep 09 09:18:34 AM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237276991 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_pipeline.1237276991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/37.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.4065281646 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 696132678 ps |
| CPU time | 16.43 seconds |
| Started | Sep 09 09:16:38 AM UTC 24 |
| Finished | Sep 09 09:16:56 AM UTC 24 |
| Peak memory | 245800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =4065281646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl _throughput_w_partial_write.4065281646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/37.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.1512896303 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 6075365657 ps |
| CPU time | 344.66 seconds |
| Started | Sep 09 09:18:35 AM UTC 24 |
| Finished | Sep 09 09:24:24 AM UTC 24 |
| Peak memory | 362548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512896303 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_access_duri ng_key_req.1512896303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/38.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_alert_test.1420077716 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 35535515 ps |
| CPU time | 0.99 seconds |
| Started | Sep 09 09:19:11 AM UTC 24 |
| Finished | Sep 09 09:19:13 AM UTC 24 |
| Peak memory | 211056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420077716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_alert_test.1420077716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/38.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_bijection.2709193254 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 47670039854 ps |
| CPU time | 1043.09 seconds |
| Started | Sep 09 09:18:10 AM UTC 24 |
| Finished | Sep 09 09:35:45 AM UTC 24 |
| Peak memory | 211952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709193254 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection.2709193254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/38.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_executable.2899992615 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 23681978992 ps |
| CPU time | 848.69 seconds |
| Started | Sep 09 09:18:36 AM UTC 24 |
| Finished | Sep 09 09:32:54 AM UTC 24 |
| Peak memory | 388964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899992615 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executable.2899992615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/38.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.801154762 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 10005028141 ps |
| CPU time | 83.43 seconds |
| Started | Sep 09 09:18:35 AM UTC 24 |
| Finished | Sep 09 09:20:01 AM UTC 24 |
| Peak memory | 212020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801154762 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_escalation.801154762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/38.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.2323897540 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 754538697 ps |
| CPU time | 40 seconds |
| Started | Sep 09 09:18:26 AM UTC 24 |
| Finished | Sep 09 09:19:07 AM UTC 24 |
| Peak memory | 302964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2323897540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ max_throughput.2323897540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/38.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.293868261 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 27489478671 ps |
| CPU time | 179.23 seconds |
| Started | Sep 09 09:18:55 AM UTC 24 |
| Finished | Sep 09 09:21:57 AM UTC 24 |
| Peak memory | 222180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293868261 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_mem_partial_access.293868261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/38.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.3180000978 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 59962239074 ps |
| CPU time | 188.05 seconds |
| Started | Sep 09 09:18:51 AM UTC 24 |
| Finished | Sep 09 09:22:02 AM UTC 24 |
| Peak memory | 212028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180000978 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_mem_walk.3180000978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/38.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.723555372 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 1377159556 ps |
| CPU time | 33.31 seconds |
| Started | Sep 09 09:18:07 AM UTC 24 |
| Finished | Sep 09 09:18:42 AM UTC 24 |
| Peak memory | 261980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723555372 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multiple_keys.723555372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/38.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access.2168580136 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 587386590 ps |
| CPU time | 20.89 seconds |
| Started | Sep 09 09:18:12 AM UTC 24 |
| Finished | Sep 09 09:18:34 AM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168580136 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_partial_access.2168580136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/38.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.3966385719 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 22175755038 ps |
| CPU time | 419.74 seconds |
| Started | Sep 09 09:18:18 AM UTC 24 |
| Finished | Sep 09 09:25:23 AM UTC 24 |
| Peak memory | 211952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966385719 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_partial_a ccess_b2b.3966385719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/38.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.2588933452 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 680762578 ps |
| CPU time | 5.72 seconds |
| Started | Sep 09 09:18:43 AM UTC 24 |
| Finished | Sep 09 09:18:49 AM UTC 24 |
| Peak memory | 211952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588933452 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.2588933452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/38.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_regwen.816413196 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 38920779215 ps |
| CPU time | 1211.45 seconds |
| Started | Sep 09 09:18:37 AM UTC 24 |
| Finished | Sep 09 09:39:03 AM UTC 24 |
| Peak memory | 388992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816413196 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.816413196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/38.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_smoke.2478498987 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 701633497 ps |
| CPU time | 9.29 seconds |
| Started | Sep 09 09:17:58 AM UTC 24 |
| Finished | Sep 09 09:18:09 AM UTC 24 |
| Peak memory | 212024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478498987 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.2478498987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/38.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all.108462086 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 109358425517 ps |
| CPU time | 2701.21 seconds |
| Started | Sep 09 09:19:09 AM UTC 24 |
| Finished | Sep 09 10:04:40 AM UTC 24 |
| Peak memory | 400912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10846208 6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all.108462086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/38.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3091186206 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 377653910 ps |
| CPU time | 13.36 seconds |
| Started | Sep 09 09:19:08 AM UTC 24 |
| Finished | Sep 09 09:19:22 AM UTC 24 |
| Peak memory | 222456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091186206 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.3091186206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/38.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.753627658 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 19200463025 ps |
| CPU time | 408.9 seconds |
| Started | Sep 09 09:18:11 AM UTC 24 |
| Finished | Sep 09 09:25:05 AM UTC 24 |
| Peak memory | 212016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753627658 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_pipeline.753627658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/38.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.2166473636 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 7521264592 ps |
| CPU time | 42.89 seconds |
| Started | Sep 09 09:18:31 AM UTC 24 |
| Finished | Sep 09 09:19:16 AM UTC 24 |
| Peak memory | 340012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2166473636 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl _throughput_w_partial_write.2166473636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/38.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.4115418921 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 12176501265 ps |
| CPU time | 770.85 seconds |
| Started | Sep 09 09:20:19 AM UTC 24 |
| Finished | Sep 09 09:33:19 AM UTC 24 |
| Peak memory | 388944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115418921 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_access_duri ng_key_req.4115418921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/39.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_alert_test.268542940 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 50570617 ps |
| CPU time | 1.02 seconds |
| Started | Sep 09 09:21:08 AM UTC 24 |
| Finished | Sep 09 09:21:11 AM UTC 24 |
| Peak memory | 211056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268542940 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_alert_test.268542940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/39.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_bijection.3060460245 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 13867497823 ps |
| CPU time | 808.12 seconds |
| Started | Sep 09 09:19:16 AM UTC 24 |
| Finished | Sep 09 09:32:54 AM UTC 24 |
| Peak memory | 211880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060460245 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection.3060460245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/39.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_executable.4292267135 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 16887277117 ps |
| CPU time | 638.51 seconds |
| Started | Sep 09 09:20:29 AM UTC 24 |
| Finished | Sep 09 09:31:15 AM UTC 24 |
| Peak memory | 386920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292267135 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executable.4292267135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/39.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.3831233107 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 6918148544 ps |
| CPU time | 19.04 seconds |
| Started | Sep 09 09:20:15 AM UTC 24 |
| Finished | Sep 09 09:20:35 AM UTC 24 |
| Peak memory | 211752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831233107 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_escalation.3831233107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/39.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.115156058 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 3283723687 ps |
| CPU time | 77.01 seconds |
| Started | Sep 09 09:20:02 AM UTC 24 |
| Finished | Sep 09 09:21:21 AM UTC 24 |
| Peak memory | 362352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 115156058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_m ax_throughput.115156058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/39.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.4009818366 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 20415588558 ps |
| CPU time | 219.04 seconds |
| Started | Sep 09 09:20:42 AM UTC 24 |
| Finished | Sep 09 09:24:24 AM UTC 24 |
| Peak memory | 222168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009818366 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_mem_partial_access.4009818366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/39.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.4124069408 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 41422327958 ps |
| CPU time | 183.7 seconds |
| Started | Sep 09 09:20:40 AM UTC 24 |
| Finished | Sep 09 09:23:46 AM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124069408 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_mem_walk.4124069408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/39.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.4266105892 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 6220522892 ps |
| CPU time | 289.34 seconds |
| Started | Sep 09 09:19:14 AM UTC 24 |
| Finished | Sep 09 09:24:08 AM UTC 24 |
| Peak memory | 350120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266105892 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multiple_keys.4266105892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/39.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access.1240299438 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 5334460622 ps |
| CPU time | 20.36 seconds |
| Started | Sep 09 09:19:53 AM UTC 24 |
| Finished | Sep 09 09:20:14 AM UTC 24 |
| Peak memory | 212144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240299438 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_partial_access.1240299438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/39.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.4213064718 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 31915165496 ps |
| CPU time | 457.55 seconds |
| Started | Sep 09 09:19:56 AM UTC 24 |
| Finished | Sep 09 09:27:40 AM UTC 24 |
| Peak memory | 212144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213064718 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_partial_a ccess_b2b.4213064718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/39.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.1821972507 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 786503242 ps |
| CPU time | 3.48 seconds |
| Started | Sep 09 09:20:37 AM UTC 24 |
| Finished | Sep 09 09:20:41 AM UTC 24 |
| Peak memory | 212016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821972507 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.1821972507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/39.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_regwen.1339760206 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 5230377305 ps |
| CPU time | 1009.25 seconds |
| Started | Sep 09 09:20:37 AM UTC 24 |
| Finished | Sep 09 09:37:38 AM UTC 24 |
| Peak memory | 382904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339760206 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.1339760206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/39.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_smoke.2432932572 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 4062056087 ps |
| CPU time | 46.46 seconds |
| Started | Sep 09 09:19:13 AM UTC 24 |
| Finished | Sep 09 09:20:01 AM UTC 24 |
| Peak memory | 313260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432932572 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.2432932572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/39.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all.2563012590 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 84769548574 ps |
| CPU time | 2031.98 seconds |
| Started | Sep 09 09:21:04 AM UTC 24 |
| Finished | Sep 09 09:55:17 AM UTC 24 |
| Peak memory | 392788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25630125 90 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_a ll.2563012590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/39.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.1157750052 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 4539789968 ps |
| CPU time | 140.92 seconds |
| Started | Sep 09 09:20:44 AM UTC 24 |
| Finished | Sep 09 09:23:07 AM UTC 24 |
| Peak memory | 290800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157750052 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.1157750052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/39.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.754683765 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 4184809809 ps |
| CPU time | 276.51 seconds |
| Started | Sep 09 09:19:24 AM UTC 24 |
| Finished | Sep 09 09:24:04 AM UTC 24 |
| Peak memory | 211960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754683765 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_pipeline.754683765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/39.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.1963880408 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 1613709869 ps |
| CPU time | 86.18 seconds |
| Started | Sep 09 09:20:02 AM UTC 24 |
| Finished | Sep 09 09:21:30 AM UTC 24 |
| Peak memory | 382828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1963880408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl _throughput_w_partial_write.1963880408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/39.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.2787071700 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 8828543570 ps |
| CPU time | 224.76 seconds |
| Started | Sep 09 08:04:32 AM UTC 24 |
| Finished | Sep 09 08:08:20 AM UTC 24 |
| Peak memory | 384952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787071700 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_access_durin g_key_req.2787071700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_alert_test.2970881932 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 14610061 ps |
| CPU time | 0.94 seconds |
| Started | Sep 09 08:04:47 AM UTC 24 |
| Finished | Sep 09 08:04:49 AM UTC 24 |
| Peak memory | 211116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970881932 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_alert_test.2970881932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_bijection.1235078819 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 89906765589 ps |
| CPU time | 1754.91 seconds |
| Started | Sep 09 08:04:16 AM UTC 24 |
| Finished | Sep 09 08:33:50 AM UTC 24 |
| Peak memory | 213700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235078819 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection.1235078819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_executable.2793162932 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 26222124542 ps |
| CPU time | 530.48 seconds |
| Started | Sep 09 08:04:33 AM UTC 24 |
| Finished | Sep 09 08:13:31 AM UTC 24 |
| Peak memory | 358240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793162932 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executable.2793162932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.3019136157 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 12471860921 ps |
| CPU time | 34.32 seconds |
| Started | Sep 09 08:04:28 AM UTC 24 |
| Finished | Sep 09 08:05:04 AM UTC 24 |
| Peak memory | 211944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019136157 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_escalation.3019136157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.1639734063 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 677569534 ps |
| CPU time | 10.17 seconds |
| Started | Sep 09 08:04:20 AM UTC 24 |
| Finished | Sep 09 08:04:31 AM UTC 24 |
| Peak memory | 224360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1639734063 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_m ax_throughput.1639734063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.1230942985 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 18263191541 ps |
| CPU time | 182.22 seconds |
| Started | Sep 09 08:04:41 AM UTC 24 |
| Finished | Sep 09 08:07:46 AM UTC 24 |
| Peak memory | 222188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230942985 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_mem_partial_access.1230942985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.414517861 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 22017222502 ps |
| CPU time | 396.55 seconds |
| Started | Sep 09 08:04:40 AM UTC 24 |
| Finished | Sep 09 08:11:22 AM UTC 24 |
| Peak memory | 222188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414517861 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_mem_walk.414517861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.3770843462 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 6376715405 ps |
| CPU time | 257.45 seconds |
| Started | Sep 09 08:04:15 AM UTC 24 |
| Finished | Sep 09 08:08:36 AM UTC 24 |
| Peak memory | 380968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770843462 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multiple_keys.3770843462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access.1160193093 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 4485287898 ps |
| CPU time | 19.49 seconds |
| Started | Sep 09 08:04:18 AM UTC 24 |
| Finished | Sep 09 08:04:39 AM UTC 24 |
| Peak memory | 211888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160193093 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_partial_access.1160193093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.2707733415 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 72724170325 ps |
| CPU time | 460.89 seconds |
| Started | Sep 09 08:04:18 AM UTC 24 |
| Finished | Sep 09 08:12:05 AM UTC 24 |
| Peak memory | 211960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707733415 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_partial_ac cess_b2b.2707733415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.493043182 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 1399164132 ps |
| CPU time | 5.72 seconds |
| Started | Sep 09 08:04:40 AM UTC 24 |
| Finished | Sep 09 08:04:46 AM UTC 24 |
| Peak memory | 211952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493043182 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.493043182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_regwen.3854333106 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 7722445337 ps |
| CPU time | 365.5 seconds |
| Started | Sep 09 08:04:39 AM UTC 24 |
| Finished | Sep 09 08:10:49 AM UTC 24 |
| Peak memory | 366524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854333106 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.3854333106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.1747698358 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 369304889 ps |
| CPU time | 3.39 seconds |
| Started | Sep 09 08:04:47 AM UTC 24 |
| Finished | Sep 09 08:04:52 AM UTC 24 |
| Peak memory | 247692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747698358 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_sec_cm.1747698358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_smoke.1288708408 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 412547077 ps |
| CPU time | 6.92 seconds |
| Started | Sep 09 08:04:12 AM UTC 24 |
| Finished | Sep 09 08:04:20 AM UTC 24 |
| Peak memory | 218304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288708408 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.1288708408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all.1902957294 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 37177257824 ps |
| CPU time | 1943.68 seconds |
| Started | Sep 09 08:04:42 AM UTC 24 |
| Finished | Sep 09 08:37:27 AM UTC 24 |
| Peak memory | 384736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19029572 94 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all.1902957294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.4270326613 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 393004042 ps |
| CPU time | 17.37 seconds |
| Started | Sep 09 08:04:41 AM UTC 24 |
| Finished | Sep 09 08:04:59 AM UTC 24 |
| Peak memory | 222192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270326613 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.4270326613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.2092026275 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 24241619105 ps |
| CPU time | 383.12 seconds |
| Started | Sep 09 08:04:17 AM UTC 24 |
| Finished | Sep 09 08:10:45 AM UTC 24 |
| Peak memory | 211948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092026275 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_pipeline.2092026275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.1561653755 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 4896563317 ps |
| CPU time | 15.44 seconds |
| Started | Sep 09 08:04:22 AM UTC 24 |
| Finished | Sep 09 08:04:39 AM UTC 24 |
| Peak memory | 239528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1561653755 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ throughput_w_partial_write.1561653755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.203618974 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 13132375927 ps |
| CPU time | 711.23 seconds |
| Started | Sep 09 09:22:06 AM UTC 24 |
| Finished | Sep 09 09:34:06 AM UTC 24 |
| Peak memory | 382820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203618974 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_access_durin g_key_req.203618974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/40.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_alert_test.859087773 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 18990559 ps |
| CPU time | 0.93 seconds |
| Started | Sep 09 09:24:05 AM UTC 24 |
| Finished | Sep 09 09:24:07 AM UTC 24 |
| Peak memory | 211032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859087773 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_alert_test.859087773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/40.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_bijection.497192067 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 718163102088 ps |
| CPU time | 2941.17 seconds |
| Started | Sep 09 09:21:20 AM UTC 24 |
| Finished | Sep 09 10:10:55 AM UTC 24 |
| Peak memory | 213580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497192067 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection.497192067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/40.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_executable.1926310457 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 4625977890 ps |
| CPU time | 115.86 seconds |
| Started | Sep 09 09:22:14 AM UTC 24 |
| Finished | Sep 09 09:24:13 AM UTC 24 |
| Peak memory | 300908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926310457 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executable.1926310457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/40.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.2325990755 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 10016244209 ps |
| CPU time | 125.74 seconds |
| Started | Sep 09 09:22:02 AM UTC 24 |
| Finished | Sep 09 09:24:10 AM UTC 24 |
| Peak memory | 226288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325990755 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_escalation.2325990755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/40.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.731892633 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 2865830546 ps |
| CPU time | 29 seconds |
| Started | Sep 09 09:21:43 AM UTC 24 |
| Finished | Sep 09 09:22:13 AM UTC 24 |
| Peak memory | 282468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 731892633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_m ax_throughput.731892633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/40.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.2753987199 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 27479204377 ps |
| CPU time | 224.83 seconds |
| Started | Sep 09 09:23:08 AM UTC 24 |
| Finished | Sep 09 09:26:57 AM UTC 24 |
| Peak memory | 222324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753987199 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_mem_partial_access.2753987199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/40.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.4117433634 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 6930368545 ps |
| CPU time | 193.35 seconds |
| Started | Sep 09 09:23:07 AM UTC 24 |
| Finished | Sep 09 09:26:24 AM UTC 24 |
| Peak memory | 222268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117433634 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_mem_walk.4117433634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/40.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.2164970347 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 39827162634 ps |
| CPU time | 732.77 seconds |
| Started | Sep 09 09:21:16 AM UTC 24 |
| Finished | Sep 09 09:33:37 AM UTC 24 |
| Peak memory | 384876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164970347 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multiple_keys.2164970347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/40.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access.3746469350 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 717824247 ps |
| CPU time | 33 seconds |
| Started | Sep 09 09:21:31 AM UTC 24 |
| Finished | Sep 09 09:22:05 AM UTC 24 |
| Peak memory | 300904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746469350 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_partial_access.3746469350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/40.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.1668407082 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 8353520452 ps |
| CPU time | 288.76 seconds |
| Started | Sep 09 09:21:32 AM UTC 24 |
| Finished | Sep 09 09:26:25 AM UTC 24 |
| Peak memory | 212016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668407082 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_partial_a ccess_b2b.1668407082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/40.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.4275302981 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 1295930008 ps |
| CPU time | 6.02 seconds |
| Started | Sep 09 09:22:59 AM UTC 24 |
| Finished | Sep 09 09:23:06 AM UTC 24 |
| Peak memory | 212024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275302981 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.4275302981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/40.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_regwen.1470492672 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 2850078497 ps |
| CPU time | 303.06 seconds |
| Started | Sep 09 09:22:18 AM UTC 24 |
| Finished | Sep 09 09:27:25 AM UTC 24 |
| Peak memory | 366444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470492672 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.1470492672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/40.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_smoke.3309677816 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 381730223 ps |
| CPU time | 6.24 seconds |
| Started | Sep 09 09:21:11 AM UTC 24 |
| Finished | Sep 09 09:21:19 AM UTC 24 |
| Peak memory | 211692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309677816 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.3309677816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/40.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all.2758002401 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 643607481007 ps |
| CPU time | 5243.71 seconds |
| Started | Sep 09 09:23:48 AM UTC 24 |
| Finished | Sep 09 10:52:08 AM UTC 24 |
| Peak memory | 390656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27580024 01 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_a ll.2758002401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/40.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.2122624899 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 17405081549 ps |
| CPU time | 115.3 seconds |
| Started | Sep 09 09:23:48 AM UTC 24 |
| Finished | Sep 09 09:25:45 AM UTC 24 |
| Peak memory | 222264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122624899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.2122624899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/40.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.191807688 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 23716593749 ps |
| CPU time | 163.19 seconds |
| Started | Sep 09 09:21:22 AM UTC 24 |
| Finished | Sep 09 09:24:08 AM UTC 24 |
| Peak memory | 212020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191807688 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_pipeline.191807688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/40.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.388930063 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 1507698097 ps |
| CPU time | 17.28 seconds |
| Started | Sep 09 09:21:58 AM UTC 24 |
| Finished | Sep 09 09:22:17 AM UTC 24 |
| Peak memory | 247780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =388930063 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ throughput_w_partial_write.388930063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/40.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.2136849973 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 22072791539 ps |
| CPU time | 723.46 seconds |
| Started | Sep 09 09:24:35 AM UTC 24 |
| Finished | Sep 09 09:36:46 AM UTC 24 |
| Peak memory | 389044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136849973 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_access_duri ng_key_req.2136849973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/41.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_alert_test.4231771778 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 46693527 ps |
| CPU time | 1.02 seconds |
| Started | Sep 09 09:25:49 AM UTC 24 |
| Finished | Sep 09 09:25:51 AM UTC 24 |
| Peak memory | 210996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231771778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_alert_test.4231771778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/41.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_bijection.2102032535 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 25283739844 ps |
| CPU time | 877.87 seconds |
| Started | Sep 09 09:24:09 AM UTC 24 |
| Finished | Sep 09 09:38:58 AM UTC 24 |
| Peak memory | 212024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102032535 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection.2102032535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/41.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_executable.430096722 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 36020465770 ps |
| CPU time | 625.64 seconds |
| Started | Sep 09 09:24:39 AM UTC 24 |
| Finished | Sep 09 09:35:12 AM UTC 24 |
| Peak memory | 385012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430096722 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executable.430096722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/41.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.4274561782 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 41382498328 ps |
| CPU time | 92.51 seconds |
| Started | Sep 09 09:24:26 AM UTC 24 |
| Finished | Sep 09 09:26:00 AM UTC 24 |
| Peak memory | 222168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274561782 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_escalation.4274561782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/41.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.1068617612 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 3083710108 ps |
| CPU time | 100.39 seconds |
| Started | Sep 09 09:24:19 AM UTC 24 |
| Finished | Sep 09 09:26:02 AM UTC 24 |
| Peak memory | 374704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1068617612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ max_throughput.1068617612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/41.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.835148132 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 5755507084 ps |
| CPU time | 96.92 seconds |
| Started | Sep 09 09:25:24 AM UTC 24 |
| Finished | Sep 09 09:27:03 AM UTC 24 |
| Peak memory | 222392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835148132 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_mem_partial_access.835148132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/41.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.2246604127 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 14433484617 ps |
| CPU time | 168.49 seconds |
| Started | Sep 09 09:25:14 AM UTC 24 |
| Finished | Sep 09 09:28:05 AM UTC 24 |
| Peak memory | 211932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246604127 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_mem_walk.2246604127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/41.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.1637906136 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 44562807575 ps |
| CPU time | 995.63 seconds |
| Started | Sep 09 09:24:09 AM UTC 24 |
| Finished | Sep 09 09:40:56 AM UTC 24 |
| Peak memory | 388956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637906136 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multiple_keys.1637906136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/41.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access.2611601559 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 438073884 ps |
| CPU time | 5.61 seconds |
| Started | Sep 09 09:24:11 AM UTC 24 |
| Finished | Sep 09 09:24:18 AM UTC 24 |
| Peak memory | 220996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611601559 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_partial_access.2611601559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/41.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.3863718098 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 12800322371 ps |
| CPU time | 369.99 seconds |
| Started | Sep 09 09:24:13 AM UTC 24 |
| Finished | Sep 09 09:30:29 AM UTC 24 |
| Peak memory | 212016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863718098 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_partial_a ccess_b2b.3863718098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/41.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.3425890202 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 1351388677 ps |
| CPU time | 6.03 seconds |
| Started | Sep 09 09:25:06 AM UTC 24 |
| Finished | Sep 09 09:25:13 AM UTC 24 |
| Peak memory | 211956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425890202 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.3425890202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/41.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_regwen.1868425502 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 10678259222 ps |
| CPU time | 509.36 seconds |
| Started | Sep 09 09:24:50 AM UTC 24 |
| Finished | Sep 09 09:33:25 AM UTC 24 |
| Peak memory | 370552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868425502 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.1868425502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/41.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_smoke.3744883477 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 6876215280 ps |
| CPU time | 24.46 seconds |
| Started | Sep 09 09:24:08 AM UTC 24 |
| Finished | Sep 09 09:24:34 AM UTC 24 |
| Peak memory | 211932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744883477 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.3744883477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/41.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all.794485295 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 221444110557 ps |
| CPU time | 3012.39 seconds |
| Started | Sep 09 09:25:46 AM UTC 24 |
| Finished | Sep 09 10:16:33 AM UTC 24 |
| Peak memory | 388476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79448529 5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all.794485295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/41.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.3585303668 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 3894817078 ps |
| CPU time | 29.89 seconds |
| Started | Sep 09 09:25:38 AM UTC 24 |
| Finished | Sep 09 09:26:10 AM UTC 24 |
| Peak memory | 222248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585303668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.3585303668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/41.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.2136611648 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 15890645371 ps |
| CPU time | 323.81 seconds |
| Started | Sep 09 09:24:11 AM UTC 24 |
| Finished | Sep 09 09:29:40 AM UTC 24 |
| Peak memory | 212136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136611648 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_pipeline.2136611648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/41.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.3896626724 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 1444071116 ps |
| CPU time | 22.48 seconds |
| Started | Sep 09 09:24:25 AM UTC 24 |
| Finished | Sep 09 09:24:49 AM UTC 24 |
| Peak memory | 261924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3896626724 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl _throughput_w_partial_write.3896626724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/41.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.1166981360 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 35067898045 ps |
| CPU time | 229.23 seconds |
| Started | Sep 09 09:26:58 AM UTC 24 |
| Finished | Sep 09 09:30:50 AM UTC 24 |
| Peak memory | 344112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166981360 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_access_duri ng_key_req.1166981360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/42.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_alert_test.4097738294 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 148709926 ps |
| CPU time | 1.02 seconds |
| Started | Sep 09 09:28:06 AM UTC 24 |
| Finished | Sep 09 09:28:08 AM UTC 24 |
| Peak memory | 211056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097738294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_alert_test.4097738294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/42.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_bijection.502498665 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 373712651976 ps |
| CPU time | 1269.3 seconds |
| Started | Sep 09 09:26:03 AM UTC 24 |
| Finished | Sep 09 09:47:26 AM UTC 24 |
| Peak memory | 212008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502498665 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection.502498665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/42.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_executable.3133019986 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 17926885382 ps |
| CPU time | 899.27 seconds |
| Started | Sep 09 09:27:05 AM UTC 24 |
| Finished | Sep 09 09:42:14 AM UTC 24 |
| Peak memory | 385072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133019986 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executable.3133019986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/42.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.3032263409 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 75507200809 ps |
| CPU time | 159.75 seconds |
| Started | Sep 09 09:26:30 AM UTC 24 |
| Finished | Sep 09 09:29:13 AM UTC 24 |
| Peak memory | 212000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3032263409 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_escalation.3032263409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/42.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.1807015838 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 1536482021 ps |
| CPU time | 80.76 seconds |
| Started | Sep 09 09:26:26 AM UTC 24 |
| Finished | Sep 09 09:27:49 AM UTC 24 |
| Peak memory | 380852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1807015838 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ max_throughput.1807015838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/42.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.732329771 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 20520251860 ps |
| CPU time | 150.62 seconds |
| Started | Sep 09 09:27:33 AM UTC 24 |
| Finished | Sep 09 09:30:06 AM UTC 24 |
| Peak memory | 229168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732329771 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_mem_partial_access.732329771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/42.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.1015931478 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 43144691574 ps |
| CPU time | 172.16 seconds |
| Started | Sep 09 09:27:26 AM UTC 24 |
| Finished | Sep 09 09:30:21 AM UTC 24 |
| Peak memory | 222116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015931478 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_mem_walk.1015931478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/42.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.1294920156 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 5770614148 ps |
| CPU time | 174.18 seconds |
| Started | Sep 09 09:26:01 AM UTC 24 |
| Finished | Sep 09 09:28:58 AM UTC 24 |
| Peak memory | 387000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294920156 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multiple_keys.1294920156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/42.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access.3066630427 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 1564721576 ps |
| CPU time | 11.09 seconds |
| Started | Sep 09 09:26:15 AM UTC 24 |
| Finished | Sep 09 09:26:27 AM UTC 24 |
| Peak memory | 211864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066630427 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_partial_access.3066630427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/42.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.554937362 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 49346952907 ps |
| CPU time | 349.76 seconds |
| Started | Sep 09 09:26:24 AM UTC 24 |
| Finished | Sep 09 09:32:19 AM UTC 24 |
| Peak memory | 211876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554937362 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_partial_ac cess_b2b.554937362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/42.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.767266395 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 379487809 ps |
| CPU time | 5.63 seconds |
| Started | Sep 09 09:27:25 AM UTC 24 |
| Finished | Sep 09 09:27:32 AM UTC 24 |
| Peak memory | 211940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767266395 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.767266395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/42.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_regwen.2279488285 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 46708631763 ps |
| CPU time | 645.59 seconds |
| Started | Sep 09 09:27:22 AM UTC 24 |
| Finished | Sep 09 09:38:15 AM UTC 24 |
| Peak memory | 388960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279488285 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.2279488285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/42.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_smoke.4243739667 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 2768285910 ps |
| CPU time | 20.96 seconds |
| Started | Sep 09 09:25:52 AM UTC 24 |
| Finished | Sep 09 09:26:14 AM UTC 24 |
| Peak memory | 247852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243739667 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.4243739667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/42.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all.1664852663 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 244388594630 ps |
| CPU time | 3291.76 seconds |
| Started | Sep 09 09:27:49 AM UTC 24 |
| Finished | Sep 09 10:23:18 AM UTC 24 |
| Peak memory | 388492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16648526 63 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_a ll.1664852663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/42.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.2801862276 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 688543074 ps |
| CPU time | 25.45 seconds |
| Started | Sep 09 09:27:40 AM UTC 24 |
| Finished | Sep 09 09:28:07 AM UTC 24 |
| Peak memory | 222192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801862276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.2801862276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/42.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.1252961750 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 5093824589 ps |
| CPU time | 256.89 seconds |
| Started | Sep 09 09:26:11 AM UTC 24 |
| Finished | Sep 09 09:30:32 AM UTC 24 |
| Peak memory | 212168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252961750 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_pipeline.1252961750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/42.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.739659858 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 1545627363 ps |
| CPU time | 54.41 seconds |
| Started | Sep 09 09:26:28 AM UTC 24 |
| Finished | Sep 09 09:27:24 AM UTC 24 |
| Peak memory | 339812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =739659858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ throughput_w_partial_write.739659858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/42.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.2944270971 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 22578734373 ps |
| CPU time | 561.37 seconds |
| Started | Sep 09 09:29:39 AM UTC 24 |
| Finished | Sep 09 09:39:07 AM UTC 24 |
| Peak memory | 384948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944270971 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_access_duri ng_key_req.2944270971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/43.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_alert_test.3251268151 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 37660812 ps |
| CPU time | 1.03 seconds |
| Started | Sep 09 09:30:37 AM UTC 24 |
| Finished | Sep 09 09:30:39 AM UTC 24 |
| Peak memory | 211056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251268151 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_alert_test.3251268151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/43.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_bijection.3443954857 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 25206013397 ps |
| CPU time | 1696.43 seconds |
| Started | Sep 09 09:28:15 AM UTC 24 |
| Finished | Sep 09 09:56:51 AM UTC 24 |
| Peak memory | 213640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443954857 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection.3443954857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/43.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_executable.693554195 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 38025309886 ps |
| CPU time | 892.47 seconds |
| Started | Sep 09 09:29:41 AM UTC 24 |
| Finished | Sep 09 09:44:44 AM UTC 24 |
| Peak memory | 384872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693554195 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executable.693554195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/43.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.191360988 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 49491058897 ps |
| CPU time | 71.27 seconds |
| Started | Sep 09 09:29:23 AM UTC 24 |
| Finished | Sep 09 09:30:36 AM UTC 24 |
| Peak memory | 212144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191360988 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_escalation.191360988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/43.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.3502034961 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 793418721 ps |
| CPU time | 90.5 seconds |
| Started | Sep 09 09:29:10 AM UTC 24 |
| Finished | Sep 09 09:30:43 AM UTC 24 |
| Peak memory | 368628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3502034961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ max_throughput.3502034961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/43.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.338164237 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 10735191195 ps |
| CPU time | 105.1 seconds |
| Started | Sep 09 09:30:29 AM UTC 24 |
| Finished | Sep 09 09:32:17 AM UTC 24 |
| Peak memory | 222244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338164237 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_mem_partial_access.338164237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/43.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.504856565 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 62859049198 ps |
| CPU time | 313.55 seconds |
| Started | Sep 09 09:30:27 AM UTC 24 |
| Finished | Sep 09 09:35:46 AM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504856565 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_mem_walk.504856565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/43.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.886149522 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 20035854459 ps |
| CPU time | 1037.22 seconds |
| Started | Sep 09 09:28:10 AM UTC 24 |
| Finished | Sep 09 09:45:39 AM UTC 24 |
| Peak memory | 391208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886149522 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multiple_keys.886149522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/43.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access.1172257276 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 782979010 ps |
| CPU time | 6.86 seconds |
| Started | Sep 09 09:29:01 AM UTC 24 |
| Finished | Sep 09 09:29:09 AM UTC 24 |
| Peak memory | 212060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172257276 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_partial_access.1172257276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/43.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.382844081 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 43430698350 ps |
| CPU time | 274.89 seconds |
| Started | Sep 09 09:29:10 AM UTC 24 |
| Finished | Sep 09 09:33:49 AM UTC 24 |
| Peak memory | 211948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382844081 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_partial_ac cess_b2b.382844081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/43.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.799812708 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 1400800446 ps |
| CPU time | 3.7 seconds |
| Started | Sep 09 09:30:22 AM UTC 24 |
| Finished | Sep 09 09:30:27 AM UTC 24 |
| Peak memory | 211948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799812708 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.799812708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/43.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_regwen.4029095511 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 60623681796 ps |
| CPU time | 1358.68 seconds |
| Started | Sep 09 09:30:07 AM UTC 24 |
| Finished | Sep 09 09:53:01 AM UTC 24 |
| Peak memory | 391220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029095511 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.4029095511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/43.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_smoke.3085936655 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 858020566 ps |
| CPU time | 60.32 seconds |
| Started | Sep 09 09:28:07 AM UTC 24 |
| Finished | Sep 09 09:29:09 AM UTC 24 |
| Peak memory | 339752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085936655 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.3085936655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/43.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all.2536823492 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 52147237721 ps |
| CPU time | 2067.71 seconds |
| Started | Sep 09 09:30:37 AM UTC 24 |
| Finished | Sep 09 10:05:27 AM UTC 24 |
| Peak memory | 396808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25368234 92 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_a ll.2536823492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/43.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.1073226097 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 7280067798 ps |
| CPU time | 148.59 seconds |
| Started | Sep 09 09:30:32 AM UTC 24 |
| Finished | Sep 09 09:33:04 AM UTC 24 |
| Peak memory | 395256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073226097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.1073226097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/43.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.2060908959 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 49842017532 ps |
| CPU time | 356.67 seconds |
| Started | Sep 09 09:28:59 AM UTC 24 |
| Finished | Sep 09 09:35:02 AM UTC 24 |
| Peak memory | 212192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060908959 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_pipeline.2060908959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/43.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.3750242187 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 5953123302 ps |
| CPU time | 79.98 seconds |
| Started | Sep 09 09:29:14 AM UTC 24 |
| Finished | Sep 09 09:30:35 AM UTC 24 |
| Peak memory | 370604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3750242187 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl _throughput_w_partial_write.3750242187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/43.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.4239094840 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 9727004150 ps |
| CPU time | 661.41 seconds |
| Started | Sep 09 09:32:15 AM UTC 24 |
| Finished | Sep 09 09:43:24 AM UTC 24 |
| Peak memory | 389044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239094840 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_access_duri ng_key_req.4239094840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/44.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_alert_test.4255114764 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 43128079 ps |
| CPU time | 0.85 seconds |
| Started | Sep 09 09:32:59 AM UTC 24 |
| Finished | Sep 09 09:33:01 AM UTC 24 |
| Peak memory | 210996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255114764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_alert_test.4255114764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/44.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_bijection.1460810229 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 172708864350 ps |
| CPU time | 2694.18 seconds |
| Started | Sep 09 09:30:42 AM UTC 24 |
| Finished | Sep 09 10:16:06 AM UTC 24 |
| Peak memory | 213648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460810229 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection.1460810229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/44.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_executable.1109386376 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 65260768322 ps |
| CPU time | 894.33 seconds |
| Started | Sep 09 09:32:18 AM UTC 24 |
| Finished | Sep 09 09:47:23 AM UTC 24 |
| Peak memory | 356204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109386376 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executable.1109386376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/44.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.1407571254 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 5058744791 ps |
| CPU time | 15.15 seconds |
| Started | Sep 09 09:31:58 AM UTC 24 |
| Finished | Sep 09 09:32:14 AM UTC 24 |
| Peak memory | 221916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407571254 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_escalation.1407571254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/44.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.3374799834 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 707076170 ps |
| CPU time | 25.42 seconds |
| Started | Sep 09 09:31:15 AM UTC 24 |
| Finished | Sep 09 09:31:42 AM UTC 24 |
| Peak memory | 270192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3374799834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ max_throughput.3374799834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/44.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.338180484 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 19132799950 ps |
| CPU time | 122.61 seconds |
| Started | Sep 09 09:32:44 AM UTC 24 |
| Finished | Sep 09 09:34:50 AM UTC 24 |
| Peak memory | 222124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338180484 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_mem_partial_access.338180484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/44.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.2296925361 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 103309046442 ps |
| CPU time | 416.54 seconds |
| Started | Sep 09 09:32:42 AM UTC 24 |
| Finished | Sep 09 09:39:45 AM UTC 24 |
| Peak memory | 222200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296925361 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_mem_walk.2296925361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/44.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.4084577727 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 9237323611 ps |
| CPU time | 713.9 seconds |
| Started | Sep 09 09:30:40 AM UTC 24 |
| Finished | Sep 09 09:42:43 AM UTC 24 |
| Peak memory | 385048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084577727 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multiple_keys.4084577727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/44.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access.2444955843 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 6662253227 ps |
| CPU time | 63.24 seconds |
| Started | Sep 09 09:30:51 AM UTC 24 |
| Finished | Sep 09 09:31:57 AM UTC 24 |
| Peak memory | 317488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444955843 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_partial_access.2444955843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/44.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.113472186 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 6813773273 ps |
| CPU time | 387.56 seconds |
| Started | Sep 09 09:31:06 AM UTC 24 |
| Finished | Sep 09 09:37:39 AM UTC 24 |
| Peak memory | 212012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113472186 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_partial_ac cess_b2b.113472186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/44.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.1680300894 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 743822929 ps |
| CPU time | 3.42 seconds |
| Started | Sep 09 09:32:37 AM UTC 24 |
| Finished | Sep 09 09:32:42 AM UTC 24 |
| Peak memory | 212016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680300894 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.1680300894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/44.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_regwen.1564975540 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 27385716792 ps |
| CPU time | 659.34 seconds |
| Started | Sep 09 09:32:20 AM UTC 24 |
| Finished | Sep 09 09:43:27 AM UTC 24 |
| Peak memory | 389048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564975540 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.1564975540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/44.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_smoke.3721328647 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 7660566058 ps |
| CPU time | 25.41 seconds |
| Started | Sep 09 09:30:39 AM UTC 24 |
| Finished | Sep 09 09:31:06 AM UTC 24 |
| Peak memory | 211960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721328647 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.3721328647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/44.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all.3519724607 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 334189422431 ps |
| CPU time | 5857.09 seconds |
| Started | Sep 09 09:32:56 AM UTC 24 |
| Finished | Sep 09 11:11:41 AM UTC 24 |
| Peak memory | 390668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35197246 07 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_a ll.3519724607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/44.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.808298950 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 248967564 ps |
| CPU time | 10.21 seconds |
| Started | Sep 09 09:32:54 AM UTC 24 |
| Finished | Sep 09 09:33:06 AM UTC 24 |
| Peak memory | 222388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808298950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.808298950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/44.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.777216157 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 10377084587 ps |
| CPU time | 296.11 seconds |
| Started | Sep 09 09:30:44 AM UTC 24 |
| Finished | Sep 09 09:35:45 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777216157 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_pipeline.777216157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/44.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.1075383928 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 14728460313 ps |
| CPU time | 58.37 seconds |
| Started | Sep 09 09:31:44 AM UTC 24 |
| Finished | Sep 09 09:32:44 AM UTC 24 |
| Peak memory | 311136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1075383928 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl _throughput_w_partial_write.1075383928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/44.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.2558446096 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 29852204678 ps |
| CPU time | 896.51 seconds |
| Started | Sep 09 09:34:08 AM UTC 24 |
| Finished | Sep 09 09:49:15 AM UTC 24 |
| Peak memory | 389048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558446096 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_access_duri ng_key_req.2558446096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/45.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_alert_test.528084871 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 14439819 ps |
| CPU time | 0.88 seconds |
| Started | Sep 09 09:35:46 AM UTC 24 |
| Finished | Sep 09 09:35:48 AM UTC 24 |
| Peak memory | 211032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528084871 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_alert_test.528084871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/45.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_bijection.2208340613 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 30470207404 ps |
| CPU time | 2300.49 seconds |
| Started | Sep 09 09:33:07 AM UTC 24 |
| Finished | Sep 09 10:11:56 AM UTC 24 |
| Peak memory | 213644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208340613 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection.2208340613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/45.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_executable.3060700541 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 73171795831 ps |
| CPU time | 837.19 seconds |
| Started | Sep 09 09:34:51 AM UTC 24 |
| Finished | Sep 09 09:48:58 AM UTC 24 |
| Peak memory | 374708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060700541 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executable.3060700541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/45.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.3521597351 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 70002390524 ps |
| CPU time | 185.91 seconds |
| Started | Sep 09 09:33:51 AM UTC 24 |
| Finished | Sep 09 09:37:00 AM UTC 24 |
| Peak memory | 212216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521597351 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_escalation.3521597351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/45.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.1674580132 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 1587719399 ps |
| CPU time | 91.39 seconds |
| Started | Sep 09 09:33:39 AM UTC 24 |
| Finished | Sep 09 09:35:13 AM UTC 24 |
| Peak memory | 374772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 1674580132 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ max_throughput.1674580132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/45.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.3745665935 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 2381104717 ps |
| CPU time | 110.04 seconds |
| Started | Sep 09 09:35:20 AM UTC 24 |
| Finished | Sep 09 09:37:13 AM UTC 24 |
| Peak memory | 229204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745665935 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_mem_partial_access.3745665935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/45.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.2919908435 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 5480760587 ps |
| CPU time | 164.33 seconds |
| Started | Sep 09 09:35:13 AM UTC 24 |
| Finished | Sep 09 09:38:00 AM UTC 24 |
| Peak memory | 222204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919908435 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_mem_walk.2919908435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/45.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.2151451884 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 51824401200 ps |
| CPU time | 1040.89 seconds |
| Started | Sep 09 09:33:05 AM UTC 24 |
| Finished | Sep 09 09:50:37 AM UTC 24 |
| Peak memory | 386916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151451884 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multiple_keys.2151451884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/45.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access.2519561904 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 490070726 ps |
| CPU time | 13.26 seconds |
| Started | Sep 09 09:33:26 AM UTC 24 |
| Finished | Sep 09 09:33:40 AM UTC 24 |
| Peak memory | 211864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519561904 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_partial_access.2519561904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/45.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.3301130527 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 239074951323 ps |
| CPU time | 466.84 seconds |
| Started | Sep 09 09:33:38 AM UTC 24 |
| Finished | Sep 09 09:41:31 AM UTC 24 |
| Peak memory | 212144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301130527 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_partial_a ccess_b2b.3301130527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/45.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.326745331 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 1402836332 ps |
| CPU time | 5.27 seconds |
| Started | Sep 09 09:35:13 AM UTC 24 |
| Finished | Sep 09 09:35:20 AM UTC 24 |
| Peak memory | 211948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326745331 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.326745331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/45.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_regwen.1240164867 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 10899044000 ps |
| CPU time | 792.51 seconds |
| Started | Sep 09 09:35:02 AM UTC 24 |
| Finished | Sep 09 09:48:23 AM UTC 24 |
| Peak memory | 389176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240164867 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.1240164867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/45.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_smoke.48950302 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 2389147769 ps |
| CPU time | 34.65 seconds |
| Started | Sep 09 09:33:02 AM UTC 24 |
| Finished | Sep 09 09:33:38 AM UTC 24 |
| Peak memory | 288804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48950302 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.48950302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/45.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all.2730802694 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 279024867815 ps |
| CPU time | 2379.91 seconds |
| Started | Sep 09 09:35:46 AM UTC 24 |
| Finished | Sep 09 10:15:51 AM UTC 24 |
| Peak memory | 392712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27308026 94 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_a ll.2730802694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/45.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3798670730 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 2319791194 ps |
| CPU time | 55.29 seconds |
| Started | Sep 09 09:35:39 AM UTC 24 |
| Finished | Sep 09 09:36:35 AM UTC 24 |
| Peak memory | 229192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798670730 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.3798670730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/45.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.987462530 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 36115550347 ps |
| CPU time | 393.63 seconds |
| Started | Sep 09 09:33:20 AM UTC 24 |
| Finished | Sep 09 09:39:59 AM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987462530 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_pipeline.987462530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/45.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.522749934 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 820438854 ps |
| CPU time | 113.93 seconds |
| Started | Sep 09 09:33:42 AM UTC 24 |
| Finished | Sep 09 09:35:38 AM UTC 24 |
| Peak memory | 380776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =522749934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ throughput_w_partial_write.522749934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/45.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.3755300000 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 14301134493 ps |
| CPU time | 892.54 seconds |
| Started | Sep 09 09:37:38 AM UTC 24 |
| Finished | Sep 09 09:52:40 AM UTC 24 |
| Peak memory | 389152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755300000 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_access_duri ng_key_req.3755300000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/46.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_alert_test.4188821977 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 14174372 ps |
| CPU time | 1.06 seconds |
| Started | Sep 09 09:39:08 AM UTC 24 |
| Finished | Sep 09 09:39:10 AM UTC 24 |
| Peak memory | 210996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188821977 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_alert_test.4188821977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/46.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_bijection.625645811 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 230722001745 ps |
| CPU time | 1755.2 seconds |
| Started | Sep 09 09:36:15 AM UTC 24 |
| Finished | Sep 09 10:05:52 AM UTC 24 |
| Peak memory | 212032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625645811 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection.625645811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/46.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_executable.818259151 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 25126072435 ps |
| CPU time | 1160.16 seconds |
| Started | Sep 09 09:37:40 AM UTC 24 |
| Finished | Sep 09 09:57:14 AM UTC 24 |
| Peak memory | 388980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818259151 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executable.818259151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/46.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.1974522976 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 54530194049 ps |
| CPU time | 150.59 seconds |
| Started | Sep 09 09:37:26 AM UTC 24 |
| Finished | Sep 09 09:39:59 AM UTC 24 |
| Peak memory | 222244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974522976 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_escalation.1974522976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/46.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.521240831 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 760061444 ps |
| CPU time | 70.78 seconds |
| Started | Sep 09 09:37:13 AM UTC 24 |
| Finished | Sep 09 09:38:25 AM UTC 24 |
| Peak memory | 348016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 521240831 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_m ax_throughput.521240831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/46.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.1078350142 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 1405423163 ps |
| CPU time | 80.85 seconds |
| Started | Sep 09 09:38:26 AM UTC 24 |
| Finished | Sep 09 09:39:48 AM UTC 24 |
| Peak memory | 229292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078350142 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_mem_partial_access.1078350142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/46.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.2040178690 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 6928514330 ps |
| CPU time | 190.32 seconds |
| Started | Sep 09 09:38:26 AM UTC 24 |
| Finished | Sep 09 09:41:39 AM UTC 24 |
| Peak memory | 222184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040178690 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_mem_walk.2040178690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/46.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.2221025235 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 36320958990 ps |
| CPU time | 1784.74 seconds |
| Started | Sep 09 09:35:48 AM UTC 24 |
| Finished | Sep 09 10:05:52 AM UTC 24 |
| Peak memory | 389120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221025235 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multiple_keys.2221025235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/46.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access.3889882195 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 3727653172 ps |
| CPU time | 23.81 seconds |
| Started | Sep 09 09:36:46 AM UTC 24 |
| Finished | Sep 09 09:37:12 AM UTC 24 |
| Peak memory | 212064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889882195 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_partial_access.3889882195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/46.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.3954814107 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 6468763393 ps |
| CPU time | 359.2 seconds |
| Started | Sep 09 09:37:01 AM UTC 24 |
| Finished | Sep 09 09:43:05 AM UTC 24 |
| Peak memory | 211948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954814107 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_partial_a ccess_b2b.3954814107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/46.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.455645984 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 1209168341 ps |
| CPU time | 6.71 seconds |
| Started | Sep 09 09:38:17 AM UTC 24 |
| Finished | Sep 09 09:38:24 AM UTC 24 |
| Peak memory | 212020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455645984 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.455645984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/46.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_regwen.2428185987 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 19328178588 ps |
| CPU time | 813.27 seconds |
| Started | Sep 09 09:38:01 AM UTC 24 |
| Finished | Sep 09 09:51:44 AM UTC 24 |
| Peak memory | 386936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428185987 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.2428185987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/46.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_smoke.3116318645 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 2510481913 ps |
| CPU time | 26.36 seconds |
| Started | Sep 09 09:35:47 AM UTC 24 |
| Finished | Sep 09 09:36:14 AM UTC 24 |
| Peak memory | 211948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116318645 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.3116318645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/46.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all.3573004643 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 193856897981 ps |
| CPU time | 2521.45 seconds |
| Started | Sep 09 09:39:04 AM UTC 24 |
| Finished | Sep 09 10:21:32 AM UTC 24 |
| Peak memory | 390660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35730046 43 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_a ll.3573004643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/46.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2660602194 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 526199713 ps |
| CPU time | 13.16 seconds |
| Started | Sep 09 09:38:59 AM UTC 24 |
| Finished | Sep 09 09:39:13 AM UTC 24 |
| Peak memory | 222192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660602194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.2660602194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/46.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.3307316790 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 20640165140 ps |
| CPU time | 497.39 seconds |
| Started | Sep 09 09:36:36 AM UTC 24 |
| Finished | Sep 09 09:45:00 AM UTC 24 |
| Peak memory | 212032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307316790 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_pipeline.3307316790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/46.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.3304446248 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 2568968292 ps |
| CPU time | 10.38 seconds |
| Started | Sep 09 09:37:14 AM UTC 24 |
| Finished | Sep 09 09:37:25 AM UTC 24 |
| Peak memory | 221992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3304446248 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl _throughput_w_partial_write.3304446248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/46.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.1973639300 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 13290148034 ps |
| CPU time | 789.9 seconds |
| Started | Sep 09 09:41:02 AM UTC 24 |
| Finished | Sep 09 09:54:22 AM UTC 24 |
| Peak memory | 386920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973639300 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_access_duri ng_key_req.1973639300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/47.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_alert_test.2267950474 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 43730683 ps |
| CPU time | 1.02 seconds |
| Started | Sep 09 09:41:58 AM UTC 24 |
| Finished | Sep 09 09:42:00 AM UTC 24 |
| Peak memory | 211056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267950474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_alert_test.2267950474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/47.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_bijection.4126379037 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 300125928404 ps |
| CPU time | 2335.25 seconds |
| Started | Sep 09 09:39:45 AM UTC 24 |
| Finished | Sep 09 10:19:07 AM UTC 24 |
| Peak memory | 213692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126379037 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection.4126379037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/47.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_executable.1403421269 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 11501653484 ps |
| CPU time | 214.93 seconds |
| Started | Sep 09 09:41:02 AM UTC 24 |
| Finished | Sep 09 09:44:41 AM UTC 24 |
| Peak memory | 380840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403421269 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executable.1403421269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/47.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.2306236992 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 12104580718 ps |
| CPU time | 59.18 seconds |
| Started | Sep 09 09:40:56 AM UTC 24 |
| Finished | Sep 09 09:41:57 AM UTC 24 |
| Peak memory | 226276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306236992 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_escalation.2306236992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/47.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.3427764055 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 1508830079 ps |
| CPU time | 39.76 seconds |
| Started | Sep 09 09:40:21 AM UTC 24 |
| Finished | Sep 09 09:41:02 AM UTC 24 |
| Peak memory | 301044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 3427764055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ max_throughput.3427764055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/47.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.806705381 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 1927398888 ps |
| CPU time | 90.64 seconds |
| Started | Sep 09 09:41:38 AM UTC 24 |
| Finished | Sep 09 09:43:11 AM UTC 24 |
| Peak memory | 222208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806705381 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_mem_partial_access.806705381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/47.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.2753129961 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 21871292556 ps |
| CPU time | 310.57 seconds |
| Started | Sep 09 09:41:32 AM UTC 24 |
| Finished | Sep 09 09:46:47 AM UTC 24 |
| Peak memory | 222136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753129961 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_mem_walk.2753129961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/47.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_multiple_keys.1958995400 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 12834979350 ps |
| CPU time | 289.77 seconds |
| Started | Sep 09 09:39:14 AM UTC 24 |
| Finished | Sep 09 09:44:08 AM UTC 24 |
| Peak memory | 385080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958995400 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multiple_keys.1958995400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/47.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access.3391918403 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 10038051795 ps |
| CPU time | 38.01 seconds |
| Started | Sep 09 09:40:00 AM UTC 24 |
| Finished | Sep 09 09:40:39 AM UTC 24 |
| Peak memory | 211948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391918403 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_partial_access.3391918403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/47.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.2716324579 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 78026529217 ps |
| CPU time | 417.73 seconds |
| Started | Sep 09 09:40:00 AM UTC 24 |
| Finished | Sep 09 09:47:03 AM UTC 24 |
| Peak memory | 211928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716324579 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_partial_a ccess_b2b.2716324579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/47.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.3094256307 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 348214101 ps |
| CPU time | 5.65 seconds |
| Started | Sep 09 09:41:31 AM UTC 24 |
| Finished | Sep 09 09:41:37 AM UTC 24 |
| Peak memory | 211944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094256307 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.3094256307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/47.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_regwen.3585878141 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 9555743121 ps |
| CPU time | 144.32 seconds |
| Started | Sep 09 09:41:15 AM UTC 24 |
| Finished | Sep 09 09:43:41 AM UTC 24 |
| Peak memory | 339908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585878141 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.3585878141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/47.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_smoke.3013006989 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 2614700961 ps |
| CPU time | 108.46 seconds |
| Started | Sep 09 09:39:11 AM UTC 24 |
| Finished | Sep 09 09:41:02 AM UTC 24 |
| Peak memory | 368556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013006989 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.3013006989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/47.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all.2827803435 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 125431899771 ps |
| CPU time | 1590.13 seconds |
| Started | Sep 09 09:41:51 AM UTC 24 |
| Finished | Sep 09 10:08:39 AM UTC 24 |
| Peak memory | 213996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28278034 35 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_a ll.2827803435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/47.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2243453528 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 15659963680 ps |
| CPU time | 196.59 seconds |
| Started | Sep 09 09:41:40 AM UTC 24 |
| Finished | Sep 09 09:45:00 AM UTC 24 |
| Peak memory | 350316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243453528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.2243453528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/47.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.3706607729 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 9024959208 ps |
| CPU time | 382.71 seconds |
| Started | Sep 09 09:39:50 AM UTC 24 |
| Finished | Sep 09 09:46:17 AM UTC 24 |
| Peak memory | 212156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706607729 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_pipeline.3706607729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/47.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.512280452 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 2659865617 ps |
| CPU time | 92.43 seconds |
| Started | Sep 09 09:40:40 AM UTC 24 |
| Finished | Sep 09 09:42:14 AM UTC 24 |
| Peak memory | 368688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =512280452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ throughput_w_partial_write.512280452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/47.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.446672071 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 26893665142 ps |
| CPU time | 740.52 seconds |
| Started | Sep 09 09:43:25 AM UTC 24 |
| Finished | Sep 09 09:55:54 AM UTC 24 |
| Peak memory | 386924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446672071 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_access_durin g_key_req.446672071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/48.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_alert_test.3629879262 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 35100194 ps |
| CPU time | 0.93 seconds |
| Started | Sep 09 09:44:21 AM UTC 24 |
| Finished | Sep 09 09:44:23 AM UTC 24 |
| Peak memory | 211056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629879262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_alert_test.3629879262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/48.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_bijection.3821329183 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 76035170117 ps |
| CPU time | 1262.46 seconds |
| Started | Sep 09 09:42:16 AM UTC 24 |
| Finished | Sep 09 10:03:33 AM UTC 24 |
| Peak memory | 212076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821329183 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection.3821329183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/48.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_executable.2007603016 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 9559112134 ps |
| CPU time | 420.91 seconds |
| Started | Sep 09 09:43:28 AM UTC 24 |
| Finished | Sep 09 09:50:34 AM UTC 24 |
| Peak memory | 362396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007603016 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executable.2007603016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/48.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.3696737507 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 43169095992 ps |
| CPU time | 103.52 seconds |
| Started | Sep 09 09:43:21 AM UTC 24 |
| Finished | Sep 09 09:45:07 AM UTC 24 |
| Peak memory | 222316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696737507 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_escalation.3696737507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/48.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.565830468 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 2807346664 ps |
| CPU time | 8.11 seconds |
| Started | Sep 09 09:43:11 AM UTC 24 |
| Finished | Sep 09 09:43:20 AM UTC 24 |
| Peak memory | 228740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 565830468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_m ax_throughput.565830468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/48.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.183646405 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 5181535917 ps |
| CPU time | 77.68 seconds |
| Started | Sep 09 09:43:42 AM UTC 24 |
| Finished | Sep 09 09:45:01 AM UTC 24 |
| Peak memory | 229228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183646405 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_mem_partial_access.183646405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/48.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.2980291539 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 16418477229 ps |
| CPU time | 302.78 seconds |
| Started | Sep 09 09:43:41 AM UTC 24 |
| Finished | Sep 09 09:48:49 AM UTC 24 |
| Peak memory | 222400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980291539 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_mem_walk.2980291539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/48.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.821165191 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 19055508283 ps |
| CPU time | 819.58 seconds |
| Started | Sep 09 09:42:14 AM UTC 24 |
| Finished | Sep 09 09:56:04 AM UTC 24 |
| Peak memory | 389040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821165191 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multiple_keys.821165191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/48.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access.4214083997 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 5643734047 ps |
| CPU time | 26.27 seconds |
| Started | Sep 09 09:42:48 AM UTC 24 |
| Finished | Sep 09 09:43:15 AM UTC 24 |
| Peak memory | 212024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214083997 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_partial_access.4214083997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/48.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.1350527540 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 14528867995 ps |
| CPU time | 223.92 seconds |
| Started | Sep 09 09:43:06 AM UTC 24 |
| Finished | Sep 09 09:46:53 AM UTC 24 |
| Peak memory | 212048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350527540 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_partial_a ccess_b2b.1350527540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/48.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.2286131678 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 1780210190 ps |
| CPU time | 5.51 seconds |
| Started | Sep 09 09:43:34 AM UTC 24 |
| Finished | Sep 09 09:43:40 AM UTC 24 |
| Peak memory | 211944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286131678 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.2286131678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/48.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_regwen.3406066262 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 6470100755 ps |
| CPU time | 196.68 seconds |
| Started | Sep 09 09:43:30 AM UTC 24 |
| Finished | Sep 09 09:46:49 AM UTC 24 |
| Peak memory | 376684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406066262 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.3406066262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/48.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_smoke.3503656142 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 1461104067 ps |
| CPU time | 44.13 seconds |
| Started | Sep 09 09:42:01 AM UTC 24 |
| Finished | Sep 09 09:42:47 AM UTC 24 |
| Peak memory | 303104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503656142 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.3503656142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/48.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all.1081213043 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 104133884018 ps |
| CPU time | 1869.18 seconds |
| Started | Sep 09 09:44:09 AM UTC 24 |
| Finished | Sep 09 10:15:39 AM UTC 24 |
| Peak memory | 361840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10812130 43 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_a ll.1081213043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/48.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3718516082 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 456093149 ps |
| CPU time | 12.99 seconds |
| Started | Sep 09 09:44:06 AM UTC 24 |
| Finished | Sep 09 09:44:20 AM UTC 24 |
| Peak memory | 222200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718516082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.3718516082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/48.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.2334920315 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 18689679037 ps |
| CPU time | 480.1 seconds |
| Started | Sep 09 09:42:44 AM UTC 24 |
| Finished | Sep 09 09:50:50 AM UTC 24 |
| Peak memory | 212156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334920315 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_pipeline.2334920315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/48.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.1694448238 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 1436184798 ps |
| CPU time | 15.94 seconds |
| Started | Sep 09 09:43:16 AM UTC 24 |
| Finished | Sep 09 09:43:33 AM UTC 24 |
| Peak memory | 245540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1694448238 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl _throughput_w_partial_write.1694448238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/48.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.3704999083 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 16762644512 ps |
| CPU time | 984.49 seconds |
| Started | Sep 09 09:45:15 AM UTC 24 |
| Finished | Sep 09 10:01:50 AM UTC 24 |
| Peak memory | 384884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704999083 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_access_duri ng_key_req.3704999083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/49.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_alert_test.3864324878 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 14690365 ps |
| CPU time | 1 seconds |
| Started | Sep 09 09:46:48 AM UTC 24 |
| Finished | Sep 09 09:46:50 AM UTC 24 |
| Peak memory | 210996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864324878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_alert_test.3864324878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/49.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_bijection.319518944 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 129749876753 ps |
| CPU time | 812.26 seconds |
| Started | Sep 09 09:44:37 AM UTC 24 |
| Finished | Sep 09 09:58:19 AM UTC 24 |
| Peak memory | 212080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319518944 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection.319518944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/49.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_executable.3939306905 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 14069442761 ps |
| CPU time | 427.85 seconds |
| Started | Sep 09 09:45:18 AM UTC 24 |
| Finished | Sep 09 09:52:31 AM UTC 24 |
| Peak memory | 382816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939306905 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executable.3939306905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/49.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.731419478 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 15610161487 ps |
| CPU time | 43.77 seconds |
| Started | Sep 09 09:45:07 AM UTC 24 |
| Finished | Sep 09 09:45:53 AM UTC 24 |
| Peak memory | 222252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731419478 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_escalation.731419478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/49.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.670120510 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 798780755 ps |
| CPU time | 106.95 seconds |
| Started | Sep 09 09:45:01 AM UTC 24 |
| Finished | Sep 09 09:46:50 AM UTC 24 |
| Peak memory | 380644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 670120510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_m ax_throughput.670120510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/49.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.4010940515 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 5201354781 ps |
| CPU time | 181.52 seconds |
| Started | Sep 09 09:45:53 AM UTC 24 |
| Finished | Sep 09 09:48:58 AM UTC 24 |
| Peak memory | 229200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010940515 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_mem_partial_access.4010940515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/49.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.866603785 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 37453537986 ps |
| CPU time | 426.37 seconds |
| Started | Sep 09 09:45:50 AM UTC 24 |
| Finished | Sep 09 09:53:02 AM UTC 24 |
| Peak memory | 222240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866603785 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_mem_walk.866603785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/49.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.4281778496 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 11706081304 ps |
| CPU time | 521.31 seconds |
| Started | Sep 09 09:44:35 AM UTC 24 |
| Finished | Sep 09 09:53:23 AM UTC 24 |
| Peak memory | 382892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281778496 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multiple_keys.4281778496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/49.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access.1140811703 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 3464041044 ps |
| CPU time | 28.1 seconds |
| Started | Sep 09 09:44:44 AM UTC 24 |
| Finished | Sep 09 09:45:14 AM UTC 24 |
| Peak memory | 257892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140811703 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_partial_access.1140811703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/49.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.1346786086 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 3471950846 ps |
| CPU time | 250.33 seconds |
| Started | Sep 09 09:45:01 AM UTC 24 |
| Finished | Sep 09 09:49:15 AM UTC 24 |
| Peak memory | 211764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346786086 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_partial_a ccess_b2b.1346786086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/49.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.138399780 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 345585043 ps |
| CPU time | 3.86 seconds |
| Started | Sep 09 09:45:44 AM UTC 24 |
| Finished | Sep 09 09:45:49 AM UTC 24 |
| Peak memory | 212020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138399780 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.138399780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/49.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_regwen.2979678121 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 15107299943 ps |
| CPU time | 329.87 seconds |
| Started | Sep 09 09:45:40 AM UTC 24 |
| Finished | Sep 09 09:51:14 AM UTC 24 |
| Peak memory | 384880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979678121 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.2979678121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/49.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_smoke.2979954553 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 909209916 ps |
| CPU time | 10.4 seconds |
| Started | Sep 09 09:44:25 AM UTC 24 |
| Finished | Sep 09 09:44:36 AM UTC 24 |
| Peak memory | 225140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979954553 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.2979954553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/49.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all.3024996293 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 255250855253 ps |
| CPU time | 4578.83 seconds |
| Started | Sep 09 09:46:31 AM UTC 24 |
| Finished | Sep 09 11:03:43 AM UTC 24 |
| Peak memory | 261560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30249962 93 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_a ll.3024996293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/49.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3610860077 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 2803399321 ps |
| CPU time | 42.42 seconds |
| Started | Sep 09 09:46:18 AM UTC 24 |
| Finished | Sep 09 09:47:02 AM UTC 24 |
| Peak memory | 222256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610860077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.3610860077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/49.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.3225773954 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 4225918589 ps |
| CPU time | 277.89 seconds |
| Started | Sep 09 09:44:41 AM UTC 24 |
| Finished | Sep 09 09:49:23 AM UTC 24 |
| Peak memory | 211956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225773954 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_pipeline.3225773954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/49.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.707848850 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 754126458 ps |
| CPU time | 13.86 seconds |
| Started | Sep 09 09:45:02 AM UTC 24 |
| Finished | Sep 09 09:45:17 AM UTC 24 |
| Peak memory | 266224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =707848850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ throughput_w_partial_write.707848850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/49.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.2067822116 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 9849408157 ps |
| CPU time | 694.65 seconds |
| Started | Sep 09 08:05:11 AM UTC 24 |
| Finished | Sep 09 08:16:54 AM UTC 24 |
| Peak memory | 386968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067822116 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_access_durin g_key_req.2067822116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_alert_test.1769877684 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 44954369 ps |
| CPU time | 1.03 seconds |
| Started | Sep 09 08:05:25 AM UTC 24 |
| Finished | Sep 09 08:05:27 AM UTC 24 |
| Peak memory | 210996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769877684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_alert_test.1769877684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_bijection.2319289488 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 43854340322 ps |
| CPU time | 1056.46 seconds |
| Started | Sep 09 08:04:51 AM UTC 24 |
| Finished | Sep 09 08:22:40 AM UTC 24 |
| Peak memory | 211952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319289488 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.2319289488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_executable.2182251324 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 20750812877 ps |
| CPU time | 315.55 seconds |
| Started | Sep 09 08:05:12 AM UTC 24 |
| Finished | Sep 09 08:10:31 AM UTC 24 |
| Peak memory | 384868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182251324 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executable.2182251324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.19731096 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 9707079025 ps |
| CPU time | 49.74 seconds |
| Started | Sep 09 08:05:10 AM UTC 24 |
| Finished | Sep 09 08:06:02 AM UTC 24 |
| Peak memory | 226356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19731096 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_escalation.19731096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.2334085440 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 2838708947 ps |
| CPU time | 15.26 seconds |
| Started | Sep 09 08:05:05 AM UTC 24 |
| Finished | Sep 09 08:05:21 AM UTC 24 |
| Peak memory | 245680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2334085440 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_m ax_throughput.2334085440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.2450750050 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 3291571945 ps |
| CPU time | 131.78 seconds |
| Started | Sep 09 08:05:22 AM UTC 24 |
| Finished | Sep 09 08:07:36 AM UTC 24 |
| Peak memory | 229216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450750050 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_mem_partial_access.2450750050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.1308526782 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 115427411566 ps |
| CPU time | 188.8 seconds |
| Started | Sep 09 08:05:20 AM UTC 24 |
| Finished | Sep 09 08:08:32 AM UTC 24 |
| Peak memory | 222176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308526782 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_mem_walk.1308526782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.1784737969 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 50257418536 ps |
| CPU time | 819.74 seconds |
| Started | Sep 09 08:04:50 AM UTC 24 |
| Finished | Sep 09 08:18:38 AM UTC 24 |
| Peak memory | 382900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784737969 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multiple_keys.1784737969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access.1291961487 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 1067843074 ps |
| CPU time | 16.95 seconds |
| Started | Sep 09 08:04:56 AM UTC 24 |
| Finished | Sep 09 08:05:14 AM UTC 24 |
| Peak memory | 212032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291961487 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_partial_access.1291961487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.3049079768 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 19353397870 ps |
| CPU time | 388.97 seconds |
| Started | Sep 09 08:05:00 AM UTC 24 |
| Finished | Sep 09 08:11:34 AM UTC 24 |
| Peak memory | 212152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049079768 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_partial_ac cess_b2b.3049079768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.729601205 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 680066266 ps |
| CPU time | 5.53 seconds |
| Started | Sep 09 08:05:18 AM UTC 24 |
| Finished | Sep 09 08:05:24 AM UTC 24 |
| Peak memory | 212028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729601205 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.729601205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_regwen.2481448933 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 3141385950 ps |
| CPU time | 581.35 seconds |
| Started | Sep 09 08:05:15 AM UTC 24 |
| Finished | Sep 09 08:15:03 AM UTC 24 |
| Peak memory | 354212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481448933 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.2481448933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_smoke.28286458 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 850207824 ps |
| CPU time | 20.83 seconds |
| Started | Sep 09 08:04:48 AM UTC 24 |
| Finished | Sep 09 08:05:11 AM UTC 24 |
| Peak memory | 247592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28286458 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.28286458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.1657126137 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 376854608 ps |
| CPU time | 17.87 seconds |
| Started | Sep 09 08:05:22 AM UTC 24 |
| Finished | Sep 09 08:05:41 AM UTC 24 |
| Peak memory | 222284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657126137 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.1657126137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.1048341854 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 54220401385 ps |
| CPU time | 320.32 seconds |
| Started | Sep 09 08:04:53 AM UTC 24 |
| Finished | Sep 09 08:10:18 AM UTC 24 |
| Peak memory | 211956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048341854 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_pipeline.1048341854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.166357571 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 4858756848 ps |
| CPU time | 13.68 seconds |
| Started | Sep 09 08:05:06 AM UTC 24 |
| Finished | Sep 09 08:05:21 AM UTC 24 |
| Peak memory | 231272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =166357571 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_t hroughput_w_partial_write.166357571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.336370058 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 27267809963 ps |
| CPU time | 817.55 seconds |
| Started | Sep 09 08:06:59 AM UTC 24 |
| Finished | Sep 09 08:20:46 AM UTC 24 |
| Peak memory | 389224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336370058 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_access_during _key_req.336370058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_alert_test.3058816451 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 23203143 ps |
| CPU time | 0.96 seconds |
| Started | Sep 09 08:07:43 AM UTC 24 |
| Finished | Sep 09 08:07:45 AM UTC 24 |
| Peak memory | 211056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058816451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_alert_test.3058816451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_bijection.997358908 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 17498207888 ps |
| CPU time | 1018.87 seconds |
| Started | Sep 09 08:05:42 AM UTC 24 |
| Finished | Sep 09 08:22:52 AM UTC 24 |
| Peak memory | 211884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997358908 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.997358908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_executable.97996287 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 36486201286 ps |
| CPU time | 455.57 seconds |
| Started | Sep 09 08:07:08 AM UTC 24 |
| Finished | Sep 09 08:14:50 AM UTC 24 |
| Peak memory | 378736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97996287 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executable.97996287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.2202582467 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 13662741248 ps |
| CPU time | 91.25 seconds |
| Started | Sep 09 08:06:42 AM UTC 24 |
| Finished | Sep 09 08:08:16 AM UTC 24 |
| Peak memory | 211888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202582467 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_escalation.2202582467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.625558885 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 1388133209 ps |
| CPU time | 8.75 seconds |
| Started | Sep 09 08:06:26 AM UTC 24 |
| Finished | Sep 09 08:06:36 AM UTC 24 |
| Peak memory | 211828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 625558885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ma x_throughput.625558885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.3826448577 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 4385589627 ps |
| CPU time | 195.4 seconds |
| Started | Sep 09 08:07:28 AM UTC 24 |
| Finished | Sep 09 08:10:46 AM UTC 24 |
| Peak memory | 222384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826448577 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_mem_partial_access.3826448577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.193633049 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 39415883044 ps |
| CPU time | 238.28 seconds |
| Started | Sep 09 08:07:28 AM UTC 24 |
| Finished | Sep 09 08:11:29 AM UTC 24 |
| Peak memory | 222196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193633049 -assert nopos tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_mem_walk.193633049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.3825688448 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 19863417862 ps |
| CPU time | 346.87 seconds |
| Started | Sep 09 08:05:42 AM UTC 24 |
| Finished | Sep 09 08:11:33 AM UTC 24 |
| Peak memory | 384892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825688448 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multiple_keys.3825688448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access.3135237491 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 861708607 ps |
| CPU time | 18.26 seconds |
| Started | Sep 09 08:06:03 AM UTC 24 |
| Finished | Sep 09 08:06:22 AM UTC 24 |
| Peak memory | 247772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135237491 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_partial_access.3135237491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.1405778992 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 36497418670 ps |
| CPU time | 500.24 seconds |
| Started | Sep 09 08:06:23 AM UTC 24 |
| Finished | Sep 09 08:14:50 AM UTC 24 |
| Peak memory | 211932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405778992 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_partial_ac cess_b2b.1405778992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.1055065689 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 1399287552 ps |
| CPU time | 5.57 seconds |
| Started | Sep 09 08:07:20 AM UTC 24 |
| Finished | Sep 09 08:07:26 AM UTC 24 |
| Peak memory | 212032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055065689 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.1055065689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_regwen.3381608035 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 13467962763 ps |
| CPU time | 885.57 seconds |
| Started | Sep 09 08:07:18 AM UTC 24 |
| Finished | Sep 09 08:22:13 AM UTC 24 |
| Peak memory | 383016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381608035 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.3381608035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_smoke.1929488193 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 2280098127 ps |
| CPU time | 15.35 seconds |
| Started | Sep 09 08:05:29 AM UTC 24 |
| Finished | Sep 09 08:05:46 AM UTC 24 |
| Peak memory | 212004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929488193 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.1929488193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all.2570086935 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 179053297134 ps |
| CPU time | 3885.79 seconds |
| Started | Sep 09 08:07:37 AM UTC 24 |
| Finished | Sep 09 09:13:03 AM UTC 24 |
| Peak memory | 394728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25700869 35 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all.2570086935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1097636433 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 2990351343 ps |
| CPU time | 29.63 seconds |
| Started | Sep 09 08:07:31 AM UTC 24 |
| Finished | Sep 09 08:08:02 AM UTC 24 |
| Peak memory | 222336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097636433 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.1097636433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.305421519 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 41300389994 ps |
| CPU time | 308.4 seconds |
| Started | Sep 09 08:05:47 AM UTC 24 |
| Finished | Sep 09 08:10:59 AM UTC 24 |
| Peak memory | 211964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305421519 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_pipeline.305421519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.3105012642 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 3047833965 ps |
| CPU time | 41.67 seconds |
| Started | Sep 09 08:06:36 AM UTC 24 |
| Finished | Sep 09 08:07:19 AM UTC 24 |
| Peak memory | 305192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =3105012642 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ throughput_w_partial_write.3105012642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.3763562323 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 37200874071 ps |
| CPU time | 1150.34 seconds |
| Started | Sep 09 08:08:32 AM UTC 24 |
| Finished | Sep 09 08:27:55 AM UTC 24 |
| Peak memory | 386936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763562323 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_access_durin g_key_req.3763562323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_alert_test.465037694 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 49060908 ps |
| CPU time | 0.95 seconds |
| Started | Sep 09 08:10:05 AM UTC 24 |
| Finished | Sep 09 08:10:07 AM UTC 24 |
| Peak memory | 210992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465037694 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_alert_test.465037694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_bijection.2444204723 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 129894153171 ps |
| CPU time | 872.55 seconds |
| Started | Sep 09 08:08:00 AM UTC 24 |
| Finished | Sep 09 08:22:43 AM UTC 24 |
| Peak memory | 212032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444204723 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.2444204723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_executable.2836076021 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 11429429748 ps |
| CPU time | 97.28 seconds |
| Started | Sep 09 08:08:33 AM UTC 24 |
| Finished | Sep 09 08:10:12 AM UTC 24 |
| Peak memory | 284512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836076021 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executable.2836076021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.621301168 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 9310821124 ps |
| CPU time | 87.25 seconds |
| Started | Sep 09 08:08:32 AM UTC 24 |
| Finished | Sep 09 08:10:01 AM UTC 24 |
| Peak memory | 212140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621301168 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_escalation.621301168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.2571984786 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 12662093449 ps |
| CPU time | 108.55 seconds |
| Started | Sep 09 08:08:22 AM UTC 24 |
| Finished | Sep 09 08:10:12 AM UTC 24 |
| Peak memory | 376684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 2571984786 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_m ax_throughput.2571984786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.3370100282 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 11853402242 ps |
| CPU time | 73.84 seconds |
| Started | Sep 09 08:08:49 AM UTC 24 |
| Finished | Sep 09 08:10:05 AM UTC 24 |
| Peak memory | 229288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370100282 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_mem_partial_access.3370100282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.2458606356 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 86229824383 ps |
| CPU time | 426.41 seconds |
| Started | Sep 09 08:08:47 AM UTC 24 |
| Finished | Sep 09 08:15:59 AM UTC 24 |
| Peak memory | 211936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458606356 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_mem_walk.2458606356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.2221023664 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 44917625635 ps |
| CPU time | 906.71 seconds |
| Started | Sep 09 08:07:47 AM UTC 24 |
| Finished | Sep 09 08:23:04 AM UTC 24 |
| Peak memory | 389164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221023664 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multiple_keys.2221023664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access.1611453286 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 595967897 ps |
| CPU time | 21.87 seconds |
| Started | Sep 09 08:08:09 AM UTC 24 |
| Finished | Sep 09 08:08:32 AM UTC 24 |
| Peak memory | 212016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611453286 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_partial_access.1611453286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.2745452535 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 87092410947 ps |
| CPU time | 239.8 seconds |
| Started | Sep 09 08:08:17 AM UTC 24 |
| Finished | Sep 09 08:12:20 AM UTC 24 |
| Peak memory | 211868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745452535 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_partial_ac cess_b2b.2745452535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.3885509926 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 3047523011 ps |
| CPU time | 7.56 seconds |
| Started | Sep 09 08:08:38 AM UTC 24 |
| Finished | Sep 09 08:08:47 AM UTC 24 |
| Peak memory | 212220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885509926 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.3885509926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_regwen.238110757 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 30997839112 ps |
| CPU time | 836.88 seconds |
| Started | Sep 09 08:08:36 AM UTC 24 |
| Finished | Sep 09 08:22:42 AM UTC 24 |
| Peak memory | 384964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238110757 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.238110757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_smoke.48786001 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 528737498 ps |
| CPU time | 19.84 seconds |
| Started | Sep 09 08:07:46 AM UTC 24 |
| Finished | Sep 09 08:08:07 AM UTC 24 |
| Peak memory | 211872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48786001 -assert nopostproc +UVM_TEST NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.48786001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all.3455558572 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 731277053228 ps |
| CPU time | 4055.16 seconds |
| Started | Sep 09 08:10:02 AM UTC 24 |
| Finished | Sep 09 09:18:17 AM UTC 24 |
| Peak memory | 392700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34555585 72 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all.3455558572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2855524537 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 5039039209 ps |
| CPU time | 99.74 seconds |
| Started | Sep 09 08:09:01 AM UTC 24 |
| Finished | Sep 09 08:10:43 AM UTC 24 |
| Peak memory | 226352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855524537 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.2855524537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.3071396588 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 4557516710 ps |
| CPU time | 337.39 seconds |
| Started | Sep 09 08:08:02 AM UTC 24 |
| Finished | Sep 09 08:13:45 AM UTC 24 |
| Peak memory | 211884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071396588 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_pipeline.3071396588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.208185615 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 670271206 ps |
| CPU time | 10.55 seconds |
| Started | Sep 09 08:08:26 AM UTC 24 |
| Finished | Sep 09 08:08:37 AM UTC 24 |
| Peak memory | 211820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =208185615 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_t hroughput_w_partial_write.208185615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.3504498624 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 8285268805 ps |
| CPU time | 348.69 seconds |
| Started | Sep 09 08:10:44 AM UTC 24 |
| Finished | Sep 09 08:16:37 AM UTC 24 |
| Peak memory | 386924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504498624 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_access_durin g_key_req.3504498624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_alert_test.792184380 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 40312512 ps |
| CPU time | 0.98 seconds |
| Started | Sep 09 08:11:02 AM UTC 24 |
| Finished | Sep 09 08:11:04 AM UTC 24 |
| Peak memory | 211052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792184380 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_alert_test.792184380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_bijection.2390432760 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 50564895013 ps |
| CPU time | 825.51 seconds |
| Started | Sep 09 08:10:13 AM UTC 24 |
| Finished | Sep 09 08:24:08 AM UTC 24 |
| Peak memory | 212032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390432760 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection.2390432760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_executable.1691496631 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 17350572117 ps |
| CPU time | 802.12 seconds |
| Started | Sep 09 08:10:46 AM UTC 24 |
| Finished | Sep 09 08:24:17 AM UTC 24 |
| Peak memory | 387120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691496631 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executable.1691496631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.1442836208 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 9831799617 ps |
| CPU time | 76.1 seconds |
| Started | Sep 09 08:10:37 AM UTC 24 |
| Finished | Sep 09 08:11:55 AM UTC 24 |
| Peak memory | 222260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442836208 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_escalation.1442836208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.4256720594 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 718677919 ps |
| CPU time | 28.6 seconds |
| Started | Sep 09 08:10:31 AM UTC 24 |
| Finished | Sep 09 08:11:01 AM UTC 24 |
| Peak memory | 278396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 4256720594 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_m ax_throughput.4256720594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.1921548294 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 4163056586 ps |
| CPU time | 78.84 seconds |
| Started | Sep 09 08:10:55 AM UTC 24 |
| Finished | Sep 09 08:12:16 AM UTC 24 |
| Peak memory | 222180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921548294 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_mem_partial_access.1921548294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.3584488949 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 49898798415 ps |
| CPU time | 171.3 seconds |
| Started | Sep 09 08:10:50 AM UTC 24 |
| Finished | Sep 09 08:13:44 AM UTC 24 |
| Peak memory | 222160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584488949 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_mem_walk.3584488949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.1036442335 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 22847082621 ps |
| CPU time | 668 seconds |
| Started | Sep 09 08:10:08 AM UTC 24 |
| Finished | Sep 09 08:21:24 AM UTC 24 |
| Peak memory | 370532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036442335 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multiple_keys.1036442335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access.20154864 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 769444534 ps |
| CPU time | 11.47 seconds |
| Started | Sep 09 08:10:18 AM UTC 24 |
| Finished | Sep 09 08:10:31 AM UTC 24 |
| Peak memory | 211872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20154864 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_partial_access.20154864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.2268246566 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 7068824524 ps |
| CPU time | 446.9 seconds |
| Started | Sep 09 08:10:28 AM UTC 24 |
| Finished | Sep 09 08:18:01 AM UTC 24 |
| Peak memory | 212152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268246566 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_partial_ac cess_b2b.2268246566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.3973091417 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 2092246514 ps |
| CPU time | 5.65 seconds |
| Started | Sep 09 08:10:48 AM UTC 24 |
| Finished | Sep 09 08:10:55 AM UTC 24 |
| Peak memory | 212148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973091417 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.3973091417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_regwen.514248988 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 5561034522 ps |
| CPU time | 136.69 seconds |
| Started | Sep 09 08:10:47 AM UTC 24 |
| Finished | Sep 09 08:13:06 AM UTC 24 |
| Peak memory | 327624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514248988 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.514248988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_smoke.1026676301 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 8200634036 ps |
| CPU time | 28.91 seconds |
| Started | Sep 09 08:10:06 AM UTC 24 |
| Finished | Sep 09 08:10:36 AM UTC 24 |
| Peak memory | 211880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026676301 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.1026676301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all.766459683 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 270942742137 ps |
| CPU time | 6050.81 seconds |
| Started | Sep 09 08:11:00 AM UTC 24 |
| Finished | Sep 09 09:52:57 AM UTC 24 |
| Peak memory | 388612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76645968 3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all.766459683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3153919316 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 624533217 ps |
| CPU time | 19.83 seconds |
| Started | Sep 09 08:11:00 AM UTC 24 |
| Finished | Sep 09 08:11:21 AM UTC 24 |
| Peak memory | 222196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153919316 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.3153919316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.2988901475 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 23239794022 ps |
| CPU time | 343.16 seconds |
| Started | Sep 09 08:10:13 AM UTC 24 |
| Finished | Sep 09 08:16:01 AM UTC 24 |
| Peak memory | 212088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988901475 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_pipeline.2988901475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.1855889985 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 1092560858 ps |
| CPU time | 59.34 seconds |
| Started | Sep 09 08:10:33 AM UTC 24 |
| Finished | Sep 09 08:11:34 AM UTC 24 |
| Peak memory | 368488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =1855889985 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ throughput_w_partial_write.1855889985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_throughput_w_partial_write/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.4054331882 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 10333149404 ps |
| CPU time | 548.93 seconds |
| Started | Sep 09 08:11:35 AM UTC 24 |
| Finished | Sep 09 08:20:50 AM UTC 24 |
| Peak memory | 389044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054331882 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_access_durin g_key_req.4054331882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_access_during_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_alert_test.364709168 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 14428589 ps |
| CPU time | 1 seconds |
| Started | Sep 09 08:12:21 AM UTC 24 |
| Finished | Sep 09 08:12:23 AM UTC 24 |
| Peak memory | 210992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364709168 - assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_alert_test.364709168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_bijection.371619619 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 110622473071 ps |
| CPU time | 1734.22 seconds |
| Started | Sep 09 08:11:20 AM UTC 24 |
| Finished | Sep 09 08:40:32 AM UTC 24 |
| Peak memory | 213652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371619619 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.371619619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_bijection/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_executable.1675432691 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 25649296331 ps |
| CPU time | 635.23 seconds |
| Started | Sep 09 08:11:35 AM UTC 24 |
| Finished | Sep 09 08:22:18 AM UTC 24 |
| Peak memory | 378736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675432691 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executable.1675432691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_executable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.3871004697 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 15092179429 ps |
| CPU time | 70.45 seconds |
| Started | Sep 09 08:11:34 AM UTC 24 |
| Finished | Sep 09 08:12:46 AM UTC 24 |
| Peak memory | 222384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871004697 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_escalation.3871004697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_lc_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.174936637 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 4253704346 ps |
| CPU time | 62.23 seconds |
| Started | Sep 09 08:11:30 AM UTC 24 |
| Finished | Sep 09 08:12:34 AM UTC 24 |
| Peak memory | 382896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed= 174936637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ma x_throughput.174936637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_max_throughput/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.2959549791 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 4993181448 ps |
| CPU time | 192.88 seconds |
| Started | Sep 09 08:12:00 AM UTC 24 |
| Finished | Sep 09 08:15:16 AM UTC 24 |
| Peak memory | 229308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959549791 -a ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_mem_partial_access.2959549791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.1555866013 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 57415247315 ps |
| CPU time | 195.58 seconds |
| Started | Sep 09 08:11:55 AM UTC 24 |
| Finished | Sep 09 08:15:14 AM UTC 24 |
| Peak memory | 222328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555866013 -assert nopo stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_mem_walk.1555866013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.1948296575 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 8552650221 ps |
| CPU time | 13.62 seconds |
| Started | Sep 09 08:11:05 AM UTC 24 |
| Finished | Sep 09 08:11:20 AM UTC 24 |
| Peak memory | 253872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948296575 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multiple_keys.1948296575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_multiple_keys/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access.876575732 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 1418354102 ps |
| CPU time | 11.88 seconds |
| Started | Sep 09 08:11:22 AM UTC 24 |
| Finished | Sep 09 08:11:35 AM UTC 24 |
| Peak memory | 211892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876575732 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_partial_access.876575732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.1285553090 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 14458130971 ps |
| CPU time | 460.08 seconds |
| Started | Sep 09 08:11:23 AM UTC 24 |
| Finished | Sep 09 08:19:09 AM UTC 24 |
| Peak memory | 212132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285553090 -as sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_partial_ac cess_b2b.1285553090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_partial_access_b2b/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.3112610800 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 352228012 ps |
| CPU time | 5.17 seconds |
| Started | Sep 09 08:11:52 AM UTC 24 |
| Finished | Sep 09 08:11:59 AM UTC 24 |
| Peak memory | 211944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112610800 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.3112610800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_regwen.1373059552 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 14678903516 ps |
| CPU time | 360.95 seconds |
| Started | Sep 09 08:11:36 AM UTC 24 |
| Finished | Sep 09 08:17:42 AM UTC 24 |
| Peak memory | 354216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373059552 -assert nopostproc +UVM_TE STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.1373059552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_smoke.987878021 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 750537393 ps |
| CPU time | 28.71 seconds |
| Started | Sep 09 08:11:04 AM UTC 24 |
| Finished | Sep 09 08:11:34 AM UTC 24 |
| Peak memory | 286728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987878021 -assert nopostproc +UVM_TES TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.987878021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all.789801506 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 557921040831 ps |
| CPU time | 3822.16 seconds |
| Started | Sep 09 08:12:17 AM UTC 24 |
| Finished | Sep 09 09:16:38 AM UTC 24 |
| Peak memory | 392640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78980150 6 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all.789801506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.3606557733 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 420317777 ps |
| CPU time | 16.8 seconds |
| Started | Sep 09 08:12:06 AM UTC 24 |
| Finished | Sep 09 08:12:24 AM UTC 24 |
| Peak memory | 222400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606557733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.3606557733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.4280926761 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 10504538371 ps |
| CPU time | 340.74 seconds |
| Started | Sep 09 08:11:21 AM UTC 24 |
| Finished | Sep 09 08:17:06 AM UTC 24 |
| Peak memory | 212152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280926761 -assert nop ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_pipeline.4280926761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_stress_pipeline/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.2097558287 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 2769669702 ps |
| CPU time | 16.61 seconds |
| Started | Sep 09 08:11:34 AM UTC 24 |
| Finished | Sep 09 08:11:52 AM UTC 24 |
| Peak memory | 245604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed =2097558287 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ throughput_w_partial_write.2097558287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_throughput_w_partial_write/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |