| T310 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_alert_test.1515869033 |
|
|
Sep 24 10:33:55 AM UTC 24 |
Sep 24 10:33:57 AM UTC 24 |
39946412 ps |
| T311 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.315587070 |
|
|
Sep 24 10:33:30 AM UTC 24 |
Sep 24 10:34:14 AM UTC 24 |
1163056762 ps |
| T312 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.2037549946 |
|
|
Sep 24 10:25:32 AM UTC 24 |
Sep 24 10:34:19 AM UTC 24 |
115388586197 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.992253514 |
|
|
Sep 24 10:19:46 AM UTC 24 |
Sep 24 10:34:23 AM UTC 24 |
18030758190 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_smoke.2653653160 |
|
|
Sep 24 10:33:58 AM UTC 24 |
Sep 24 10:34:23 AM UTC 24 |
1443121787 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.219895579 |
|
|
Sep 24 10:22:07 AM UTC 24 |
Sep 24 10:34:25 AM UTC 24 |
65710379503 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.2662891295 |
|
|
Sep 24 10:25:51 AM UTC 24 |
Sep 24 10:34:32 AM UTC 24 |
42166719121 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access.3522102164 |
|
|
Sep 24 10:34:24 AM UTC 24 |
Sep 24 10:35:05 AM UTC 24 |
993050137 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.1458724344 |
|
|
Sep 24 10:30:29 AM UTC 24 |
Sep 24 10:35:09 AM UTC 24 |
4563100657 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_bijection.1757448445 |
|
|
Sep 24 09:49:08 AM UTC 24 |
Sep 24 10:35:40 AM UTC 24 |
138846304760 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.832358390 |
|
|
Sep 24 10:34:32 AM UTC 24 |
Sep 24 10:35:51 AM UTC 24 |
795312777 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.3020182885 |
|
|
Sep 24 10:35:06 AM UTC 24 |
Sep 24 10:36:21 AM UTC 24 |
2791315916 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.1525670151 |
|
|
Sep 24 10:35:10 AM UTC 24 |
Sep 24 10:36:52 AM UTC 24 |
51068311223 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.870041862 |
|
|
Sep 24 10:36:52 AM UTC 24 |
Sep 24 10:37:00 AM UTC 24 |
1397370596 ps |
| T18 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_regwen.2718289532 |
|
|
Sep 24 10:11:56 AM UTC 24 |
Sep 24 10:37:10 AM UTC 24 |
15821165437 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.879527965 |
|
|
Sep 24 10:33:29 AM UTC 24 |
Sep 24 10:37:30 AM UTC 24 |
21885497851 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.2244341719 |
|
|
Sep 24 10:34:24 AM UTC 24 |
Sep 24 10:37:43 AM UTC 24 |
2744984601 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.395211197 |
|
|
Sep 24 10:37:31 AM UTC 24 |
Sep 24 10:38:11 AM UTC 24 |
804590340 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_regwen.1974322802 |
|
|
Sep 24 10:33:13 AM UTC 24 |
Sep 24 10:38:14 AM UTC 24 |
2156146580 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_alert_test.3933799932 |
|
|
Sep 24 10:38:12 AM UTC 24 |
Sep 24 10:38:14 AM UTC 24 |
20575842 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_smoke.2354847937 |
|
|
Sep 24 10:38:15 AM UTC 24 |
Sep 24 10:38:52 AM UTC 24 |
3132811652 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.2496004556 |
|
|
Sep 24 10:09:47 AM UTC 24 |
Sep 24 10:39:08 AM UTC 24 |
31546934114 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_regwen.693962265 |
|
|
Sep 24 10:25:28 AM UTC 24 |
Sep 24 10:39:59 AM UTC 24 |
21832017397 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.701658329 |
|
|
Sep 24 10:37:01 AM UTC 24 |
Sep 24 10:40:09 AM UTC 24 |
10474960787 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all.4202723532 |
|
|
Sep 24 09:53:53 AM UTC 24 |
Sep 24 10:40:15 AM UTC 24 |
364231749770 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.2192929593 |
|
|
Sep 24 10:37:11 AM UTC 24 |
Sep 24 10:40:37 AM UTC 24 |
11590261474 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_regwen.1581294712 |
|
|
Sep 24 10:28:06 AM UTC 24 |
Sep 24 10:40:42 AM UTC 24 |
12050128879 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access.3193633100 |
|
|
Sep 24 10:40:00 AM UTC 24 |
Sep 24 10:41:14 AM UTC 24 |
9294922214 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.1478261689 |
|
|
Sep 24 10:34:26 AM UTC 24 |
Sep 24 10:41:15 AM UTC 24 |
12697966986 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_bijection.2813351772 |
|
|
Sep 24 09:54:12 AM UTC 24 |
Sep 24 10:41:20 AM UTC 24 |
320767185325 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all.3519955136 |
|
|
Sep 24 09:51:15 AM UTC 24 |
Sep 24 10:41:20 AM UTC 24 |
630330764819 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_executable.360786434 |
|
|
Sep 24 10:28:04 AM UTC 24 |
Sep 24 10:41:20 AM UTC 24 |
34754435213 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.1460197667 |
|
|
Sep 24 10:41:21 AM UTC 24 |
Sep 24 10:41:27 AM UTC 24 |
480731876 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.1034618534 |
|
|
Sep 24 10:35:41 AM UTC 24 |
Sep 24 10:41:31 AM UTC 24 |
12521479762 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.2821325066 |
|
|
Sep 24 10:40:43 AM UTC 24 |
Sep 24 10:41:33 AM UTC 24 |
4599474790 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.180839617 |
|
|
Sep 24 10:31:34 AM UTC 24 |
Sep 24 10:41:35 AM UTC 24 |
76014230478 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.824230044 |
|
|
Sep 24 10:40:16 AM UTC 24 |
Sep 24 10:41:35 AM UTC 24 |
3152500215 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_alert_test.3895277615 |
|
|
Sep 24 10:41:36 AM UTC 24 |
Sep 24 10:41:39 AM UTC 24 |
11246011 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.418764432 |
|
|
Sep 24 10:33:19 AM UTC 24 |
Sep 24 10:41:50 AM UTC 24 |
295667387746 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.316588636 |
|
|
Sep 24 10:40:38 AM UTC 24 |
Sep 24 10:41:52 AM UTC 24 |
825938193 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.1411183648 |
|
|
Sep 24 10:41:32 AM UTC 24 |
Sep 24 10:41:59 AM UTC 24 |
685387822 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_executable.2818376259 |
|
|
Sep 24 10:16:21 AM UTC 24 |
Sep 24 10:42:15 AM UTC 24 |
22472874086 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_smoke.67652392 |
|
|
Sep 24 10:41:36 AM UTC 24 |
Sep 24 10:42:16 AM UTC 24 |
5881908329 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access.4263759055 |
|
|
Sep 24 10:42:00 AM UTC 24 |
Sep 24 10:42:27 AM UTC 24 |
1302192337 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.2489683663 |
|
|
Sep 24 10:42:17 AM UTC 24 |
Sep 24 10:42:37 AM UTC 24 |
3131957937 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.2237474668 |
|
|
Sep 24 10:29:54 AM UTC 24 |
Sep 24 10:42:39 AM UTC 24 |
6920138746 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_executable.700115296 |
|
|
Sep 24 10:25:28 AM UTC 24 |
Sep 24 10:42:59 AM UTC 24 |
9598817810 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.2822231544 |
|
|
Sep 24 10:41:28 AM UTC 24 |
Sep 24 10:43:38 AM UTC 24 |
24175233565 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.207105427 |
|
|
Sep 24 10:42:28 AM UTC 24 |
Sep 24 10:43:44 AM UTC 24 |
1704634343 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.3270712261 |
|
|
Sep 24 10:42:38 AM UTC 24 |
Sep 24 10:43:51 AM UTC 24 |
49972432127 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.4028091143 |
|
|
Sep 24 10:43:45 AM UTC 24 |
Sep 24 10:43:51 AM UTC 24 |
362862444 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.748318522 |
|
|
Sep 24 10:32:59 AM UTC 24 |
Sep 24 10:44:03 AM UTC 24 |
42625000058 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_executable.2255102114 |
|
|
Sep 24 10:35:52 AM UTC 24 |
Sep 24 10:44:14 AM UTC 24 |
59804214538 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.3477894106 |
|
|
Sep 24 10:39:09 AM UTC 24 |
Sep 24 10:45:01 AM UTC 24 |
4522417377 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_alert_test.896625104 |
|
|
Sep 24 10:45:03 AM UTC 24 |
Sep 24 10:45:05 AM UTC 24 |
10947398 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.1189093010 |
|
|
Sep 24 10:40:10 AM UTC 24 |
Sep 24 10:45:05 AM UTC 24 |
65421824059 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.1817577949 |
|
|
Sep 24 10:42:40 AM UTC 24 |
Sep 24 10:45:09 AM UTC 24 |
2764517464 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.297245999 |
|
|
Sep 24 10:44:04 AM UTC 24 |
Sep 24 10:45:15 AM UTC 24 |
1191867218 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.2958509944 |
|
|
Sep 24 10:28:01 AM UTC 24 |
Sep 24 10:45:39 AM UTC 24 |
16216277013 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_smoke.1384130452 |
|
|
Sep 24 10:45:06 AM UTC 24 |
Sep 24 10:45:39 AM UTC 24 |
1692733108 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.1695247447 |
|
|
Sep 24 10:43:52 AM UTC 24 |
Sep 24 10:45:58 AM UTC 24 |
6620644702 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access.1441054329 |
|
|
Sep 24 10:45:40 AM UTC 24 |
Sep 24 10:46:00 AM UTC 24 |
7089967848 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.1015242362 |
|
|
Sep 24 10:41:53 AM UTC 24 |
Sep 24 10:46:12 AM UTC 24 |
17566882006 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_regwen.1586617380 |
|
|
Sep 24 10:41:20 AM UTC 24 |
Sep 24 10:46:18 AM UTC 24 |
8211951610 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_bijection.1137037384 |
|
|
Sep 24 10:38:53 AM UTC 24 |
Sep 24 10:46:32 AM UTC 24 |
14061882005 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.3522689293 |
|
|
Sep 24 10:34:14 AM UTC 24 |
Sep 24 10:46:50 AM UTC 24 |
19252130703 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.1675267721 |
|
|
Sep 24 10:41:40 AM UTC 24 |
Sep 24 10:46:54 AM UTC 24 |
29972378147 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.3392851961 |
|
|
Sep 24 10:46:54 AM UTC 24 |
Sep 24 10:47:00 AM UTC 24 |
2789839329 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.1851476704 |
|
|
Sep 24 10:41:22 AM UTC 24 |
Sep 24 10:47:12 AM UTC 24 |
21010006429 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.2110050653 |
|
|
Sep 24 10:45:59 AM UTC 24 |
Sep 24 10:47:39 AM UTC 24 |
3048854112 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.1974192979 |
|
|
Sep 24 10:46:01 AM UTC 24 |
Sep 24 10:47:41 AM UTC 24 |
2866087698 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_regwen.770335864 |
|
|
Sep 24 10:46:51 AM UTC 24 |
Sep 24 10:47:52 AM UTC 24 |
10399339934 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.1800079227 |
|
|
Sep 24 10:46:13 AM UTC 24 |
Sep 24 10:47:52 AM UTC 24 |
11493328462 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_alert_test.2593587043 |
|
|
Sep 24 10:47:52 AM UTC 24 |
Sep 24 10:47:54 AM UTC 24 |
15765600 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.1618076273 |
|
|
Sep 24 10:45:06 AM UTC 24 |
Sep 24 10:48:08 AM UTC 24 |
30570303619 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_executable.3236499773 |
|
|
Sep 24 10:41:15 AM UTC 24 |
Sep 24 10:48:32 AM UTC 24 |
4675094652 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.3787768753 |
|
|
Sep 24 10:47:14 AM UTC 24 |
Sep 24 10:48:34 AM UTC 24 |
971085743 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_bijection.3805602826 |
|
|
Sep 24 10:30:02 AM UTC 24 |
Sep 24 10:48:35 AM UTC 24 |
61515125185 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.147608721 |
|
|
Sep 24 10:47:40 AM UTC 24 |
Sep 24 10:48:42 AM UTC 24 |
5490008307 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_bijection.352050749 |
|
|
Sep 24 10:02:44 AM UTC 24 |
Sep 24 10:48:45 AM UTC 24 |
165341532236 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access.3484215107 |
|
|
Sep 24 10:48:35 AM UTC 24 |
Sep 24 10:49:05 AM UTC 24 |
1181705902 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_smoke.4220555719 |
|
|
Sep 24 10:47:53 AM UTC 24 |
Sep 24 10:49:28 AM UTC 24 |
1644870165 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.2120780932 |
|
|
Sep 24 10:43:52 AM UTC 24 |
Sep 24 10:49:39 AM UTC 24 |
14536197023 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_bijection.2051974542 |
|
|
Sep 24 10:06:07 AM UTC 24 |
Sep 24 10:49:58 AM UTC 24 |
137946226890 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.3956703732 |
|
|
Sep 24 10:48:45 AM UTC 24 |
Sep 24 10:50:01 AM UTC 24 |
779948514 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.4183392214 |
|
|
Sep 24 10:49:06 AM UTC 24 |
Sep 24 10:50:02 AM UTC 24 |
8324885085 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.3559464206 |
|
|
Sep 24 10:45:16 AM UTC 24 |
Sep 24 10:50:09 AM UTC 24 |
9953819261 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.538864631 |
|
|
Sep 24 10:50:02 AM UTC 24 |
Sep 24 10:50:09 AM UTC 24 |
353536644 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.4050861642 |
|
|
Sep 24 10:48:43 AM UTC 24 |
Sep 24 10:50:19 AM UTC 24 |
15048798575 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.336513764 |
|
|
Sep 24 10:42:17 AM UTC 24 |
Sep 24 10:50:23 AM UTC 24 |
6898264754 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_alert_test.2643411351 |
|
|
Sep 24 10:50:24 AM UTC 24 |
Sep 24 10:50:26 AM UTC 24 |
34775044 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.2717576012 |
|
|
Sep 24 10:47:01 AM UTC 24 |
Sep 24 10:50:29 AM UTC 24 |
41428405279 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_smoke.1047588524 |
|
|
Sep 24 10:50:27 AM UTC 24 |
Sep 24 10:51:02 AM UTC 24 |
14521299885 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.3068762462 |
|
|
Sep 24 10:47:55 AM UTC 24 |
Sep 24 10:51:10 AM UTC 24 |
4867812944 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.206338740 |
|
|
Sep 24 10:50:09 AM UTC 24 |
Sep 24 10:51:34 AM UTC 24 |
10759434554 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access.1870966517 |
|
|
Sep 24 10:51:35 AM UTC 24 |
Sep 24 10:51:59 AM UTC 24 |
1467101320 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.54494246 |
|
|
Sep 24 10:50:11 AM UTC 24 |
Sep 24 10:53:36 AM UTC 24 |
9571192704 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all.2212288263 |
|
|
Sep 24 10:05:04 AM UTC 24 |
Sep 24 10:53:37 AM UTC 24 |
50710594583 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_bijection.3985507530 |
|
|
Sep 24 10:41:52 AM UTC 24 |
Sep 24 10:53:47 AM UTC 24 |
55739663077 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_bijection.1331803284 |
|
|
Sep 24 10:14:28 AM UTC 24 |
Sep 24 10:53:53 AM UTC 24 |
32140228610 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.363733372 |
|
|
Sep 24 10:53:36 AM UTC 24 |
Sep 24 10:54:20 AM UTC 24 |
718007352 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.634534353 |
|
|
Sep 24 10:53:38 AM UTC 24 |
Sep 24 10:54:24 AM UTC 24 |
763491825 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.2037828181 |
|
|
Sep 24 10:45:40 AM UTC 24 |
Sep 24 10:54:38 AM UTC 24 |
68351256985 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.895456247 |
|
|
Sep 24 10:48:33 AM UTC 24 |
Sep 24 10:54:39 AM UTC 24 |
6065533985 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.2821180767 |
|
|
Sep 24 10:54:38 AM UTC 24 |
Sep 24 10:54:47 AM UTC 24 |
4785339881 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_regwen.1874749353 |
|
|
Sep 24 10:36:21 AM UTC 24 |
Sep 24 10:54:49 AM UTC 24 |
6181351560 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.978148998 |
|
|
Sep 24 10:53:49 AM UTC 24 |
Sep 24 10:54:55 AM UTC 24 |
25812232084 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.3288977007 |
|
|
Sep 24 10:50:03 AM UTC 24 |
Sep 24 10:56:19 AM UTC 24 |
15442761991 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_alert_test.962921930 |
|
|
Sep 24 10:56:20 AM UTC 24 |
Sep 24 10:56:22 AM UTC 24 |
142340664 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_smoke.3953055189 |
|
|
Sep 24 10:56:23 AM UTC 24 |
Sep 24 10:56:35 AM UTC 24 |
728249233 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.459027745 |
|
|
Sep 24 10:54:51 AM UTC 24 |
Sep 24 10:56:48 AM UTC 24 |
28069031014 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.252687277 |
|
|
Sep 24 10:50:30 AM UTC 24 |
Sep 24 10:57:12 AM UTC 24 |
3874917409 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.1449430328 |
|
|
Sep 24 10:54:48 AM UTC 24 |
Sep 24 10:57:22 AM UTC 24 |
5242057200 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_bijection.1211783819 |
|
|
Sep 24 10:34:20 AM UTC 24 |
Sep 24 10:57:27 AM UTC 24 |
20027218155 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_regwen.908624578 |
|
|
Sep 24 10:54:25 AM UTC 24 |
Sep 24 10:57:42 AM UTC 24 |
10084183620 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access.3558126448 |
|
|
Sep 24 10:57:23 AM UTC 24 |
Sep 24 10:57:43 AM UTC 24 |
1685584583 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_executable.2854270155 |
|
|
Sep 24 10:33:11 AM UTC 24 |
Sep 24 10:57:48 AM UTC 24 |
24488543090 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.1224303819 |
|
|
Sep 24 10:54:40 AM UTC 24 |
Sep 24 10:57:54 AM UTC 24 |
7051570400 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.2236188715 |
|
|
Sep 24 10:57:44 AM UTC 24 |
Sep 24 10:57:55 AM UTC 24 |
2778381467 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.4214930732 |
|
|
Sep 24 10:57:42 AM UTC 24 |
Sep 24 10:57:56 AM UTC 24 |
682147529 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_executable.1908551979 |
|
|
Sep 24 10:42:59 AM UTC 24 |
Sep 24 10:58:42 AM UTC 24 |
62635797605 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.3901156666 |
|
|
Sep 24 10:58:43 AM UTC 24 |
Sep 24 10:58:51 AM UTC 24 |
1612812435 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.1794870264 |
|
|
Sep 24 10:48:36 AM UTC 24 |
Sep 24 10:58:59 AM UTC 24 |
18810753813 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.476485194 |
|
|
Sep 24 10:52:00 AM UTC 24 |
Sep 24 10:59:04 AM UTC 24 |
15892224363 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all.993877009 |
|
|
Sep 24 10:08:28 AM UTC 24 |
Sep 24 10:59:24 AM UTC 24 |
101456152647 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.1219777975 |
|
|
Sep 24 10:38:16 AM UTC 24 |
Sep 24 10:59:26 AM UTC 24 |
17425243631 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.1809362177 |
|
|
Sep 24 10:51:11 AM UTC 24 |
Sep 24 10:59:27 AM UTC 24 |
9353472427 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_alert_test.87290761 |
|
|
Sep 24 10:59:27 AM UTC 24 |
Sep 24 10:59:29 AM UTC 24 |
56403840 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_smoke.1813021877 |
|
|
Sep 24 10:59:28 AM UTC 24 |
Sep 24 10:59:38 AM UTC 24 |
701941520 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.3410013836 |
|
|
Sep 24 10:57:49 AM UTC 24 |
Sep 24 10:59:47 AM UTC 24 |
51619823213 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_smoke.947067184 |
|
|
Sep 24 11:05:59 AM UTC 24 |
Sep 24 11:06:13 AM UTC 24 |
743115336 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.3453190740 |
|
|
Sep 24 10:41:15 AM UTC 24 |
Sep 24 10:59:48 AM UTC 24 |
56906557305 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_bijection.1647863982 |
|
|
Sep 24 10:26:00 AM UTC 24 |
Sep 24 10:59:50 AM UTC 24 |
200953808679 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access.2260073895 |
|
|
Sep 24 10:59:50 AM UTC 24 |
Sep 24 11:00:04 AM UTC 24 |
649698381 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_regwen.3312828507 |
|
|
Sep 24 10:43:39 AM UTC 24 |
Sep 24 11:00:18 AM UTC 24 |
67268368640 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.487149557 |
|
|
Sep 24 11:00:07 AM UTC 24 |
Sep 24 11:00:21 AM UTC 24 |
9999153301 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.541754733 |
|
|
Sep 24 11:00:18 AM UTC 24 |
Sep 24 11:00:29 AM UTC 24 |
1373576541 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.317052309 |
|
|
Sep 24 10:59:06 AM UTC 24 |
Sep 24 11:00:48 AM UTC 24 |
4908553662 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_bijection.3926623893 |
|
|
Sep 24 10:22:28 AM UTC 24 |
Sep 24 11:00:54 AM UTC 24 |
31112850653 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.4158759289 |
|
|
Sep 24 10:59:00 AM UTC 24 |
Sep 24 11:01:10 AM UTC 24 |
6147856975 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.2807612459 |
|
|
Sep 24 11:01:11 AM UTC 24 |
Sep 24 11:01:17 AM UTC 24 |
677279504 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.4031489332 |
|
|
Sep 24 11:00:22 AM UTC 24 |
Sep 24 11:01:32 AM UTC 24 |
14061104934 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.1335280708 |
|
|
Sep 24 10:57:13 AM UTC 24 |
Sep 24 11:02:09 AM UTC 24 |
4781010676 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.1012122144 |
|
|
Sep 24 10:57:28 AM UTC 24 |
Sep 24 11:02:24 AM UTC 24 |
16593094340 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.2224311996 |
|
|
Sep 24 10:59:48 AM UTC 24 |
Sep 24 11:02:25 AM UTC 24 |
3152105642 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_alert_test.3834778675 |
|
|
Sep 24 11:02:26 AM UTC 24 |
Sep 24 11:02:28 AM UTC 24 |
17855681 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.2947146055 |
|
|
Sep 24 10:58:51 AM UTC 24 |
Sep 24 11:02:28 AM UTC 24 |
44969817413 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.3403787461 |
|
|
Sep 24 11:02:10 AM UTC 24 |
Sep 24 11:02:44 AM UTC 24 |
789462804 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.757434603 |
|
|
Sep 24 10:53:54 AM UTC 24 |
Sep 24 11:02:46 AM UTC 24 |
51989432899 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_smoke.1028403715 |
|
|
Sep 24 11:02:29 AM UTC 24 |
Sep 24 11:02:49 AM UTC 24 |
794372887 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.3744252751 |
|
|
Sep 24 11:01:33 AM UTC 24 |
Sep 24 11:02:59 AM UTC 24 |
6262047768 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access.3138187830 |
|
|
Sep 24 11:02:49 AM UTC 24 |
Sep 24 11:03:17 AM UTC 24 |
603003241 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.3391440886 |
|
|
Sep 24 11:01:18 AM UTC 24 |
Sep 24 11:03:48 AM UTC 24 |
7897131936 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_regwen.2853820482 |
|
|
Sep 24 10:57:57 AM UTC 24 |
Sep 24 11:03:56 AM UTC 24 |
2746861295 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.1458298823 |
|
|
Sep 24 10:46:19 AM UTC 24 |
Sep 24 11:03:57 AM UTC 24 |
13599931819 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.2502463069 |
|
|
Sep 24 11:03:57 AM UTC 24 |
Sep 24 11:04:08 AM UTC 24 |
759791026 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_executable.2366008231 |
|
|
Sep 24 10:46:33 AM UTC 24 |
Sep 24 11:04:10 AM UTC 24 |
103835613013 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_executable.1070929634 |
|
|
Sep 24 10:49:41 AM UTC 24 |
Sep 24 11:04:18 AM UTC 24 |
31415470887 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.1277294403 |
|
|
Sep 24 11:03:18 AM UTC 24 |
Sep 24 11:04:20 AM UTC 24 |
2940746932 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.4232239122 |
|
|
Sep 24 11:04:19 AM UTC 24 |
Sep 24 11:04:27 AM UTC 24 |
361434508 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.2810507734 |
|
|
Sep 24 11:03:49 AM UTC 24 |
Sep 24 11:05:33 AM UTC 24 |
3241708586 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_regwen.2084230493 |
|
|
Sep 24 10:49:59 AM UTC 24 |
Sep 24 11:05:41 AM UTC 24 |
64194044990 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.2388524315 |
|
|
Sep 24 10:59:51 AM UTC 24 |
Sep 24 11:05:55 AM UTC 24 |
116833500060 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_alert_test.2843087252 |
|
|
Sep 24 11:05:56 AM UTC 24 |
Sep 24 11:05:58 AM UTC 24 |
15948131 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.880084804 |
|
|
Sep 24 11:04:28 AM UTC 24 |
Sep 24 11:06:04 AM UTC 24 |
2877776415 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_regwen.3584887245 |
|
|
Sep 24 11:04:11 AM UTC 24 |
Sep 24 11:06:20 AM UTC 24 |
6647831383 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.2013493222 |
|
|
Sep 24 11:05:34 AM UTC 24 |
Sep 24 11:06:26 AM UTC 24 |
5150695058 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.1058211021 |
|
|
Sep 24 11:03:58 AM UTC 24 |
Sep 24 11:06:43 AM UTC 24 |
7574208273 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access.3587526580 |
|
|
Sep 24 11:06:26 AM UTC 24 |
Sep 24 11:06:47 AM UTC 24 |
4939290580 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.2038697739 |
|
|
Sep 24 10:49:29 AM UTC 24 |
Sep 24 11:07:16 AM UTC 24 |
56932766323 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.2173036311 |
|
|
Sep 24 11:07:17 AM UTC 24 |
Sep 24 11:07:33 AM UTC 24 |
2689850326 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_executable.604028096 |
|
|
Sep 24 10:54:21 AM UTC 24 |
Sep 24 11:07:38 AM UTC 24 |
21337382863 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_executable.3524756679 |
|
|
Sep 24 11:00:50 AM UTC 24 |
Sep 24 11:08:05 AM UTC 24 |
39101324967 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_executable.860512840 |
|
|
Sep 24 10:57:56 AM UTC 24 |
Sep 24 11:08:16 AM UTC 24 |
16435725121 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.2812460771 |
|
|
Sep 24 11:06:48 AM UTC 24 |
Sep 24 11:08:18 AM UTC 24 |
773168214 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.2549952014 |
|
|
Sep 24 11:08:20 AM UTC 24 |
Sep 24 11:08:27 AM UTC 24 |
721892479 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all.421770282 |
|
|
Sep 24 09:56:03 AM UTC 24 |
Sep 24 11:09:57 AM UTC 24 |
305166182114 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.1223889292 |
|
|
Sep 24 11:02:46 AM UTC 24 |
Sep 24 11:10:05 AM UTC 24 |
5400272976 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.335285126 |
|
|
Sep 24 11:07:34 AM UTC 24 |
Sep 24 11:10:06 AM UTC 24 |
14527746176 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.4139691232 |
|
|
Sep 24 11:02:59 AM UTC 24 |
Sep 24 11:10:16 AM UTC 24 |
14456386402 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_alert_test.3422340735 |
|
|
Sep 24 11:10:17 AM UTC 24 |
Sep 24 11:10:19 AM UTC 24 |
42821513 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.339570060 |
|
|
Sep 24 11:10:06 AM UTC 24 |
Sep 24 11:10:22 AM UTC 24 |
953355625 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_smoke.3203535261 |
|
|
Sep 24 11:10:20 AM UTC 24 |
Sep 24 11:10:44 AM UTC 24 |
742915385 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.382004253 |
|
|
Sep 24 11:09:58 AM UTC 24 |
Sep 24 11:11:14 AM UTC 24 |
2435203616 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.2964733135 |
|
|
Sep 24 11:04:21 AM UTC 24 |
Sep 24 11:11:20 AM UTC 24 |
86069029759 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access.668489636 |
|
|
Sep 24 11:11:21 AM UTC 24 |
Sep 24 11:11:50 AM UTC 24 |
2465558393 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.1663797125 |
|
|
Sep 24 11:06:43 AM UTC 24 |
Sep 24 11:12:17 AM UTC 24 |
24766403319 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.4250759458 |
|
|
Sep 24 11:12:18 AM UTC 24 |
Sep 24 11:13:11 AM UTC 24 |
743219604 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_executable.2142666026 |
|
|
Sep 24 11:04:08 AM UTC 24 |
Sep 24 11:13:42 AM UTC 24 |
4187367802 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_regwen.3868737978 |
|
|
Sep 24 11:00:55 AM UTC 24 |
Sep 24 11:13:47 AM UTC 24 |
9994885411 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.3112963868 |
|
|
Sep 24 11:13:44 AM UTC 24 |
Sep 24 11:13:55 AM UTC 24 |
875327571 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.2272021848 |
|
|
Sep 24 11:06:21 AM UTC 24 |
Sep 24 11:14:15 AM UTC 24 |
4839882101 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.3119818656 |
|
|
Sep 24 10:59:30 AM UTC 24 |
Sep 24 11:14:25 AM UTC 24 |
12801425522 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.2837871678 |
|
|
Sep 24 11:13:12 AM UTC 24 |
Sep 24 11:14:26 AM UTC 24 |
779165076 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.1261480258 |
|
|
Sep 24 11:14:26 AM UTC 24 |
Sep 24 11:14:32 AM UTC 24 |
344761483 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.3060002819 |
|
|
Sep 24 11:07:39 AM UTC 24 |
Sep 24 11:14:48 AM UTC 24 |
10323102371 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.832054817 |
|
|
Sep 24 11:14:49 AM UTC 24 |
Sep 24 11:15:22 AM UTC 24 |
6149998393 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_bijection.3909611449 |
|
|
Sep 24 10:48:09 AM UTC 24 |
Sep 24 11:15:23 AM UTC 24 |
21282993624 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_alert_test.234453465 |
|
|
Sep 24 11:15:24 AM UTC 24 |
Sep 24 11:15:26 AM UTC 24 |
21055344 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_bijection.3851941193 |
|
|
Sep 24 11:02:44 AM UTC 24 |
Sep 24 11:15:32 AM UTC 24 |
41395188151 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.373296920 |
|
|
Sep 24 10:56:37 AM UTC 24 |
Sep 24 11:15:35 AM UTC 24 |
11652571977 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.2529540217 |
|
|
Sep 24 11:11:15 AM UTC 24 |
Sep 24 11:15:41 AM UTC 24 |
8114373694 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_smoke.1679248999 |
|
|
Sep 24 11:15:27 AM UTC 24 |
Sep 24 11:15:44 AM UTC 24 |
392983226 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.2780397265 |
|
|
Sep 24 10:57:55 AM UTC 24 |
Sep 24 11:15:46 AM UTC 24 |
157516061976 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.1471861271 |
|
|
Sep 24 11:08:28 AM UTC 24 |
Sep 24 11:15:47 AM UTC 24 |
13836520563 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_bijection.2141961399 |
|
|
Sep 24 10:56:50 AM UTC 24 |
Sep 24 11:15:55 AM UTC 24 |
137186893525 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.3396411474 |
|
|
Sep 24 11:15:48 AM UTC 24 |
Sep 24 11:16:00 AM UTC 24 |
675725398 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_executable.2221228165 |
|
|
Sep 24 11:08:05 AM UTC 24 |
Sep 24 11:16:05 AM UTC 24 |
7257147134 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.482095823 |
|
|
Sep 24 11:15:56 AM UTC 24 |
Sep 24 11:16:20 AM UTC 24 |
1484555227 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access.1657139123 |
|
|
Sep 24 11:15:46 AM UTC 24 |
Sep 24 11:16:37 AM UTC 24 |
2295122972 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.4143454390 |
|
|
Sep 24 11:06:05 AM UTC 24 |
Sep 24 11:16:50 AM UTC 24 |
82941098876 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.4065828536 |
|
|
Sep 24 11:16:51 AM UTC 24 |
Sep 24 11:16:58 AM UTC 24 |
680402484 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.665219927 |
|
|
Sep 24 11:16:00 AM UTC 24 |
Sep 24 11:17:46 AM UTC 24 |
8735977887 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.3765556287 |
|
|
Sep 24 11:11:52 AM UTC 24 |
Sep 24 11:18:03 AM UTC 24 |
22454966772 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.3539950720 |
|
|
Sep 24 11:00:30 AM UTC 24 |
Sep 24 11:18:11 AM UTC 24 |
25439655849 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.3851529744 |
|
|
Sep 24 11:18:04 AM UTC 24 |
Sep 24 11:18:19 AM UTC 24 |
4775109516 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_alert_test.4088455283 |
|
|
Sep 24 11:18:20 AM UTC 24 |
Sep 24 11:18:22 AM UTC 24 |
14981726 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.2334887925 |
|
|
Sep 24 11:14:33 AM UTC 24 |
Sep 24 11:18:27 AM UTC 24 |
30667627128 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.3665215626 |
|
|
Sep 24 11:02:29 AM UTC 24 |
Sep 24 11:18:38 AM UTC 24 |
67364388143 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_smoke.837603179 |
|
|
Sep 24 11:18:23 AM UTC 24 |
Sep 24 11:18:52 AM UTC 24 |
408128774 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_bijection.1339025096 |
|
|
Sep 24 10:45:10 AM UTC 24 |
Sep 24 11:19:07 AM UTC 24 |
153576485894 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all.432714595 |
|
|
Sep 24 09:59:51 AM UTC 24 |
Sep 24 11:19:11 AM UTC 24 |
250076734826 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_regwen.288180354 |
|
|
Sep 24 11:14:16 AM UTC 24 |
Sep 24 11:19:26 AM UTC 24 |
39818994661 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.2428994772 |
|
|
Sep 24 11:17:47 AM UTC 24 |
Sep 24 11:19:30 AM UTC 24 |
10541355887 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access.2940240694 |
|
|
Sep 24 11:19:07 AM UTC 24 |
Sep 24 11:20:01 AM UTC 24 |
1337821283 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_executable.764913998 |
|
|
Sep 24 11:13:57 AM UTC 24 |
Sep 24 11:20:05 AM UTC 24 |
30973711980 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.123876715 |
|
|
Sep 24 11:19:31 AM UTC 24 |
Sep 24 11:20:12 AM UTC 24 |
1448137044 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.322905114 |
|
|
Sep 24 11:13:48 AM UTC 24 |
Sep 24 11:20:17 AM UTC 24 |
27417779140 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.3019327297 |
|
|
Sep 24 11:10:23 AM UTC 24 |
Sep 24 11:20:32 AM UTC 24 |
5385911561 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.178747454 |
|
|
Sep 24 11:20:33 AM UTC 24 |
Sep 24 11:20:41 AM UTC 24 |
1410312233 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.3798491660 |
|
|
Sep 24 11:20:02 AM UTC 24 |
Sep 24 11:20:48 AM UTC 24 |
4639008114 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.3300997000 |
|
|
Sep 24 11:19:28 AM UTC 24 |
Sep 24 11:20:49 AM UTC 24 |
1701094745 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.3090797184 |
|
|
Sep 24 11:15:47 AM UTC 24 |
Sep 24 11:21:27 AM UTC 24 |
9411233110 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.3917794771 |
|
|
Sep 24 11:14:27 AM UTC 24 |
Sep 24 11:21:33 AM UTC 24 |
20681285696 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_alert_test.4109762361 |
|
|
Sep 24 11:21:33 AM UTC 24 |
Sep 24 11:21:36 AM UTC 24 |
38346025 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_executable.3691921061 |
|
|
Sep 24 11:16:21 AM UTC 24 |
Sep 24 11:21:49 AM UTC 24 |
27052055835 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_smoke.176638046 |
|
|
Sep 24 11:21:37 AM UTC 24 |
Sep 24 11:22:00 AM UTC 24 |
1963248931 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.4068598330 |
|
|
Sep 24 11:20:49 AM UTC 24 |
Sep 24 11:22:29 AM UTC 24 |
3850522473 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.411767862 |
|
|
Sep 24 11:20:50 AM UTC 24 |
Sep 24 11:22:51 AM UTC 24 |
12230741867 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.2717267910 |
|
|
Sep 24 11:15:41 AM UTC 24 |
Sep 24 11:23:04 AM UTC 24 |
11124925264 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.1099922326 |
|
|
Sep 24 11:20:05 AM UTC 24 |
Sep 24 11:23:17 AM UTC 24 |
4009226573 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access.2997998775 |
|
|
Sep 24 11:22:52 AM UTC 24 |
Sep 24 11:23:39 AM UTC 24 |
4936758857 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.2926990559 |
|
|
Sep 24 11:16:59 AM UTC 24 |
Sep 24 11:23:52 AM UTC 24 |
21121162950 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.2836503254 |
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|
Sep 24 11:23:17 AM UTC 24 |
Sep 24 11:24:01 AM UTC 24 |
739275073 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_executable.2309192442 |
|
|
Sep 24 11:20:12 AM UTC 24 |
Sep 24 11:24:03 AM UTC 24 |
19676874169 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.3501995047 |
|
|
Sep 24 11:20:42 AM UTC 24 |
Sep 24 11:24:07 AM UTC 24 |
13867765477 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all.3627525386 |
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|
Sep 24 10:02:29 AM UTC 24 |
Sep 24 11:24:49 AM UTC 24 |
406466676938 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.4214670017 |
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|
Sep 24 11:24:49 AM UTC 24 |
Sep 24 11:24:54 AM UTC 24 |
1351318229 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.3118380469 |
|
|
Sep 24 11:23:53 AM UTC 24 |
Sep 24 11:25:07 AM UTC 24 |
10715072175 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.3920215477 |
|
|
Sep 24 11:23:40 AM UTC 24 |
Sep 24 11:25:55 AM UTC 24 |
818964147 ps |