| T803 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.2662798787 |
|
|
Sep 24 12:06:14 PM UTC 24 |
Sep 24 12:11:03 PM UTC 24 |
11327299139 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_regwen.843423102 |
|
|
Sep 24 12:09:49 PM UTC 24 |
Sep 24 12:11:05 PM UTC 24 |
2039204825 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_executable.3762020570 |
|
|
Sep 24 11:57:12 AM UTC 24 |
Sep 24 12:11:05 PM UTC 24 |
6500922556 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_executable.4125416034 |
|
|
Sep 24 12:09:45 PM UTC 24 |
Sep 24 12:11:07 PM UTC 24 |
25890965057 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_executable.3309456984 |
|
|
Sep 24 12:04:16 PM UTC 24 |
Sep 24 12:11:20 PM UTC 24 |
78816606518 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all.1533034264 |
|
|
Sep 24 11:46:46 AM UTC 24 |
Sep 24 12:11:33 PM UTC 24 |
45933133234 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_smoke.1630830687 |
|
|
Sep 24 12:10:58 PM UTC 24 |
Sep 24 12:11:38 PM UTC 24 |
1091540837 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.1068530590 |
|
|
Sep 24 11:51:50 AM UTC 24 |
Sep 24 12:11:38 PM UTC 24 |
17315368907 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.1804485405 |
|
|
Sep 24 12:11:22 PM UTC 24 |
Sep 24 12:11:53 PM UTC 24 |
3018789555 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.88948192 |
|
|
Sep 24 12:11:35 PM UTC 24 |
Sep 24 12:12:00 PM UTC 24 |
2913358325 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.1504972559 |
|
|
Sep 24 12:05:40 PM UTC 24 |
Sep 24 12:12:01 PM UTC 24 |
5726294263 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.3005895856 |
|
|
Sep 24 12:10:06 PM UTC 24 |
Sep 24 12:12:08 PM UTC 24 |
2862829403 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.1149999708 |
|
|
Sep 24 12:12:02 PM UTC 24 |
Sep 24 12:12:08 PM UTC 24 |
361134676 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.2784570221 |
|
|
Sep 24 12:10:59 PM UTC 24 |
Sep 24 12:12:14 PM UTC 24 |
15480107431 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1779278837 |
|
|
Sep 24 12:12:15 PM UTC 24 |
Sep 24 12:12:26 PM UTC 24 |
455518512 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.2010078850 |
|
|
Sep 24 12:04:39 PM UTC 24 |
Sep 24 12:12:33 PM UTC 24 |
24651365682 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_regwen.545022085 |
|
|
Sep 24 12:07:11 PM UTC 24 |
Sep 24 12:12:34 PM UTC 24 |
4770332813 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_alert_test.2363268113 |
|
|
Sep 24 12:12:33 PM UTC 24 |
Sep 24 12:12:36 PM UTC 24 |
29412642 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.2122018057 |
|
|
Sep 24 11:50:27 AM UTC 24 |
Sep 24 12:12:37 PM UTC 24 |
22282401032 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.1059443169 |
|
|
Sep 24 11:58:11 AM UTC 24 |
Sep 24 12:12:43 PM UTC 24 |
9759177308 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access.3268206626 |
|
|
Sep 24 12:11:07 PM UTC 24 |
Sep 24 12:13:05 PM UTC 24 |
3999000645 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.3671796255 |
|
|
Sep 24 12:03:45 PM UTC 24 |
Sep 24 12:13:06 PM UTC 24 |
36480191371 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_smoke.1033518101 |
|
|
Sep 24 12:12:34 PM UTC 24 |
Sep 24 12:13:26 PM UTC 24 |
19842485305 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.3801255795 |
|
|
Sep 24 12:11:38 PM UTC 24 |
Sep 24 12:13:26 PM UTC 24 |
49273173050 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.906224338 |
|
|
Sep 24 12:12:09 PM UTC 24 |
Sep 24 12:13:33 PM UTC 24 |
5774160044 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access.21492967 |
|
|
Sep 24 12:13:06 PM UTC 24 |
Sep 24 12:13:43 PM UTC 24 |
3309071887 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.3247549577 |
|
|
Sep 24 12:07:33 PM UTC 24 |
Sep 24 12:13:43 PM UTC 24 |
21012225112 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.542804988 |
|
|
Sep 24 12:13:27 PM UTC 24 |
Sep 24 12:14:00 PM UTC 24 |
753671339 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all.2957955287 |
|
|
Sep 24 12:12:27 PM UTC 24 |
Sep 24 12:14:04 PM UTC 24 |
15645870475 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.1621677385 |
|
|
Sep 24 11:59:27 AM UTC 24 |
Sep 24 12:14:05 PM UTC 24 |
87537567868 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all.1195240279 |
|
|
Sep 24 11:10:07 AM UTC 24 |
Sep 24 12:14:09 PM UTC 24 |
279417971084 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.2390560174 |
|
|
Sep 24 12:08:36 PM UTC 24 |
Sep 24 12:14:09 PM UTC 24 |
15056170730 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.4002253490 |
|
|
Sep 24 12:14:05 PM UTC 24 |
Sep 24 12:14:10 PM UTC 24 |
741833819 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3313956189 |
|
|
Sep 24 12:14:10 PM UTC 24 |
Sep 24 12:14:18 PM UTC 24 |
774530418 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_alert_test.3030524104 |
|
|
Sep 24 12:14:19 PM UTC 24 |
Sep 24 12:14:21 PM UTC 24 |
14032249 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.3103517396 |
|
|
Sep 24 12:13:27 PM UTC 24 |
Sep 24 12:14:24 PM UTC 24 |
1636349910 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.3145070306 |
|
|
Sep 24 12:00:37 PM UTC 24 |
Sep 24 12:14:53 PM UTC 24 |
46614654430 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.53569079 |
|
|
Sep 24 12:09:05 PM UTC 24 |
Sep 24 12:15:03 PM UTC 24 |
4154311890 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.1741456472 |
|
|
Sep 24 12:13:34 PM UTC 24 |
Sep 24 12:15:07 PM UTC 24 |
36239855833 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_smoke.489172821 |
|
|
Sep 24 12:14:22 PM UTC 24 |
Sep 24 12:15:11 PM UTC 24 |
4436221627 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.2312407251 |
|
|
Sep 24 12:11:07 PM UTC 24 |
Sep 24 12:15:27 PM UTC 24 |
37390348464 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.937939664 |
|
|
Sep 24 12:15:28 PM UTC 24 |
Sep 24 12:15:38 PM UTC 24 |
698489254 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_executable.2744837309 |
|
|
Sep 24 12:02:17 PM UTC 24 |
Sep 24 12:15:44 PM UTC 24 |
43658102080 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.2454219703 |
|
|
Sep 24 12:15:39 PM UTC 24 |
Sep 24 12:15:55 PM UTC 24 |
2812551995 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.1017151066 |
|
|
Sep 24 12:09:59 PM UTC 24 |
Sep 24 12:15:58 PM UTC 24 |
42217183256 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_bijection.2551801892 |
|
|
Sep 24 11:35:01 AM UTC 24 |
Sep 24 12:16:12 PM UTC 24 |
100696581583 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access.4217177096 |
|
|
Sep 24 12:15:08 PM UTC 24 |
Sep 24 12:16:25 PM UTC 24 |
3354453144 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.147094315 |
|
|
Sep 24 12:16:26 PM UTC 24 |
Sep 24 12:16:32 PM UTC 24 |
668165413 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all.1702926509 |
|
|
Sep 24 10:33:35 AM UTC 24 |
Sep 24 12:16:53 PM UTC 24 |
108605724876 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.2364085211 |
|
|
Sep 24 12:14:10 PM UTC 24 |
Sep 24 12:17:17 PM UTC 24 |
16356003678 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.3822403876 |
|
|
Sep 24 12:15:45 PM UTC 24 |
Sep 24 12:17:19 PM UTC 24 |
59875288158 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.316829543 |
|
|
Sep 24 12:12:45 PM UTC 24 |
Sep 24 12:17:28 PM UTC 24 |
32005622631 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_alert_test.2167954670 |
|
|
Sep 24 12:17:29 PM UTC 24 |
Sep 24 12:17:32 PM UTC 24 |
39438801 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_bijection.693247953 |
|
|
Sep 24 11:53:41 AM UTC 24 |
Sep 24 12:17:35 PM UTC 24 |
115418535015 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.3169744609 |
|
|
Sep 24 12:15:04 PM UTC 24 |
Sep 24 12:17:39 PM UTC 24 |
23395826356 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_smoke.3182065545 |
|
|
Sep 24 12:17:32 PM UTC 24 |
Sep 24 12:17:49 PM UTC 24 |
500783310 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_executable.517172345 |
|
|
Sep 24 12:07:02 PM UTC 24 |
Sep 24 12:18:13 PM UTC 24 |
8966958572 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.1830103203 |
|
|
Sep 24 12:11:06 PM UTC 24 |
Sep 24 12:18:40 PM UTC 24 |
10186151393 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3063110757 |
|
|
Sep 24 12:17:18 PM UTC 24 |
Sep 24 12:18:47 PM UTC 24 |
4896218802 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_bijection.19670961 |
|
|
Sep 24 12:00:47 PM UTC 24 |
Sep 24 12:19:05 PM UTC 24 |
205745530291 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.2020253040 |
|
|
Sep 24 12:19:05 PM UTC 24 |
Sep 24 12:19:20 PM UTC 24 |
3234069371 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.3594217974 |
|
|
Sep 24 12:12:09 PM UTC 24 |
Sep 24 12:19:20 PM UTC 24 |
86134358848 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access.2019618941 |
|
|
Sep 24 12:18:14 PM UTC 24 |
Sep 24 12:19:26 PM UTC 24 |
996583497 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.4006058217 |
|
|
Sep 24 12:16:32 PM UTC 24 |
Sep 24 12:19:26 PM UTC 24 |
23887194325 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_regwen.181430799 |
|
|
Sep 24 11:54:31 AM UTC 24 |
Sep 24 12:19:27 PM UTC 24 |
142463586320 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.2301279176 |
|
|
Sep 24 12:19:28 PM UTC 24 |
Sep 24 12:19:36 PM UTC 24 |
1353486521 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.2371766892 |
|
|
Sep 24 12:18:48 PM UTC 24 |
Sep 24 12:19:39 PM UTC 24 |
1448281621 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.3985927874 |
|
|
Sep 24 12:13:44 PM UTC 24 |
Sep 24 12:19:45 PM UTC 24 |
6579484833 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.149231287 |
|
|
Sep 24 12:14:06 PM UTC 24 |
Sep 24 12:19:49 PM UTC 24 |
81540388077 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.4216015592 |
|
|
Sep 24 12:08:06 PM UTC 24 |
Sep 24 12:19:58 PM UTC 24 |
26767941623 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_alert_test.631225283 |
|
|
Sep 24 12:19:59 PM UTC 24 |
Sep 24 12:20:01 PM UTC 24 |
73395340 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.2533680248 |
|
|
Sep 24 12:19:20 PM UTC 24 |
Sep 24 12:20:01 PM UTC 24 |
5777411689 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_bijection.3508557486 |
|
|
Sep 24 12:03:20 PM UTC 24 |
Sep 24 12:20:06 PM UTC 24 |
15384255783 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1768998495 |
|
|
Sep 24 12:19:46 PM UTC 24 |
Sep 24 12:20:14 PM UTC 24 |
788955333 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.3763384109 |
|
|
Sep 24 12:02:15 PM UTC 24 |
Sep 24 12:20:32 PM UTC 24 |
36614747967 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.2147765403 |
|
|
Sep 24 12:16:53 PM UTC 24 |
Sep 24 12:20:36 PM UTC 24 |
25843039319 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_smoke.3489228241 |
|
|
Sep 24 12:20:02 PM UTC 24 |
Sep 24 12:20:40 PM UTC 24 |
5740268623 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access.89096255 |
|
|
Sep 24 12:20:34 PM UTC 24 |
Sep 24 12:20:46 PM UTC 24 |
847426789 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.1778227334 |
|
|
Sep 24 12:20:47 PM UTC 24 |
Sep 24 12:20:59 PM UTC 24 |
2795826044 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.3754744954 |
|
|
Sep 24 12:15:12 PM UTC 24 |
Sep 24 12:21:01 PM UTC 24 |
13502180898 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_executable.3680180535 |
|
|
Sep 24 11:59:34 AM UTC 24 |
Sep 24 12:21:07 PM UTC 24 |
74538357991 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.1603964769 |
|
|
Sep 24 12:20:02 PM UTC 24 |
Sep 24 12:21:47 PM UTC 24 |
12080588652 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.2471081936 |
|
|
Sep 24 12:20:41 PM UTC 24 |
Sep 24 12:22:11 PM UTC 24 |
776096998 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_regwen.3994706965 |
|
|
Sep 24 12:02:20 PM UTC 24 |
Sep 24 12:22:15 PM UTC 24 |
15287591734 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.554450831 |
|
|
Sep 24 12:22:13 PM UTC 24 |
Sep 24 12:22:20 PM UTC 24 |
679609387 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.140373898 |
|
|
Sep 24 12:19:40 PM UTC 24 |
Sep 24 12:22:25 PM UTC 24 |
21424278837 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_executable.503836597 |
|
|
Sep 24 12:11:55 PM UTC 24 |
Sep 24 12:22:31 PM UTC 24 |
5061793817 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_executable.3373407126 |
|
|
Sep 24 12:13:44 PM UTC 24 |
Sep 24 12:22:57 PM UTC 24 |
8737700440 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_alert_test.3803571247 |
|
|
Sep 24 12:22:58 PM UTC 24 |
Sep 24 12:23:00 PM UTC 24 |
12701176 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.947988624 |
|
|
Sep 24 12:22:26 PM UTC 24 |
Sep 24 12:23:00 PM UTC 24 |
2359421343 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.3796810648 |
|
|
Sep 24 12:20:59 PM UTC 24 |
Sep 24 12:23:15 PM UTC 24 |
15311992146 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.691601435 |
|
|
Sep 24 12:13:07 PM UTC 24 |
Sep 24 12:23:20 PM UTC 24 |
51250945347 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.3463761855 |
|
|
Sep 24 12:19:37 PM UTC 24 |
Sep 24 12:23:32 PM UTC 24 |
25609148469 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_regwen.339740026 |
|
|
Sep 24 12:14:01 PM UTC 24 |
Sep 24 12:23:53 PM UTC 24 |
11362825078 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.703250739 |
|
|
Sep 24 12:18:42 PM UTC 24 |
Sep 24 12:24:12 PM UTC 24 |
4188559097 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.2754994965 |
|
|
Sep 24 12:15:56 PM UTC 24 |
Sep 24 12:24:27 PM UTC 24 |
75831611655 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.508740302 |
|
|
Sep 24 12:17:50 PM UTC 24 |
Sep 24 12:24:43 PM UTC 24 |
9846218198 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.265392427 |
|
|
Sep 24 12:22:16 PM UTC 24 |
Sep 24 12:24:48 PM UTC 24 |
10962425052 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.3368944984 |
|
|
Sep 24 12:22:21 PM UTC 24 |
Sep 24 12:24:58 PM UTC 24 |
1639553026 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_regwen.2719032961 |
|
|
Sep 24 12:04:19 PM UTC 24 |
Sep 24 12:25:00 PM UTC 24 |
6528424512 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.2713516444 |
|
|
Sep 24 12:09:34 PM UTC 24 |
Sep 24 12:25:10 PM UTC 24 |
8573698480 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_bijection.2609778468 |
|
|
Sep 24 12:05:40 PM UTC 24 |
Sep 24 12:25:48 PM UTC 24 |
660424315204 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_bijection.1543715910 |
|
|
Sep 24 11:55:50 AM UTC 24 |
Sep 24 12:26:06 PM UTC 24 |
164480664502 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.2814439162 |
|
|
Sep 24 12:20:15 PM UTC 24 |
Sep 24 12:26:21 PM UTC 24 |
4848373620 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.29826773 |
|
|
Sep 24 12:12:37 PM UTC 24 |
Sep 24 12:26:40 PM UTC 24 |
18369031796 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_executable.1322025866 |
|
|
Sep 24 12:15:58 PM UTC 24 |
Sep 24 12:26:57 PM UTC 24 |
37314810357 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_bijection.1041709770 |
|
|
Sep 24 11:58:11 AM UTC 24 |
Sep 24 12:27:59 PM UTC 24 |
138425075216 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.616610145 |
|
|
Sep 24 12:06:48 PM UTC 24 |
Sep 24 12:28:12 PM UTC 24 |
90389690351 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_bijection.3702992431 |
|
|
Sep 24 11:50:01 AM UTC 24 |
Sep 24 12:28:15 PM UTC 24 |
122008548115 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.2589484583 |
|
|
Sep 24 12:20:37 PM UTC 24 |
Sep 24 12:28:16 PM UTC 24 |
21166796115 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_bijection.1709185409 |
|
|
Sep 24 11:49:23 AM UTC 24 |
Sep 24 12:28:25 PM UTC 24 |
464337535839 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all.3257472699 |
|
|
Sep 24 11:43:03 AM UTC 24 |
Sep 24 12:28:31 PM UTC 24 |
237679496287 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all.3757034093 |
|
|
Sep 24 10:25:45 AM UTC 24 |
Sep 24 12:28:44 PM UTC 24 |
1809536867959 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_regwen.3152387659 |
|
|
Sep 24 12:16:13 PM UTC 24 |
Sep 24 12:29:17 PM UTC 24 |
9155910945 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_bijection.1950483574 |
|
|
Sep 24 12:11:04 PM UTC 24 |
Sep 24 12:29:48 PM UTC 24 |
56013405982 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_bijection.2873761328 |
|
|
Sep 24 11:51:52 AM UTC 24 |
Sep 24 12:29:59 PM UTC 24 |
91137071642 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_regwen.1896482987 |
|
|
Sep 24 12:12:02 PM UTC 24 |
Sep 24 12:30:06 PM UTC 24 |
3256097830 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_bijection.1882884574 |
|
|
Sep 24 11:47:09 AM UTC 24 |
Sep 24 12:31:47 PM UTC 24 |
101250412230 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.2831829897 |
|
|
Sep 24 12:19:22 PM UTC 24 |
Sep 24 12:32:34 PM UTC 24 |
7735201504 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_bijection.475833848 |
|
|
Sep 24 12:12:38 PM UTC 24 |
Sep 24 12:33:09 PM UTC 24 |
105957940108 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.1267147622 |
|
|
Sep 24 12:11:39 PM UTC 24 |
Sep 24 12:33:24 PM UTC 24 |
63257188508 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_executable.1219238327 |
|
|
Sep 24 12:21:08 PM UTC 24 |
Sep 24 12:34:34 PM UTC 24 |
6872502601 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_bijection.3498678597 |
|
|
Sep 24 12:17:40 PM UTC 24 |
Sep 24 12:35:12 PM UTC 24 |
14010869986 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all.1611978802 |
|
|
Sep 24 12:07:53 PM UTC 24 |
Sep 24 12:35:17 PM UTC 24 |
111976541294 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_multiple_keys.3312458945 |
|
|
Sep 24 12:14:26 PM UTC 24 |
Sep 24 12:35:20 PM UTC 24 |
52482003746 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_regwen.2659735365 |
|
|
Sep 24 12:21:48 PM UTC 24 |
Sep 24 12:35:26 PM UTC 24 |
88302134558 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_all.2888433675 |
|
|
Sep 24 10:29:24 AM UTC 24 |
Sep 24 12:36:07 PM UTC 24 |
207810534896 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_regwen.599968951 |
|
|
Sep 24 12:19:27 PM UTC 24 |
Sep 24 12:36:14 PM UTC 24 |
13825467929 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.587228142 |
|
|
Sep 24 12:21:03 PM UTC 24 |
Sep 24 12:37:03 PM UTC 24 |
15630064705 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.2031022560 |
|
|
Sep 24 12:17:37 PM UTC 24 |
Sep 24 12:39:51 PM UTC 24 |
12006562416 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_executable.3408322160 |
|
|
Sep 24 12:19:27 PM UTC 24 |
Sep 24 12:40:09 PM UTC 24 |
29582110130 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all.2669540693 |
|
|
Sep 24 10:17:36 AM UTC 24 |
Sep 24 12:43:41 PM UTC 24 |
553722937305 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all.3103284365 |
|
|
Sep 24 11:26:08 AM UTC 24 |
Sep 24 12:44:54 PM UTC 24 |
933529757420 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_bijection.583961362 |
|
|
Sep 24 12:08:27 PM UTC 24 |
Sep 24 12:52:29 PM UTC 24 |
165044092799 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_bijection.2330163440 |
|
|
Sep 24 12:14:54 PM UTC 24 |
Sep 24 12:54:44 PM UTC 24 |
99676615227 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all.3585893793 |
|
|
Sep 24 11:55:33 AM UTC 24 |
Sep 24 12:54:52 PM UTC 24 |
204107989407 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all.3108345115 |
|
|
Sep 24 11:51:27 AM UTC 24 |
Sep 24 12:57:16 PM UTC 24 |
324397099483 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all.2691560912 |
|
|
Sep 24 11:49:59 AM UTC 24 |
Sep 24 12:57:51 PM UTC 24 |
494826736553 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_bijection.411687256 |
|
|
Sep 24 12:20:07 PM UTC 24 |
Sep 24 01:03:02 PM UTC 24 |
454210324112 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all.2649606912 |
|
|
Sep 24 12:10:44 PM UTC 24 |
Sep 24 01:03:42 PM UTC 24 |
443001689250 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all.4036424860 |
|
|
Sep 24 12:14:11 PM UTC 24 |
Sep 24 01:11:26 PM UTC 24 |
61095797190 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all.646477263 |
|
|
Sep 24 12:03:12 PM UTC 24 |
Sep 24 01:11:36 PM UTC 24 |
210608464497 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all.3073505254 |
|
|
Sep 24 11:18:13 AM UTC 24 |
Sep 24 01:15:50 PM UTC 24 |
720274317971 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all.2585768406 |
|
|
Sep 24 11:58:06 AM UTC 24 |
Sep 24 01:15:54 PM UTC 24 |
294532822336 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all.2303365872 |
|
|
Sep 24 12:19:49 PM UTC 24 |
Sep 24 01:18:40 PM UTC 24 |
126501956359 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all.3439848171 |
|
|
Sep 24 12:00:29 PM UTC 24 |
Sep 24 01:23:12 PM UTC 24 |
238154981496 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all.2867553957 |
|
|
Sep 24 12:17:20 PM UTC 24 |
Sep 24 01:23:15 PM UTC 24 |
61399246648 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all.1428774799 |
|
|
Sep 24 12:05:05 PM UTC 24 |
Sep 24 01:28:09 PM UTC 24 |
303306092214 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all.3465147825 |
|
|
Sep 24 11:02:25 AM UTC 24 |
Sep 24 01:29:57 PM UTC 24 |
185839844187 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all.1741591596 |
|
|
Sep 24 11:53:11 AM UTC 24 |
Sep 24 02:09:01 PM UTC 24 |
358937715548 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all.1828609873 |
|
|
Sep 24 11:49:10 AM UTC 24 |
Sep 24 02:18:18 PM UTC 24 |
395727021475 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all.2934907865 |
|
|
Sep 24 12:22:32 PM UTC 24 |
Sep 24 02:41:46 PM UTC 24 |
1309143348768 ps |
| T68 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2818040016 |
|
|
Sep 24 08:47:50 AM UTC 24 |
Sep 24 08:47:51 AM UTC 24 |
50908162 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.185977465 |
|
|
Sep 24 08:47:50 AM UTC 24 |
Sep 24 08:47:51 AM UTC 24 |
25960029 ps |
| T98 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3904548516 |
|
|
Sep 24 08:47:50 AM UTC 24 |
Sep 24 08:47:52 AM UTC 24 |
24553854 ps |
| T69 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3244358318 |
|
|
Sep 24 08:47:50 AM UTC 24 |
Sep 24 08:47:52 AM UTC 24 |
16182372 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2294335312 |
|
|
Sep 24 08:47:50 AM UTC 24 |
Sep 24 08:47:52 AM UTC 24 |
30349908 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.27433529 |
|
|
Sep 24 08:47:50 AM UTC 24 |
Sep 24 08:47:52 AM UTC 24 |
255179311 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2732894835 |
|
|
Sep 24 08:47:51 AM UTC 24 |
Sep 24 08:47:53 AM UTC 24 |
18101102 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.415237881 |
|
|
Sep 24 08:47:51 AM UTC 24 |
Sep 24 08:47:53 AM UTC 24 |
34046233 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1803127501 |
|
|
Sep 24 08:47:51 AM UTC 24 |
Sep 24 08:47:53 AM UTC 24 |
24689507 ps |
| T99 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3765465118 |
|
|
Sep 24 08:47:51 AM UTC 24 |
Sep 24 08:47:53 AM UTC 24 |
49071158 ps |
| T100 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2274012978 |
|
|
Sep 24 08:47:51 AM UTC 24 |
Sep 24 08:47:53 AM UTC 24 |
58291095 ps |
| T72 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3794801685 |
|
|
Sep 24 08:47:51 AM UTC 24 |
Sep 24 08:47:53 AM UTC 24 |
34652693 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2892919551 |
|
|
Sep 24 08:47:51 AM UTC 24 |
Sep 24 08:47:53 AM UTC 24 |
45451841 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2275075414 |
|
|
Sep 24 08:47:51 AM UTC 24 |
Sep 24 08:47:53 AM UTC 24 |
30054418 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3020721596 |
|
|
Sep 24 08:47:52 AM UTC 24 |
Sep 24 08:47:53 AM UTC 24 |
31428446 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.545412582 |
|
|
Sep 24 08:47:52 AM UTC 24 |
Sep 24 08:47:53 AM UTC 24 |
15054488 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1094989429 |
|
|
Sep 24 08:47:50 AM UTC 24 |
Sep 24 08:47:54 AM UTC 24 |
79290607 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1316950106 |
|
|
Sep 24 08:47:52 AM UTC 24 |
Sep 24 08:47:54 AM UTC 24 |
56218261 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3284468130 |
|
|
Sep 24 08:47:52 AM UTC 24 |
Sep 24 08:47:54 AM UTC 24 |
15450154 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.607660888 |
|
|
Sep 24 08:47:51 AM UTC 24 |
Sep 24 08:47:54 AM UTC 24 |
49049787 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.536732109 |
|
|
Sep 24 08:47:51 AM UTC 24 |
Sep 24 08:47:54 AM UTC 24 |
401305759 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.397541652 |
|
|
Sep 24 08:47:52 AM UTC 24 |
Sep 24 08:47:54 AM UTC 24 |
104523522 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1764155610 |
|
|
Sep 24 08:47:52 AM UTC 24 |
Sep 24 08:47:54 AM UTC 24 |
365165198 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1426883311 |
|
|
Sep 24 08:47:50 AM UTC 24 |
Sep 24 08:47:54 AM UTC 24 |
1355088137 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1796982278 |
|
|
Sep 24 08:47:55 AM UTC 24 |
Sep 24 08:48:00 AM UTC 24 |
254673588 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.6381717 |
|
|
Sep 24 08:47:51 AM UTC 24 |
Sep 24 08:47:54 AM UTC 24 |
330757734 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3523609556 |
|
|
Sep 24 08:47:58 AM UTC 24 |
Sep 24 08:48:02 AM UTC 24 |
484888503 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1313609589 |
|
|
Sep 24 08:47:51 AM UTC 24 |
Sep 24 08:47:55 AM UTC 24 |
155371978 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1653064225 |
|
|
Sep 24 08:47:53 AM UTC 24 |
Sep 24 08:47:55 AM UTC 24 |
22444886 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1581626159 |
|
|
Sep 24 08:47:53 AM UTC 24 |
Sep 24 08:47:55 AM UTC 24 |
16915117 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.894830187 |
|
|
Sep 24 08:47:51 AM UTC 24 |
Sep 24 08:47:55 AM UTC 24 |
107571161 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2008860717 |
|
|
Sep 24 08:47:53 AM UTC 24 |
Sep 24 08:47:55 AM UTC 24 |
13480222 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1181008129 |
|
|
Sep 24 08:47:53 AM UTC 24 |
Sep 24 08:47:55 AM UTC 24 |
66815094 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2572631888 |
|
|
Sep 24 08:47:53 AM UTC 24 |
Sep 24 08:47:55 AM UTC 24 |
14678991 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1961195378 |
|
|
Sep 24 08:47:54 AM UTC 24 |
Sep 24 08:47:55 AM UTC 24 |
49653189 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.649651885 |
|
|
Sep 24 08:47:53 AM UTC 24 |
Sep 24 08:47:56 AM UTC 24 |
71969280 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1545986968 |
|
|
Sep 24 08:47:53 AM UTC 24 |
Sep 24 08:47:56 AM UTC 24 |
185985980 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3730675596 |
|
|
Sep 24 08:47:52 AM UTC 24 |
Sep 24 08:47:56 AM UTC 24 |
288782611 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3420319556 |
|
|
Sep 24 08:47:53 AM UTC 24 |
Sep 24 08:47:56 AM UTC 24 |
353179057 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2952021163 |
|
|
Sep 24 08:47:53 AM UTC 24 |
Sep 24 08:47:56 AM UTC 24 |
536851621 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2997934642 |
|
|
Sep 24 08:47:52 AM UTC 24 |
Sep 24 08:47:56 AM UTC 24 |
558098303 ps |
| T104 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.542579433 |
|
|
Sep 24 08:47:55 AM UTC 24 |
Sep 24 08:47:57 AM UTC 24 |
36347313 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.4177722466 |
|
|
Sep 24 08:47:51 AM UTC 24 |
Sep 24 08:47:57 AM UTC 24 |
257429654 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.69053003 |
|
|
Sep 24 08:47:55 AM UTC 24 |
Sep 24 08:47:57 AM UTC 24 |
43614697 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2228640279 |
|
|
Sep 24 08:47:58 AM UTC 24 |
Sep 24 08:48:00 AM UTC 24 |
52952112 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3318955306 |
|
|
Sep 24 08:47:53 AM UTC 24 |
Sep 24 08:47:57 AM UTC 24 |
68421529 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1977893813 |
|
|
Sep 24 08:47:51 AM UTC 24 |
Sep 24 08:47:57 AM UTC 24 |
1452707983 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2893926127 |
|
|
Sep 24 08:47:57 AM UTC 24 |
Sep 24 08:48:00 AM UTC 24 |
238910161 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2354249134 |
|
|
Sep 24 08:47:55 AM UTC 24 |
Sep 24 08:47:57 AM UTC 24 |
71068273 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2647277365 |
|
|
Sep 24 08:47:55 AM UTC 24 |
Sep 24 08:47:57 AM UTC 24 |
13170408 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.59242349 |
|
|
Sep 24 08:47:52 AM UTC 24 |
Sep 24 08:47:57 AM UTC 24 |
1444923846 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1091984319 |
|
|
Sep 24 08:47:55 AM UTC 24 |
Sep 24 08:47:57 AM UTC 24 |
78187624 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3768253251 |
|
|
Sep 24 08:47:55 AM UTC 24 |
Sep 24 08:47:57 AM UTC 24 |
31762371 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.833176715 |
|
|
Sep 24 08:47:55 AM UTC 24 |
Sep 24 08:47:57 AM UTC 24 |
287461297 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1524585165 |
|
|
Sep 24 08:47:55 AM UTC 24 |
Sep 24 08:47:58 AM UTC 24 |
296921030 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2097666281 |
|
|
Sep 24 08:47:55 AM UTC 24 |
Sep 24 08:47:58 AM UTC 24 |
252719650 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3222897079 |
|
|
Sep 24 08:47:53 AM UTC 24 |
Sep 24 08:47:58 AM UTC 24 |
721775404 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2864814900 |
|
|
Sep 24 08:47:57 AM UTC 24 |
Sep 24 08:47:58 AM UTC 24 |
20106664 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1915489391 |
|
|
Sep 24 08:47:58 AM UTC 24 |
Sep 24 08:48:00 AM UTC 24 |
59664115 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1025521019 |
|
|
Sep 24 08:47:57 AM UTC 24 |
Sep 24 08:47:59 AM UTC 24 |
28180207 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3674474503 |
|
|
Sep 24 08:47:57 AM UTC 24 |
Sep 24 08:47:59 AM UTC 24 |
14606810 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2920568121 |
|
|
Sep 24 08:47:57 AM UTC 24 |
Sep 24 08:47:59 AM UTC 24 |
12209894 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2365918545 |
|
|
Sep 24 08:47:54 AM UTC 24 |
Sep 24 08:47:59 AM UTC 24 |
1435710861 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3588348471 |
|
|
Sep 24 08:47:55 AM UTC 24 |
Sep 24 08:47:59 AM UTC 24 |
345297559 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2786270317 |
|
|
Sep 24 08:47:57 AM UTC 24 |
Sep 24 08:47:59 AM UTC 24 |
609800344 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1561504419 |
|
|
Sep 24 08:47:55 AM UTC 24 |
Sep 24 08:48:00 AM UTC 24 |
370066888 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.614954213 |
|
|
Sep 24 08:47:57 AM UTC 24 |
Sep 24 08:48:00 AM UTC 24 |
21618791 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3423374507 |
|
|
Sep 24 08:47:58 AM UTC 24 |
Sep 24 08:48:00 AM UTC 24 |
49442839 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3609211845 |
|
|
Sep 24 08:47:58 AM UTC 24 |
Sep 24 08:48:00 AM UTC 24 |
12108423 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1872783798 |
|
|
Sep 24 08:47:59 AM UTC 24 |
Sep 24 08:48:00 AM UTC 24 |
29974285 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2410282856 |
|
|
Sep 24 08:47:55 AM UTC 24 |
Sep 24 08:48:01 AM UTC 24 |
1377587641 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2883380710 |
|
|
Sep 24 08:47:57 AM UTC 24 |
Sep 24 08:48:01 AM UTC 24 |
271178270 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2077518992 |
|
|
Sep 24 08:47:55 AM UTC 24 |
Sep 24 08:48:01 AM UTC 24 |
1237456042 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3794308077 |
|
|
Sep 24 08:47:57 AM UTC 24 |
Sep 24 08:48:01 AM UTC 24 |
93905308 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1926492963 |
|
|
Sep 24 08:47:55 AM UTC 24 |
Sep 24 08:48:01 AM UTC 24 |
161676585 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1048528532 |
|
|
Sep 24 08:48:00 AM UTC 24 |
Sep 24 08:48:02 AM UTC 24 |
29092623 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2034440369 |
|
|
Sep 24 08:48:00 AM UTC 24 |
Sep 24 08:48:02 AM UTC 24 |
20746113 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2449815772 |
|
|
Sep 24 08:48:00 AM UTC 24 |
Sep 24 08:48:02 AM UTC 24 |
15461737 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3771561327 |
|
|
Sep 24 08:47:57 AM UTC 24 |
Sep 24 08:48:02 AM UTC 24 |
426390047 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1109952288 |
|
|
Sep 24 08:47:59 AM UTC 24 |
Sep 24 08:48:02 AM UTC 24 |
663070877 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.632131392 |
|
|
Sep 24 08:47:57 AM UTC 24 |
Sep 24 08:48:03 AM UTC 24 |
1429452606 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.63336428 |
|
|
Sep 24 08:47:57 AM UTC 24 |
Sep 24 08:48:03 AM UTC 24 |
489848996 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3847581523 |
|
|
Sep 24 08:47:58 AM UTC 24 |
Sep 24 08:48:03 AM UTC 24 |
1483876376 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3306533684 |
|
|
Sep 24 08:48:00 AM UTC 24 |
Sep 24 08:48:03 AM UTC 24 |
72775025 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.103138695 |
|
|
Sep 24 08:48:01 AM UTC 24 |
Sep 24 08:48:03 AM UTC 24 |
34368485 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1514538010 |
|
|
Sep 24 08:48:02 AM UTC 24 |
Sep 24 08:48:03 AM UTC 24 |
27749867 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1896727387 |
|
|
Sep 24 08:48:01 AM UTC 24 |
Sep 24 08:48:03 AM UTC 24 |
16865933 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2386095651 |
|
|
Sep 24 08:47:58 AM UTC 24 |
Sep 24 08:48:03 AM UTC 24 |
1437027108 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2683230254 |
|
|
Sep 24 08:48:00 AM UTC 24 |
Sep 24 08:48:04 AM UTC 24 |
1924555905 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2826305086 |
|
|
Sep 24 08:47:59 AM UTC 24 |
Sep 24 08:48:04 AM UTC 24 |
479349407 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2420762178 |
|
|
Sep 24 08:48:02 AM UTC 24 |
Sep 24 08:48:04 AM UTC 24 |
55699088 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2891566675 |
|
|
Sep 24 08:48:01 AM UTC 24 |
Sep 24 08:48:04 AM UTC 24 |
157063411 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1252740945 |
|
|
Sep 24 08:47:58 AM UTC 24 |
Sep 24 08:48:04 AM UTC 24 |
358217058 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3706119220 |
|
|
Sep 24 08:48:02 AM UTC 24 |
Sep 24 08:48:05 AM UTC 24 |
611121590 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2096281169 |
|
|
Sep 24 08:48:03 AM UTC 24 |
Sep 24 08:48:05 AM UTC 24 |
51395549 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2621613430 |
|
|
Sep 24 08:48:03 AM UTC 24 |
Sep 24 08:48:05 AM UTC 24 |
160630636 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.269512966 |
|
|
Sep 24 08:48:00 AM UTC 24 |
Sep 24 08:48:05 AM UTC 24 |
377578918 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3981648189 |
|
|
Sep 24 08:48:01 AM UTC 24 |
Sep 24 08:48:05 AM UTC 24 |
63006071 ps |