| T121 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.2220900468 |
|
|
Sep 24 11:25:56 AM UTC 24 |
Sep 24 11:26:08 AM UTC 24 |
210927431 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all.3410148325 |
|
|
Sep 24 10:37:44 AM UTC 24 |
Sep 24 11:26:27 AM UTC 24 |
82900733619 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_alert_test.769348497 |
|
|
Sep 24 11:26:27 AM UTC 24 |
Sep 24 11:26:30 AM UTC 24 |
13893624 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.4019988053 |
|
|
Sep 24 11:18:53 AM UTC 24 |
Sep 24 11:26:36 AM UTC 24 |
25308956085 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_smoke.359609263 |
|
|
Sep 24 11:26:31 AM UTC 24 |
Sep 24 11:26:41 AM UTC 24 |
10147931976 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.2516780526 |
|
|
Sep 24 11:22:30 AM UTC 24 |
Sep 24 11:26:50 AM UTC 24 |
48066798713 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.808138706 |
|
|
Sep 24 11:25:08 AM UTC 24 |
Sep 24 11:28:44 AM UTC 24 |
5101060787 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access.3246513967 |
|
|
Sep 24 11:28:45 AM UTC 24 |
Sep 24 11:28:58 AM UTC 24 |
776841406 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.1682187944 |
|
|
Sep 24 11:24:55 AM UTC 24 |
Sep 24 11:28:59 AM UTC 24 |
27709686083 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.3474717299 |
|
|
Sep 24 11:29:01 AM UTC 24 |
Sep 24 11:29:40 AM UTC 24 |
2880470415 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.2785789380 |
|
|
Sep 24 11:29:31 AM UTC 24 |
Sep 24 11:29:44 AM UTC 24 |
2909047580 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.3632042854 |
|
|
Sep 24 11:29:41 AM UTC 24 |
Sep 24 11:30:03 AM UTC 24 |
4806466757 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all.3376463517 |
|
|
Sep 24 11:05:42 AM UTC 24 |
Sep 24 11:30:41 AM UTC 24 |
269026971624 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.3787550059 |
|
|
Sep 24 11:19:12 AM UTC 24 |
Sep 24 11:31:38 AM UTC 24 |
98214916074 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.519666717 |
|
|
Sep 24 11:31:39 AM UTC 24 |
Sep 24 11:31:46 AM UTC 24 |
706033102 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.1039215890 |
|
|
Sep 24 11:23:04 AM UTC 24 |
Sep 24 11:32:11 AM UTC 24 |
76997236096 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.2315570682 |
|
|
Sep 24 11:26:51 AM UTC 24 |
Sep 24 11:33:05 AM UTC 24 |
5150502920 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.3975221265 |
|
|
Sep 24 11:33:06 AM UTC 24 |
Sep 24 11:33:22 AM UTC 24 |
210308245 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.2033578751 |
|
|
Sep 24 11:16:06 AM UTC 24 |
Sep 24 11:33:58 AM UTC 24 |
11958702318 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_alert_test.2876524921 |
|
|
Sep 24 11:33:58 AM UTC 24 |
Sep 24 11:34:01 AM UTC 24 |
26085281 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_smoke.3186645279 |
|
|
Sep 24 11:34:02 AM UTC 24 |
Sep 24 11:34:44 AM UTC 24 |
3905447143 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.2369397479 |
|
|
Sep 24 11:21:50 AM UTC 24 |
Sep 24 11:35:00 AM UTC 24 |
11230841265 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.2126671804 |
|
|
Sep 24 11:32:12 AM UTC 24 |
Sep 24 11:35:07 AM UTC 24 |
3354681025 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.549665863 |
|
|
Sep 24 11:31:46 AM UTC 24 |
Sep 24 11:37:12 AM UTC 24 |
57732127017 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access.1283584678 |
|
|
Sep 24 11:37:14 AM UTC 24 |
Sep 24 11:37:26 AM UTC 24 |
942917130 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.3731752934 |
|
|
Sep 24 11:24:02 AM UTC 24 |
Sep 24 11:37:40 AM UTC 24 |
10482856445 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_bijection.2134947502 |
|
|
Sep 24 11:22:01 AM UTC 24 |
Sep 24 11:37:49 AM UTC 24 |
47049681817 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.1811275152 |
|
|
Sep 24 11:37:41 AM UTC 24 |
Sep 24 11:37:52 AM UTC 24 |
723137854 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_regwen.3475964685 |
|
|
Sep 24 11:16:37 AM UTC 24 |
Sep 24 11:37:57 AM UTC 24 |
38777468555 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.1002805462 |
|
|
Sep 24 11:18:28 AM UTC 24 |
Sep 24 11:38:12 AM UTC 24 |
92358594776 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_bijection.1555398918 |
|
|
Sep 24 10:59:38 AM UTC 24 |
Sep 24 11:38:24 AM UTC 24 |
33145835301 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.3217914205 |
|
|
Sep 24 11:37:49 AM UTC 24 |
Sep 24 11:38:26 AM UTC 24 |
3189561063 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.606938769 |
|
|
Sep 24 11:38:28 AM UTC 24 |
Sep 24 11:38:35 AM UTC 24 |
2243403856 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all.3456135100 |
|
|
Sep 24 11:21:28 AM UTC 24 |
Sep 24 11:38:39 AM UTC 24 |
53993683661 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_bijection.2373085314 |
|
|
Sep 24 11:10:45 AM UTC 24 |
Sep 24 11:38:42 AM UTC 24 |
333126646977 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.3826252741 |
|
|
Sep 24 11:38:42 AM UTC 24 |
Sep 24 11:39:07 AM UTC 24 |
1676470781 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.335778981 |
|
|
Sep 24 11:35:08 AM UTC 24 |
Sep 24 11:39:23 AM UTC 24 |
16262942655 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_regwen.1740056861 |
|
|
Sep 24 11:08:17 AM UTC 24 |
Sep 24 11:39:25 AM UTC 24 |
71044996240 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_alert_test.843373132 |
|
|
Sep 24 11:39:24 AM UTC 24 |
Sep 24 11:39:27 AM UTC 24 |
23540064 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.2303948991 |
|
|
Sep 24 11:37:53 AM UTC 24 |
Sep 24 11:39:31 AM UTC 24 |
28693943913 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_smoke.3811344339 |
|
|
Sep 24 11:39:26 AM UTC 24 |
Sep 24 11:39:37 AM UTC 24 |
777392224 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all.2041490685 |
|
|
Sep 24 10:47:42 AM UTC 24 |
Sep 24 11:39:47 AM UTC 24 |
287608909789 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.118765554 |
|
|
Sep 24 11:38:40 AM UTC 24 |
Sep 24 11:40:05 AM UTC 24 |
2467732985 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.2825450076 |
|
|
Sep 24 11:29:44 AM UTC 24 |
Sep 24 11:40:43 AM UTC 24 |
15352178040 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.3413444108 |
|
|
Sep 24 11:28:59 AM UTC 24 |
Sep 24 11:40:54 AM UTC 24 |
8415897772 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access.1379383619 |
|
|
Sep 24 11:39:48 AM UTC 24 |
Sep 24 11:41:06 AM UTC 24 |
8410845519 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_regwen.1426992363 |
|
|
Sep 24 11:30:42 AM UTC 24 |
Sep 24 11:42:04 AM UTC 24 |
20912324573 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_bijection.4177017754 |
|
|
Sep 24 11:18:39 AM UTC 24 |
Sep 24 11:42:08 AM UTC 24 |
79255850661 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.2043299959 |
|
|
Sep 24 11:40:44 AM UTC 24 |
Sep 24 11:42:15 AM UTC 24 |
3189089719 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.3160281321 |
|
|
Sep 24 11:41:06 AM UTC 24 |
Sep 24 11:42:20 AM UTC 24 |
5689838156 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.1882301775 |
|
|
Sep 24 11:42:20 AM UTC 24 |
Sep 24 11:42:27 AM UTC 24 |
1534604996 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.59857378 |
|
|
Sep 24 11:38:37 AM UTC 24 |
Sep 24 11:42:37 AM UTC 24 |
15756485474 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.3956146633 |
|
|
Sep 24 11:40:55 AM UTC 24 |
Sep 24 11:42:48 AM UTC 24 |
782271491 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.3349931761 |
|
|
Sep 24 11:42:48 AM UTC 24 |
Sep 24 11:43:02 AM UTC 24 |
235093859 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all.3570082377 |
|
|
Sep 24 10:50:21 AM UTC 24 |
Sep 24 11:43:03 AM UTC 24 |
182960971891 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_alert_test.2948150706 |
|
|
Sep 24 11:43:04 AM UTC 24 |
Sep 24 11:43:06 AM UTC 24 |
18147715 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_regwen.1471184132 |
|
|
Sep 24 11:42:16 AM UTC 24 |
Sep 24 11:43:24 AM UTC 24 |
9288207956 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.380738251 |
|
|
Sep 24 11:15:32 AM UTC 24 |
Sep 24 11:43:26 AM UTC 24 |
84662751070 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_regwen.3654293092 |
|
|
Sep 24 11:24:07 AM UTC 24 |
Sep 24 11:43:26 AM UTC 24 |
90466100856 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all.2148840313 |
|
|
Sep 24 10:44:15 AM UTC 24 |
Sep 24 11:43:59 AM UTC 24 |
70557921217 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access.1957904634 |
|
|
Sep 24 11:44:00 AM UTC 24 |
Sep 24 11:44:21 AM UTC 24 |
1134085064 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_smoke.1642740934 |
|
|
Sep 24 11:43:07 AM UTC 24 |
Sep 24 11:44:34 AM UTC 24 |
2165828478 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.1416504432 |
|
|
Sep 24 11:39:38 AM UTC 24 |
Sep 24 11:44:43 AM UTC 24 |
17767352259 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_regwen.1323078612 |
|
|
Sep 24 11:20:17 AM UTC 24 |
Sep 24 11:44:45 AM UTC 24 |
4055797520 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.3338005943 |
|
|
Sep 24 11:44:34 AM UTC 24 |
Sep 24 11:45:17 AM UTC 24 |
993189945 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.1659209956 |
|
|
Sep 24 11:42:28 AM UTC 24 |
Sep 24 11:45:42 AM UTC 24 |
2634785478 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.2225083260 |
|
|
Sep 24 11:42:38 AM UTC 24 |
Sep 24 11:45:49 AM UTC 24 |
4850765729 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.870312903 |
|
|
Sep 24 11:44:44 AM UTC 24 |
Sep 24 11:46:20 AM UTC 24 |
1161543031 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.2366282081 |
|
|
Sep 24 11:46:21 AM UTC 24 |
Sep 24 11:46:29 AM UTC 24 |
1404127783 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.3169077806 |
|
|
Sep 24 11:37:27 AM UTC 24 |
Sep 24 11:46:34 AM UTC 24 |
29406337994 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_executable.1478806507 |
|
|
Sep 24 11:24:03 AM UTC 24 |
Sep 24 11:46:36 AM UTC 24 |
69195751112 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all.1083386539 |
|
|
Sep 24 09:49:58 AM UTC 24 |
Sep 24 11:46:45 AM UTC 24 |
1443238421215 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.1436600007 |
|
|
Sep 24 11:44:47 AM UTC 24 |
Sep 24 11:46:46 AM UTC 24 |
45352265907 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_alert_test.4022878123 |
|
|
Sep 24 11:46:47 AM UTC 24 |
Sep 24 11:46:49 AM UTC 24 |
38605921 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_bijection.566821494 |
|
|
Sep 24 11:15:36 AM UTC 24 |
Sep 24 11:46:53 AM UTC 24 |
108792388617 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.860738208 |
|
|
Sep 24 11:26:37 AM UTC 24 |
Sep 24 11:47:08 AM UTC 24 |
20184321413 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.766544733 |
|
|
Sep 24 11:46:37 AM UTC 24 |
Sep 24 11:47:09 AM UTC 24 |
2168591852 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_smoke.3779168714 |
|
|
Sep 24 11:46:50 AM UTC 24 |
Sep 24 11:47:17 AM UTC 24 |
1172760355 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access.1692993757 |
|
|
Sep 24 11:47:17 AM UTC 24 |
Sep 24 11:47:47 AM UTC 24 |
1265574294 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.2035512839 |
|
|
Sep 24 11:43:28 AM UTC 24 |
Sep 24 11:48:01 AM UTC 24 |
16112653285 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.680185609 |
|
|
Sep 24 11:46:29 AM UTC 24 |
Sep 24 11:48:56 AM UTC 24 |
5370556176 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.2011042384 |
|
|
Sep 24 11:48:57 AM UTC 24 |
Sep 24 11:49:02 AM UTC 24 |
1409869381 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.1614454280 |
|
|
Sep 24 11:48:08 AM UTC 24 |
Sep 24 11:49:04 AM UTC 24 |
11832528298 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_alert_test.590168668 |
|
|
Sep 24 11:49:10 AM UTC 24 |
Sep 24 11:49:13 AM UTC 24 |
19827232 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.2762688378 |
|
|
Sep 24 11:49:08 AM UTC 24 |
Sep 24 11:49:14 AM UTC 24 |
97407743 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all.2995821650 |
|
|
Sep 24 10:41:34 AM UTC 24 |
Sep 24 11:49:22 AM UTC 24 |
385189506290 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_regwen.3580329074 |
|
|
Sep 24 11:48:39 AM UTC 24 |
Sep 24 11:49:31 AM UTC 24 |
1173322057 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.2532567502 |
|
|
Sep 24 11:48:03 AM UTC 24 |
Sep 24 11:49:35 AM UTC 24 |
820655003 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.745062753 |
|
|
Sep 24 11:46:35 AM UTC 24 |
Sep 24 11:49:47 AM UTC 24 |
22226849701 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.2778928868 |
|
|
Sep 24 11:48:06 AM UTC 24 |
Sep 24 11:49:50 AM UTC 24 |
1541537781 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access.3213800692 |
|
|
Sep 24 11:49:34 AM UTC 24 |
Sep 24 11:49:50 AM UTC 24 |
708154412 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_smoke.3147299610 |
|
|
Sep 24 11:49:14 AM UTC 24 |
Sep 24 11:49:52 AM UTC 24 |
5698991432 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.1993846198 |
|
|
Sep 24 11:44:22 AM UTC 24 |
Sep 24 11:49:56 AM UTC 24 |
20819264549 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.192094239 |
|
|
Sep 24 11:49:48 AM UTC 24 |
Sep 24 11:49:58 AM UTC 24 |
697557178 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.2551276594 |
|
|
Sep 24 11:49:52 AM UTC 24 |
Sep 24 11:49:59 AM UTC 24 |
1528340450 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.45378276 |
|
|
Sep 24 11:49:38 AM UTC 24 |
Sep 24 11:49:59 AM UTC 24 |
1445628364 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_alert_test.3424850980 |
|
|
Sep 24 11:49:59 AM UTC 24 |
Sep 24 11:50:01 AM UTC 24 |
37594639 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_smoke.816269191 |
|
|
Sep 24 11:50:00 AM UTC 24 |
Sep 24 11:50:23 AM UTC 24 |
1066070146 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.620078376 |
|
|
Sep 24 11:49:57 AM UTC 24 |
Sep 24 11:50:26 AM UTC 24 |
3900912739 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.1549809226 |
|
|
Sep 24 11:49:50 AM UTC 24 |
Sep 24 11:50:53 AM UTC 24 |
29638081623 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access.314414101 |
|
|
Sep 24 11:50:12 AM UTC 24 |
Sep 24 11:50:54 AM UTC 24 |
1047919542 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.600939 |
|
|
Sep 24 11:45:19 AM UTC 24 |
Sep 24 11:51:03 AM UTC 24 |
5256157771 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.1949511018 |
|
|
Sep 24 11:50:59 AM UTC 24 |
Sep 24 11:51:05 AM UTC 24 |
399202456 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.9344457 |
|
|
Sep 24 11:49:57 AM UTC 24 |
Sep 24 11:51:10 AM UTC 24 |
999159128 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.4189540578 |
|
|
Sep 24 11:37:57 AM UTC 24 |
Sep 24 11:51:26 AM UTC 24 |
13503440819 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.3021351636 |
|
|
Sep 24 11:40:06 AM UTC 24 |
Sep 24 11:51:40 AM UTC 24 |
16171586703 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_alert_test.2117659092 |
|
|
Sep 24 11:51:42 AM UTC 24 |
Sep 24 11:51:43 AM UTC 24 |
18007456 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.1516090679 |
|
|
Sep 24 11:50:26 AM UTC 24 |
Sep 24 11:51:49 AM UTC 24 |
47782911953 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_regwen.982701521 |
|
|
Sep 24 11:38:25 AM UTC 24 |
Sep 24 11:51:51 AM UTC 24 |
13328268146 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_executable.1497198496 |
|
|
Sep 24 11:30:04 AM UTC 24 |
Sep 24 11:51:53 AM UTC 24 |
80754937031 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.3590957868 |
|
|
Sep 24 11:50:24 AM UTC 24 |
Sep 24 11:52:04 AM UTC 24 |
1574266786 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.3119780237 |
|
|
Sep 24 11:51:11 AM UTC 24 |
Sep 24 11:52:04 AM UTC 24 |
1245041892 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_executable.1979979735 |
|
|
Sep 24 11:38:13 AM UTC 24 |
Sep 24 11:52:16 AM UTC 24 |
26695388096 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_smoke.4199164435 |
|
|
Sep 24 11:51:45 AM UTC 24 |
Sep 24 11:52:18 AM UTC 24 |
5623972739 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.1630401697 |
|
|
Sep 24 11:50:21 AM UTC 24 |
Sep 24 11:52:20 AM UTC 24 |
767857182 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access.1021135346 |
|
|
Sep 24 11:52:05 AM UTC 24 |
Sep 24 11:52:25 AM UTC 24 |
909054333 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.1739383648 |
|
|
Sep 24 11:52:17 AM UTC 24 |
Sep 24 11:52:29 AM UTC 24 |
711831476 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.541476931 |
|
|
Sep 24 11:51:06 AM UTC 24 |
Sep 24 11:52:36 AM UTC 24 |
1013094425 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.3237635105 |
|
|
Sep 24 11:47:10 AM UTC 24 |
Sep 24 11:52:48 AM UTC 24 |
21253950675 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.4149319270 |
|
|
Sep 24 11:52:49 AM UTC 24 |
Sep 24 11:52:56 AM UTC 24 |
1349220027 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.3695528445 |
|
|
Sep 24 11:49:54 AM UTC 24 |
Sep 24 11:53:01 AM UTC 24 |
27686539068 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.4222705004 |
|
|
Sep 24 11:49:06 AM UTC 24 |
Sep 24 11:53:08 AM UTC 24 |
36551309321 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all.290575671 |
|
|
Sep 24 10:21:21 AM UTC 24 |
Sep 24 11:53:09 AM UTC 24 |
67564635236 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.1514579807 |
|
|
Sep 24 11:50:04 AM UTC 24 |
Sep 24 11:53:15 AM UTC 24 |
14827109978 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_regwen.1323805237 |
|
|
Sep 24 11:45:50 AM UTC 24 |
Sep 24 11:53:16 AM UTC 24 |
13956534978 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_alert_test.3988860527 |
|
|
Sep 24 11:53:16 AM UTC 24 |
Sep 24 11:53:18 AM UTC 24 |
36146103 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_executable.2519378279 |
|
|
Sep 24 11:42:09 AM UTC 24 |
Sep 24 11:53:40 AM UTC 24 |
95634380460 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_all.20547237 |
|
|
Sep 24 11:33:22 AM UTC 24 |
Sep 24 11:53:43 AM UTC 24 |
17178305985 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.1702207954 |
|
|
Sep 24 11:52:19 AM UTC 24 |
Sep 24 11:53:49 AM UTC 24 |
786856286 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.859182722 |
|
|
Sep 24 11:47:49 AM UTC 24 |
Sep 24 11:54:00 AM UTC 24 |
12238309948 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_smoke.1779436643 |
|
|
Sep 24 11:53:17 AM UTC 24 |
Sep 24 11:54:09 AM UTC 24 |
761165649 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access.2661037083 |
|
|
Sep 24 11:53:50 AM UTC 24 |
Sep 24 11:54:12 AM UTC 24 |
4747152643 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.1407717219 |
|
|
Sep 24 11:52:21 AM UTC 24 |
Sep 24 11:54:21 AM UTC 24 |
24036894577 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.3937848221 |
|
|
Sep 24 11:49:32 AM UTC 24 |
Sep 24 11:54:22 AM UTC 24 |
7748774369 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.972049678 |
|
|
Sep 24 11:54:10 AM UTC 24 |
Sep 24 11:54:27 AM UTC 24 |
1616536736 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.2282815791 |
|
|
Sep 24 11:42:05 AM UTC 24 |
Sep 24 11:54:30 AM UTC 24 |
47007208399 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.1051731566 |
|
|
Sep 24 11:53:01 AM UTC 24 |
Sep 24 11:54:45 AM UTC 24 |
4387985631 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_bijection.3817546341 |
|
|
Sep 24 11:43:27 AM UTC 24 |
Sep 24 11:54:51 AM UTC 24 |
63161692763 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.403307827 |
|
|
Sep 24 11:54:45 AM UTC 24 |
Sep 24 11:54:53 AM UTC 24 |
1397468790 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.3569129818 |
|
|
Sep 24 11:39:28 AM UTC 24 |
Sep 24 11:55:15 AM UTC 24 |
87307918226 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.2950633621 |
|
|
Sep 24 11:49:03 AM UTC 24 |
Sep 24 11:55:32 AM UTC 24 |
71842224309 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.2874474604 |
|
|
Sep 24 11:54:22 AM UTC 24 |
Sep 24 11:55:38 AM UTC 24 |
14173696350 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_alert_test.601823934 |
|
|
Sep 24 11:55:39 AM UTC 24 |
Sep 24 11:55:41 AM UTC 24 |
24856524 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.2839507784 |
|
|
Sep 24 11:54:13 AM UTC 24 |
Sep 24 11:55:42 AM UTC 24 |
3085162766 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.862658330 |
|
|
Sep 24 11:55:16 AM UTC 24 |
Sep 24 11:55:49 AM UTC 24 |
982927306 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_smoke.4184198653 |
|
|
Sep 24 11:55:42 AM UTC 24 |
Sep 24 11:55:52 AM UTC 24 |
674780601 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all.2049818620 |
|
|
Sep 24 10:54:57 AM UTC 24 |
Sep 24 11:56:05 AM UTC 24 |
163780136358 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.699409163 |
|
|
Sep 24 11:51:55 AM UTC 24 |
Sep 24 11:56:18 AM UTC 24 |
35191584816 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access.1316980533 |
|
|
Sep 24 11:56:06 AM UTC 24 |
Sep 24 11:56:22 AM UTC 24 |
487540781 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.3066301942 |
|
|
Sep 24 11:43:24 AM UTC 24 |
Sep 24 11:56:55 AM UTC 24 |
199886856613 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.2903526182 |
|
|
Sep 24 11:54:54 AM UTC 24 |
Sep 24 11:57:01 AM UTC 24 |
9867563720 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.3468010572 |
|
|
Sep 24 11:56:23 AM UTC 24 |
Sep 24 11:57:04 AM UTC 24 |
766089114 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.133261876 |
|
|
Sep 24 11:56:56 AM UTC 24 |
Sep 24 11:57:11 AM UTC 24 |
678792143 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_executable.3887746690 |
|
|
Sep 24 11:49:51 AM UTC 24 |
Sep 24 11:57:33 AM UTC 24 |
5878799750 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.4198003577 |
|
|
Sep 24 11:50:19 AM UTC 24 |
Sep 24 11:57:35 AM UTC 24 |
14780082782 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.3707503761 |
|
|
Sep 24 11:49:36 AM UTC 24 |
Sep 24 11:57:38 AM UTC 24 |
6259475522 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.4152752549 |
|
|
Sep 24 11:57:36 AM UTC 24 |
Sep 24 11:57:43 AM UTC 24 |
1165711814 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.2906985090 |
|
|
Sep 24 11:53:10 AM UTC 24 |
Sep 24 11:57:46 AM UTC 24 |
9798848767 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.3097301684 |
|
|
Sep 24 11:51:04 AM UTC 24 |
Sep 24 11:58:04 AM UTC 24 |
65958789886 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.1233485640 |
|
|
Sep 24 11:34:45 AM UTC 24 |
Sep 24 11:58:06 AM UTC 24 |
41380225080 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.2459733574 |
|
|
Sep 24 11:52:57 AM UTC 24 |
Sep 24 11:58:07 AM UTC 24 |
27647868316 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.1763572569 |
|
|
Sep 24 11:57:48 AM UTC 24 |
Sep 24 11:58:08 AM UTC 24 |
4744631855 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.2459688708 |
|
|
Sep 24 11:57:03 AM UTC 24 |
Sep 24 11:58:09 AM UTC 24 |
14511627700 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_alert_test.1062929507 |
|
|
Sep 24 11:58:07 AM UTC 24 |
Sep 24 11:58:09 AM UTC 24 |
20174902 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_smoke.1303021685 |
|
|
Sep 24 11:58:07 AM UTC 24 |
Sep 24 11:58:41 AM UTC 24 |
2886703885 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.2535597829 |
|
|
Sep 24 11:53:44 AM UTC 24 |
Sep 24 11:58:47 AM UTC 24 |
4716331595 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access.2876082962 |
|
|
Sep 24 11:58:41 AM UTC 24 |
Sep 24 11:59:01 AM UTC 24 |
13764099129 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_executable.1022083835 |
|
|
Sep 24 11:48:34 AM UTC 24 |
Sep 24 11:59:13 AM UTC 24 |
13543280690 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.2017249586 |
|
|
Sep 24 11:54:52 AM UTC 24 |
Sep 24 11:59:15 AM UTC 24 |
5715928981 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.1250960595 |
|
|
Sep 24 11:52:05 AM UTC 24 |
Sep 24 11:59:33 AM UTC 24 |
19228554003 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.2437761159 |
|
|
Sep 24 11:59:14 AM UTC 24 |
Sep 24 11:59:35 AM UTC 24 |
723290664 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.3992145188 |
|
|
Sep 24 11:48:20 AM UTC 24 |
Sep 24 11:59:46 AM UTC 24 |
6809136400 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.2936385233 |
|
|
Sep 24 11:59:46 AM UTC 24 |
Sep 24 11:59:53 AM UTC 24 |
2404259911 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.961981668 |
|
|
Sep 24 11:54:01 AM UTC 24 |
Sep 24 12:00:20 PM UTC 24 |
10741377387 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.515164248 |
|
|
Sep 24 11:57:45 AM UTC 24 |
Sep 24 12:00:26 PM UTC 24 |
2536736275 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.1684272482 |
|
|
Sep 24 11:55:53 AM UTC 24 |
Sep 24 12:00:28 PM UTC 24 |
3522716423 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.3063088239 |
|
|
Sep 24 11:57:05 AM UTC 24 |
Sep 24 12:00:30 PM UTC 24 |
3064969619 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_alert_test.4048721417 |
|
|
Sep 24 12:00:32 PM UTC 24 |
Sep 24 12:00:34 PM UTC 24 |
31955643 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.1098228471 |
|
|
Sep 24 11:59:02 AM UTC 24 |
Sep 24 12:00:36 PM UTC 24 |
1592410023 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.3189875398 |
|
|
Sep 24 12:00:27 PM UTC 24 |
Sep 24 12:00:46 PM UTC 24 |
1447770191 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.85770647 |
|
|
Sep 24 11:59:16 AM UTC 24 |
Sep 24 12:00:49 PM UTC 24 |
18992805003 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_smoke.3468484380 |
|
|
Sep 24 12:00:35 PM UTC 24 |
Sep 24 12:00:57 PM UTC 24 |
520132816 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.1076266965 |
|
|
Sep 24 11:49:15 AM UTC 24 |
Sep 24 12:01:08 PM UTC 24 |
8239600149 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access.41774332 |
|
|
Sep 24 12:00:58 PM UTC 24 |
Sep 24 12:01:26 PM UTC 24 |
907857455 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_executable.3003364338 |
|
|
Sep 24 11:54:28 AM UTC 24 |
Sep 24 12:01:37 PM UTC 24 |
23679684383 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_regwen.1679598464 |
|
|
Sep 24 11:52:36 AM UTC 24 |
Sep 24 12:01:40 PM UTC 24 |
3076907084 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.87928025 |
|
|
Sep 24 12:01:27 PM UTC 24 |
Sep 24 12:02:13 PM UTC 24 |
1511603476 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all.1298919981 |
|
|
Sep 24 11:15:23 AM UTC 24 |
Sep 24 12:02:16 PM UTC 24 |
34466958813 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_regwen.660700035 |
|
|
Sep 24 11:50:56 AM UTC 24 |
Sep 24 12:02:19 PM UTC 24 |
2491105053 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.2339026479 |
|
|
Sep 24 11:52:26 AM UTC 24 |
Sep 24 12:02:22 PM UTC 24 |
11072080787 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.2175604878 |
|
|
Sep 24 12:02:23 PM UTC 24 |
Sep 24 12:02:29 PM UTC 24 |
1350416627 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.3335907431 |
|
|
Sep 24 11:59:55 AM UTC 24 |
Sep 24 12:02:42 PM UTC 24 |
2689046588 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.250106134 |
|
|
Sep 24 11:57:40 AM UTC 24 |
Sep 24 12:02:59 PM UTC 24 |
5473704086 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.1525818865 |
|
|
Sep 24 11:54:23 AM UTC 24 |
Sep 24 12:03:11 PM UTC 24 |
58925736888 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.533691712 |
|
|
Sep 24 12:01:38 PM UTC 24 |
Sep 24 12:03:12 PM UTC 24 |
958342536 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_alert_test.838472680 |
|
|
Sep 24 12:03:12 PM UTC 24 |
Sep 24 12:03:14 PM UTC 24 |
30059159 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_regwen.745812018 |
|
|
Sep 24 11:59:36 AM UTC 24 |
Sep 24 12:03:16 PM UTC 24 |
2702386050 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.307100941 |
|
|
Sep 24 11:53:19 AM UTC 24 |
Sep 24 12:03:19 PM UTC 24 |
19406667894 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.2142240080 |
|
|
Sep 24 12:03:00 PM UTC 24 |
Sep 24 12:03:29 PM UTC 24 |
683328907 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.3394617811 |
|
|
Sep 24 11:49:51 AM UTC 24 |
Sep 24 12:03:43 PM UTC 24 |
22588423192 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_smoke.4128952577 |
|
|
Sep 24 12:03:16 PM UTC 24 |
Sep 24 12:03:44 PM UTC 24 |
592274953 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.3176391190 |
|
|
Sep 24 12:00:22 PM UTC 24 |
Sep 24 12:03:47 PM UTC 24 |
18313540066 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all.4206712417 |
|
|
Sep 24 10:59:25 AM UTC 24 |
Sep 24 12:03:51 PM UTC 24 |
805574784938 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.73603865 |
|
|
Sep 24 11:50:00 AM UTC 24 |
Sep 24 12:03:58 PM UTC 24 |
18401445543 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.737676522 |
|
|
Sep 24 11:58:12 AM UTC 24 |
Sep 24 12:04:12 PM UTC 24 |
7398983214 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access.3827522033 |
|
|
Sep 24 12:03:45 PM UTC 24 |
Sep 24 12:04:15 PM UTC 24 |
2981829503 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.317276931 |
|
|
Sep 24 12:02:43 PM UTC 24 |
Sep 24 12:04:18 PM UTC 24 |
26214180094 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.365799743 |
|
|
Sep 24 12:03:52 PM UTC 24 |
Sep 24 12:04:35 PM UTC 24 |
756913207 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.2616977294 |
|
|
Sep 24 12:01:41 PM UTC 24 |
Sep 24 12:04:38 PM UTC 24 |
17861513804 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.3104703148 |
|
|
Sep 24 12:04:36 PM UTC 24 |
Sep 24 12:04:41 PM UTC 24 |
350404916 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.2607681766 |
|
|
Sep 24 11:58:49 AM UTC 24 |
Sep 24 12:04:53 PM UTC 24 |
44248255996 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.533626604 |
|
|
Sep 24 11:56:20 AM UTC 24 |
Sep 24 12:05:04 PM UTC 24 |
80736635430 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.2552890451 |
|
|
Sep 24 12:03:48 PM UTC 24 |
Sep 24 12:05:15 PM UTC 24 |
3400829092 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_alert_test.3872398499 |
|
|
Sep 24 12:05:15 PM UTC 24 |
Sep 24 12:05:18 PM UTC 24 |
22388911 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3525674513 |
|
|
Sep 24 12:04:54 PM UTC 24 |
Sep 24 12:05:23 PM UTC 24 |
1660809761 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_regwen.294618027 |
|
|
Sep 24 11:57:34 AM UTC 24 |
Sep 24 12:05:39 PM UTC 24 |
4689370760 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_bijection.2475601924 |
|
|
Sep 24 11:39:32 AM UTC 24 |
Sep 24 12:05:40 PM UTC 24 |
20004672113 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.1634535524 |
|
|
Sep 24 12:04:00 PM UTC 24 |
Sep 24 12:05:51 PM UTC 24 |
26913352503 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access.3176916524 |
|
|
Sep 24 12:05:52 PM UTC 24 |
Sep 24 12:06:13 PM UTC 24 |
1062975955 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_executable.2028023093 |
|
|
Sep 24 11:52:30 AM UTC 24 |
Sep 24 12:06:28 PM UTC 24 |
6836793740 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.1445064451 |
|
|
Sep 24 12:06:15 PM UTC 24 |
Sep 24 12:06:32 PM UTC 24 |
2797069144 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.1463217681 |
|
|
Sep 24 12:06:34 PM UTC 24 |
Sep 24 12:06:47 PM UTC 24 |
7147245179 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.1988905957 |
|
|
Sep 24 11:55:43 AM UTC 24 |
Sep 24 12:07:01 PM UTC 24 |
36357359930 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_smoke.1403133175 |
|
|
Sep 24 12:05:19 PM UTC 24 |
Sep 24 12:07:10 PM UTC 24 |
1934220120 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.3920097169 |
|
|
Sep 24 12:04:43 PM UTC 24 |
Sep 24 12:07:24 PM UTC 24 |
6372860045 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.882828743 |
|
|
Sep 24 12:07:25 PM UTC 24 |
Sep 24 12:07:32 PM UTC 24 |
1461909004 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_bijection.2394368124 |
|
|
Sep 24 11:26:42 AM UTC 24 |
Sep 24 12:07:35 PM UTC 24 |
106786594920 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_executable.1532966434 |
|
|
Sep 24 11:45:43 AM UTC 24 |
Sep 24 12:07:43 PM UTC 24 |
10172347503 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.2235854608 |
|
|
Sep 24 12:00:51 PM UTC 24 |
Sep 24 12:07:52 PM UTC 24 |
14974603074 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.1787860776 |
|
|
Sep 24 12:03:17 PM UTC 24 |
Sep 24 12:08:01 PM UTC 24 |
2591176459 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_alert_test.2678733287 |
|
|
Sep 24 12:08:01 PM UTC 24 |
Sep 24 12:08:04 PM UTC 24 |
38351865 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.315563652 |
|
|
Sep 24 12:07:44 PM UTC 24 |
Sep 24 12:08:06 PM UTC 24 |
556533309 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.492971975 |
|
|
Sep 24 12:06:29 PM UTC 24 |
Sep 24 12:08:26 PM UTC 24 |
2530608587 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.2342961102 |
|
|
Sep 24 12:04:13 PM UTC 24 |
Sep 24 12:08:35 PM UTC 24 |
6060487676 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.1066759854 |
|
|
Sep 24 12:03:30 PM UTC 24 |
Sep 24 12:08:44 PM UTC 24 |
18175942337 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_smoke.1228803050 |
|
|
Sep 24 12:08:05 PM UTC 24 |
Sep 24 12:09:04 PM UTC 24 |
768918397 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access.1256770702 |
|
|
Sep 24 12:08:45 PM UTC 24 |
Sep 24 12:09:16 PM UTC 24 |
2329040640 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.3187190670 |
|
|
Sep 24 11:46:54 AM UTC 24 |
Sep 24 12:09:17 PM UTC 24 |
79845805723 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.1873823556 |
|
|
Sep 24 12:09:17 PM UTC 24 |
Sep 24 12:09:26 PM UTC 24 |
2790910036 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.2976779130 |
|
|
Sep 24 12:09:18 PM UTC 24 |
Sep 24 12:09:33 PM UTC 24 |
802642455 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.2273991369 |
|
|
Sep 24 12:02:31 PM UTC 24 |
Sep 24 12:09:44 PM UTC 24 |
89991774328 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.1805702439 |
|
|
Sep 24 12:05:24 PM UTC 24 |
Sep 24 12:09:48 PM UTC 24 |
14873818765 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.2756303667 |
|
|
Sep 24 12:09:27 PM UTC 24 |
Sep 24 12:09:58 PM UTC 24 |
21046933936 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.2889766767 |
|
|
Sep 24 12:01:08 PM UTC 24 |
Sep 24 12:09:58 PM UTC 24 |
49008946317 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.1191724954 |
|
|
Sep 24 12:09:59 PM UTC 24 |
Sep 24 12:10:04 PM UTC 24 |
350112258 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.2657018471 |
|
|
Sep 24 12:07:36 PM UTC 24 |
Sep 24 12:10:30 PM UTC 24 |
10212196359 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_regwen.1793195853 |
|
|
Sep 24 11:49:51 AM UTC 24 |
Sep 24 12:10:44 PM UTC 24 |
74975585244 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_executable.459305142 |
|
|
Sep 24 11:50:55 AM UTC 24 |
Sep 24 12:10:54 PM UTC 24 |
17938506945 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.607386169 |
|
|
Sep 24 12:10:31 PM UTC 24 |
Sep 24 12:10:57 PM UTC 24 |
952111734 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_alert_test.1124000595 |
|
|
Sep 24 12:10:56 PM UTC 24 |
Sep 24 12:10:58 PM UTC 24 |
31421952 ps |