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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.30 99.25 95.11 99.72 100.00 96.38 99.13 98.54


Total test records in report: 1037
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
T1011 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.664824488 Sep 24 08:48:01 AM UTC 24 Sep 24 08:48:06 AM UTC 24 1359817734 ps
T93 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1537336645 Sep 24 08:48:04 AM UTC 24 Sep 24 08:48:06 AM UTC 24 23462380 ps
T1012 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.870120077 Sep 24 08:48:01 AM UTC 24 Sep 24 08:48:06 AM UTC 24 455997320 ps
T1013 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2346920796 Sep 24 08:48:04 AM UTC 24 Sep 24 08:48:07 AM UTC 24 26053380 ps
T1014 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.390171027 Sep 24 08:48:04 AM UTC 24 Sep 24 08:48:07 AM UTC 24 71995168 ps
T1015 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3659904984 Sep 24 08:48:05 AM UTC 24 Sep 24 08:48:07 AM UTC 24 54639742 ps
T1016 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.551122936 Sep 24 08:48:03 AM UTC 24 Sep 24 08:48:07 AM UTC 24 500504672 ps
T1017 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1381119226 Sep 24 08:48:03 AM UTC 24 Sep 24 08:48:07 AM UTC 24 605279562 ps
T141 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1382507544 Sep 24 08:48:03 AM UTC 24 Sep 24 08:48:07 AM UTC 24 406760392 ps
T1018 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3900231550 Sep 24 08:48:00 AM UTC 24 Sep 24 08:48:07 AM UTC 24 6793599705 ps
T136 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2290911205 Sep 24 08:48:04 AM UTC 24 Sep 24 08:48:08 AM UTC 24 868000377 ps
T1019 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2194230779 Sep 24 08:48:02 AM UTC 24 Sep 24 08:48:08 AM UTC 24 1599638233 ps
T1020 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1153314646 Sep 24 08:48:03 AM UTC 24 Sep 24 08:48:08 AM UTC 24 717135114 ps
T1021 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1000608084 Sep 24 08:48:04 AM UTC 24 Sep 24 08:48:09 AM UTC 24 91970467 ps
T1022 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2617717386 Sep 24 08:48:03 AM UTC 24 Sep 24 08:48:09 AM UTC 24 108444190 ps
T1023 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.522068345 Sep 24 08:48:05 AM UTC 24 Sep 24 08:48:10 AM UTC 24 1739509510 ps
T1024 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2957382524 Sep 24 08:48:04 AM UTC 24 Sep 24 08:48:10 AM UTC 24 1361001000 ps
T88 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3505605229 Sep 24 08:47:52 AM UTC 24 Sep 24 08:48:23 AM UTC 24 4031824288 ps
T89 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3865496414 Sep 24 08:47:57 AM UTC 24 Sep 24 08:48:27 AM UTC 24 3884262938 ps
T94 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3841596199 Sep 24 08:47:57 AM UTC 24 Sep 24 08:48:28 AM UTC 24 4470395810 ps
T1025 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.861291316 Sep 24 08:48:03 AM UTC 24 Sep 24 08:48:36 AM UTC 24 14236443864 ps
T90 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.4142237405 Sep 24 08:48:04 AM UTC 24 Sep 24 08:48:37 AM UTC 24 3708252291 ps
T91 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1526779242 Sep 24 08:47:53 AM UTC 24 Sep 24 08:48:43 AM UTC 24 7305822584 ps
T95 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.548122360 Sep 24 08:47:51 AM UTC 24 Sep 24 08:48:46 AM UTC 24 14450866090 ps
T92 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2579976880 Sep 24 08:47:55 AM UTC 24 Sep 24 08:48:47 AM UTC 24 7478223447 ps
T1026 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3574427612 Sep 24 08:47:51 AM UTC 24 Sep 24 08:48:47 AM UTC 24 7962887576 ps
T1027 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.313091623 Sep 24 08:47:53 AM UTC 24 Sep 24 08:48:48 AM UTC 24 7351435084 ps
T1028 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.630874299 Sep 24 08:47:55 AM UTC 24 Sep 24 08:48:50 AM UTC 24 7181088355 ps
T1029 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.982537560 Sep 24 08:47:50 AM UTC 24 Sep 24 08:48:51 AM UTC 24 14100622448 ps
T1030 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2702202058 Sep 24 08:47:59 AM UTC 24 Sep 24 08:48:52 AM UTC 24 7424414821 ps
T1031 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3793596301 Sep 24 08:48:01 AM UTC 24 Sep 24 08:48:53 AM UTC 24 14711251764 ps
T1032 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1743092265 Sep 24 08:47:58 AM UTC 24 Sep 24 08:48:55 AM UTC 24 29387371002 ps
T1033 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.6208669 Sep 24 08:47:55 AM UTC 24 Sep 24 08:48:56 AM UTC 24 29333312115 ps
T1034 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3624092922 Sep 24 08:47:55 AM UTC 24 Sep 24 08:48:58 AM UTC 24 28105941994 ps
T1035 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1116062530 Sep 24 08:48:01 AM UTC 24 Sep 24 08:48:58 AM UTC 24 14093363643 ps
T1036 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3332099765 Sep 24 08:48:03 AM UTC 24 Sep 24 08:49:00 AM UTC 24 14694971483 ps
T1037 /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3823712091 Sep 24 08:48:00 AM UTC 24 Sep 24 08:49:07 AM UTC 24 100335057371 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.3378520034
Short name T5
Test name
Test status
Simulation time 788820219 ps
CPU time 10.5 seconds
Started Sep 24 09:49:08 AM UTC 24
Finished Sep 24 09:49:19 AM UTC 24
Peak memory 247612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3378520034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_
throughput_w_partial_write.3378520034
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/0.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.178081057
Short name T24
Test name
Test status
Simulation time 8257703574 ps
CPU time 76.98 seconds
Started Sep 24 09:49:40 AM UTC 24
Finished Sep 24 09:50:59 AM UTC 24
Peak memory 260412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178081057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.178081057
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/1.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.267186562
Short name T9
Test name
Test status
Simulation time 58349588908 ps
CPU time 64.76 seconds
Started Sep 24 09:49:08 AM UTC 24
Finished Sep 24 09:50:14 AM UTC 24
Peak memory 211796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267186562 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_escalation.267186562
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/0.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_regwen.1705138285
Short name T113
Test name
Test status
Simulation time 36869893347 ps
CPU time 615.91 seconds
Started Sep 24 09:51:00 AM UTC 24
Finished Sep 24 10:01:24 AM UTC 24
Peak memory 373164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705138285 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.1705138285
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/3.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.1881311892
Short name T6
Test name
Test status
Simulation time 115018909 ps
CPU time 2.79 seconds
Started Sep 24 09:49:40 AM UTC 24
Finished Sep 24 09:49:43 AM UTC 24
Peak memory 248356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881311892 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_sec_cm.1881311892
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2952021163
Short name T130
Test name
Test status
Simulation time 536851621 ps
CPU time 2.17 seconds
Started Sep 24 08:47:53 AM UTC 24
Finished Sep 24 08:47:56 AM UTC 24
Peak memory 224068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952
021163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_
intg_err.2952021163
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/4.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.940859925
Short name T59
Test name
Test status
Simulation time 8701916868 ps
CPU time 207.63 seconds
Started Sep 24 09:49:39 AM UTC 24
Finished Sep 24 09:53:10 AM UTC 24
Peak memory 212356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940859925 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_partial_acc
ess_b2b.940859925
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/1.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_regwen.1933314515
Short name T153
Test name
Test status
Simulation time 16117969119 ps
CPU time 1504.4 seconds
Started Sep 24 09:55:36 AM UTC 24
Finished Sep 24 10:20:58 AM UTC 24
Peak memory 391456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933314515 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.1933314515
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/5.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.415237881
Short name T70
Test name
Test status
Simulation time 34046233 ps
CPU time 0.68 seconds
Started Sep 24 08:47:51 AM UTC 24
Finished Sep 24 08:47:53 AM UTC 24
Peak memory 212496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415237881 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_rw.415237881
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/1.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.1669789606
Short name T84
Test name
Test status
Simulation time 4571248769 ps
CPU time 194.98 seconds
Started Sep 24 09:49:39 AM UTC 24
Finished Sep 24 09:52:58 AM UTC 24
Peak memory 229868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669789606 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_mem_partial_access.1669789606
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/1.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.3814565538
Short name T38
Test name
Test status
Simulation time 1415102221 ps
CPU time 47.02 seconds
Started Sep 24 09:51:10 AM UTC 24
Finished Sep 24 09:51:59 AM UTC 24
Peak memory 222716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814565538 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.3814565538
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/3.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.652225473
Short name T3
Test name
Test status
Simulation time 1019289141 ps
CPU time 3.86 seconds
Started Sep 24 09:49:08 AM UTC 24
Finished Sep 24 09:49:13 AM UTC 24
Peak memory 212288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652225473 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.652225473
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/0.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_regwen.2429762597
Short name T126
Test name
Test status
Simulation time 81971510632 ps
CPU time 1139.06 seconds
Started Sep 24 09:49:08 AM UTC 24
Finished Sep 24 10:08:19 AM UTC 24
Peak memory 386836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429762597 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.2429762597
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/0.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.3748007060
Short name T155
Test name
Test status
Simulation time 19495939033 ps
CPU time 105.25 seconds
Started Sep 24 10:11:16 AM UTC 24
Finished Sep 24 10:13:03 AM UTC 24
Peak memory 212492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748007060 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_escalation.3748007060
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/10.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_alert_test.20576730
Short name T1
Test name
Test status
Simulation time 15591825 ps
CPU time 0.89 seconds
Started Sep 24 09:49:08 AM UTC 24
Finished Sep 24 09:49:10 AM UTC 24
Peak memory 211492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20576730 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_alert_test.20576730
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/0.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.536732109
Short name T116
Test name
Test status
Simulation time 401305759 ps
CPU time 1.68 seconds
Started Sep 24 08:47:51 AM UTC 24
Finished Sep 24 08:47:54 AM UTC 24
Peak memory 222824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5367
32109 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_i
ntg_err.536732109
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/1.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1109952288
Short name T138
Test name
Test status
Simulation time 663070877 ps
CPU time 2.56 seconds
Started Sep 24 08:47:59 AM UTC 24
Finished Sep 24 08:48:02 AM UTC 24
Peak memory 224036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109
952288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl
_intg_err.1109952288
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/13.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.459027745
Short name T143
Test name
Test status
Simulation time 28069031014 ps
CPU time 115.74 seconds
Started Sep 24 10:54:51 AM UTC 24
Finished Sep 24 10:56:48 AM UTC 24
Peak memory 367016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459027745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.459027745
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/21.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2683230254
Short name T139
Test name
Test status
Simulation time 1924555905 ps
CPU time 2.77 seconds
Started Sep 24 08:48:00 AM UTC 24
Finished Sep 24 08:48:04 AM UTC 24
Peak memory 224036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683
230254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_tl
_intg_err.2683230254
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/14.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2290911205
Short name T136
Test name
Test status
Simulation time 868000377 ps
CPU time 2.33 seconds
Started Sep 24 08:48:04 AM UTC 24
Finished Sep 24 08:48:08 AM UTC 24
Peak memory 224044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290
911205 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl
_intg_err.2290911205
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/19.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3574427612
Short name T1026
Test name
Test status
Simulation time 7962887576 ps
CPU time 54.86 seconds
Started Sep 24 08:47:51 AM UTC 24
Finished Sep 24 08:48:47 AM UTC 24
Peak memory 214268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
574427612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_
passthru_mem_tl_intg_err.3574427612
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/1.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3244358318
Short name T69
Test name
Test status
Simulation time 16182372 ps
CPU time 0.73 seconds
Started Sep 24 08:47:50 AM UTC 24
Finished Sep 24 08:47:52 AM UTC 24
Peak memory 212344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244358
318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_al
iasing.3244358318
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2294335312
Short name T112
Test name
Test status
Simulation time 30349908 ps
CPU time 1.18 seconds
Started Sep 24 08:47:50 AM UTC 24
Finished Sep 24 08:47:52 AM UTC 24
Peak memory 212520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294335
312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_bi
t_bash.2294335312
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2818040016
Short name T68
Test name
Test status
Simulation time 50908162 ps
CPU time 0.67 seconds
Started Sep 24 08:47:50 AM UTC 24
Finished Sep 24 08:47:51 AM UTC 24
Peak memory 212612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818040
016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_hw
_reset.2818040016
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1426883311
Short name T959
Test name
Test status
Simulation time 1355088137 ps
CPU time 3.41 seconds
Started Sep 24 08:47:50 AM UTC 24
Finished Sep 24 08:47:54 AM UTC 24
Peak memory 224096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000
00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=1426883311 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.1426883311
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.185977465
Short name T111
Test name
Test status
Simulation time 25960029 ps
CPU time 0.68 seconds
Started Sep 24 08:47:50 AM UTC 24
Finished Sep 24 08:47:51 AM UTC 24
Peak memory 212516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185977465 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_rw.185977465
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.982537560
Short name T1029
Test name
Test status
Simulation time 14100622448 ps
CPU time 59.64 seconds
Started Sep 24 08:47:50 AM UTC 24
Finished Sep 24 08:48:51 AM UTC 24
Peak memory 213996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9
82537560 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_p
assthru_mem_tl_intg_err.982537560
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/0.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3904548516
Short name T98
Test name
Test status
Simulation time 24553854 ps
CPU time 0.76 seconds
Started Sep 24 08:47:50 AM UTC 24
Finished Sep 24 08:47:52 AM UTC 24
Peak memory 212684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000
00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=3904548516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram
_ctrl_same_csr_outstanding.3904548516
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/0.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1094989429
Short name T957
Test name
Test status
Simulation time 79290607 ps
CPU time 2.83 seconds
Started Sep 24 08:47:50 AM UTC 24
Finished Sep 24 08:47:54 AM UTC 24
Peak memory 226404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094989429 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_tl_errors.1094989429
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/0.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.27433529
Short name T115
Test name
Test status
Simulation time 255179311 ps
CPU time 1.63 seconds
Started Sep 24 08:47:50 AM UTC 24
Finished Sep 24 08:47:52 AM UTC 24
Peak memory 212688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743
3529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_tl_in
tg_err.27433529
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/0.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1803127501
Short name T71
Test name
Test status
Simulation time 24689507 ps
CPU time 0.75 seconds
Started Sep 24 08:47:51 AM UTC 24
Finished Sep 24 08:47:53 AM UTC 24
Peak memory 212344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803127
501 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_al
iasing.1803127501
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/1.sram_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.607660888
Short name T75
Test name
Test status
Simulation time 49049787 ps
CPU time 1.72 seconds
Started Sep 24 08:47:51 AM UTC 24
Finished Sep 24 08:47:54 AM UTC 24
Peak memory 212516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6076608
88 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_bit
_bash.607660888
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/1.sram_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2732894835
Short name T953
Test name
Test status
Simulation time 18101102 ps
CPU time 0.7 seconds
Started Sep 24 08:47:51 AM UTC 24
Finished Sep 24 08:47:53 AM UTC 24
Peak memory 212632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732894
835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_hw
_reset.2732894835
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/1.sram_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1977893813
Short name T971
Test name
Test status
Simulation time 1452707983 ps
CPU time 4.58 seconds
Started Sep 24 08:47:51 AM UTC 24
Finished Sep 24 08:47:57 AM UTC 24
Peak memory 224300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000
00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=1977893813 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.1977893813
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2274012978
Short name T100
Test name
Test status
Simulation time 58291095 ps
CPU time 0.81 seconds
Started Sep 24 08:47:51 AM UTC 24
Finished Sep 24 08:47:53 AM UTC 24
Peak memory 212684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000
00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=2274012978 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram
_ctrl_same_csr_outstanding.2274012978
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/1.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.894830187
Short name T962
Test name
Test status
Simulation time 107571161 ps
CPU time 2.88 seconds
Started Sep 24 08:47:51 AM UTC 24
Finished Sep 24 08:47:55 AM UTC 24
Peak memory 224032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894830187 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_errors.894830187
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/1.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.632131392
Short name T996
Test name
Test status
Simulation time 1429452606 ps
CPU time 4.57 seconds
Started Sep 24 08:47:57 AM UTC 24
Finished Sep 24 08:48:03 AM UTC 24
Peak memory 224424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000
00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=632131392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.632131392
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3674474503
Short name T81
Test name
Test status
Simulation time 14606810 ps
CPU time 0.78 seconds
Started Sep 24 08:47:57 AM UTC 24
Finished Sep 24 08:47:59 AM UTC 24
Peak memory 212732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674474503 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_rw.3674474503
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/10.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3865496414
Short name T89
Test name
Test status
Simulation time 3884262938 ps
CPU time 29.05 seconds
Started Sep 24 08:47:57 AM UTC 24
Finished Sep 24 08:48:27 AM UTC 24
Peak memory 214056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
865496414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl
_passthru_mem_tl_intg_err.3865496414
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/10.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2920568121
Short name T981
Test name
Test status
Simulation time 12209894 ps
CPU time 0.93 seconds
Started Sep 24 08:47:57 AM UTC 24
Finished Sep 24 08:47:59 AM UTC 24
Peak memory 212684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000
00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=2920568121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sra
m_ctrl_same_csr_outstanding.2920568121
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/10.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3794308077
Short name T990
Test name
Test status
Simulation time 93905308 ps
CPU time 3.17 seconds
Started Sep 24 08:47:57 AM UTC 24
Finished Sep 24 08:48:01 AM UTC 24
Peak memory 224104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794308077 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl_errors.3794308077
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/10.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2883380710
Short name T132
Test name
Test status
Simulation time 271178270 ps
CPU time 2.87 seconds
Started Sep 24 08:47:57 AM UTC 24
Finished Sep 24 08:48:01 AM UTC 24
Peak memory 223988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883
380710 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl
_intg_err.2883380710
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/10.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2386095651
Short name T1002
Test name
Test status
Simulation time 1437027108 ps
CPU time 4.21 seconds
Started Sep 24 08:47:58 AM UTC 24
Finished Sep 24 08:48:03 AM UTC 24
Peak memory 223776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000
00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=2386095651 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.2386095651
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2228640279
Short name T969
Test name
Test status
Simulation time 52952112 ps
CPU time 0.86 seconds
Started Sep 24 08:47:58 AM UTC 24
Finished Sep 24 08:48:00 AM UTC 24
Peak memory 212516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228640279 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_rw.2228640279
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/11.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3841596199
Short name T94
Test name
Test status
Simulation time 4470395810 ps
CPU time 29.41 seconds
Started Sep 24 08:47:57 AM UTC 24
Finished Sep 24 08:48:28 AM UTC 24
Peak memory 213732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
841596199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl
_passthru_mem_tl_intg_err.3841596199
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/11.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1915489391
Short name T979
Test name
Test status
Simulation time 59664115 ps
CPU time 0.94 seconds
Started Sep 24 08:47:58 AM UTC 24
Finished Sep 24 08:48:00 AM UTC 24
Peak memory 212576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000
00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=1915489391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sra
m_ctrl_same_csr_outstanding.1915489391
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/11.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.63336428
Short name T997
Test name
Test status
Simulation time 489848996 ps
CPU time 4.59 seconds
Started Sep 24 08:47:57 AM UTC 24
Finished Sep 24 08:48:03 AM UTC 24
Peak memory 224040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63336428 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl_errors.63336428
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/11.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2893926127
Short name T131
Test name
Test status
Simulation time 238910161 ps
CPU time 1.92 seconds
Started Sep 24 08:47:57 AM UTC 24
Finished Sep 24 08:48:00 AM UTC 24
Peak memory 222584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893
926127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl
_intg_err.2893926127
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/11.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1252740945
Short name T1006
Test name
Test status
Simulation time 358217058 ps
CPU time 4.66 seconds
Started Sep 24 08:47:58 AM UTC 24
Finished Sep 24 08:48:04 AM UTC 24
Peak memory 224380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000
00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=1252740945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.1252740945
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3609211845
Short name T987
Test name
Test status
Simulation time 12108423 ps
CPU time 0.98 seconds
Started Sep 24 08:47:58 AM UTC 24
Finished Sep 24 08:48:00 AM UTC 24
Peak memory 211980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609211845 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_rw.3609211845
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/12.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1743092265
Short name T1032
Test name
Test status
Simulation time 29387371002 ps
CPU time 55.62 seconds
Started Sep 24 08:47:58 AM UTC 24
Finished Sep 24 08:48:55 AM UTC 24
Peak memory 213924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1
743092265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl
_passthru_mem_tl_intg_err.1743092265
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/12.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3423374507
Short name T986
Test name
Test status
Simulation time 49442839 ps
CPU time 0.93 seconds
Started Sep 24 08:47:58 AM UTC 24
Finished Sep 24 08:48:00 AM UTC 24
Peak memory 212576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000
00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=3423374507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sra
m_ctrl_same_csr_outstanding.3423374507
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/12.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3847581523
Short name T998
Test name
Test status
Simulation time 1483876376 ps
CPU time 3.7 seconds
Started Sep 24 08:47:58 AM UTC 24
Finished Sep 24 08:48:03 AM UTC 24
Peak memory 214060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847581523 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl_errors.3847581523
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/12.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3523609556
Short name T133
Test name
Test status
Simulation time 484888503 ps
CPU time 2.43 seconds
Started Sep 24 08:47:58 AM UTC 24
Finished Sep 24 08:48:02 AM UTC 24
Peak memory 223916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523
609556 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl
_intg_err.3523609556
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/12.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.269512966
Short name T1009
Test name
Test status
Simulation time 377578918 ps
CPU time 4.46 seconds
Started Sep 24 08:48:00 AM UTC 24
Finished Sep 24 08:48:05 AM UTC 24
Peak memory 224096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000
00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=269512966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.269512966
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1872783798
Short name T82
Test name
Test status
Simulation time 29974285 ps
CPU time 0.75 seconds
Started Sep 24 08:47:59 AM UTC 24
Finished Sep 24 08:48:00 AM UTC 24
Peak memory 212732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872783798 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_rw.1872783798
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/13.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2702202058
Short name T1030
Test name
Test status
Simulation time 7424414821 ps
CPU time 51.9 seconds
Started Sep 24 08:47:59 AM UTC 24
Finished Sep 24 08:48:52 AM UTC 24
Peak memory 214004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2
702202058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl
_passthru_mem_tl_intg_err.2702202058
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/13.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1048528532
Short name T992
Test name
Test status
Simulation time 29092623 ps
CPU time 0.96 seconds
Started Sep 24 08:48:00 AM UTC 24
Finished Sep 24 08:48:02 AM UTC 24
Peak memory 212336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000
00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=1048528532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sra
m_ctrl_same_csr_outstanding.1048528532
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/13.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2826305086
Short name T1003
Test name
Test status
Simulation time 479349407 ps
CPU time 4.25 seconds
Started Sep 24 08:47:59 AM UTC 24
Finished Sep 24 08:48:04 AM UTC 24
Peak memory 224096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826305086 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl_errors.2826305086
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/13.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3900231550
Short name T1018
Test name
Test status
Simulation time 6793599705 ps
CPU time 5.91 seconds
Started Sep 24 08:48:00 AM UTC 24
Finished Sep 24 08:48:07 AM UTC 24
Peak memory 224232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000
00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=3900231550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.3900231550
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2034440369
Short name T993
Test name
Test status
Simulation time 20746113 ps
CPU time 0.85 seconds
Started Sep 24 08:48:00 AM UTC 24
Finished Sep 24 08:48:02 AM UTC 24
Peak memory 212732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034440369 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_rw.2034440369
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/14.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3823712091
Short name T1037
Test name
Test status
Simulation time 100335057371 ps
CPU time 65.79 seconds
Started Sep 24 08:48:00 AM UTC 24
Finished Sep 24 08:49:07 AM UTC 24
Peak memory 213980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
823712091 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl
_passthru_mem_tl_intg_err.3823712091
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/14.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2449815772
Short name T994
Test name
Test status
Simulation time 15461737 ps
CPU time 0.85 seconds
Started Sep 24 08:48:00 AM UTC 24
Finished Sep 24 08:48:02 AM UTC 24
Peak memory 212336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000
00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=2449815772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sra
m_ctrl_same_csr_outstanding.2449815772
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/14.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3306533684
Short name T999
Test name
Test status
Simulation time 72775025 ps
CPU time 2.22 seconds
Started Sep 24 08:48:00 AM UTC 24
Finished Sep 24 08:48:03 AM UTC 24
Peak memory 213808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306533684 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_tl_errors.3306533684
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/14.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.664824488
Short name T1011
Test name
Test status
Simulation time 1359817734 ps
CPU time 3.81 seconds
Started Sep 24 08:48:01 AM UTC 24
Finished Sep 24 08:48:06 AM UTC 24
Peak memory 223848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000
00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=664824488 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.664824488
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.103138695
Short name T1000
Test name
Test status
Simulation time 34368485 ps
CPU time 0.86 seconds
Started Sep 24 08:48:01 AM UTC 24
Finished Sep 24 08:48:03 AM UTC 24
Peak memory 212516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103138695 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_rw.103138695
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/15.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1116062530
Short name T1035
Test name
Test status
Simulation time 14093363643 ps
CPU time 55.62 seconds
Started Sep 24 08:48:01 AM UTC 24
Finished Sep 24 08:48:58 AM UTC 24
Peak memory 214008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1
116062530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl
_passthru_mem_tl_intg_err.1116062530
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/15.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1896727387
Short name T1001
Test name
Test status
Simulation time 16865933 ps
CPU time 0.93 seconds
Started Sep 24 08:48:01 AM UTC 24
Finished Sep 24 08:48:03 AM UTC 24
Peak memory 212684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000
00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=1896727387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sra
m_ctrl_same_csr_outstanding.1896727387
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/15.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.870120077
Short name T1012
Test name
Test status
Simulation time 455997320 ps
CPU time 4.18 seconds
Started Sep 24 08:48:01 AM UTC 24
Finished Sep 24 08:48:06 AM UTC 24
Peak memory 224032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870120077 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl_errors.870120077
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/15.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2891566675
Short name T1005
Test name
Test status
Simulation time 157063411 ps
CPU time 1.84 seconds
Started Sep 24 08:48:01 AM UTC 24
Finished Sep 24 08:48:04 AM UTC 24
Peak memory 222824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891
566675 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl
_intg_err.2891566675
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/15.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2194230779
Short name T1019
Test name
Test status
Simulation time 1599638233 ps
CPU time 5.31 seconds
Started Sep 24 08:48:02 AM UTC 24
Finished Sep 24 08:48:08 AM UTC 24
Peak memory 228072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000
00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=2194230779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.2194230779
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1514538010
Short name T83
Test name
Test status
Simulation time 27749867 ps
CPU time 0.74 seconds
Started Sep 24 08:48:02 AM UTC 24
Finished Sep 24 08:48:03 AM UTC 24
Peak memory 212500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514538010 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_rw.1514538010
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/16.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3793596301
Short name T1031
Test name
Test status
Simulation time 14711251764 ps
CPU time 49.72 seconds
Started Sep 24 08:48:01 AM UTC 24
Finished Sep 24 08:48:53 AM UTC 24
Peak memory 213984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
793596301 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl
_passthru_mem_tl_intg_err.3793596301
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/16.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2420762178
Short name T1004
Test name
Test status
Simulation time 55699088 ps
CPU time 1.22 seconds
Started Sep 24 08:48:02 AM UTC 24
Finished Sep 24 08:48:04 AM UTC 24
Peak memory 212684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000
00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=2420762178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sra
m_ctrl_same_csr_outstanding.2420762178
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/16.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3981648189
Short name T1010
Test name
Test status
Simulation time 63006071 ps
CPU time 3.03 seconds
Started Sep 24 08:48:01 AM UTC 24
Finished Sep 24 08:48:05 AM UTC 24
Peak memory 213784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981648189 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl_errors.3981648189
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/16.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3706119220
Short name T140
Test name
Test status
Simulation time 611121590 ps
CPU time 2.26 seconds
Started Sep 24 08:48:02 AM UTC 24
Finished Sep 24 08:48:05 AM UTC 24
Peak memory 224064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706
119220 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl
_intg_err.3706119220
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/16.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1153314646
Short name T1020
Test name
Test status
Simulation time 717135114 ps
CPU time 4.32 seconds
Started Sep 24 08:48:03 AM UTC 24
Finished Sep 24 08:48:08 AM UTC 24
Peak memory 224120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000
00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=1153314646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.1153314646
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2096281169
Short name T1007
Test name
Test status
Simulation time 51395549 ps
CPU time 1.01 seconds
Started Sep 24 08:48:03 AM UTC 24
Finished Sep 24 08:48:05 AM UTC 24
Peak memory 212732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096281169 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_rw.2096281169
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/17.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.861291316
Short name T1025
Test name
Test status
Simulation time 14236443864 ps
CPU time 31.74 seconds
Started Sep 24 08:48:03 AM UTC 24
Finished Sep 24 08:48:36 AM UTC 24
Peak memory 214120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8
61291316 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_
passthru_mem_tl_intg_err.861291316
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/17.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2621613430
Short name T1008
Test name
Test status
Simulation time 160630636 ps
CPU time 1.01 seconds
Started Sep 24 08:48:03 AM UTC 24
Finished Sep 24 08:48:05 AM UTC 24
Peak memory 212684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000
00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=2621613430 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sra
m_ctrl_same_csr_outstanding.2621613430
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/17.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.551122936
Short name T1016
Test name
Test status
Simulation time 500504672 ps
CPU time 2.83 seconds
Started Sep 24 08:48:03 AM UTC 24
Finished Sep 24 08:48:07 AM UTC 24
Peak memory 224364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551122936 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_errors.551122936
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/17.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1381119226
Short name T1017
Test name
Test status
Simulation time 605279562 ps
CPU time 2.83 seconds
Started Sep 24 08:48:03 AM UTC 24
Finished Sep 24 08:48:07 AM UTC 24
Peak memory 224100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381
119226 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl
_intg_err.1381119226
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/17.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2957382524
Short name T1024
Test name
Test status
Simulation time 1361001000 ps
CPU time 5.01 seconds
Started Sep 24 08:48:04 AM UTC 24
Finished Sep 24 08:48:10 AM UTC 24
Peak memory 224104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000
00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=2957382524 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.2957382524
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1537336645
Short name T93
Test name
Test status
Simulation time 23462380 ps
CPU time 1 seconds
Started Sep 24 08:48:04 AM UTC 24
Finished Sep 24 08:48:06 AM UTC 24
Peak memory 212732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537336645 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_rw.1537336645
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/18.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3332099765
Short name T1036
Test name
Test status
Simulation time 14694971483 ps
CPU time 55.03 seconds
Started Sep 24 08:48:03 AM UTC 24
Finished Sep 24 08:49:00 AM UTC 24
Peak memory 213928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
332099765 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl
_passthru_mem_tl_intg_err.3332099765
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/18.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2346920796
Short name T1013
Test name
Test status
Simulation time 26053380 ps
CPU time 1.21 seconds
Started Sep 24 08:48:04 AM UTC 24
Finished Sep 24 08:48:07 AM UTC 24
Peak memory 212684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000
00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=2346920796 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sra
m_ctrl_same_csr_outstanding.2346920796
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/18.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2617717386
Short name T1022
Test name
Test status
Simulation time 108444190 ps
CPU time 4.74 seconds
Started Sep 24 08:48:03 AM UTC 24
Finished Sep 24 08:48:09 AM UTC 24
Peak memory 224304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617717386 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_tl_errors.2617717386
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/18.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1382507544
Short name T141
Test name
Test status
Simulation time 406760392 ps
CPU time 2.74 seconds
Started Sep 24 08:48:03 AM UTC 24
Finished Sep 24 08:48:07 AM UTC 24
Peak memory 223972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382
507544 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_tl
_intg_err.1382507544
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/18.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.522068345
Short name T1023
Test name
Test status
Simulation time 1739509510 ps
CPU time 4.14 seconds
Started Sep 24 08:48:05 AM UTC 24
Finished Sep 24 08:48:10 AM UTC 24
Peak memory 223844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000
00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=522068345 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.522068345
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.390171027
Short name T1014
Test name
Test status
Simulation time 71995168 ps
CPU time 1.06 seconds
Started Sep 24 08:48:04 AM UTC 24
Finished Sep 24 08:48:07 AM UTC 24
Peak memory 212400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390171027 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_rw.390171027
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/19.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.4142237405
Short name T90
Test name
Test status
Simulation time 3708252291 ps
CPU time 30.91 seconds
Started Sep 24 08:48:04 AM UTC 24
Finished Sep 24 08:48:37 AM UTC 24
Peak memory 214052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4
142237405 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl
_passthru_mem_tl_intg_err.4142237405
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/19.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3659904984
Short name T1015
Test name
Test status
Simulation time 54639742 ps
CPU time 1.17 seconds
Started Sep 24 08:48:05 AM UTC 24
Finished Sep 24 08:48:07 AM UTC 24
Peak memory 212684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000
00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=3659904984 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sra
m_ctrl_same_csr_outstanding.3659904984
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/19.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1000608084
Short name T1021
Test name
Test status
Simulation time 91970467 ps
CPU time 3.11 seconds
Started Sep 24 08:48:04 AM UTC 24
Finished Sep 24 08:48:09 AM UTC 24
Peak memory 214140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000608084 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl_errors.1000608084
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/19.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2275075414
Short name T954
Test name
Test status
Simulation time 30054418 ps
CPU time 0.76 seconds
Started Sep 24 08:47:51 AM UTC 24
Finished Sep 24 08:47:53 AM UTC 24
Peak memory 212520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275075
414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_al
iasing.2275075414
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/2.sram_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1313609589
Short name T961
Test name
Test status
Simulation time 155371978 ps
CPU time 2.04 seconds
Started Sep 24 08:47:51 AM UTC 24
Finished Sep 24 08:47:55 AM UTC 24
Peak memory 213768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313609
589 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_bi
t_bash.1313609589
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/2.sram_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3794801685
Short name T72
Test name
Test status
Simulation time 34652693 ps
CPU time 0.8 seconds
Started Sep 24 08:47:51 AM UTC 24
Finished Sep 24 08:47:53 AM UTC 24
Peak memory 212632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794801
685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_hw
_reset.3794801685
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/2.sram_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.59242349
Short name T974
Test name
Test status
Simulation time 1444923846 ps
CPU time 4.28 seconds
Started Sep 24 08:47:52 AM UTC 24
Finished Sep 24 08:47:57 AM UTC 24
Peak memory 223764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000
00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=59242349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.59242349
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3765465118
Short name T99
Test name
Test status
Simulation time 49071158 ps
CPU time 0.68 seconds
Started Sep 24 08:47:51 AM UTC 24
Finished Sep 24 08:47:53 AM UTC 24
Peak memory 212516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765465118 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_rw.3765465118
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/2.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.548122360
Short name T95
Test name
Test status
Simulation time 14450866090 ps
CPU time 53.34 seconds
Started Sep 24 08:47:51 AM UTC 24
Finished Sep 24 08:48:46 AM UTC 24
Peak memory 214056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5
48122360 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_p
assthru_mem_tl_intg_err.548122360
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/2.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2892919551
Short name T73
Test name
Test status
Simulation time 45451841 ps
CPU time 0.75 seconds
Started Sep 24 08:47:51 AM UTC 24
Finished Sep 24 08:47:53 AM UTC 24
Peak memory 212576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000
00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=2892919551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram
_ctrl_same_csr_outstanding.2892919551
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/2.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.4177722466
Short name T968
Test name
Test status
Simulation time 257429654 ps
CPU time 4.4 seconds
Started Sep 24 08:47:51 AM UTC 24
Finished Sep 24 08:47:57 AM UTC 24
Peak memory 213864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177722466 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_errors.4177722466
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/2.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.6381717
Short name T128
Test name
Test status
Simulation time 330757734 ps
CPU time 2.17 seconds
Started Sep 24 08:47:51 AM UTC 24
Finished Sep 24 08:47:54 AM UTC 24
Peak memory 223976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6381
717 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_int
g_err.6381717
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/2.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1316950106
Short name T74
Test name
Test status
Simulation time 56218261 ps
CPU time 0.79 seconds
Started Sep 24 08:47:52 AM UTC 24
Finished Sep 24 08:47:54 AM UTC 24
Peak memory 212344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316950
106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_al
iasing.1316950106
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/3.sram_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.397541652
Short name T958
Test name
Test status
Simulation time 104523522 ps
CPU time 1.23 seconds
Started Sep 24 08:47:52 AM UTC 24
Finished Sep 24 08:47:54 AM UTC 24
Peak memory 212340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975416
52 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_bit
_bash.397541652
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/3.sram_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.545412582
Short name T956
Test name
Test status
Simulation time 15054488 ps
CPU time 0.72 seconds
Started Sep 24 08:47:52 AM UTC 24
Finished Sep 24 08:47:53 AM UTC 24
Peak memory 212504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5454125
82 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_hw_
reset.545412582
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/3.sram_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2997934642
Short name T967
Test name
Test status
Simulation time 558098303 ps
CPU time 3.37 seconds
Started Sep 24 08:47:52 AM UTC 24
Finished Sep 24 08:47:56 AM UTC 24
Peak memory 227956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000
00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=2997934642 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.2997934642
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3020721596
Short name T955
Test name
Test status
Simulation time 31428446 ps
CPU time 0.67 seconds
Started Sep 24 08:47:52 AM UTC 24
Finished Sep 24 08:47:53 AM UTC 24
Peak memory 212340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020721596 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_rw.3020721596
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/3.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3505605229
Short name T88
Test name
Test status
Simulation time 4031824288 ps
CPU time 30.15 seconds
Started Sep 24 08:47:52 AM UTC 24
Finished Sep 24 08:48:23 AM UTC 24
Peak memory 213808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
505605229 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_
passthru_mem_tl_intg_err.3505605229
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/3.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3284468130
Short name T101
Test name
Test status
Simulation time 15450154 ps
CPU time 0.86 seconds
Started Sep 24 08:47:52 AM UTC 24
Finished Sep 24 08:47:54 AM UTC 24
Peak memory 212684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000
00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=3284468130 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram
_ctrl_same_csr_outstanding.3284468130
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/3.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3730675596
Short name T966
Test name
Test status
Simulation time 288782611 ps
CPU time 3.01 seconds
Started Sep 24 08:47:52 AM UTC 24
Finished Sep 24 08:47:56 AM UTC 24
Peak memory 214116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730675596 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_errors.3730675596
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/3.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1764155610
Short name T117
Test name
Test status
Simulation time 365165198 ps
CPU time 1.54 seconds
Started Sep 24 08:47:52 AM UTC 24
Finished Sep 24 08:47:54 AM UTC 24
Peak memory 224324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764
155610 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_
intg_err.1764155610
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/3.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2008860717
Short name T79
Test name
Test status
Simulation time 13480222 ps
CPU time 0.79 seconds
Started Sep 24 08:47:53 AM UTC 24
Finished Sep 24 08:47:55 AM UTC 24
Peak memory 212520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008860
717 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_al
iasing.2008860717
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/4.sram_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.649651885
Short name T964
Test name
Test status
Simulation time 71969280 ps
CPU time 1.41 seconds
Started Sep 24 08:47:53 AM UTC 24
Finished Sep 24 08:47:56 AM UTC 24
Peak memory 212564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6496518
85 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_bit
_bash.649651885
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/4.sram_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1653064225
Short name T76
Test name
Test status
Simulation time 22444886 ps
CPU time 0.79 seconds
Started Sep 24 08:47:53 AM UTC 24
Finished Sep 24 08:47:55 AM UTC 24
Peak memory 211752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653064
225 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_hw
_reset.1653064225
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/4.sram_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3222897079
Short name T977
Test name
Test status
Simulation time 721775404 ps
CPU time 3.99 seconds
Started Sep 24 08:47:53 AM UTC 24
Finished Sep 24 08:47:58 AM UTC 24
Peak memory 223772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000
00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=3222897079 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.3222897079
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1581626159
Short name T77
Test name
Test status
Simulation time 16915117 ps
CPU time 0.7 seconds
Started Sep 24 08:47:53 AM UTC 24
Finished Sep 24 08:47:55 AM UTC 24
Peak memory 212340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581626159 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_rw.1581626159
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/4.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.313091623
Short name T1027
Test name
Test status
Simulation time 7351435084 ps
CPU time 53.18 seconds
Started Sep 24 08:47:53 AM UTC 24
Finished Sep 24 08:48:48 AM UTC 24
Peak memory 213996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
13091623 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_p
assthru_mem_tl_intg_err.313091623
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/4.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1181008129
Short name T102
Test name
Test status
Simulation time 66815094 ps
CPU time 0.9 seconds
Started Sep 24 08:47:53 AM UTC 24
Finished Sep 24 08:47:55 AM UTC 24
Peak memory 212576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000
00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=1181008129 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram
_ctrl_same_csr_outstanding.1181008129
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/4.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1545986968
Short name T965
Test name
Test status
Simulation time 185985980 ps
CPU time 1.76 seconds
Started Sep 24 08:47:53 AM UTC 24
Finished Sep 24 08:47:56 AM UTC 24
Peak memory 212580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545986968 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_errors.1545986968
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/4.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2365918545
Short name T982
Test name
Test status
Simulation time 1435710861 ps
CPU time 4.42 seconds
Started Sep 24 08:47:54 AM UTC 24
Finished Sep 24 08:47:59 AM UTC 24
Peak memory 224344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000
00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=2365918545 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.2365918545
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2572631888
Short name T963
Test name
Test status
Simulation time 14678991 ps
CPU time 0.76 seconds
Started Sep 24 08:47:53 AM UTC 24
Finished Sep 24 08:47:55 AM UTC 24
Peak memory 212516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572631888 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_rw.2572631888
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/5.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.1526779242
Short name T91
Test name
Test status
Simulation time 7305822584 ps
CPU time 48.32 seconds
Started Sep 24 08:47:53 AM UTC 24
Finished Sep 24 08:48:43 AM UTC 24
Peak memory 214012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1
526779242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_
passthru_mem_tl_intg_err.1526779242
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/5.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1961195378
Short name T103
Test name
Test status
Simulation time 49653189 ps
CPU time 0.82 seconds
Started Sep 24 08:47:54 AM UTC 24
Finished Sep 24 08:47:55 AM UTC 24
Peak memory 212576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000
00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=1961195378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram
_ctrl_same_csr_outstanding.1961195378
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/5.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3318955306
Short name T970
Test name
Test status
Simulation time 68421529 ps
CPU time 2.55 seconds
Started Sep 24 08:47:53 AM UTC 24
Finished Sep 24 08:47:57 AM UTC 24
Peak memory 224228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318955306 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_errors.3318955306
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/5.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3420319556
Short name T129
Test name
Test status
Simulation time 353179057 ps
CPU time 1.56 seconds
Started Sep 24 08:47:53 AM UTC 24
Finished Sep 24 08:47:56 AM UTC 24
Peak memory 222824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420
319556 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_
intg_err.3420319556
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/5.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1561504419
Short name T984
Test name
Test status
Simulation time 370066888 ps
CPU time 3.72 seconds
Started Sep 24 08:47:55 AM UTC 24
Finished Sep 24 08:48:00 AM UTC 24
Peak memory 224020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000
00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=1561504419 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.1561504419
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.542579433
Short name T104
Test name
Test status
Simulation time 36347313 ps
CPU time 0.72 seconds
Started Sep 24 08:47:55 AM UTC 24
Finished Sep 24 08:47:57 AM UTC 24
Peak memory 212404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542579433 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_rw.542579433
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/6.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3624092922
Short name T1034
Test name
Test status
Simulation time 28105941994 ps
CPU time 61.38 seconds
Started Sep 24 08:47:55 AM UTC 24
Finished Sep 24 08:48:58 AM UTC 24
Peak memory 214008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
624092922 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_
passthru_mem_tl_intg_err.3624092922
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/6.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.69053003
Short name T105
Test name
Test status
Simulation time 43614697 ps
CPU time 0.93 seconds
Started Sep 24 08:47:55 AM UTC 24
Finished Sep 24 08:47:57 AM UTC 24
Peak memory 212680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000
00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=69053003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_c
trl_same_csr_outstanding.69053003
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/6.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2097666281
Short name T976
Test name
Test status
Simulation time 252719650 ps
CPU time 2.15 seconds
Started Sep 24 08:47:55 AM UTC 24
Finished Sep 24 08:47:58 AM UTC 24
Peak memory 224124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097666281 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_errors.2097666281
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/6.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.833176715
Short name T134
Test name
Test status
Simulation time 287461297 ps
CPU time 1.57 seconds
Started Sep 24 08:47:55 AM UTC 24
Finished Sep 24 08:47:57 AM UTC 24
Peak memory 212584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8331
76715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_i
ntg_err.833176715
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/6.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2077518992
Short name T989
Test name
Test status
Simulation time 1237456042 ps
CPU time 4.75 seconds
Started Sep 24 08:47:55 AM UTC 24
Finished Sep 24 08:48:01 AM UTC 24
Peak memory 224124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000
00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=2077518992 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.2077518992
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2647277365
Short name T973
Test name
Test status
Simulation time 13170408 ps
CPU time 0.93 seconds
Started Sep 24 08:47:55 AM UTC 24
Finished Sep 24 08:47:57 AM UTC 24
Peak memory 212340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647277365 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_rw.2647277365
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/7.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.630874299
Short name T1028
Test name
Test status
Simulation time 7181088355 ps
CPU time 53.93 seconds
Started Sep 24 08:47:55 AM UTC 24
Finished Sep 24 08:48:50 AM UTC 24
Peak memory 214052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6
30874299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_p
assthru_mem_tl_intg_err.630874299
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/7.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2354249134
Short name T972
Test name
Test status
Simulation time 71068273 ps
CPU time 0.87 seconds
Started Sep 24 08:47:55 AM UTC 24
Finished Sep 24 08:47:57 AM UTC 24
Peak memory 212576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000
00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=2354249134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram
_ctrl_same_csr_outstanding.2354249134
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/7.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1926492963
Short name T991
Test name
Test status
Simulation time 161676585 ps
CPU time 5.01 seconds
Started Sep 24 08:47:55 AM UTC 24
Finished Sep 24 08:48:01 AM UTC 24
Peak memory 224052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926492963 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_tl_errors.1926492963
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/7.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1524585165
Short name T137
Test name
Test status
Simulation time 296921030 ps
CPU time 1.74 seconds
Started Sep 24 08:47:55 AM UTC 24
Finished Sep 24 08:47:58 AM UTC 24
Peak memory 212612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524
585165 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_tl_
intg_err.1524585165
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/7.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2410282856
Short name T988
Test name
Test status
Simulation time 1377587641 ps
CPU time 4.14 seconds
Started Sep 24 08:47:55 AM UTC 24
Finished Sep 24 08:48:01 AM UTC 24
Peak memory 223840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000
00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=2410282856 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.2410282856
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3768253251
Short name T80
Test name
Test status
Simulation time 31762371 ps
CPU time 0.85 seconds
Started Sep 24 08:47:55 AM UTC 24
Finished Sep 24 08:47:57 AM UTC 24
Peak memory 212340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768253251 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_rw.3768253251
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/8.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.6208669
Short name T1033
Test name
Test status
Simulation time 29333312115 ps
CPU time 59.58 seconds
Started Sep 24 08:47:55 AM UTC 24
Finished Sep 24 08:48:56 AM UTC 24
Peak memory 213972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6
208669 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_pas
sthru_mem_tl_intg_err.6208669
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/8.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1091984319
Short name T975
Test name
Test status
Simulation time 78187624 ps
CPU time 0.82 seconds
Started Sep 24 08:47:55 AM UTC 24
Finished Sep 24 08:47:57 AM UTC 24
Peak memory 212576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000
00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=1091984319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram
_ctrl_same_csr_outstanding.1091984319
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/8.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1796982278
Short name T960
Test name
Test status
Simulation time 254673588 ps
CPU time 3.9 seconds
Started Sep 24 08:47:55 AM UTC 24
Finished Sep 24 08:48:00 AM UTC 24
Peak memory 213868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796982278 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_errors.1796982278
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/8.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3588348471
Short name T135
Test name
Test status
Simulation time 345297559 ps
CPU time 2.85 seconds
Started Sep 24 08:47:55 AM UTC 24
Finished Sep 24 08:47:59 AM UTC 24
Peak memory 224008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588
348471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_
intg_err.3588348471
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/8.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3771561327
Short name T995
Test name
Test status
Simulation time 426390047 ps
CPU time 4.16 seconds
Started Sep 24 08:47:57 AM UTC 24
Finished Sep 24 08:48:02 AM UTC 24
Peak memory 225748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000
00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=3771561327 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.3771561327
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2864814900
Short name T978
Test name
Test status
Simulation time 20106664 ps
CPU time 0.77 seconds
Started Sep 24 08:47:57 AM UTC 24
Finished Sep 24 08:47:58 AM UTC 24
Peak memory 212516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864814900 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_rw.2864814900
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/9.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2579976880
Short name T92
Test name
Test status
Simulation time 7478223447 ps
CPU time 50.01 seconds
Started Sep 24 08:47:55 AM UTC 24
Finished Sep 24 08:48:47 AM UTC 24
Peak memory 214068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2
579976880 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_
passthru_mem_tl_intg_err.2579976880
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/9.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1025521019
Short name T980
Test name
Test status
Simulation time 28180207 ps
CPU time 1.03 seconds
Started Sep 24 08:47:57 AM UTC 24
Finished Sep 24 08:47:59 AM UTC 24
Peak memory 212684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000
00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=1025521019 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram
_ctrl_same_csr_outstanding.1025521019
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/9.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.614954213
Short name T985
Test name
Test status
Simulation time 21618791 ps
CPU time 2.18 seconds
Started Sep 24 08:47:57 AM UTC 24
Finished Sep 24 08:48:00 AM UTC 24
Peak memory 224140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614954213 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_errors.614954213
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/9.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2786270317
Short name T983
Test name
Test status
Simulation time 609800344 ps
CPU time 1.83 seconds
Started Sep 24 08:47:57 AM UTC 24
Finished Sep 24 08:47:59 AM UTC 24
Peak memory 224324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786
270317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_
intg_err.2786270317
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/9.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.2239321749
Short name T195
Test name
Test status
Simulation time 108935553557 ps
CPU time 899 seconds
Started Sep 24 09:49:08 AM UTC 24
Finished Sep 24 10:04:17 AM UTC 24
Peak memory 390944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239321749 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_access_durin
g_key_req.2239321749
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/0.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_bijection.1757448445
Short name T319
Test name
Test status
Simulation time 138846304760 ps
CPU time 2761.99 seconds
Started Sep 24 09:49:08 AM UTC 24
Finished Sep 24 10:35:40 AM UTC 24
Peak memory 213912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757448445 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.1757448445
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/0.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_executable.3356481265
Short name T26
Test name
Test status
Simulation time 9954264968 ps
CPU time 350.42 seconds
Started Sep 24 09:49:08 AM UTC 24
Finished Sep 24 09:55:03 AM UTC 24
Peak memory 368824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356481265 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executable.3356481265
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/0.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.1355583146
Short name T29
Test name
Test status
Simulation time 796188904 ps
CPU time 45.11 seconds
Started Sep 24 09:49:08 AM UTC 24
Finished Sep 24 09:49:54 AM UTC 24
Peak memory 358828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1355583146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_m
ax_throughput.1355583146
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/0.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.2938286315
Short name T42
Test name
Test status
Simulation time 3133609629 ps
CPU time 99.95 seconds
Started Sep 24 09:49:08 AM UTC 24
Finished Sep 24 09:50:50 AM UTC 24
Peak memory 222608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938286315 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_mem_partial_access.2938286315
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/0.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.111019369
Short name T44
Test name
Test status
Simulation time 28220146497 ps
CPU time 326.18 seconds
Started Sep 24 09:49:08 AM UTC 24
Finished Sep 24 09:54:39 AM UTC 24
Peak memory 222740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111019369 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_mem_walk.111019369
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/0.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.942161037
Short name T226
Test name
Test status
Simulation time 20545333377 ps
CPU time 1351.15 seconds
Started Sep 24 09:49:07 AM UTC 24
Finished Sep 24 10:11:55 AM UTC 24
Peak memory 376552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942161037 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multiple_keys.942161037
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/0.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access.1462524040
Short name T8
Test name
Test status
Simulation time 6970635759 ps
CPU time 25.13 seconds
Started Sep 24 09:49:08 AM UTC 24
Finished Sep 24 09:49:34 AM UTC 24
Peak memory 212420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462524040 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_partial_access.1462524040
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/0.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.3642073997
Short name T106
Test name
Test status
Simulation time 20757527499 ps
CPU time 313.41 seconds
Started Sep 24 09:49:08 AM UTC 24
Finished Sep 24 09:54:26 AM UTC 24
Peak memory 212424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642073997 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_partial_ac
cess_b2b.3642073997
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/0.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.2177028155
Short name T2
Test name
Test status
Simulation time 217509304 ps
CPU time 2.07 seconds
Started Sep 24 09:49:08 AM UTC 24
Finished Sep 24 09:49:11 AM UTC 24
Peak memory 248460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177028155 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_sec_cm.2177028155
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_smoke.3551512300
Short name T35
Test name
Test status
Simulation time 3996976306 ps
CPU time 65.67 seconds
Started Sep 24 09:49:07 AM UTC 24
Finished Sep 24 09:50:15 AM UTC 24
Peak memory 379056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551512300 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.3551512300
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/0.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all.2187768330
Short name T149
Test name
Test status
Simulation time 187277212559 ps
CPU time 1953.24 seconds
Started Sep 24 09:49:08 AM UTC 24
Finished Sep 24 10:22:03 AM UTC 24
Peak memory 388888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21877683
30 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all.2187768330
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/0.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1827811917
Short name T25
Test name
Test status
Simulation time 27037149955 ps
CPU time 151.19 seconds
Started Sep 24 09:49:08 AM UTC 24
Finished Sep 24 09:51:42 AM UTC 24
Peak memory 377244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827811917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all_with_rand_reset.1827811917
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/0.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.2097097066
Short name T108
Test name
Test status
Simulation time 8633014049 ps
CPU time 380.79 seconds
Started Sep 24 09:49:08 AM UTC 24
Finished Sep 24 09:55:34 AM UTC 24
Peak memory 212492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097097066 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_pipeline.2097097066
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/0.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.3218131835
Short name T41
Test name
Test status
Simulation time 35821029941 ps
CPU time 603.61 seconds
Started Sep 24 09:49:39 AM UTC 24
Finished Sep 24 09:59:50 AM UTC 24
Peak memory 389544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218131835 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_access_durin
g_key_req.3218131835
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/1.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_alert_test.504164457
Short name T13
Test name
Test status
Simulation time 38832394 ps
CPU time 0.87 seconds
Started Sep 24 09:49:40 AM UTC 24
Finished Sep 24 09:49:42 AM UTC 24
Peak memory 210876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504164457 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_alert_test.504164457
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/1.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_bijection.1358862355
Short name T250
Test name
Test status
Simulation time 268932950667 ps
CPU time 1755.19 seconds
Started Sep 24 09:49:08 AM UTC 24
Finished Sep 24 10:18:43 AM UTC 24
Peak memory 213944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358862355 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection.1358862355
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/1.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_executable.3074679814
Short name T150
Test name
Test status
Simulation time 102874920942 ps
CPU time 1064.62 seconds
Started Sep 24 09:49:39 AM UTC 24
Finished Sep 24 10:07:37 AM UTC 24
Peak memory 385476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074679814 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executable.3074679814
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/1.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.1870810978
Short name T10
Test name
Test status
Simulation time 12856418697 ps
CPU time 87.06 seconds
Started Sep 24 09:49:39 AM UTC 24
Finished Sep 24 09:51:08 AM UTC 24
Peak memory 212484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870810978 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_escalation.1870810978
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/1.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.1345480380
Short name T12
Test name
Test status
Simulation time 1389595186 ps
CPU time 6.92 seconds
Started Sep 24 09:49:39 AM UTC 24
Finished Sep 24 09:49:47 AM UTC 24
Peak memory 222516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1345480380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_m
ax_throughput.1345480380
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/1.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.1532043658
Short name T45
Test name
Test status
Simulation time 21004018113 ps
CPU time 309.55 seconds
Started Sep 24 09:49:39 AM UTC 24
Finished Sep 24 09:54:54 AM UTC 24
Peak memory 222688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532043658 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_mem_walk.1532043658
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/1.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.3531721400
Short name T57
Test name
Test status
Simulation time 12572245758 ps
CPU time 137.03 seconds
Started Sep 24 09:49:08 AM UTC 24
Finished Sep 24 09:51:28 AM UTC 24
Peak memory 385308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531721400 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multiple_keys.3531721400
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/1.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access.2509087476
Short name T34
Test name
Test status
Simulation time 1269974212 ps
CPU time 23.63 seconds
Started Sep 24 09:49:38 AM UTC 24
Finished Sep 24 09:50:03 AM UTC 24
Peak memory 212220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509087476 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_partial_access.2509087476
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/1.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.208403677
Short name T14
Test name
Test status
Simulation time 1348915735 ps
CPU time 3.84 seconds
Started Sep 24 09:49:39 AM UTC 24
Finished Sep 24 09:49:44 AM UTC 24
Peak memory 212532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208403677 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.208403677
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/1.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_regwen.3819048539
Short name T28
Test name
Test status
Simulation time 4160263918 ps
CPU time 75.31 seconds
Started Sep 24 09:49:39 AM UTC 24
Finished Sep 24 09:50:57 AM UTC 24
Peak memory 212288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819048539 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.3819048539
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/1.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_smoke.2560032071
Short name T4
Test name
Test status
Simulation time 5042830030 ps
CPU time 4.39 seconds
Started Sep 24 09:49:08 AM UTC 24
Finished Sep 24 09:49:14 AM UTC 24
Peak memory 212576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560032071 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.2560032071
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/1.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all.715057238
Short name T17
Test name
Test status
Simulation time 247010986515 ps
CPU time 2582.03 seconds
Started Sep 24 09:49:40 AM UTC 24
Finished Sep 24 10:33:10 AM UTC 24
Peak memory 392960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71505723
8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all.715057238
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/1.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.3234956709
Short name T109
Test name
Test status
Simulation time 4877951558 ps
CPU time 364.77 seconds
Started Sep 24 09:49:38 AM UTC 24
Finished Sep 24 09:55:48 AM UTC 24
Peak memory 212552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234956709 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_pipeline.3234956709
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/1.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.1062355938
Short name T22
Test name
Test status
Simulation time 3119570623 ps
CPU time 15.57 seconds
Started Sep 24 09:49:39 AM UTC 24
Finished Sep 24 09:49:56 AM UTC 24
Peak memory 235740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1062355938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_
throughput_w_partial_write.1062355938
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/1.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.2055188763
Short name T229
Test name
Test status
Simulation time 3376370981 ps
CPU time 72.14 seconds
Started Sep 24 10:11:33 AM UTC 24
Finished Sep 24 10:12:47 AM UTC 24
Peak memory 252212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055188763 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_access_duri
ng_key_req.2055188763
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/10.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_alert_test.2056925300
Short name T231
Test name
Test status
Simulation time 30218729 ps
CPU time 0.96 seconds
Started Sep 24 10:13:44 AM UTC 24
Finished Sep 24 10:13:46 AM UTC 24
Peak memory 211352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2056925300
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_alert_test.2056925300
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/10.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_bijection.1995962191
Short name T297
Test name
Test status
Simulation time 180083815758 ps
CPU time 1256.18 seconds
Started Sep 24 10:10:06 AM UTC 24
Finished Sep 24 10:31:19 AM UTC 24
Peak memory 212344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995962191 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection.1995962191
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/10.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_executable.1397431487
Short name T279
Test name
Test status
Simulation time 16559134605 ps
CPU time 853.52 seconds
Started Sep 24 10:11:35 AM UTC 24
Finished Sep 24 10:25:59 AM UTC 24
Peak memory 383464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397431487 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executable.1397431487
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/10.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.3228324545
Short name T222
Test name
Test status
Simulation time 675407310 ps
CPU time 7.46 seconds
Started Sep 24 10:10:58 AM UTC 24
Finished Sep 24 10:11:06 AM UTC 24
Peak memory 228716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3228324545 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_
max_throughput.3228324545
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/10.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.543631537
Short name T55
Test name
Test status
Simulation time 8059942156 ps
CPU time 206.19 seconds
Started Sep 24 10:12:04 AM UTC 24
Finished Sep 24 10:15:34 AM UTC 24
Peak memory 223056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543631537 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_mem_partial_access.543631537
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/10.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.1534891839
Short name T246
Test name
Test status
Simulation time 28789386016 ps
CPU time 358.05 seconds
Started Sep 24 10:12:03 AM UTC 24
Finished Sep 24 10:18:07 AM UTC 24
Peak memory 212408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534891839 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_mem_walk.1534891839
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/10.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.2496004556
Short name T330
Test name
Test status
Simulation time 31546934114 ps
CPU time 1739.67 seconds
Started Sep 24 10:09:47 AM UTC 24
Finished Sep 24 10:39:08 AM UTC 24
Peak memory 393056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496004556 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multiple_keys.2496004556
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/10.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access.2568551628
Short name T221
Test name
Test status
Simulation time 825132510 ps
CPU time 13.09 seconds
Started Sep 24 10:10:42 AM UTC 24
Finished Sep 24 10:10:57 AM UTC 24
Peak memory 243996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568551628 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_partial_access.2568551628
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/10.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.3789116344
Short name T237
Test name
Test status
Simulation time 45873401461 ps
CPU time 322.63 seconds
Started Sep 24 10:10:52 AM UTC 24
Finished Sep 24 10:16:20 AM UTC 24
Peak memory 212388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789116344 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_partial_a
ccess_b2b.3789116344
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/10.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.1621470327
Short name T228
Test name
Test status
Simulation time 344902365 ps
CPU time 3.5 seconds
Started Sep 24 10:11:58 AM UTC 24
Finished Sep 24 10:12:03 AM UTC 24
Peak memory 212296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621470327 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.1621470327
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/10.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_regwen.2718289532
Short name T18
Test name
Test status
Simulation time 15821165437 ps
CPU time 1495.93 seconds
Started Sep 24 10:11:56 AM UTC 24
Finished Sep 24 10:37:10 AM UTC 24
Peak memory 389404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718289532 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.2718289532
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/10.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_smoke.630646702
Short name T217
Test name
Test status
Simulation time 2988704432 ps
CPU time 28.16 seconds
Started Sep 24 10:09:35 AM UTC 24
Finished Sep 24 10:10:05 AM UTC 24
Peak memory 212472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630646702 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.630646702
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/10.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all.2185257373
Short name T301
Test name
Test status
Simulation time 55488200464 ps
CPU time 1176.3 seconds
Started Sep 24 10:13:05 AM UTC 24
Finished Sep 24 10:32:55 AM UTC 24
Peak memory 385504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21852573
73 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_a
ll.2185257373
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/10.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2764610916
Short name T54
Test name
Test status
Simulation time 1012951784 ps
CPU time 98.5 seconds
Started Sep 24 10:12:48 AM UTC 24
Finished Sep 24 10:14:29 AM UTC 24
Peak memory 348440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764610916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.2764610916
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/10.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.354295688
Short name T233
Test name
Test status
Simulation time 4380509024 ps
CPU time 297.6 seconds
Started Sep 24 10:10:12 AM UTC 24
Finished Sep 24 10:15:14 AM UTC 24
Peak memory 212340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354295688 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_pipeline.354295688
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/10.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.2126128532
Short name T223
Test name
Test status
Simulation time 1393261058 ps
CPU time 6.79 seconds
Started Sep 24 10:11:07 AM UTC 24
Finished Sep 24 10:11:14 AM UTC 24
Peak memory 212032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2126128532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl
_throughput_w_partial_write.2126128532
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/10.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.966051293
Short name T280
Test name
Test status
Simulation time 10069623640 ps
CPU time 614.49 seconds
Started Sep 24 10:15:54 AM UTC 24
Finished Sep 24 10:26:16 AM UTC 24
Peak memory 383188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966051293 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_access_durin
g_key_req.966051293
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/11.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_alert_test.2020746155
Short name T244
Test name
Test status
Simulation time 115836541 ps
CPU time 1.11 seconds
Started Sep 24 10:17:48 AM UTC 24
Finished Sep 24 10:17:50 AM UTC 24
Peak memory 210884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020746155
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_alert_test.2020746155
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/11.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_bijection.1331803284
Short name T406
Test name
Test status
Simulation time 32140228610 ps
CPU time 2338.65 seconds
Started Sep 24 10:14:28 AM UTC 24
Finished Sep 24 10:53:53 AM UTC 24
Peak memory 214092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331803284 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection.1331803284
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/11.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_executable.2818376259
Short name T350
Test name
Test status
Simulation time 22472874086 ps
CPU time 1536.59 seconds
Started Sep 24 10:16:21 AM UTC 24
Finished Sep 24 10:42:15 AM UTC 24
Peak memory 390940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818376259 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executable.2818376259
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/11.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.3959950094
Short name T241
Test name
Test status
Simulation time 19910510660 ps
CPU time 70.44 seconds
Started Sep 24 10:15:45 AM UTC 24
Finished Sep 24 10:16:57 AM UTC 24
Peak memory 212436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959950094 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_escalation.3959950094
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/11.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.2095850546
Short name T239
Test name
Test status
Simulation time 1523177172 ps
CPU time 81.78 seconds
Started Sep 24 10:15:28 AM UTC 24
Finished Sep 24 10:16:51 AM UTC 24
Peak memory 375008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2095850546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_
max_throughput.2095850546
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/11.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.101283445
Short name T249
Test name
Test status
Simulation time 5306261868 ps
CPU time 92.16 seconds
Started Sep 24 10:16:57 AM UTC 24
Finished Sep 24 10:18:32 AM UTC 24
Peak memory 229592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101283445 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_mem_partial_access.101283445
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/11.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.4209740643
Short name T270
Test name
Test status
Simulation time 21128501619 ps
CPU time 504.29 seconds
Started Sep 24 10:16:55 AM UTC 24
Finished Sep 24 10:25:26 AM UTC 24
Peak memory 222692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209740643 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_mem_walk.4209740643
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/11.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.3910874133
Short name T300
Test name
Test status
Simulation time 44392078197 ps
CPU time 1039.1 seconds
Started Sep 24 10:14:20 AM UTC 24
Finished Sep 24 10:31:53 AM UTC 24
Peak memory 385316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910874133 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multiple_keys.3910874133
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/11.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access.2909185917
Short name T235
Test name
Test status
Simulation time 3358492955 ps
CPU time 36.07 seconds
Started Sep 24 10:15:06 AM UTC 24
Finished Sep 24 10:15:44 AM UTC 24
Peak memory 212596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909185917 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_partial_access.2909185917
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/11.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.1558248024
Short name T277
Test name
Test status
Simulation time 90906742811 ps
CPU time 625.81 seconds
Started Sep 24 10:15:15 AM UTC 24
Finished Sep 24 10:25:49 AM UTC 24
Peak memory 212368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558248024 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_partial_a
ccess_b2b.1558248024
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/11.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.2859530200
Short name T242
Test name
Test status
Simulation time 728436852 ps
CPU time 6.23 seconds
Started Sep 24 10:16:52 AM UTC 24
Finished Sep 24 10:17:00 AM UTC 24
Peak memory 212560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859530200 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.2859530200
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/11.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_regwen.958195145
Short name T127
Test name
Test status
Simulation time 117581632036 ps
CPU time 441.44 seconds
Started Sep 24 10:16:30 AM UTC 24
Finished Sep 24 10:23:57 AM UTC 24
Peak memory 381412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958195145 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.958195145
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/11.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_smoke.2318720997
Short name T232
Test name
Test status
Simulation time 746542394 ps
CPU time 31.26 seconds
Started Sep 24 10:13:47 AM UTC 24
Finished Sep 24 10:14:20 AM UTC 24
Peak memory 282852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318720997 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.2318720997
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/11.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all.2669540693
Short name T932
Test name
Test status
Simulation time 553722937305 ps
CPU time 8671.74 seconds
Started Sep 24 10:17:36 AM UTC 24
Finished Sep 24 12:43:41 PM UTC 24
Peak memory 392988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26695406
93 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_a
ll.2669540693
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/11.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.72693618
Short name T56
Test name
Test status
Simulation time 4755360582 ps
CPU time 45.4 seconds
Started Sep 24 10:17:01 AM UTC 24
Finished Sep 24 10:17:47 AM UTC 24
Peak memory 227016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72693618 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.72693618
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/11.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.3828776404
Short name T258
Test name
Test status
Simulation time 19890076231 ps
CPU time 365.18 seconds
Started Sep 24 10:14:29 AM UTC 24
Finished Sep 24 10:20:40 AM UTC 24
Peak memory 212476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828776404 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_pipeline.3828776404
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/11.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.3117772629
Short name T240
Test name
Test status
Simulation time 827339817 ps
CPU time 77.72 seconds
Started Sep 24 10:15:35 AM UTC 24
Finished Sep 24 10:16:54 AM UTC 24
Peak memory 381084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3117772629 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl
_throughput_w_partial_write.3117772629
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/11.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.992253514
Short name T313
Test name
Test status
Simulation time 18030758190 ps
CPU time 866.88 seconds
Started Sep 24 10:19:46 AM UTC 24
Finished Sep 24 10:34:23 AM UTC 24
Peak memory 387364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992253514 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_access_durin
g_key_req.992253514
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/12.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_alert_test.2004516059
Short name T261
Test name
Test status
Simulation time 14080561 ps
CPU time 0.97 seconds
Started Sep 24 10:22:04 AM UTC 24
Finished Sep 24 10:22:06 AM UTC 24
Peak memory 211352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004516059
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_alert_test.2004516059
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/12.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_bijection.757224251
Short name T304
Test name
Test status
Simulation time 93327214617 ps
CPU time 894.79 seconds
Started Sep 24 10:18:08 AM UTC 24
Finished Sep 24 10:33:14 AM UTC 24
Peak memory 212480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757224251 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection.757224251
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/12.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_executable.2693464618
Short name T284
Test name
Test status
Simulation time 13251502101 ps
CPU time 445.52 seconds
Started Sep 24 10:20:12 AM UTC 24
Finished Sep 24 10:27:43 AM UTC 24
Peak memory 385240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693464618 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executable.2693464618
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/12.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.2769730965
Short name T253
Test name
Test status
Simulation time 14517347147 ps
CPU time 27.44 seconds
Started Sep 24 10:19:17 AM UTC 24
Finished Sep 24 10:19:45 AM UTC 24
Peak memory 212416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769730965 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_escalation.2769730965
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/12.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.2122231972
Short name T254
Test name
Test status
Simulation time 1542715056 ps
CPU time 85.03 seconds
Started Sep 24 10:18:45 AM UTC 24
Finished Sep 24 10:20:12 AM UTC 24
Peak memory 370916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2122231972 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_
max_throughput.2122231972
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/12.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.2356482604
Short name T262
Test name
Test status
Simulation time 23881614236 ps
CPU time 103.54 seconds
Started Sep 24 10:20:40 AM UTC 24
Finished Sep 24 10:22:26 AM UTC 24
Peak memory 222980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356482604 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_mem_partial_access.2356482604
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/12.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.1488829352
Short name T275
Test name
Test status
Simulation time 93947145328 ps
CPU time 300.99 seconds
Started Sep 24 10:20:39 AM UTC 24
Finished Sep 24 10:25:45 AM UTC 24
Peak memory 222692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488829352 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_mem_walk.1488829352
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/12.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.3476156837
Short name T287
Test name
Test status
Simulation time 13701787059 ps
CPU time 595.67 seconds
Started Sep 24 10:17:59 AM UTC 24
Finished Sep 24 10:28:02 AM UTC 24
Peak memory 387556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476156837 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multiple_keys.3476156837
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/12.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access.1640577965
Short name T251
Test name
Test status
Simulation time 1463814741 ps
CPU time 35.71 seconds
Started Sep 24 10:18:18 AM UTC 24
Finished Sep 24 10:18:56 AM UTC 24
Peak memory 212288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640577965 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_partial_access.1640577965
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/12.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.3332989126
Short name T289
Test name
Test status
Simulation time 80685446346 ps
CPU time 585.9 seconds
Started Sep 24 10:18:32 AM UTC 24
Finished Sep 24 10:28:26 AM UTC 24
Peak memory 212476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332989126 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_partial_a
ccess_b2b.3332989126
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/12.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.4058178552
Short name T257
Test name
Test status
Simulation time 1525078856 ps
CPU time 5.44 seconds
Started Sep 24 10:20:32 AM UTC 24
Finished Sep 24 10:20:39 AM UTC 24
Peak memory 212564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058178552 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.4058178552
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/12.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_regwen.2493463853
Short name T299
Test name
Test status
Simulation time 25630922748 ps
CPU time 661.62 seconds
Started Sep 24 10:20:30 AM UTC 24
Finished Sep 24 10:31:40 AM UTC 24
Peak memory 356616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493463853 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.2493463853
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/12.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_smoke.1928658838
Short name T248
Test name
Test status
Simulation time 1358979232 ps
CPU time 25.15 seconds
Started Sep 24 10:17:51 AM UTC 24
Finished Sep 24 10:18:17 AM UTC 24
Peak memory 212424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928658838 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.1928658838
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/12.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all.290575671
Short name T676
Test name
Test status
Simulation time 67564635236 ps
CPU time 5445.26 seconds
Started Sep 24 10:21:21 AM UTC 24
Finished Sep 24 11:53:09 AM UTC 24
Peak memory 401156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29057567
1 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all.290575671
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/12.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.3298641593
Short name T259
Test name
Test status
Simulation time 355398408 ps
CPU time 19.42 seconds
Started Sep 24 10:21:00 AM UTC 24
Finished Sep 24 10:21:20 AM UTC 24
Peak memory 222740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298641593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.3298641593
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/12.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.3247465198
Short name T265
Test name
Test status
Simulation time 6848681824 ps
CPU time 355.35 seconds
Started Sep 24 10:18:13 AM UTC 24
Finished Sep 24 10:24:14 AM UTC 24
Peak memory 212424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247465198 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_pipeline.3247465198
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/12.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.1275606555
Short name T255
Test name
Test status
Simulation time 3122910482 ps
CPU time 90.88 seconds
Started Sep 24 10:18:57 AM UTC 24
Finished Sep 24 10:20:30 AM UTC 24
Peak memory 383268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1275606555 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl
_throughput_w_partial_write.1275606555
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/12.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.295790413
Short name T292
Test name
Test status
Simulation time 13173787485 ps
CPU time 224.34 seconds
Started Sep 24 10:25:25 AM UTC 24
Finished Sep 24 10:29:12 AM UTC 24
Peak memory 374940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295790413 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_access_durin
g_key_req.295790413
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/13.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_alert_test.1252254140
Short name T278
Test name
Test status
Simulation time 13376076 ps
CPU time 1.03 seconds
Started Sep 24 10:25:48 AM UTC 24
Finished Sep 24 10:25:50 AM UTC 24
Peak memory 211352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252254140
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_alert_test.1252254140
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/13.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_bijection.3926623893
Short name T444
Test name
Test status
Simulation time 31112850653 ps
CPU time 2278.68 seconds
Started Sep 24 10:22:28 AM UTC 24
Finished Sep 24 11:00:54 AM UTC 24
Peak memory 213992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926623893 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection.3926623893
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/13.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_executable.700115296
Short name T355
Test name
Test status
Simulation time 9598817810 ps
CPU time 1037.51 seconds
Started Sep 24 10:25:28 AM UTC 24
Finished Sep 24 10:42:59 AM UTC 24
Peak memory 389328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700115296 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executable.700115296
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/13.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.2840252626
Short name T269
Test name
Test status
Simulation time 6794123520 ps
CPU time 28.54 seconds
Started Sep 24 10:24:57 AM UTC 24
Finished Sep 24 10:25:26 AM UTC 24
Peak memory 212360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840252626 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_escalation.2840252626
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/13.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.2265719590
Short name T272
Test name
Test status
Simulation time 751555482 ps
CPU time 72.99 seconds
Started Sep 24 10:24:15 AM UTC 24
Finished Sep 24 10:25:30 AM UTC 24
Peak memory 321692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2265719590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_
max_throughput.2265719590
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/13.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.892598206
Short name T87
Test name
Test status
Simulation time 69565768368 ps
CPU time 225.78 seconds
Started Sep 24 10:25:36 AM UTC 24
Finished Sep 24 10:29:26 AM UTC 24
Peak memory 222796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892598206 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_mem_partial_access.892598206
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/13.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.2037549946
Short name T312
Test name
Test status
Simulation time 115388586197 ps
CPU time 520.37 seconds
Started Sep 24 10:25:32 AM UTC 24
Finished Sep 24 10:34:19 AM UTC 24
Peak memory 222672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037549946 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_mem_walk.2037549946
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/13.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.219895579
Short name T315
Test name
Test status
Simulation time 65710379503 ps
CPU time 728.29 seconds
Started Sep 24 10:22:07 AM UTC 24
Finished Sep 24 10:34:25 AM UTC 24
Peak memory 383476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219895579 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multiple_keys.219895579
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/13.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access.1385617007
Short name T266
Test name
Test status
Simulation time 600949381 ps
CPU time 27.67 seconds
Started Sep 24 10:23:58 AM UTC 24
Finished Sep 24 10:24:28 AM UTC 24
Peak memory 276608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385617007 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_partial_access.1385617007
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/13.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.4032718703
Short name T288
Test name
Test status
Simulation time 7229843445 ps
CPU time 239.65 seconds
Started Sep 24 10:24:01 AM UTC 24
Finished Sep 24 10:28:05 AM UTC 24
Peak memory 212336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032718703 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_partial_a
ccess_b2b.4032718703
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/13.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.2226762819
Short name T274
Test name
Test status
Simulation time 350933420 ps
CPU time 6.28 seconds
Started Sep 24 10:25:30 AM UTC 24
Finished Sep 24 10:25:38 AM UTC 24
Peak memory 212300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226762819 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.2226762819
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/13.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_regwen.693962265
Short name T331
Test name
Test status
Simulation time 21832017397 ps
CPU time 860.99 seconds
Started Sep 24 10:25:28 AM UTC 24
Finished Sep 24 10:39:59 AM UTC 24
Peak memory 391380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693962265 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.693962265
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/13.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_smoke.1066947229
Short name T263
Test name
Test status
Simulation time 881386267 ps
CPU time 27.35 seconds
Started Sep 24 10:22:04 AM UTC 24
Finished Sep 24 10:22:33 AM UTC 24
Peak memory 212248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066947229 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.1066947229
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/13.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all.3757034093
Short name T913
Test name
Test status
Simulation time 1809536867959 ps
CPU time 7298.61 seconds
Started Sep 24 10:25:45 AM UTC 24
Finished Sep 24 12:28:44 PM UTC 24
Peak memory 390936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37570340
93 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_a
ll.3757034093
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/13.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.2667164942
Short name T282
Test name
Test status
Simulation time 700976613 ps
CPU time 55.37 seconds
Started Sep 24 10:25:38 AM UTC 24
Finished Sep 24 10:26:35 AM UTC 24
Peak memory 224716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667164942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.2667164942
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/13.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.3232266475
Short name T268
Test name
Test status
Simulation time 3099786502 ps
CPU time 166.89 seconds
Started Sep 24 10:22:34 AM UTC 24
Finished Sep 24 10:25:24 AM UTC 24
Peak memory 212616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232266475 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_pipeline.3232266475
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/13.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.898753711
Short name T276
Test name
Test status
Simulation time 827960437 ps
CPU time 77.14 seconds
Started Sep 24 10:24:28 AM UTC 24
Finished Sep 24 10:25:47 AM UTC 24
Peak memory 381160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=898753711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_
throughput_w_partial_write.898753711
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/13.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.2958509944
Short name T367
Test name
Test status
Simulation time 16216277013 ps
CPU time 1045.35 seconds
Started Sep 24 10:28:01 AM UTC 24
Finished Sep 24 10:45:39 AM UTC 24
Peak memory 389376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958509944 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_access_duri
ng_key_req.2958509944
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/14.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_alert_test.4242794302
Short name T293
Test name
Test status
Simulation time 38730251 ps
CPU time 1.04 seconds
Started Sep 24 10:29:26 AM UTC 24
Finished Sep 24 10:29:28 AM UTC 24
Peak memory 211352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242794302
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_alert_test.4242794302
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/14.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_bijection.1647863982
Short name T438
Test name
Test status
Simulation time 200953808679 ps
CPU time 2004.93 seconds
Started Sep 24 10:26:00 AM UTC 24
Finished Sep 24 10:59:50 AM UTC 24
Peak memory 214076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647863982 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection.1647863982
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/14.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_executable.360786434
Short name T340
Test name
Test status
Simulation time 34754435213 ps
CPU time 786.7 seconds
Started Sep 24 10:28:04 AM UTC 24
Finished Sep 24 10:41:20 AM UTC 24
Peak memory 383328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360786434 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executable.360786434
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/14.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.3832600519
Short name T294
Test name
Test status
Simulation time 9755418568 ps
CPU time 110.11 seconds
Started Sep 24 10:28:01 AM UTC 24
Finished Sep 24 10:29:53 AM UTC 24
Peak memory 212556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832600519 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_escalation.3832600519
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/14.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.152832022
Short name T291
Test name
Test status
Simulation time 778194768 ps
CPU time 95.12 seconds
Started Sep 24 10:27:17 AM UTC 24
Finished Sep 24 10:28:54 AM UTC 24
Peak memory 381356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
152832022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_m
ax_throughput.152832022
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/14.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.4238483121
Short name T298
Test name
Test status
Simulation time 5068084961 ps
CPU time 155 seconds
Started Sep 24 10:28:55 AM UTC 24
Finished Sep 24 10:31:33 AM UTC 24
Peak memory 229600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238483121 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_mem_partial_access.4238483121
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/14.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.4134839696
Short name T309
Test name
Test status
Simulation time 15151078531 ps
CPU time 313.81 seconds
Started Sep 24 10:28:35 AM UTC 24
Finished Sep 24 10:33:54 AM UTC 24
Peak memory 222620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134839696 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_mem_walk.4134839696
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/14.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.2662891295
Short name T316
Test name
Test status
Simulation time 42166719121 ps
CPU time 513.32 seconds
Started Sep 24 10:25:51 AM UTC 24
Finished Sep 24 10:34:32 AM UTC 24
Peak memory 362708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662891295 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multiple_keys.2662891295
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/14.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access.4240819301
Short name T283
Test name
Test status
Simulation time 3048179396 ps
CPU time 40.99 seconds
Started Sep 24 10:26:34 AM UTC 24
Finished Sep 24 10:27:16 AM UTC 24
Peak memory 317652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240819301 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_partial_access.4240819301
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/14.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.2340377323
Short name T308
Test name
Test status
Simulation time 44399062434 ps
CPU time 411.45 seconds
Started Sep 24 10:26:36 AM UTC 24
Finished Sep 24 10:33:33 AM UTC 24
Peak memory 212468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340377323 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_partial_a
ccess_b2b.2340377323
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/14.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.2114679504
Short name T290
Test name
Test status
Simulation time 1411834201 ps
CPU time 6 seconds
Started Sep 24 10:28:27 AM UTC 24
Finished Sep 24 10:28:34 AM UTC 24
Peak memory 212304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114679504 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.2114679504
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/14.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_regwen.1581294712
Short name T335
Test name
Test status
Simulation time 12050128879 ps
CPU time 746.41 seconds
Started Sep 24 10:28:06 AM UTC 24
Finished Sep 24 10:40:42 AM UTC 24
Peak memory 387612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581294712 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.1581294712
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/14.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_smoke.1445743388
Short name T285
Test name
Test status
Simulation time 1585343443 ps
CPU time 127.53 seconds
Started Sep 24 10:25:49 AM UTC 24
Finished Sep 24 10:27:59 AM UTC 24
Peak memory 379108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445743388 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.1445743388
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/14.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_all.2888433675
Short name T927
Test name
Test status
Simulation time 207810534896 ps
CPU time 7517.59 seconds
Started Sep 24 10:29:24 AM UTC 24
Finished Sep 24 12:36:07 PM UTC 24
Peak memory 401116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28884336
75 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_a
ll.2888433675
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/14.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.3945419066
Short name T118
Test name
Test status
Simulation time 688220109 ps
CPU time 8.8 seconds
Started Sep 24 10:29:13 AM UTC 24
Finished Sep 24 10:29:23 AM UTC 24
Peak memory 222740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945419066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.3945419066
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/14.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.1419528788
Short name T296
Test name
Test status
Simulation time 32317240198 ps
CPU time 247.4 seconds
Started Sep 24 10:26:17 AM UTC 24
Finished Sep 24 10:30:28 AM UTC 24
Peak memory 212424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419528788 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_pipeline.1419528788
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/14.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.1945166172
Short name T286
Test name
Test status
Simulation time 2801960270 ps
CPU time 13.99 seconds
Started Sep 24 10:27:44 AM UTC 24
Finished Sep 24 10:28:00 AM UTC 24
Peak memory 222708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1945166172 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl
_throughput_w_partial_write.1945166172
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/14.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.748318522
Short name T360
Test name
Test status
Simulation time 42625000058 ps
CPU time 656.12 seconds
Started Sep 24 10:32:59 AM UTC 24
Finished Sep 24 10:44:03 AM UTC 24
Peak memory 387336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748318522 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_access_durin
g_key_req.748318522
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/15.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_alert_test.1515869033
Short name T310
Test name
Test status
Simulation time 39946412 ps
CPU time 0.99 seconds
Started Sep 24 10:33:55 AM UTC 24
Finished Sep 24 10:33:57 AM UTC 24
Peak memory 211352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515869033
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_alert_test.1515869033
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/15.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_bijection.3805602826
Short name T386
Test name
Test status
Simulation time 61515125185 ps
CPU time 1099.95 seconds
Started Sep 24 10:30:02 AM UTC 24
Finished Sep 24 10:48:35 AM UTC 24
Peak memory 212612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805602826 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection.3805602826
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/15.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_executable.2854270155
Short name T422
Test name
Test status
Simulation time 24488543090 ps
CPU time 1459.47 seconds
Started Sep 24 10:33:11 AM UTC 24
Finished Sep 24 10:57:48 AM UTC 24
Peak memory 384816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854270155 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executable.2854270155
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/15.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.124679419
Short name T306
Test name
Test status
Simulation time 13885127370 ps
CPU time 30.71 seconds
Started Sep 24 10:32:56 AM UTC 24
Finished Sep 24 10:33:28 AM UTC 24
Peak memory 222732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124679419 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_escalation.124679419
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/15.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.68566876
Short name T307
Test name
Test status
Simulation time 1410202985 ps
CPU time 105.1 seconds
Started Sep 24 10:31:42 AM UTC 24
Finished Sep 24 10:33:29 AM UTC 24
Peak memory 372968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
68566876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ma
x_throughput.68566876
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/15.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.879527965
Short name T324
Test name
Test status
Simulation time 21885497851 ps
CPU time 237.37 seconds
Started Sep 24 10:33:29 AM UTC 24
Finished Sep 24 10:37:30 AM UTC 24
Peak memory 229876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879527965 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_mem_partial_access.879527965
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/15.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.418764432
Short name T347
Test name
Test status
Simulation time 295667387746 ps
CPU time 503.64 seconds
Started Sep 24 10:33:19 AM UTC 24
Finished Sep 24 10:41:50 AM UTC 24
Peak memory 222744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418764432 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_mem_walk.418764432
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/15.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.2237474668
Short name T354
Test name
Test status
Simulation time 6920138746 ps
CPU time 755.3 seconds
Started Sep 24 10:29:54 AM UTC 24
Finished Sep 24 10:42:39 AM UTC 24
Peak memory 381216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237474668 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multiple_keys.2237474668
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/15.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access.3381373440
Short name T303
Test name
Test status
Simulation time 5035109963 ps
CPU time 110.38 seconds
Started Sep 24 10:31:19 AM UTC 24
Finished Sep 24 10:33:12 AM UTC 24
Peak memory 360672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381373440 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_partial_access.3381373440
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/15.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.180839617
Short name T344
Test name
Test status
Simulation time 76014230478 ps
CPU time 593.96 seconds
Started Sep 24 10:31:34 AM UTC 24
Finished Sep 24 10:41:35 AM UTC 24
Peak memory 212352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180839617 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_partial_ac
cess_b2b.180839617
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/15.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.1454742554
Short name T305
Test name
Test status
Simulation time 678995452 ps
CPU time 3.54 seconds
Started Sep 24 10:33:14 AM UTC 24
Finished Sep 24 10:33:19 AM UTC 24
Peak memory 212500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454742554 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.1454742554
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/15.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_regwen.1974322802
Short name T327
Test name
Test status
Simulation time 2156146580 ps
CPU time 297.08 seconds
Started Sep 24 10:33:13 AM UTC 24
Finished Sep 24 10:38:14 AM UTC 24
Peak memory 385432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974322802 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.1974322802
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/15.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_smoke.583289819
Short name T295
Test name
Test status
Simulation time 2619750258 ps
CPU time 29.53 seconds
Started Sep 24 10:29:30 AM UTC 24
Finished Sep 24 10:30:01 AM UTC 24
Peak memory 212472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583289819 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.583289819
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/15.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all.1702926509
Short name T850
Test name
Test status
Simulation time 108605724876 ps
CPU time 6133.2 seconds
Started Sep 24 10:33:35 AM UTC 24
Finished Sep 24 12:16:53 PM UTC 24
Peak memory 392960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17029265
09 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_a
ll.1702926509
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/15.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.315587070
Short name T311
Test name
Test status
Simulation time 1163056762 ps
CPU time 42 seconds
Started Sep 24 10:33:30 AM UTC 24
Finished Sep 24 10:34:14 AM UTC 24
Peak memory 225016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315587070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.315587070
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/15.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.1458724344
Short name T318
Test name
Test status
Simulation time 4563100657 ps
CPU time 275.42 seconds
Started Sep 24 10:30:29 AM UTC 24
Finished Sep 24 10:35:09 AM UTC 24
Peak memory 212392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458724344 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_pipeline.1458724344
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/15.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.3745565896
Short name T302
Test name
Test status
Simulation time 1572414355 ps
CPU time 62.06 seconds
Started Sep 24 10:31:54 AM UTC 24
Finished Sep 24 10:32:58 AM UTC 24
Peak memory 328100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3745565896 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl
_throughput_w_partial_write.3745565896
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/15.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.1034618534
Short name T342
Test name
Test status
Simulation time 12521479762 ps
CPU time 345.5 seconds
Started Sep 24 10:35:41 AM UTC 24
Finished Sep 24 10:41:31 AM UTC 24
Peak memory 387296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034618534 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_access_duri
ng_key_req.1034618534
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/16.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_alert_test.3933799932
Short name T328
Test name
Test status
Simulation time 20575842 ps
CPU time 1.08 seconds
Started Sep 24 10:38:12 AM UTC 24
Finished Sep 24 10:38:14 AM UTC 24
Peak memory 211352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933799932
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_alert_test.3933799932
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/16.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_bijection.1211783819
Short name T419
Test name
Test status
Simulation time 20027218155 ps
CPU time 1371.51 seconds
Started Sep 24 10:34:20 AM UTC 24
Finished Sep 24 10:57:27 AM UTC 24
Peak memory 214204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211783819 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection.1211783819
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/16.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_executable.2255102114
Short name T361
Test name
Test status
Simulation time 59804214538 ps
CPU time 496.17 seconds
Started Sep 24 10:35:52 AM UTC 24
Finished Sep 24 10:44:14 AM UTC 24
Peak memory 354572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255102114 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executable.2255102114
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/16.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.1525670151
Short name T322
Test name
Test status
Simulation time 51068311223 ps
CPU time 100.1 seconds
Started Sep 24 10:35:10 AM UTC 24
Finished Sep 24 10:36:52 AM UTC 24
Peak memory 212384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525670151 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_escalation.1525670151
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/16.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.832358390
Short name T320
Test name
Test status
Simulation time 795312777 ps
CPU time 77.09 seconds
Started Sep 24 10:34:32 AM UTC 24
Finished Sep 24 10:35:51 AM UTC 24
Peak memory 352496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
832358390 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_m
ax_throughput.832358390
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/16.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.2192929593
Short name T334
Test name
Test status
Simulation time 11590261474 ps
CPU time 202.63 seconds
Started Sep 24 10:37:11 AM UTC 24
Finished Sep 24 10:40:37 AM UTC 24
Peak memory 229548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192929593 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_mem_partial_access.2192929593
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/16.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.701658329
Short name T332
Test name
Test status
Simulation time 10474960787 ps
CPU time 184.42 seconds
Started Sep 24 10:37:01 AM UTC 24
Finished Sep 24 10:40:09 AM UTC 24
Peak memory 222948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701658329 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_mem_walk.701658329
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/16.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.3522689293
Short name T374
Test name
Test status
Simulation time 19252130703 ps
CPU time 748.07 seconds
Started Sep 24 10:34:14 AM UTC 24
Finished Sep 24 10:46:50 AM UTC 24
Peak memory 389388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522689293 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multiple_keys.3522689293
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/16.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access.3522102164
Short name T317
Test name
Test status
Simulation time 993050137 ps
CPU time 39.05 seconds
Started Sep 24 10:34:24 AM UTC 24
Finished Sep 24 10:35:05 AM UTC 24
Peak memory 286864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522102164 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_partial_access.3522102164
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/16.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.1478261689
Short name T337
Test name
Test status
Simulation time 12697966986 ps
CPU time 402.81 seconds
Started Sep 24 10:34:26 AM UTC 24
Finished Sep 24 10:41:15 AM UTC 24
Peak memory 212348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478261689 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_partial_a
ccess_b2b.1478261689
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/16.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.870041862
Short name T323
Test name
Test status
Simulation time 1397370596 ps
CPU time 7.01 seconds
Started Sep 24 10:36:52 AM UTC 24
Finished Sep 24 10:37:00 AM UTC 24
Peak memory 212560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870041862 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.870041862
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/16.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_regwen.1874749353
Short name T412
Test name
Test status
Simulation time 6181351560 ps
CPU time 1094.1 seconds
Started Sep 24 10:36:21 AM UTC 24
Finished Sep 24 10:54:49 AM UTC 24
Peak memory 387364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874749353 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.1874749353
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/16.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_smoke.2653653160
Short name T314
Test name
Test status
Simulation time 1443121787 ps
CPU time 24.25 seconds
Started Sep 24 10:33:58 AM UTC 24
Finished Sep 24 10:34:23 AM UTC 24
Peak memory 264420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653653160 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.2653653160
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/16.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all.3410148325
Short name T556
Test name
Test status
Simulation time 82900733619 ps
CPU time 2891.36 seconds
Started Sep 24 10:37:44 AM UTC 24
Finished Sep 24 11:26:27 AM UTC 24
Peak memory 401108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34101483
25 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_a
ll.3410148325
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/16.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.395211197
Short name T326
Test name
Test status
Simulation time 804590340 ps
CPU time 38.01 seconds
Started Sep 24 10:37:31 AM UTC 24
Finished Sep 24 10:38:11 AM UTC 24
Peak memory 224776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395211197 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.395211197
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/16.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.2244341719
Short name T325
Test name
Test status
Simulation time 2744984601 ps
CPU time 195.34 seconds
Started Sep 24 10:34:24 AM UTC 24
Finished Sep 24 10:37:43 AM UTC 24
Peak memory 212512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244341719 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_pipeline.2244341719
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/16.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.3020182885
Short name T321
Test name
Test status
Simulation time 2791315916 ps
CPU time 73.34 seconds
Started Sep 24 10:35:06 AM UTC 24
Finished Sep 24 10:36:21 AM UTC 24
Peak memory 336092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3020182885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl
_throughput_w_partial_write.3020182885
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/16.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.3453190740
Short name T437
Test name
Test status
Simulation time 56906557305 ps
CPU time 1100.59 seconds
Started Sep 24 10:41:15 AM UTC 24
Finished Sep 24 10:59:48 AM UTC 24
Peak memory 389564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453190740 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_access_duri
ng_key_req.3453190740
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/17.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_alert_test.3895277615
Short name T346
Test name
Test status
Simulation time 11246011 ps
CPU time 1.03 seconds
Started Sep 24 10:41:36 AM UTC 24
Finished Sep 24 10:41:39 AM UTC 24
Peak memory 211352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895277615
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_alert_test.3895277615
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/17.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_bijection.1137037384
Short name T373
Test name
Test status
Simulation time 14061882005 ps
CPU time 452.44 seconds
Started Sep 24 10:38:53 AM UTC 24
Finished Sep 24 10:46:32 AM UTC 24
Peak memory 212492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137037384 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection.1137037384
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/17.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_executable.3236499773
Short name T384
Test name
Test status
Simulation time 4675094652 ps
CPU time 430.78 seconds
Started Sep 24 10:41:15 AM UTC 24
Finished Sep 24 10:48:32 AM UTC 24
Peak memory 377052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236499773 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executable.3236499773
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/17.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.2821325066
Short name T343
Test name
Test status
Simulation time 4599474790 ps
CPU time 48.13 seconds
Started Sep 24 10:40:43 AM UTC 24
Finished Sep 24 10:41:33 AM UTC 24
Peak memory 212492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821325066 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_escalation.2821325066
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/17.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.824230044
Short name T345
Test name
Test status
Simulation time 3152500215 ps
CPU time 77.75 seconds
Started Sep 24 10:40:16 AM UTC 24
Finished Sep 24 10:41:35 AM UTC 24
Peak memory 370840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
824230044 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_m
ax_throughput.824230044
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/17.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.2822231544
Short name T356
Test name
Test status
Simulation time 24175233565 ps
CPU time 127.97 seconds
Started Sep 24 10:41:28 AM UTC 24
Finished Sep 24 10:43:38 AM UTC 24
Peak memory 224692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822231544 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_mem_partial_access.2822231544
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/17.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.1851476704
Short name T377
Test name
Test status
Simulation time 21010006429 ps
CPU time 345.46 seconds
Started Sep 24 10:41:22 AM UTC 24
Finished Sep 24 10:47:12 AM UTC 24
Peak memory 222620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851476704 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_mem_walk.1851476704
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/17.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.1219777975
Short name T431
Test name
Test status
Simulation time 17425243631 ps
CPU time 1256.08 seconds
Started Sep 24 10:38:16 AM UTC 24
Finished Sep 24 10:59:26 AM UTC 24
Peak memory 389492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219777975 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multiple_keys.1219777975
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/17.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access.3193633100
Short name T336
Test name
Test status
Simulation time 9294922214 ps
CPU time 72.12 seconds
Started Sep 24 10:40:00 AM UTC 24
Finished Sep 24 10:41:14 AM UTC 24
Peak memory 375064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193633100 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_partial_access.3193633100
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/17.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.1189093010
Short name T364
Test name
Test status
Simulation time 65421824059 ps
CPU time 291.45 seconds
Started Sep 24 10:40:10 AM UTC 24
Finished Sep 24 10:45:05 AM UTC 24
Peak memory 212404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189093010 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_partial_a
ccess_b2b.1189093010
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/17.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.1460197667
Short name T341
Test name
Test status
Simulation time 480731876 ps
CPU time 5.33 seconds
Started Sep 24 10:41:21 AM UTC 24
Finished Sep 24 10:41:27 AM UTC 24
Peak memory 212560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460197667 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.1460197667
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/17.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_regwen.1586617380
Short name T372
Test name
Test status
Simulation time 8211951610 ps
CPU time 293.29 seconds
Started Sep 24 10:41:20 AM UTC 24
Finished Sep 24 10:46:18 AM UTC 24
Peak memory 356540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586617380 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.1586617380
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/17.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_smoke.2354847937
Short name T329
Test name
Test status
Simulation time 3132811652 ps
CPU time 34.85 seconds
Started Sep 24 10:38:15 AM UTC 24
Finished Sep 24 10:38:52 AM UTC 24
Peak memory 323776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354847937 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.2354847937
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/17.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all.2995821650
Short name T640
Test name
Test status
Simulation time 385189506290 ps
CPU time 4023.29 seconds
Started Sep 24 10:41:34 AM UTC 24
Finished Sep 24 11:49:22 AM UTC 24
Peak memory 401244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29958216
50 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_a
ll.2995821650
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/17.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.1411183648
Short name T349
Test name
Test status
Simulation time 685387822 ps
CPU time 26.18 seconds
Started Sep 24 10:41:32 AM UTC 24
Finished Sep 24 10:41:59 AM UTC 24
Peak memory 222724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411183648 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.1411183648
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/17.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.3477894106
Short name T362
Test name
Test status
Simulation time 4522417377 ps
CPU time 346.16 seconds
Started Sep 24 10:39:09 AM UTC 24
Finished Sep 24 10:45:01 AM UTC 24
Peak memory 212352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477894106 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_pipeline.3477894106
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/17.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.316588636
Short name T348
Test name
Test status
Simulation time 825938193 ps
CPU time 72.54 seconds
Started Sep 24 10:40:38 AM UTC 24
Finished Sep 24 10:41:52 AM UTC 24
Peak memory 377256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=316588636 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_
throughput_w_partial_write.316588636
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/17.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.1817577949
Short name T365
Test name
Test status
Simulation time 2764517464 ps
CPU time 146.66 seconds
Started Sep 24 10:42:40 AM UTC 24
Finished Sep 24 10:45:09 AM UTC 24
Peak memory 383440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817577949 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_access_duri
ng_key_req.1817577949
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/18.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_alert_test.896625104
Short name T363
Test name
Test status
Simulation time 10947398 ps
CPU time 1.01 seconds
Started Sep 24 10:45:03 AM UTC 24
Finished Sep 24 10:45:05 AM UTC 24
Peak memory 210880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896625104 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_alert_test.896625104
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/18.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_bijection.3985507530
Short name T405
Test name
Test status
Simulation time 55739663077 ps
CPU time 706.33 seconds
Started Sep 24 10:41:52 AM UTC 24
Finished Sep 24 10:53:47 AM UTC 24
Peak memory 212344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985507530 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection.3985507530
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/18.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_executable.1908551979
Short name T426
Test name
Test status
Simulation time 62635797605 ps
CPU time 931.25 seconds
Started Sep 24 10:42:59 AM UTC 24
Finished Sep 24 10:58:42 AM UTC 24
Peak memory 389412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908551979 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executable.1908551979
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/18.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.3270712261
Short name T358
Test name
Test status
Simulation time 49972432127 ps
CPU time 71.2 seconds
Started Sep 24 10:42:38 AM UTC 24
Finished Sep 24 10:43:51 AM UTC 24
Peak memory 222900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270712261 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_escalation.3270712261
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/18.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.2489683663
Short name T353
Test name
Test status
Simulation time 3131957937 ps
CPU time 18.71 seconds
Started Sep 24 10:42:17 AM UTC 24
Finished Sep 24 10:42:37 AM UTC 24
Peak memory 249996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2489683663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_
max_throughput.2489683663
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/18.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.1695247447
Short name T369
Test name
Test status
Simulation time 6620644702 ps
CPU time 123.96 seconds
Started Sep 24 10:43:52 AM UTC 24
Finished Sep 24 10:45:58 AM UTC 24
Peak memory 222640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695247447 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_mem_partial_access.1695247447
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/18.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.2120780932
Short name T390
Test name
Test status
Simulation time 14536197023 ps
CPU time 342.9 seconds
Started Sep 24 10:43:52 AM UTC 24
Finished Sep 24 10:49:39 AM UTC 24
Peak memory 222616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120780932 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_mem_walk.2120780932
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/18.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.1675267721
Short name T375
Test name
Test status
Simulation time 29972378147 ps
CPU time 309.97 seconds
Started Sep 24 10:41:40 AM UTC 24
Finished Sep 24 10:46:54 AM UTC 24
Peak memory 368876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675267721 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multiple_keys.1675267721
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/18.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access.4263759055
Short name T352
Test name
Test status
Simulation time 1302192337 ps
CPU time 24.68 seconds
Started Sep 24 10:42:00 AM UTC 24
Finished Sep 24 10:42:27 AM UTC 24
Peak memory 212444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263759055 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_partial_access.4263759055
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/18.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.336513764
Short name T397
Test name
Test status
Simulation time 6898264754 ps
CPU time 478.94 seconds
Started Sep 24 10:42:17 AM UTC 24
Finished Sep 24 10:50:23 AM UTC 24
Peak memory 212524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336513764 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_partial_ac
cess_b2b.336513764
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/18.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.4028091143
Short name T359
Test name
Test status
Simulation time 362862444 ps
CPU time 5.31 seconds
Started Sep 24 10:43:45 AM UTC 24
Finished Sep 24 10:43:51 AM UTC 24
Peak memory 212296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028091143 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.4028091143
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/18.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_regwen.3312828507
Short name T440
Test name
Test status
Simulation time 67268368640 ps
CPU time 986.09 seconds
Started Sep 24 10:43:39 AM UTC 24
Finished Sep 24 11:00:18 AM UTC 24
Peak memory 385316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312828507 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.3312828507
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/18.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_smoke.67652392
Short name T351
Test name
Test status
Simulation time 5881908329 ps
CPU time 37.7 seconds
Started Sep 24 10:41:36 AM UTC 24
Finished Sep 24 10:42:16 AM UTC 24
Peak memory 212420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67652392 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.67652392
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/18.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all.2148840313
Short name T614
Test name
Test status
Simulation time 70557921217 ps
CPU time 3545.4 seconds
Started Sep 24 10:44:15 AM UTC 24
Finished Sep 24 11:43:59 AM UTC 24
Peak memory 390940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21488403
13 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_a
ll.2148840313
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/18.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.297245999
Short name T366
Test name
Test status
Simulation time 1191867218 ps
CPU time 69.49 seconds
Started Sep 24 10:44:04 AM UTC 24
Finished Sep 24 10:45:15 AM UTC 24
Peak memory 226904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297245999 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.297245999
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/18.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.1015242362
Short name T371
Test name
Test status
Simulation time 17566882006 ps
CPU time 253.9 seconds
Started Sep 24 10:41:53 AM UTC 24
Finished Sep 24 10:46:12 AM UTC 24
Peak memory 212672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015242362 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_pipeline.1015242362
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/18.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.207105427
Short name T357
Test name
Test status
Simulation time 1704634343 ps
CPU time 74.77 seconds
Started Sep 24 10:42:28 AM UTC 24
Finished Sep 24 10:43:44 AM UTC 24
Peak memory 381092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=207105427 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_
throughput_w_partial_write.207105427
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/18.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.1458298823
Short name T460
Test name
Test status
Simulation time 13599931819 ps
CPU time 1044.63 seconds
Started Sep 24 10:46:19 AM UTC 24
Finished Sep 24 11:03:57 AM UTC 24
Peak memory 385332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458298823 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_access_duri
ng_key_req.1458298823
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/19.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_alert_test.2593587043
Short name T382
Test name
Test status
Simulation time 15765600 ps
CPU time 0.98 seconds
Started Sep 24 10:47:52 AM UTC 24
Finished Sep 24 10:47:54 AM UTC 24
Peak memory 211352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593587043
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_alert_test.2593587043
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/19.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_bijection.1339025096
Short name T526
Test name
Test status
Simulation time 153576485894 ps
CPU time 2012.02 seconds
Started Sep 24 10:45:10 AM UTC 24
Finished Sep 24 11:19:07 AM UTC 24
Peak memory 213996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339025096 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection.1339025096
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/19.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_executable.2366008231
Short name T462
Test name
Test status
Simulation time 103835613013 ps
CPU time 1043.7 seconds
Started Sep 24 10:46:33 AM UTC 24
Finished Sep 24 11:04:10 AM UTC 24
Peak memory 389416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366008231 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executable.2366008231
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/19.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.1800079227
Short name T381
Test name
Test status
Simulation time 11493328462 ps
CPU time 97.34 seconds
Started Sep 24 10:46:13 AM UTC 24
Finished Sep 24 10:47:52 AM UTC 24
Peak memory 222628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800079227 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_escalation.1800079227
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/19.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.2110050653
Short name T378
Test name
Test status
Simulation time 3048854112 ps
CPU time 97.69 seconds
Started Sep 24 10:45:59 AM UTC 24
Finished Sep 24 10:47:39 AM UTC 24
Peak memory 381216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2110050653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_
max_throughput.2110050653
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/19.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.3787768753
Short name T385
Test name
Test status
Simulation time 971085743 ps
CPU time 78.01 seconds
Started Sep 24 10:47:14 AM UTC 24
Finished Sep 24 10:48:34 AM UTC 24
Peak memory 229784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787768753 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_mem_partial_access.3787768753
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/19.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.2717576012
Short name T399
Test name
Test status
Simulation time 41428405279 ps
CPU time 204.04 seconds
Started Sep 24 10:47:01 AM UTC 24
Finished Sep 24 10:50:29 AM UTC 24
Peak memory 222648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717576012 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_mem_walk.2717576012
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/19.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.1618076273
Short name T383
Test name
Test status
Simulation time 30570303619 ps
CPU time 179.48 seconds
Started Sep 24 10:45:06 AM UTC 24
Finished Sep 24 10:48:08 AM UTC 24
Peak memory 356588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618076273 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multiple_keys.1618076273
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/19.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access.1441054329
Short name T370
Test name
Test status
Simulation time 7089967848 ps
CPU time 18.55 seconds
Started Sep 24 10:45:40 AM UTC 24
Finished Sep 24 10:46:00 AM UTC 24
Peak memory 237780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441054329 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_partial_access.1441054329
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/19.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.2037828181
Short name T409
Test name
Test status
Simulation time 68351256985 ps
CPU time 530.21 seconds
Started Sep 24 10:45:40 AM UTC 24
Finished Sep 24 10:54:38 AM UTC 24
Peak memory 212676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037828181 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_partial_a
ccess_b2b.2037828181
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/19.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.3392851961
Short name T376
Test name
Test status
Simulation time 2789839329 ps
CPU time 5.06 seconds
Started Sep 24 10:46:54 AM UTC 24
Finished Sep 24 10:47:00 AM UTC 24
Peak memory 212360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392851961 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.3392851961
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/19.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_regwen.770335864
Short name T380
Test name
Test status
Simulation time 10399339934 ps
CPU time 58.71 seconds
Started Sep 24 10:46:51 AM UTC 24
Finished Sep 24 10:47:52 AM UTC 24
Peak memory 248024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770335864 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.770335864
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/19.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_smoke.1384130452
Short name T368
Test name
Test status
Simulation time 1692733108 ps
CPU time 32.22 seconds
Started Sep 24 10:45:06 AM UTC 24
Finished Sep 24 10:45:39 AM UTC 24
Peak memory 212116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384130452 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.1384130452
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/19.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all.2041490685
Short name T596
Test name
Test status
Simulation time 287608909789 ps
CPU time 3089.25 seconds
Started Sep 24 10:47:42 AM UTC 24
Finished Sep 24 11:39:47 AM UTC 24
Peak memory 380972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20414906
85 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_a
ll.2041490685
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/19.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.147608721
Short name T119
Test name
Test status
Simulation time 5490008307 ps
CPU time 60.81 seconds
Started Sep 24 10:47:40 AM UTC 24
Finished Sep 24 10:48:42 AM UTC 24
Peak memory 224844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147608721 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.147608721
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/19.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.3559464206
Short name T394
Test name
Test status
Simulation time 9953819261 ps
CPU time 286.95 seconds
Started Sep 24 10:45:16 AM UTC 24
Finished Sep 24 10:50:09 AM UTC 24
Peak memory 212424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559464206 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_pipeline.3559464206
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/19.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.1974192979
Short name T379
Test name
Test status
Simulation time 2866087698 ps
CPU time 98.02 seconds
Started Sep 24 10:46:01 AM UTC 24
Finished Sep 24 10:47:41 AM UTC 24
Peak memory 368928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1974192979 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl
_throughput_w_partial_write.1974192979
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/19.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.3823701076
Short name T40
Test name
Test status
Simulation time 17825159399 ps
CPU time 543.12 seconds
Started Sep 24 09:49:40 AM UTC 24
Finished Sep 24 09:58:50 AM UTC 24
Peak memory 379096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823701076 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_access_durin
g_key_req.3823701076
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/2.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_alert_test.2008501732
Short name T15
Test name
Test status
Simulation time 35261366 ps
CPU time 1.04 seconds
Started Sep 24 09:50:04 AM UTC 24
Finished Sep 24 09:50:06 AM UTC 24
Peak memory 211416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008501732
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_alert_test.2008501732
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/2.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_bijection.1944497289
Short name T273
Test name
Test status
Simulation time 39119497456 ps
CPU time 2130.03 seconds
Started Sep 24 09:49:40 AM UTC 24
Finished Sep 24 10:25:35 AM UTC 24
Peak memory 213912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944497289 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection.1944497289
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/2.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_executable.266065858
Short name T27
Test name
Test status
Simulation time 9385980231 ps
CPU time 660.26 seconds
Started Sep 24 09:49:43 AM UTC 24
Finished Sep 24 10:00:53 AM UTC 24
Peak memory 379244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266065858 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executable.266065858
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/2.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.4226047866
Short name T11
Test name
Test status
Simulation time 63954920870 ps
CPU time 110.19 seconds
Started Sep 24 09:49:40 AM UTC 24
Finished Sep 24 09:51:32 AM UTC 24
Peak memory 212432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226047866 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_escalation.4226047866
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/2.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.885118329
Short name T21
Test name
Test status
Simulation time 5388407663 ps
CPU time 30.54 seconds
Started Sep 24 09:49:40 AM UTC 24
Finished Sep 24 09:50:12 AM UTC 24
Peak memory 270632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
885118329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ma
x_throughput.885118329
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/2.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.3765686691
Short name T78
Test name
Test status
Simulation time 6293289326 ps
CPU time 126.21 seconds
Started Sep 24 09:49:53 AM UTC 24
Finished Sep 24 09:52:02 AM UTC 24
Peak memory 229656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765686691 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_mem_partial_access.3765686691
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/2.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.4030144336
Short name T156
Test name
Test status
Simulation time 8210474525 ps
CPU time 246.18 seconds
Started Sep 24 09:49:49 AM UTC 24
Finished Sep 24 09:53:59 AM UTC 24
Peak memory 222704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030144336 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_mem_walk.4030144336
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/2.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.1738936513
Short name T36
Test name
Test status
Simulation time 1876488171 ps
CPU time 41.03 seconds
Started Sep 24 09:49:40 AM UTC 24
Finished Sep 24 09:50:22 AM UTC 24
Peak memory 301152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738936513 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multiple_keys.1738936513
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/2.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access.3336847562
Short name T30
Test name
Test status
Simulation time 707727585 ps
CPU time 18.21 seconds
Started Sep 24 09:49:40 AM UTC 24
Finished Sep 24 09:49:59 AM UTC 24
Peak memory 239688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336847562 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_partial_access.3336847562
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/2.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.1719760250
Short name T172
Test name
Test status
Simulation time 17629321761 ps
CPU time 520.58 seconds
Started Sep 24 09:49:40 AM UTC 24
Finished Sep 24 09:58:27 AM UTC 24
Peak memory 212568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719760250 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_partial_ac
cess_b2b.1719760250
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/2.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.3931025955
Short name T31
Test name
Test status
Simulation time 376090934 ps
CPU time 5.8 seconds
Started Sep 24 09:49:45 AM UTC 24
Finished Sep 24 09:49:52 AM UTC 24
Peak memory 212116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931025955 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.3931025955
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/2.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_regwen.604440582
Short name T114
Test name
Test status
Simulation time 55468619472 ps
CPU time 847.81 seconds
Started Sep 24 09:49:45 AM UTC 24
Finished Sep 24 10:04:04 AM UTC 24
Peak memory 391152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604440582 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.604440582
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/2.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.106981528
Short name T7
Test name
Test status
Simulation time 541543231 ps
CPU time 3.2 seconds
Started Sep 24 09:50:02 AM UTC 24
Finished Sep 24 09:50:06 AM UTC 24
Peak memory 248348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106981528 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_sec_cm.106981528
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_smoke.2243271174
Short name T51
Test name
Test status
Simulation time 3921071701 ps
CPU time 86.41 seconds
Started Sep 24 09:49:40 AM UTC 24
Finished Sep 24 09:51:08 AM UTC 24
Peak memory 377120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243271174 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.2243271174
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/2.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all.1083386539
Short name T626
Test name
Test status
Simulation time 1443238421215 ps
CPU time 6930.77 seconds
Started Sep 24 09:49:58 AM UTC 24
Finished Sep 24 11:46:45 AM UTC 24
Peak memory 393052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10833865
39 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all.1083386539
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/2.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.2611785831
Short name T23
Test name
Test status
Simulation time 5139694491 ps
CPU time 46.62 seconds
Started Sep 24 09:49:56 AM UTC 24
Finished Sep 24 09:50:44 AM UTC 24
Peak memory 226896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611785831 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.2611785831
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/2.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.2918498620
Short name T107
Test name
Test status
Simulation time 16760122032 ps
CPU time 295.47 seconds
Started Sep 24 09:49:40 AM UTC 24
Finished Sep 24 09:54:40 AM UTC 24
Peak memory 212436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918498620 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_pipeline.2918498620
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/2.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.2925316703
Short name T49
Test name
Test status
Simulation time 796579540 ps
CPU time 76.61 seconds
Started Sep 24 09:49:40 AM UTC 24
Finished Sep 24 09:50:59 AM UTC 24
Peak memory 344300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2925316703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_
throughput_w_partial_write.2925316703
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/2.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.2038697739
Short name T475
Test name
Test status
Simulation time 56932766323 ps
CPU time 1054.32 seconds
Started Sep 24 10:49:29 AM UTC 24
Finished Sep 24 11:07:16 AM UTC 24
Peak memory 389356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038697739 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_access_duri
ng_key_req.2038697739
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/20.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_alert_test.2643411351
Short name T398
Test name
Test status
Simulation time 34775044 ps
CPU time 1.08 seconds
Started Sep 24 10:50:24 AM UTC 24
Finished Sep 24 10:50:26 AM UTC 24
Peak memory 211352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643411351
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_alert_test.2643411351
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/20.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_bijection.3909611449
Short name T503
Test name
Test status
Simulation time 21282993624 ps
CPU time 1614.41 seconds
Started Sep 24 10:48:09 AM UTC 24
Finished Sep 24 11:15:23 AM UTC 24
Peak memory 214020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909611449 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection.3909611449
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/20.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_executable.1070929634
Short name T463
Test name
Test status
Simulation time 31415470887 ps
CPU time 866.31 seconds
Started Sep 24 10:49:41 AM UTC 24
Finished Sep 24 11:04:18 AM UTC 24
Peak memory 387288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070929634 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executable.1070929634
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/20.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.4183392214
Short name T393
Test name
Test status
Simulation time 8324885085 ps
CPU time 54.67 seconds
Started Sep 24 10:49:06 AM UTC 24
Finished Sep 24 10:50:02 AM UTC 24
Peak memory 226752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183392214 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_escalation.4183392214
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/20.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.4050861642
Short name T396
Test name
Test status
Simulation time 15048798575 ps
CPU time 94 seconds
Started Sep 24 10:48:43 AM UTC 24
Finished Sep 24 10:50:19 AM UTC 24
Peak memory 362980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
4050861642 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_
max_throughput.4050861642
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/20.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.206338740
Short name T402
Test name
Test status
Simulation time 10759434554 ps
CPU time 82.66 seconds
Started Sep 24 10:50:09 AM UTC 24
Finished Sep 24 10:51:34 AM UTC 24
Peak memory 224808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206338740 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_mem_partial_access.206338740
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/20.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.3288977007
Short name T414
Test name
Test status
Simulation time 15442761991 ps
CPU time 369.82 seconds
Started Sep 24 10:50:03 AM UTC 24
Finished Sep 24 10:56:19 AM UTC 24
Peak memory 222880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288977007 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_mem_walk.3288977007
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/20.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.3068762462
Short name T401
Test name
Test status
Simulation time 4867812944 ps
CPU time 191.3 seconds
Started Sep 24 10:47:55 AM UTC 24
Finished Sep 24 10:51:10 AM UTC 24
Peak memory 368780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068762462 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multiple_keys.3068762462
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/20.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access.3484215107
Short name T388
Test name
Test status
Simulation time 1181705902 ps
CPU time 28.25 seconds
Started Sep 24 10:48:35 AM UTC 24
Finished Sep 24 10:49:05 AM UTC 24
Peak memory 212368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484215107 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_partial_access.3484215107
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/20.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.1794870264
Short name T428
Test name
Test status
Simulation time 18810753813 ps
CPU time 613.3 seconds
Started Sep 24 10:48:36 AM UTC 24
Finished Sep 24 10:58:59 AM UTC 24
Peak memory 212404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794870264 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_partial_a
ccess_b2b.1794870264
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/20.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.538864631
Short name T395
Test name
Test status
Simulation time 353536644 ps
CPU time 5.78 seconds
Started Sep 24 10:50:02 AM UTC 24
Finished Sep 24 10:50:09 AM UTC 24
Peak memory 212372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538864631 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.538864631
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/20.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_regwen.2084230493
Short name T467
Test name
Test status
Simulation time 64194044990 ps
CPU time 931.65 seconds
Started Sep 24 10:49:59 AM UTC 24
Finished Sep 24 11:05:41 AM UTC 24
Peak memory 385244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084230493 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.2084230493
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/20.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_smoke.4220555719
Short name T389
Test name
Test status
Simulation time 1644870165 ps
CPU time 92.83 seconds
Started Sep 24 10:47:53 AM UTC 24
Finished Sep 24 10:49:28 AM UTC 24
Peak memory 376960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220555719 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.4220555719
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/20.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all.3570082377
Short name T609
Test name
Test status
Simulation time 182960971891 ps
CPU time 3128.36 seconds
Started Sep 24 10:50:21 AM UTC 24
Finished Sep 24 11:43:03 AM UTC 24
Peak memory 401196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35700823
77 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_a
ll.3570082377
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/20.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.54494246
Short name T120
Test name
Test status
Simulation time 9571192704 ps
CPU time 201.33 seconds
Started Sep 24 10:50:11 AM UTC 24
Finished Sep 24 10:53:36 AM UTC 24
Peak memory 393636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54494246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.54494246
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/20.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.895456247
Short name T410
Test name
Test status
Simulation time 6065533985 ps
CPU time 360.98 seconds
Started Sep 24 10:48:33 AM UTC 24
Finished Sep 24 10:54:39 AM UTC 24
Peak memory 212600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895456247 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_pipeline.895456247
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/20.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.3956703732
Short name T392
Test name
Test status
Simulation time 779948514 ps
CPU time 73.51 seconds
Started Sep 24 10:48:45 AM UTC 24
Finished Sep 24 10:50:01 AM UTC 24
Peak memory 340384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3956703732 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl
_throughput_w_partial_write.3956703732
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/20.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.757434603
Short name T454
Test name
Test status
Simulation time 51989432899 ps
CPU time 524.74 seconds
Started Sep 24 10:53:54 AM UTC 24
Finished Sep 24 11:02:46 AM UTC 24
Peak memory 334048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757434603 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_access_durin
g_key_req.757434603
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/21.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_alert_test.962921930
Short name T415
Test name
Test status
Simulation time 142340664 ps
CPU time 1.2 seconds
Started Sep 24 10:56:20 AM UTC 24
Finished Sep 24 10:56:22 AM UTC 24
Peak memory 211472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962921930 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_alert_test.962921930
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/21.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_executable.604028096
Short name T477
Test name
Test status
Simulation time 21337382863 ps
CPU time 786.65 seconds
Started Sep 24 10:54:21 AM UTC 24
Finished Sep 24 11:07:38 AM UTC 24
Peak memory 383164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604028096 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executable.604028096
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/21.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.978148998
Short name T413
Test name
Test status
Simulation time 25812232084 ps
CPU time 64.72 seconds
Started Sep 24 10:53:49 AM UTC 24
Finished Sep 24 10:54:55 AM UTC 24
Peak memory 222608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978148998 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_escalation.978148998
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/21.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.363733372
Short name T407
Test name
Test status
Simulation time 718007352 ps
CPU time 42.49 seconds
Started Sep 24 10:53:36 AM UTC 24
Finished Sep 24 10:54:20 AM UTC 24
Peak memory 295152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
363733372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_m
ax_throughput.363733372
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/21.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.1449430328
Short name T418
Test name
Test status
Simulation time 5242057200 ps
CPU time 150.96 seconds
Started Sep 24 10:54:48 AM UTC 24
Finished Sep 24 10:57:22 AM UTC 24
Peak memory 222764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449430328 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_mem_partial_access.1449430328
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/21.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.1224303819
Short name T423
Test name
Test status
Simulation time 7051570400 ps
CPU time 190.06 seconds
Started Sep 24 10:54:40 AM UTC 24
Finished Sep 24 10:57:54 AM UTC 24
Peak memory 222880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224303819 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_mem_walk.1224303819
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/21.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.252687277
Short name T417
Test name
Test status
Simulation time 3874917409 ps
CPU time 396.29 seconds
Started Sep 24 10:50:30 AM UTC 24
Finished Sep 24 10:57:12 AM UTC 24
Peak memory 381216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252687277 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multiple_keys.252687277
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/21.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access.1870966517
Short name T403
Test name
Test status
Simulation time 1467101320 ps
CPU time 22.81 seconds
Started Sep 24 10:51:35 AM UTC 24
Finished Sep 24 10:51:59 AM UTC 24
Peak memory 260240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870966517 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_partial_access.1870966517
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/21.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.476485194
Short name T429
Test name
Test status
Simulation time 15892224363 ps
CPU time 418.45 seconds
Started Sep 24 10:52:00 AM UTC 24
Finished Sep 24 10:59:04 AM UTC 24
Peak memory 212368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476485194 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_partial_ac
cess_b2b.476485194
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/21.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.2821180767
Short name T411
Test name
Test status
Simulation time 4785339881 ps
CPU time 8.1 seconds
Started Sep 24 10:54:38 AM UTC 24
Finished Sep 24 10:54:47 AM UTC 24
Peak memory 212436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821180767 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.2821180767
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/21.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_regwen.908624578
Short name T420
Test name
Test status
Simulation time 10084183620 ps
CPU time 193.7 seconds
Started Sep 24 10:54:25 AM UTC 24
Finished Sep 24 10:57:42 AM UTC 24
Peak memory 383132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908624578 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.908624578
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/21.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_smoke.1047588524
Short name T400
Test name
Test status
Simulation time 14521299885 ps
CPU time 33.7 seconds
Started Sep 24 10:50:27 AM UTC 24
Finished Sep 24 10:51:02 AM UTC 24
Peak memory 212392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047588524 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.1047588524
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/21.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all.2049818620
Short name T699
Test name
Test status
Simulation time 163780136358 ps
CPU time 3629.7 seconds
Started Sep 24 10:54:57 AM UTC 24
Finished Sep 24 11:56:05 AM UTC 24
Peak memory 393252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20498186
20 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_a
ll.2049818620
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/21.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.1809362177
Short name T432
Test name
Test status
Simulation time 9353472427 ps
CPU time 488.61 seconds
Started Sep 24 10:51:11 AM UTC 24
Finished Sep 24 10:59:27 AM UTC 24
Peak memory 212388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809362177 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_pipeline.1809362177
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/21.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.634534353
Short name T408
Test name
Test status
Simulation time 763491825 ps
CPU time 44.12 seconds
Started Sep 24 10:53:38 AM UTC 24
Finished Sep 24 10:54:24 AM UTC 24
Peak memory 317668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=634534353 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_
throughput_w_partial_write.634534353
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/21.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.2780397265
Short name T509
Test name
Test status
Simulation time 157516061976 ps
CPU time 1058.19 seconds
Started Sep 24 10:57:55 AM UTC 24
Finished Sep 24 11:15:46 AM UTC 24
Peak memory 385252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780397265 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_access_duri
ng_key_req.2780397265
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/22.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_alert_test.87290761
Short name T433
Test name
Test status
Simulation time 56403840 ps
CPU time 1.03 seconds
Started Sep 24 10:59:27 AM UTC 24
Finished Sep 24 10:59:29 AM UTC 24
Peak memory 211352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87290761 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_alert_test.87290761
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/22.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_bijection.2141961399
Short name T511
Test name
Test status
Simulation time 137186893525 ps
CPU time 1132.1 seconds
Started Sep 24 10:56:50 AM UTC 24
Finished Sep 24 11:15:55 AM UTC 24
Peak memory 212488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141961399 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection.2141961399
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/22.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_executable.860512840
Short name T479
Test name
Test status
Simulation time 16435725121 ps
CPU time 612.41 seconds
Started Sep 24 10:57:56 AM UTC 24
Finished Sep 24 11:08:16 AM UTC 24
Peak memory 370976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860512840 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executable.860512840
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/22.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.3410013836
Short name T435
Test name
Test status
Simulation time 51619823213 ps
CPU time 116.22 seconds
Started Sep 24 10:57:49 AM UTC 24
Finished Sep 24 10:59:47 AM UTC 24
Peak memory 212472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410013836 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_escalation.3410013836
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/22.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.4214930732
Short name T425
Test name
Test status
Simulation time 682147529 ps
CPU time 12.39 seconds
Started Sep 24 10:57:42 AM UTC 24
Finished Sep 24 10:57:56 AM UTC 24
Peak memory 222640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
4214930732 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_
max_throughput.4214930732
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/22.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.4158759289
Short name T445
Test name
Test status
Simulation time 6147856975 ps
CPU time 128.02 seconds
Started Sep 24 10:59:00 AM UTC 24
Finished Sep 24 11:01:10 AM UTC 24
Peak memory 222724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158759289 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_mem_partial_access.4158759289
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/22.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.2947146055
Short name T452
Test name
Test status
Simulation time 44969817413 ps
CPU time 212.9 seconds
Started Sep 24 10:58:51 AM UTC 24
Finished Sep 24 11:02:28 AM UTC 24
Peak memory 222620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947146055 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_mem_walk.2947146055
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/22.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.373296920
Short name T506
Test name
Test status
Simulation time 11652571977 ps
CPU time 1125.19 seconds
Started Sep 24 10:56:37 AM UTC 24
Finished Sep 24 11:15:35 AM UTC 24
Peak memory 390940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373296920 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multiple_keys.373296920
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/22.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access.3558126448
Short name T421
Test name
Test status
Simulation time 1685584583 ps
CPU time 18.29 seconds
Started Sep 24 10:57:23 AM UTC 24
Finished Sep 24 10:57:43 AM UTC 24
Peak memory 212592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558126448 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_partial_access.3558126448
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/22.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.1012122144
Short name T449
Test name
Test status
Simulation time 16593094340 ps
CPU time 290.78 seconds
Started Sep 24 10:57:28 AM UTC 24
Finished Sep 24 11:02:24 AM UTC 24
Peak memory 212576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012122144 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_partial_a
ccess_b2b.1012122144
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/22.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.3901156666
Short name T427
Test name
Test status
Simulation time 1612812435 ps
CPU time 6.6 seconds
Started Sep 24 10:58:43 AM UTC 24
Finished Sep 24 10:58:51 AM UTC 24
Peak memory 212564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901156666 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.3901156666
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/22.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_regwen.2853820482
Short name T459
Test name
Test status
Simulation time 2746861295 ps
CPU time 354.46 seconds
Started Sep 24 10:57:57 AM UTC 24
Finished Sep 24 11:03:56 AM UTC 24
Peak memory 379172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853820482 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.2853820482
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/22.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_smoke.3953055189
Short name T416
Test name
Test status
Simulation time 728249233 ps
CPU time 10.62 seconds
Started Sep 24 10:56:23 AM UTC 24
Finished Sep 24 10:56:35 AM UTC 24
Peak memory 218492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953055189 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.3953055189
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/22.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all.4206712417
Short name T755
Test name
Test status
Simulation time 805574784938 ps
CPU time 3827.54 seconds
Started Sep 24 10:59:25 AM UTC 24
Finished Sep 24 12:03:51 PM UTC 24
Peak memory 395036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42067124
17 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_a
ll.4206712417
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/22.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.317052309
Short name T443
Test name
Test status
Simulation time 4908553662 ps
CPU time 100.02 seconds
Started Sep 24 10:59:06 AM UTC 24
Finished Sep 24 11:00:48 AM UTC 24
Peak memory 228976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317052309 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.317052309
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/22.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.1335280708
Short name T448
Test name
Test status
Simulation time 4781010676 ps
CPU time 291.25 seconds
Started Sep 24 10:57:13 AM UTC 24
Finished Sep 24 11:02:09 AM UTC 24
Peak memory 212396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335280708 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_pipeline.1335280708
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/22.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.2236188715
Short name T424
Test name
Test status
Simulation time 2778381467 ps
CPU time 8.9 seconds
Started Sep 24 10:57:44 AM UTC 24
Finished Sep 24 10:57:55 AM UTC 24
Peak memory 222408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2236188715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl
_throughput_w_partial_write.2236188715
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/22.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.3539950720
Short name T520
Test name
Test status
Simulation time 25439655849 ps
CPU time 1048.23 seconds
Started Sep 24 11:00:30 AM UTC 24
Finished Sep 24 11:18:11 AM UTC 24
Peak memory 387368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539950720 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_access_duri
ng_key_req.3539950720
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/23.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_alert_test.3834778675
Short name T451
Test name
Test status
Simulation time 17855681 ps
CPU time 1.01 seconds
Started Sep 24 11:02:26 AM UTC 24
Finished Sep 24 11:02:28 AM UTC 24
Peak memory 210884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834778675
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_alert_test.3834778675
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/23.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_bijection.1555398918
Short name T585
Test name
Test status
Simulation time 33145835301 ps
CPU time 2299.31 seconds
Started Sep 24 10:59:38 AM UTC 24
Finished Sep 24 11:38:24 AM UTC 24
Peak memory 213992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555398918 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection.1555398918
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/23.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_executable.3524756679
Short name T478
Test name
Test status
Simulation time 39101324967 ps
CPU time 429.28 seconds
Started Sep 24 11:00:50 AM UTC 24
Finished Sep 24 11:08:05 AM UTC 24
Peak memory 387424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524756679 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executable.3524756679
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/23.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.4031489332
Short name T447
Test name
Test status
Simulation time 14061104934 ps
CPU time 68.06 seconds
Started Sep 24 11:00:22 AM UTC 24
Finished Sep 24 11:01:32 AM UTC 24
Peak memory 212336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031489332 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_escalation.4031489332
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/23.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.487149557
Short name T441
Test name
Test status
Simulation time 9999153301 ps
CPU time 12.9 seconds
Started Sep 24 11:00:07 AM UTC 24
Finished Sep 24 11:00:21 AM UTC 24
Peak memory 262296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
487149557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_m
ax_throughput.487149557
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/23.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.3744252751
Short name T456
Test name
Test status
Simulation time 6262047768 ps
CPU time 83.57 seconds
Started Sep 24 11:01:33 AM UTC 24
Finished Sep 24 11:02:59 AM UTC 24
Peak memory 222764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744252751 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_mem_partial_access.3744252751
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/23.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.3391440886
Short name T458
Test name
Test status
Simulation time 7897131936 ps
CPU time 147.06 seconds
Started Sep 24 11:01:18 AM UTC 24
Finished Sep 24 11:03:48 AM UTC 24
Peak memory 222688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391440886 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_mem_walk.3391440886
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/23.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.3119818656
Short name T498
Test name
Test status
Simulation time 12801425522 ps
CPU time 884.07 seconds
Started Sep 24 10:59:30 AM UTC 24
Finished Sep 24 11:14:25 AM UTC 24
Peak memory 387272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119818656 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multiple_keys.3119818656
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/23.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access.2260073895
Short name T439
Test name
Test status
Simulation time 649698381 ps
CPU time 13.27 seconds
Started Sep 24 10:59:50 AM UTC 24
Finished Sep 24 11:00:04 AM UTC 24
Peak memory 212508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260073895 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_partial_access.2260073895
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/23.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.2388524315
Short name T468
Test name
Test status
Simulation time 116833500060 ps
CPU time 358.8 seconds
Started Sep 24 10:59:51 AM UTC 24
Finished Sep 24 11:05:55 AM UTC 24
Peak memory 212480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388524315 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_partial_a
ccess_b2b.2388524315
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/23.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.2807612459
Short name T446
Test name
Test status
Simulation time 677279504 ps
CPU time 5.33 seconds
Started Sep 24 11:01:11 AM UTC 24
Finished Sep 24 11:01:17 AM UTC 24
Peak memory 212436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807612459 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.2807612459
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/23.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_regwen.3868737978
Short name T495
Test name
Test status
Simulation time 9994885411 ps
CPU time 762.8 seconds
Started Sep 24 11:00:55 AM UTC 24
Finished Sep 24 11:13:47 AM UTC 24
Peak memory 387268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868737978 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.3868737978
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/23.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_smoke.1813021877
Short name T434
Test name
Test status
Simulation time 701941520 ps
CPU time 8.33 seconds
Started Sep 24 10:59:28 AM UTC 24
Finished Sep 24 10:59:38 AM UTC 24
Peak memory 212352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813021877 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.1813021877
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/23.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all.3465147825
Short name T949
Test name
Test status
Simulation time 185839844187 ps
CPU time 8752.87 seconds
Started Sep 24 11:02:25 AM UTC 24
Finished Sep 24 01:29:57 PM UTC 24
Peak memory 392960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34651478
25 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_a
ll.3465147825
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/23.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.3403787461
Short name T453
Test name
Test status
Simulation time 789462804 ps
CPU time 31.77 seconds
Started Sep 24 11:02:10 AM UTC 24
Finished Sep 24 11:02:44 AM UTC 24
Peak memory 224792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403787461 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.3403787461
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/23.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.2224311996
Short name T450
Test name
Test status
Simulation time 3152105642 ps
CPU time 153.79 seconds
Started Sep 24 10:59:48 AM UTC 24
Finished Sep 24 11:02:25 AM UTC 24
Peak memory 212344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224311996 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_pipeline.2224311996
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/23.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.541754733
Short name T442
Test name
Test status
Simulation time 1373576541 ps
CPU time 10.11 seconds
Started Sep 24 11:00:18 AM UTC 24
Finished Sep 24 11:00:29 AM UTC 24
Peak memory 222568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=541754733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_
throughput_w_partial_write.541754733
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/23.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.1058211021
Short name T473
Test name
Test status
Simulation time 7574208273 ps
CPU time 161.78 seconds
Started Sep 24 11:03:58 AM UTC 24
Finished Sep 24 11:06:43 AM UTC 24
Peak memory 321728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058211021 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_access_duri
ng_key_req.1058211021
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/24.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_alert_test.2843087252
Short name T469
Test name
Test status
Simulation time 15948131 ps
CPU time 1.09 seconds
Started Sep 24 11:05:56 AM UTC 24
Finished Sep 24 11:05:58 AM UTC 24
Peak memory 211352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843087252
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_alert_test.2843087252
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/24.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_bijection.3851941193
Short name T505
Test name
Test status
Simulation time 41395188151 ps
CPU time 756.96 seconds
Started Sep 24 11:02:44 AM UTC 24
Finished Sep 24 11:15:32 AM UTC 24
Peak memory 212492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851941193 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection.3851941193
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/24.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_executable.2142666026
Short name T494
Test name
Test status
Simulation time 4187367802 ps
CPU time 567.48 seconds
Started Sep 24 11:04:08 AM UTC 24
Finished Sep 24 11:13:42 AM UTC 24
Peak memory 387556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142666026 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executable.2142666026
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/24.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.2502463069
Short name T461
Test name
Test status
Simulation time 759791026 ps
CPU time 9.56 seconds
Started Sep 24 11:03:57 AM UTC 24
Finished Sep 24 11:04:08 AM UTC 24
Peak memory 212028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502463069 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_escalation.2502463069
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/24.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.1277294403
Short name T464
Test name
Test status
Simulation time 2940746932 ps
CPU time 60.74 seconds
Started Sep 24 11:03:18 AM UTC 24
Finished Sep 24 11:04:20 AM UTC 24
Peak memory 327876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1277294403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_
max_throughput.1277294403
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/24.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.880084804
Short name T470
Test name
Test status
Simulation time 2877776415 ps
CPU time 93.85 seconds
Started Sep 24 11:04:28 AM UTC 24
Finished Sep 24 11:06:04 AM UTC 24
Peak memory 222672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880084804 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_mem_partial_access.880084804
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/24.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.2964733135
Short name T490
Test name
Test status
Simulation time 86069029759 ps
CPU time 413.51 seconds
Started Sep 24 11:04:21 AM UTC 24
Finished Sep 24 11:11:20 AM UTC 24
Peak memory 222620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964733135 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_mem_walk.2964733135
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/24.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.3665215626
Short name T524
Test name
Test status
Simulation time 67364388143 ps
CPU time 957.12 seconds
Started Sep 24 11:02:29 AM UTC 24
Finished Sep 24 11:18:38 AM UTC 24
Peak memory 387608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665215626 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multiple_keys.3665215626
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/24.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access.3138187830
Short name T457
Test name
Test status
Simulation time 603003241 ps
CPU time 26.39 seconds
Started Sep 24 11:02:49 AM UTC 24
Finished Sep 24 11:03:17 AM UTC 24
Peak memory 212244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138187830 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_partial_access.3138187830
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/24.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.4139691232
Short name T485
Test name
Test status
Simulation time 14456386402 ps
CPU time 430.43 seconds
Started Sep 24 11:02:59 AM UTC 24
Finished Sep 24 11:10:16 AM UTC 24
Peak memory 212348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139691232 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_partial_a
ccess_b2b.4139691232
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/24.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.4232239122
Short name T465
Test name
Test status
Simulation time 361434508 ps
CPU time 5.94 seconds
Started Sep 24 11:04:19 AM UTC 24
Finished Sep 24 11:04:27 AM UTC 24
Peak memory 212564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232239122 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.4232239122
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/24.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_regwen.3584887245
Short name T471
Test name
Test status
Simulation time 6647831383 ps
CPU time 126.35 seconds
Started Sep 24 11:04:11 AM UTC 24
Finished Sep 24 11:06:20 AM UTC 24
Peak memory 385312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584887245 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.3584887245
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/24.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_smoke.1028403715
Short name T455
Test name
Test status
Simulation time 794372887 ps
CPU time 18.47 seconds
Started Sep 24 11:02:29 AM UTC 24
Finished Sep 24 11:02:49 AM UTC 24
Peak memory 212584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028403715 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.1028403715
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/24.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all.3376463517
Short name T567
Test name
Test status
Simulation time 269026971624 ps
CPU time 1481.04 seconds
Started Sep 24 11:05:42 AM UTC 24
Finished Sep 24 11:30:41 AM UTC 24
Peak memory 384740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33764635
17 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_a
ll.3376463517
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/24.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.2013493222
Short name T472
Test name
Test status
Simulation time 5150695058 ps
CPU time 49.75 seconds
Started Sep 24 11:05:34 AM UTC 24
Finished Sep 24 11:06:26 AM UTC 24
Peak memory 222860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013493222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.2013493222
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/24.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.1223889292
Short name T483
Test name
Test status
Simulation time 5400272976 ps
CPU time 432.77 seconds
Started Sep 24 11:02:46 AM UTC 24
Finished Sep 24 11:10:05 AM UTC 24
Peak memory 212404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223889292 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_pipeline.1223889292
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/24.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.2810507734
Short name T466
Test name
Test status
Simulation time 3241708586 ps
CPU time 101.58 seconds
Started Sep 24 11:03:49 AM UTC 24
Finished Sep 24 11:05:33 AM UTC 24
Peak memory 372928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2810507734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl
_throughput_w_partial_write.2810507734
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/24.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.3060002819
Short name T501
Test name
Test status
Simulation time 10323102371 ps
CPU time 422.59 seconds
Started Sep 24 11:07:39 AM UTC 24
Finished Sep 24 11:14:48 AM UTC 24
Peak memory 358692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060002819 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_access_duri
ng_key_req.3060002819
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/25.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_alert_test.3422340735
Short name T486
Test name
Test status
Simulation time 42821513 ps
CPU time 0.98 seconds
Started Sep 24 11:10:17 AM UTC 24
Finished Sep 24 11:10:19 AM UTC 24
Peak memory 211352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422340735
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_alert_test.3422340735
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/25.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_executable.2221228165
Short name T513
Test name
Test status
Simulation time 7257147134 ps
CPU time 473.54 seconds
Started Sep 24 11:08:05 AM UTC 24
Finished Sep 24 11:16:05 AM UTC 24
Peak memory 365028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221228165 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executable.2221228165
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/25.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.335285126
Short name T484
Test name
Test status
Simulation time 14527746176 ps
CPU time 149.47 seconds
Started Sep 24 11:07:34 AM UTC 24
Finished Sep 24 11:10:06 AM UTC 24
Peak memory 222680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335285126 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_escalation.335285126
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/25.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.2812460771
Short name T480
Test name
Test status
Simulation time 773168214 ps
CPU time 87.99 seconds
Started Sep 24 11:06:48 AM UTC 24
Finished Sep 24 11:08:18 AM UTC 24
Peak memory 377060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2812460771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_
max_throughput.2812460771
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/25.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.382004253
Short name T489
Test name
Test status
Simulation time 2435203616 ps
CPU time 74.04 seconds
Started Sep 24 11:09:58 AM UTC 24
Finished Sep 24 11:11:14 AM UTC 24
Peak memory 222732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382004253 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_mem_partial_access.382004253
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/25.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.1471861271
Short name T510
Test name
Test status
Simulation time 13836520563 ps
CPU time 433.48 seconds
Started Sep 24 11:08:28 AM UTC 24
Finished Sep 24 11:15:47 AM UTC 24
Peak memory 222672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471861271 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_mem_walk.1471861271
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/25.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.4143454390
Short name T516
Test name
Test status
Simulation time 82941098876 ps
CPU time 637.68 seconds
Started Sep 24 11:06:05 AM UTC 24
Finished Sep 24 11:16:50 AM UTC 24
Peak memory 358880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143454390 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multiple_keys.4143454390
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/25.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access.3587526580
Short name T474
Test name
Test status
Simulation time 4939290580 ps
CPU time 19.76 seconds
Started Sep 24 11:06:26 AM UTC 24
Finished Sep 24 11:06:47 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587526580 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_partial_access.3587526580
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/25.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.1663797125
Short name T492
Test name
Test status
Simulation time 24766403319 ps
CPU time 328.83 seconds
Started Sep 24 11:06:43 AM UTC 24
Finished Sep 24 11:12:17 AM UTC 24
Peak memory 212476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663797125 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_partial_a
ccess_b2b.1663797125
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/25.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.2549952014
Short name T481
Test name
Test status
Simulation time 721892479 ps
CPU time 5.91 seconds
Started Sep 24 11:08:20 AM UTC 24
Finished Sep 24 11:08:27 AM UTC 24
Peak memory 212564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549952014 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.2549952014
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/25.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_regwen.1740056861
Short name T592
Test name
Test status
Simulation time 71044996240 ps
CPU time 1845.57 seconds
Started Sep 24 11:08:17 AM UTC 24
Finished Sep 24 11:39:25 AM UTC 24
Peak memory 389024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740056861 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.1740056861
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/25.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_smoke.947067184
Short name T436
Test name
Test status
Simulation time 743115336 ps
CPU time 13.34 seconds
Started Sep 24 11:05:59 AM UTC 24
Finished Sep 24 11:06:13 AM UTC 24
Peak memory 212528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947067184 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.947067184
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/25.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all.1195240279
Short name T832
Test name
Test status
Simulation time 279417971084 ps
CPU time 3794.34 seconds
Started Sep 24 11:10:07 AM UTC 24
Finished Sep 24 12:14:09 PM UTC 24
Peak memory 391204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11952402
79 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_a
ll.1195240279
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/25.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.339570060
Short name T487
Test name
Test status
Simulation time 953355625 ps
CPU time 14.06 seconds
Started Sep 24 11:10:06 AM UTC 24
Finished Sep 24 11:10:22 AM UTC 24
Peak memory 222724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339570060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.339570060
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/25.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.2272021848
Short name T497
Test name
Test status
Simulation time 4839882101 ps
CPU time 466.7 seconds
Started Sep 24 11:06:21 AM UTC 24
Finished Sep 24 11:14:15 AM UTC 24
Peak memory 212344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272021848 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_pipeline.2272021848
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/25.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.2173036311
Short name T476
Test name
Test status
Simulation time 2689850326 ps
CPU time 14.7 seconds
Started Sep 24 11:07:17 AM UTC 24
Finished Sep 24 11:07:33 AM UTC 24
Peak memory 222708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2173036311 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl
_throughput_w_partial_write.2173036311
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/25.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.322905114
Short name T533
Test name
Test status
Simulation time 27417779140 ps
CPU time 383.95 seconds
Started Sep 24 11:13:48 AM UTC 24
Finished Sep 24 11:20:17 AM UTC 24
Peak memory 379168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322905114 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_access_durin
g_key_req.322905114
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/26.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_alert_test.234453465
Short name T504
Test name
Test status
Simulation time 21055344 ps
CPU time 1.04 seconds
Started Sep 24 11:15:24 AM UTC 24
Finished Sep 24 11:15:26 AM UTC 24
Peak memory 211472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234453465 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_alert_test.234453465
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/26.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_bijection.2373085314
Short name T589
Test name
Test status
Simulation time 333126646977 ps
CPU time 1656.28 seconds
Started Sep 24 11:10:45 AM UTC 24
Finished Sep 24 11:38:42 AM UTC 24
Peak memory 213884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373085314 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection.2373085314
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/26.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_executable.764913998
Short name T531
Test name
Test status
Simulation time 30973711980 ps
CPU time 361.89 seconds
Started Sep 24 11:13:57 AM UTC 24
Finished Sep 24 11:20:05 AM UTC 24
Peak memory 331988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764913998 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executable.764913998
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/26.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.3112963868
Short name T496
Test name
Test status
Simulation time 875327571 ps
CPU time 10.69 seconds
Started Sep 24 11:13:44 AM UTC 24
Finished Sep 24 11:13:55 AM UTC 24
Peak memory 222600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112963868 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_escalation.3112963868
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/26.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.4250759458
Short name T493
Test name
Test status
Simulation time 743219604 ps
CPU time 51.68 seconds
Started Sep 24 11:12:18 AM UTC 24
Finished Sep 24 11:13:11 AM UTC 24
Peak memory 323740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
4250759458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_
max_throughput.4250759458
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/26.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.2334887925
Short name T523
Test name
Test status
Simulation time 30667627128 ps
CPU time 229.37 seconds
Started Sep 24 11:14:33 AM UTC 24
Finished Sep 24 11:18:27 AM UTC 24
Peak memory 229660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334887925 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_mem_partial_access.2334887925
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/26.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.3917794771
Short name T539
Test name
Test status
Simulation time 20681285696 ps
CPU time 419.38 seconds
Started Sep 24 11:14:27 AM UTC 24
Finished Sep 24 11:21:33 AM UTC 24
Peak memory 212432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917794771 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_mem_walk.3917794771
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/26.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.3019327297
Short name T534
Test name
Test status
Simulation time 5385911561 ps
CPU time 601.71 seconds
Started Sep 24 11:10:23 AM UTC 24
Finished Sep 24 11:20:32 AM UTC 24
Peak memory 389536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019327297 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multiple_keys.3019327297
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/26.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access.668489636
Short name T491
Test name
Test status
Simulation time 2465558393 ps
CPU time 27.72 seconds
Started Sep 24 11:11:21 AM UTC 24
Finished Sep 24 11:11:50 AM UTC 24
Peak memory 212372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668489636 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_partial_access.668489636
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/26.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.3765556287
Short name T519
Test name
Test status
Simulation time 22454966772 ps
CPU time 365.86 seconds
Started Sep 24 11:11:52 AM UTC 24
Finished Sep 24 11:18:03 AM UTC 24
Peak memory 212500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765556287 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_partial_a
ccess_b2b.3765556287
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/26.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.1261480258
Short name T500
Test name
Test status
Simulation time 344761483 ps
CPU time 4.97 seconds
Started Sep 24 11:14:26 AM UTC 24
Finished Sep 24 11:14:32 AM UTC 24
Peak memory 212296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261480258 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.1261480258
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/26.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_regwen.288180354
Short name T528
Test name
Test status
Simulation time 39818994661 ps
CPU time 305.91 seconds
Started Sep 24 11:14:16 AM UTC 24
Finished Sep 24 11:19:26 AM UTC 24
Peak memory 360800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288180354 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.288180354
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/26.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_smoke.3203535261
Short name T488
Test name
Test status
Simulation time 742915385 ps
CPU time 22.73 seconds
Started Sep 24 11:10:20 AM UTC 24
Finished Sep 24 11:10:44 AM UTC 24
Peak memory 252108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203535261 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.3203535261
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/26.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all.1298919981
Short name T740
Test name
Test status
Simulation time 34466958813 ps
CPU time 2783.37 seconds
Started Sep 24 11:15:23 AM UTC 24
Finished Sep 24 12:02:16 PM UTC 24
Peak memory 401440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12989199
81 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_a
ll.1298919981
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/26.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.832054817
Short name T502
Test name
Test status
Simulation time 6149998393 ps
CPU time 31.86 seconds
Started Sep 24 11:14:49 AM UTC 24
Finished Sep 24 11:15:22 AM UTC 24
Peak memory 222792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832054817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.832054817
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/26.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.2529540217
Short name T507
Test name
Test status
Simulation time 8114373694 ps
CPU time 261.21 seconds
Started Sep 24 11:11:15 AM UTC 24
Finished Sep 24 11:15:41 AM UTC 24
Peak memory 212500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529540217 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_pipeline.2529540217
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/26.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.2837871678
Short name T499
Test name
Test status
Simulation time 779165076 ps
CPU time 72.08 seconds
Started Sep 24 11:13:12 AM UTC 24
Finished Sep 24 11:14:26 AM UTC 24
Peak memory 340120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2837871678 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl
_throughput_w_partial_write.2837871678
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/26.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.2033578751
Short name T573
Test name
Test status
Simulation time 11958702318 ps
CPU time 1058.68 seconds
Started Sep 24 11:16:06 AM UTC 24
Finished Sep 24 11:33:58 AM UTC 24
Peak memory 389480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033578751 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_access_duri
ng_key_req.2033578751
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/27.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_alert_test.4088455283
Short name T522
Test name
Test status
Simulation time 14981726 ps
CPU time 1.06 seconds
Started Sep 24 11:18:20 AM UTC 24
Finished Sep 24 11:18:22 AM UTC 24
Peak memory 211352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088455283
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_alert_test.4088455283
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/27.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_bijection.566821494
Short name T629
Test name
Test status
Simulation time 108792388617 ps
CPU time 1853.89 seconds
Started Sep 24 11:15:36 AM UTC 24
Finished Sep 24 11:46:53 AM UTC 24
Peak memory 214012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566821494 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection.566821494
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/27.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_executable.3691921061
Short name T541
Test name
Test status
Simulation time 27052055835 ps
CPU time 323.59 seconds
Started Sep 24 11:16:21 AM UTC 24
Finished Sep 24 11:21:49 AM UTC 24
Peak memory 379312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691921061 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executable.3691921061
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/27.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.665219927
Short name T518
Test name
Test status
Simulation time 8735977887 ps
CPU time 103.47 seconds
Started Sep 24 11:16:00 AM UTC 24
Finished Sep 24 11:17:46 AM UTC 24
Peak memory 222872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665219927 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_escalation.665219927
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/27.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.3396411474
Short name T512
Test name
Test status
Simulation time 675725398 ps
CPU time 10.6 seconds
Started Sep 24 11:15:48 AM UTC 24
Finished Sep 24 11:16:00 AM UTC 24
Peak memory 228664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3396411474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_
max_throughput.3396411474
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/27.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.2428994772
Short name T529
Test name
Test status
Simulation time 10541355887 ps
CPU time 100.75 seconds
Started Sep 24 11:17:47 AM UTC 24
Finished Sep 24 11:19:30 AM UTC 24
Peak memory 229868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428994772 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_mem_partial_access.2428994772
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/27.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.2926990559
Short name T548
Test name
Test status
Simulation time 21121162950 ps
CPU time 407.42 seconds
Started Sep 24 11:16:59 AM UTC 24
Finished Sep 24 11:23:52 AM UTC 24
Peak memory 222788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926990559 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_mem_walk.2926990559
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/27.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.380738251
Short name T612
Test name
Test status
Simulation time 84662751070 ps
CPU time 1655 seconds
Started Sep 24 11:15:32 AM UTC 24
Finished Sep 24 11:43:26 AM UTC 24
Peak memory 389072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380738251 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multiple_keys.380738251
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/27.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access.1657139123
Short name T515
Test name
Test status
Simulation time 2295122972 ps
CPU time 49.43 seconds
Started Sep 24 11:15:46 AM UTC 24
Finished Sep 24 11:16:37 AM UTC 24
Peak memory 334340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657139123 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_partial_access.1657139123
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/27.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.3090797184
Short name T538
Test name
Test status
Simulation time 9411233110 ps
CPU time 335.85 seconds
Started Sep 24 11:15:47 AM UTC 24
Finished Sep 24 11:21:27 AM UTC 24
Peak memory 212368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090797184 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_partial_a
ccess_b2b.3090797184
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/27.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.4065828536
Short name T517
Test name
Test status
Simulation time 680402484 ps
CPU time 6.38 seconds
Started Sep 24 11:16:51 AM UTC 24
Finished Sep 24 11:16:58 AM UTC 24
Peak memory 212372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065828536 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.4065828536
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/27.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_regwen.3475964685
Short name T583
Test name
Test status
Simulation time 38777468555 ps
CPU time 1264.38 seconds
Started Sep 24 11:16:37 AM UTC 24
Finished Sep 24 11:37:57 AM UTC 24
Peak memory 391620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475964685 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.3475964685
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/27.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_smoke.1679248999
Short name T508
Test name
Test status
Simulation time 392983226 ps
CPU time 16.09 seconds
Started Sep 24 11:15:27 AM UTC 24
Finished Sep 24 11:15:44 AM UTC 24
Peak memory 256172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679248999 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.1679248999
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/27.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all.3073505254
Short name T943
Test name
Test status
Simulation time 720274317971 ps
CPU time 6978.75 seconds
Started Sep 24 11:18:13 AM UTC 24
Finished Sep 24 01:15:50 PM UTC 24
Peak memory 399104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30735052
54 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_a
ll.3073505254
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/27.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.3851529744
Short name T521
Test name
Test status
Simulation time 4775109516 ps
CPU time 13.73 seconds
Started Sep 24 11:18:04 AM UTC 24
Finished Sep 24 11:18:19 AM UTC 24
Peak memory 222680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851529744 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.3851529744
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/27.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.2717267910
Short name T545
Test name
Test status
Simulation time 11124925264 ps
CPU time 435.97 seconds
Started Sep 24 11:15:41 AM UTC 24
Finished Sep 24 11:23:04 AM UTC 24
Peak memory 212496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717267910 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_pipeline.2717267910
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/27.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.482095823
Short name T514
Test name
Test status
Simulation time 1484555227 ps
CPU time 23.19 seconds
Started Sep 24 11:15:56 AM UTC 24
Finished Sep 24 11:16:20 AM UTC 24
Peak memory 262304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=482095823 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_
throughput_w_partial_write.482095823
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/27.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.1099922326
Short name T546
Test name
Test status
Simulation time 4009226573 ps
CPU time 188.69 seconds
Started Sep 24 11:20:05 AM UTC 24
Finished Sep 24 11:23:17 AM UTC 24
Peak memory 385228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099922326 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_access_duri
ng_key_req.1099922326
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/28.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_alert_test.4109762361
Short name T540
Test name
Test status
Simulation time 38346025 ps
CPU time 1.01 seconds
Started Sep 24 11:21:33 AM UTC 24
Finished Sep 24 11:21:36 AM UTC 24
Peak memory 210884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109762361
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_alert_test.4109762361
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/28.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_bijection.4177017754
Short name T602
Test name
Test status
Simulation time 79255850661 ps
CPU time 1391.64 seconds
Started Sep 24 11:18:39 AM UTC 24
Finished Sep 24 11:42:08 AM UTC 24
Peak memory 213880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177017754 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection.4177017754
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/28.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_executable.2309192442
Short name T550
Test name
Test status
Simulation time 19676874169 ps
CPU time 226.82 seconds
Started Sep 24 11:20:12 AM UTC 24
Finished Sep 24 11:24:03 AM UTC 24
Peak memory 385296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309192442 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executable.2309192442
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/28.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.3798491660
Short name T536
Test name
Test status
Simulation time 4639008114 ps
CPU time 44.63 seconds
Started Sep 24 11:20:02 AM UTC 24
Finished Sep 24 11:20:48 AM UTC 24
Peak memory 222900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798491660 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_escalation.3798491660
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/28.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.3300997000
Short name T537
Test name
Test status
Simulation time 1701094745 ps
CPU time 79.73 seconds
Started Sep 24 11:19:28 AM UTC 24
Finished Sep 24 11:20:49 AM UTC 24
Peak memory 375076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3300997000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_
max_throughput.3300997000
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/28.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.4068598330
Short name T543
Test name
Test status
Simulation time 3850522473 ps
CPU time 98.14 seconds
Started Sep 24 11:20:49 AM UTC 24
Finished Sep 24 11:22:29 AM UTC 24
Peak memory 229580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068598330 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_mem_partial_access.4068598330
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/28.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.3501995047
Short name T551
Test name
Test status
Simulation time 13867765477 ps
CPU time 201.72 seconds
Started Sep 24 11:20:42 AM UTC 24
Finished Sep 24 11:24:07 AM UTC 24
Peak memory 222884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501995047 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_mem_walk.3501995047
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/28.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.1002805462
Short name T584
Test name
Test status
Simulation time 92358594776 ps
CPU time 1169.76 seconds
Started Sep 24 11:18:28 AM UTC 24
Finished Sep 24 11:38:12 AM UTC 24
Peak memory 389520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002805462 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multiple_keys.1002805462
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/28.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access.2940240694
Short name T530
Test name
Test status
Simulation time 1337821283 ps
CPU time 51.74 seconds
Started Sep 24 11:19:07 AM UTC 24
Finished Sep 24 11:20:01 AM UTC 24
Peak memory 317664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940240694 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_partial_access.2940240694
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/28.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.3787550059
Short name T568
Test name
Test status
Simulation time 98214916074 ps
CPU time 736.38 seconds
Started Sep 24 11:19:12 AM UTC 24
Finished Sep 24 11:31:38 AM UTC 24
Peak memory 212320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787550059 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_partial_a
ccess_b2b.3787550059
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/28.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.178747454
Short name T535
Test name
Test status
Simulation time 1410312233 ps
CPU time 6.75 seconds
Started Sep 24 11:20:33 AM UTC 24
Finished Sep 24 11:20:41 AM UTC 24
Peak memory 212624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178747454 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.178747454
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/28.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_regwen.1323078612
Short name T618
Test name
Test status
Simulation time 4055797520 ps
CPU time 1450.04 seconds
Started Sep 24 11:20:17 AM UTC 24
Finished Sep 24 11:44:45 AM UTC 24
Peak memory 388964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323078612 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.1323078612
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/28.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_smoke.837603179
Short name T525
Test name
Test status
Simulation time 408128774 ps
CPU time 27.79 seconds
Started Sep 24 11:18:23 AM UTC 24
Finished Sep 24 11:18:52 AM UTC 24
Peak memory 280728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837603179 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.837603179
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/28.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all.3456135100
Short name T588
Test name
Test status
Simulation time 53993683661 ps
CPU time 1017.23 seconds
Started Sep 24 11:21:28 AM UTC 24
Finished Sep 24 11:38:39 AM UTC 24
Peak memory 344356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34561351
00 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_a
ll.3456135100
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/28.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.411767862
Short name T544
Test name
Test status
Simulation time 12230741867 ps
CPU time 118.57 seconds
Started Sep 24 11:20:50 AM UTC 24
Finished Sep 24 11:22:51 AM UTC 24
Peak memory 373148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411767862 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.411767862
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/28.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.4019988053
Short name T558
Test name
Test status
Simulation time 25308956085 ps
CPU time 456.94 seconds
Started Sep 24 11:18:53 AM UTC 24
Finished Sep 24 11:26:36 AM UTC 24
Peak memory 212360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019988053 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_pipeline.4019988053
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/28.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.123876715
Short name T532
Test name
Test status
Simulation time 1448137044 ps
CPU time 39.22 seconds
Started Sep 24 11:19:31 AM UTC 24
Finished Sep 24 11:20:12 AM UTC 24
Peak memory 311448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=123876715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_
throughput_w_partial_write.123876715
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/28.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.3731752934
Short name T580
Test name
Test status
Simulation time 10482856445 ps
CPU time 807.8 seconds
Started Sep 24 11:24:02 AM UTC 24
Finished Sep 24 11:37:40 AM UTC 24
Peak memory 387268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731752934 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_access_duri
ng_key_req.3731752934
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/29.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_alert_test.769348497
Short name T557
Test name
Test status
Simulation time 13893624 ps
CPU time 1.1 seconds
Started Sep 24 11:26:27 AM UTC 24
Finished Sep 24 11:26:30 AM UTC 24
Peak memory 211472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769348497 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_alert_test.769348497
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/29.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_bijection.2134947502
Short name T581
Test name
Test status
Simulation time 47049681817 ps
CPU time 936.17 seconds
Started Sep 24 11:22:01 AM UTC 24
Finished Sep 24 11:37:49 AM UTC 24
Peak memory 212420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134947502 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection.2134947502
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/29.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_executable.1478806507
Short name T625
Test name
Test status
Simulation time 69195751112 ps
CPU time 1336.84 seconds
Started Sep 24 11:24:03 AM UTC 24
Finished Sep 24 11:46:36 AM UTC 24
Peak memory 388956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478806507 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executable.1478806507
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/29.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.3118380469
Short name T554
Test name
Test status
Simulation time 10715072175 ps
CPU time 72.6 seconds
Started Sep 24 11:23:53 AM UTC 24
Finished Sep 24 11:25:07 AM UTC 24
Peak memory 226784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118380469 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_escalation.3118380469
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/29.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.2836503254
Short name T549
Test name
Test status
Simulation time 739275073 ps
CPU time 41.87 seconds
Started Sep 24 11:23:17 AM UTC 24
Finished Sep 24 11:24:01 AM UTC 24
Peak memory 299164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2836503254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_
max_throughput.2836503254
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/29.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.808138706
Short name T561
Test name
Test status
Simulation time 5101060787 ps
CPU time 211.87 seconds
Started Sep 24 11:25:08 AM UTC 24
Finished Sep 24 11:28:44 AM UTC 24
Peak memory 222888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808138706 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_mem_partial_access.808138706
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/29.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.1682187944
Short name T563
Test name
Test status
Simulation time 27709686083 ps
CPU time 240.92 seconds
Started Sep 24 11:24:55 AM UTC 24
Finished Sep 24 11:28:59 AM UTC 24
Peak memory 222672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682187944 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_mem_walk.1682187944
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/29.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.2369397479
Short name T576
Test name
Test status
Simulation time 11230841265 ps
CPU time 780.42 seconds
Started Sep 24 11:21:50 AM UTC 24
Finished Sep 24 11:35:00 AM UTC 24
Peak memory 381220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369397479 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multiple_keys.2369397479
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/29.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access.2997998775
Short name T547
Test name
Test status
Simulation time 4936758857 ps
CPU time 45.07 seconds
Started Sep 24 11:22:52 AM UTC 24
Finished Sep 24 11:23:39 AM UTC 24
Peak memory 282884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997998775 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_partial_access.2997998775
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/29.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.1039215890
Short name T570
Test name
Test status
Simulation time 76997236096 ps
CPU time 539.59 seconds
Started Sep 24 11:23:04 AM UTC 24
Finished Sep 24 11:32:11 AM UTC 24
Peak memory 212372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039215890 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_partial_a
ccess_b2b.1039215890
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/29.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.4214670017
Short name T553
Test name
Test status
Simulation time 1351318229 ps
CPU time 3.62 seconds
Started Sep 24 11:24:49 AM UTC 24
Finished Sep 24 11:24:54 AM UTC 24
Peak memory 212296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214670017 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.4214670017
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/29.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_regwen.3654293092
Short name T613
Test name
Test status
Simulation time 90466100856 ps
CPU time 1145.62 seconds
Started Sep 24 11:24:07 AM UTC 24
Finished Sep 24 11:43:26 AM UTC 24
Peak memory 389412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654293092 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.3654293092
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/29.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_smoke.176638046
Short name T542
Test name
Test status
Simulation time 1963248931 ps
CPU time 22.54 seconds
Started Sep 24 11:21:37 AM UTC 24
Finished Sep 24 11:22:00 AM UTC 24
Peak memory 212332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176638046 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.176638046
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/29.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all.3103284365
Short name T933
Test name
Test status
Simulation time 933529757420 ps
CPU time 4670.29 seconds
Started Sep 24 11:26:08 AM UTC 24
Finished Sep 24 12:44:54 PM UTC 24
Peak memory 384796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31032843
65 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_a
ll.3103284365
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/29.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.2220900468
Short name T121
Test name
Test status
Simulation time 210927431 ps
CPU time 10.27 seconds
Started Sep 24 11:25:56 AM UTC 24
Finished Sep 24 11:26:08 AM UTC 24
Peak memory 222932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220900468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.2220900468
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/29.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.2516780526
Short name T560
Test name
Test status
Simulation time 48066798713 ps
CPU time 255.53 seconds
Started Sep 24 11:22:30 AM UTC 24
Finished Sep 24 11:26:50 AM UTC 24
Peak memory 212680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516780526 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_pipeline.2516780526
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/29.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.3920215477
Short name T555
Test name
Test status
Simulation time 818964147 ps
CPU time 132.63 seconds
Started Sep 24 11:23:40 AM UTC 24
Finished Sep 24 11:25:55 AM UTC 24
Peak memory 381152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3920215477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl
_throughput_w_partial_write.3920215477
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/29.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.3295000254
Short name T86
Test name
Test status
Simulation time 130936441246 ps
CPU time 653.62 seconds
Started Sep 24 09:50:51 AM UTC 24
Finished Sep 24 10:01:51 AM UTC 24
Peak memory 383188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295000254 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_access_durin
g_key_req.3295000254
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/3.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_alert_test.1659517642
Short name T58
Test name
Test status
Simulation time 46969175 ps
CPU time 1.09 seconds
Started Sep 24 09:51:29 AM UTC 24
Finished Sep 24 09:51:31 AM UTC 24
Peak memory 210884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659517642
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_alert_test.1659517642
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/3.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_bijection.4170039977
Short name T281
Test name
Test status
Simulation time 31856928072 ps
CPU time 2155.49 seconds
Started Sep 24 09:50:14 AM UTC 24
Finished Sep 24 10:26:33 AM UTC 24
Peak memory 214068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170039977 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.4170039977
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/3.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_executable.2234254256
Short name T145
Test name
Test status
Simulation time 7182370147 ps
CPU time 896.13 seconds
Started Sep 24 09:50:59 AM UTC 24
Finished Sep 24 10:06:06 AM UTC 24
Peak memory 383460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234254256 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executable.2234254256
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/3.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.691796253
Short name T19
Test name
Test status
Simulation time 10653695532 ps
CPU time 84.51 seconds
Started Sep 24 09:50:49 AM UTC 24
Finished Sep 24 09:52:15 AM UTC 24
Peak memory 222552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691796253 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_escalation.691796253
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/3.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.979061593
Short name T125
Test name
Test status
Simulation time 1228792832 ps
CPU time 56.86 seconds
Started Sep 24 09:50:32 AM UTC 24
Finished Sep 24 09:51:31 AM UTC 24
Peak memory 350372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
979061593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ma
x_throughput.979061593
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/3.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.976545929
Short name T43
Test name
Test status
Simulation time 20879144224 ps
CPU time 177.55 seconds
Started Sep 24 09:51:10 AM UTC 24
Finished Sep 24 09:54:11 AM UTC 24
Peak memory 222856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976545929 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_mem_partial_access.976545929
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/3.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.3155955009
Short name T164
Test name
Test status
Simulation time 26265145786 ps
CPU time 260.66 seconds
Started Sep 24 09:51:06 AM UTC 24
Finished Sep 24 09:55:31 AM UTC 24
Peak memory 222692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155955009 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_mem_walk.3155955009
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/3.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.1609550956
Short name T173
Test name
Test status
Simulation time 18652616832 ps
CPU time 503.83 seconds
Started Sep 24 09:50:08 AM UTC 24
Finished Sep 24 09:58:38 AM UTC 24
Peak memory 389600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609550956 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multiple_keys.1609550956
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/3.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access.4253705174
Short name T37
Test name
Test status
Simulation time 2683487456 ps
CPU time 13.07 seconds
Started Sep 24 09:50:16 AM UTC 24
Finished Sep 24 09:50:31 AM UTC 24
Peak memory 235656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253705174 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_partial_access.4253705174
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/3.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.106273729
Short name T110
Test name
Test status
Simulation time 13673421235 ps
CPU time 359.46 seconds
Started Sep 24 09:50:24 AM UTC 24
Finished Sep 24 09:56:29 AM UTC 24
Peak memory 212560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106273729 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_partial_acc
ess_b2b.106273729
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/3.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.1540322086
Short name T50
Test name
Test status
Simulation time 684888551 ps
CPU time 4.2 seconds
Started Sep 24 09:51:00 AM UTC 24
Finished Sep 24 09:51:05 AM UTC 24
Peak memory 212296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540322086 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.1540322086
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/3.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.3919253189
Short name T32
Test name
Test status
Simulation time 854901361 ps
CPU time 5.4 seconds
Started Sep 24 09:51:24 AM UTC 24
Finished Sep 24 09:51:31 AM UTC 24
Peak memory 248404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919253189 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_sec_cm.3919253189
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/3.sram_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_smoke.3768596383
Short name T48
Test name
Test status
Simulation time 1219137373 ps
CPU time 37.44 seconds
Started Sep 24 09:50:08 AM UTC 24
Finished Sep 24 09:50:47 AM UTC 24
Peak memory 278672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768596383 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.3768596383
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/3.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all.3519955136
Short name T339
Test name
Test status
Simulation time 630330764819 ps
CPU time 2969.62 seconds
Started Sep 24 09:51:15 AM UTC 24
Finished Sep 24 10:41:20 AM UTC 24
Peak memory 380664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35199551
36 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all.3519955136
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/3.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.1507752521
Short name T60
Test name
Test status
Simulation time 6950983867 ps
CPU time 212.42 seconds
Started Sep 24 09:50:16 AM UTC 24
Finished Sep 24 09:53:52 AM UTC 24
Peak memory 212468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507752521 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_pipeline.1507752521
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/3.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.3729220215
Short name T52
Test name
Test status
Simulation time 5231991881 ps
CPU time 37.77 seconds
Started Sep 24 09:50:45 AM UTC 24
Finished Sep 24 09:51:24 AM UTC 24
Peak memory 303560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3729220215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_
throughput_w_partial_write.3729220215
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/3.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.2825450076
Short name T598
Test name
Test status
Simulation time 15352178040 ps
CPU time 651.23 seconds
Started Sep 24 11:29:44 AM UTC 24
Finished Sep 24 11:40:43 AM UTC 24
Peak memory 389340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825450076 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_access_duri
ng_key_req.2825450076
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/30.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_alert_test.2876524921
Short name T574
Test name
Test status
Simulation time 26085281 ps
CPU time 1.09 seconds
Started Sep 24 11:33:58 AM UTC 24
Finished Sep 24 11:34:01 AM UTC 24
Peak memory 210884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876524921
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_alert_test.2876524921
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/30.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_bijection.2394368124
Short name T779
Test name
Test status
Simulation time 106786594920 ps
CPU time 2424.5 seconds
Started Sep 24 11:26:42 AM UTC 24
Finished Sep 24 12:07:35 PM UTC 24
Peak memory 214068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394368124 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection.2394368124
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/30.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_executable.1497198496
Short name T664
Test name
Test status
Simulation time 80754937031 ps
CPU time 1293.81 seconds
Started Sep 24 11:30:04 AM UTC 24
Finished Sep 24 11:51:53 AM UTC 24
Peak memory 389828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497198496 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executable.1497198496
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/30.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.3632042854
Short name T566
Test name
Test status
Simulation time 4806466757 ps
CPU time 20.78 seconds
Started Sep 24 11:29:41 AM UTC 24
Finished Sep 24 11:30:03 AM UTC 24
Peak memory 222404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632042854 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_escalation.3632042854
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/30.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.3474717299
Short name T564
Test name
Test status
Simulation time 2880470415 ps
CPU time 38.12 seconds
Started Sep 24 11:29:01 AM UTC 24
Finished Sep 24 11:29:40 AM UTC 24
Peak memory 301252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3474717299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_
max_throughput.3474717299
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/30.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.2126671804
Short name T577
Test name
Test status
Simulation time 3354681025 ps
CPU time 172.08 seconds
Started Sep 24 11:32:12 AM UTC 24
Finished Sep 24 11:35:07 AM UTC 24
Peak memory 229656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126671804 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_mem_partial_access.2126671804
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/30.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.549665863
Short name T578
Test name
Test status
Simulation time 57732127017 ps
CPU time 320.78 seconds
Started Sep 24 11:31:46 AM UTC 24
Finished Sep 24 11:37:12 AM UTC 24
Peak memory 222668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549665863 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_mem_walk.549665863
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/30.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.860738208
Short name T630
Test name
Test status
Simulation time 20184321413 ps
CPU time 1218.12 seconds
Started Sep 24 11:26:37 AM UTC 24
Finished Sep 24 11:47:08 AM UTC 24
Peak memory 389500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860738208 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multiple_keys.860738208
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/30.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access.3246513967
Short name T562
Test name
Test status
Simulation time 776841406 ps
CPU time 11.93 seconds
Started Sep 24 11:28:45 AM UTC 24
Finished Sep 24 11:28:58 AM UTC 24
Peak memory 212396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246513967 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_partial_access.3246513967
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/30.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.3413444108
Short name T599
Test name
Test status
Simulation time 8415897772 ps
CPU time 705.09 seconds
Started Sep 24 11:28:59 AM UTC 24
Finished Sep 24 11:40:54 AM UTC 24
Peak memory 212692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413444108 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_partial_a
ccess_b2b.3413444108
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/30.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.519666717
Short name T569
Test name
Test status
Simulation time 706033102 ps
CPU time 4.91 seconds
Started Sep 24 11:31:39 AM UTC 24
Finished Sep 24 11:31:46 AM UTC 24
Peak memory 212560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519666717 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.519666717
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/30.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_regwen.1426992363
Short name T601
Test name
Test status
Simulation time 20912324573 ps
CPU time 673.97 seconds
Started Sep 24 11:30:42 AM UTC 24
Finished Sep 24 11:42:04 AM UTC 24
Peak memory 389412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426992363 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.1426992363
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/30.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_smoke.359609263
Short name T559
Test name
Test status
Simulation time 10147931976 ps
CPU time 9.41 seconds
Started Sep 24 11:26:31 AM UTC 24
Finished Sep 24 11:26:41 AM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359609263 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.359609263
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/30.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_all.20547237
Short name T681
Test name
Test status
Simulation time 17178305985 ps
CPU time 1205.54 seconds
Started Sep 24 11:33:22 AM UTC 24
Finished Sep 24 11:53:43 AM UTC 24
Peak memory 399756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20547237
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all.20547237
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/30.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.3975221265
Short name T572
Test name
Test status
Simulation time 210308245 ps
CPU time 13.93 seconds
Started Sep 24 11:33:06 AM UTC 24
Finished Sep 24 11:33:22 AM UTC 24
Peak memory 222672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975221265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.3975221265
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/30.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.2315570682
Short name T571
Test name
Test status
Simulation time 5150502920 ps
CPU time 369 seconds
Started Sep 24 11:26:51 AM UTC 24
Finished Sep 24 11:33:05 AM UTC 24
Peak memory 212404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315570682 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_pipeline.2315570682
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/30.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.2785789380
Short name T565
Test name
Test status
Simulation time 2909047580 ps
CPU time 10.95 seconds
Started Sep 24 11:29:31 AM UTC 24
Finished Sep 24 11:29:44 AM UTC 24
Peak memory 222636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2785789380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl
_throughput_w_partial_write.2785789380
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/30.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.4189540578
Short name T659
Test name
Test status
Simulation time 13503440819 ps
CPU time 799.74 seconds
Started Sep 24 11:37:57 AM UTC 24
Finished Sep 24 11:51:26 AM UTC 24
Peak memory 379076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189540578 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_access_duri
ng_key_req.4189540578
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/31.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_alert_test.843373132
Short name T593
Test name
Test status
Simulation time 23540064 ps
CPU time 0.85 seconds
Started Sep 24 11:39:24 AM UTC 24
Finished Sep 24 11:39:27 AM UTC 24
Peak memory 211408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843373132 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_alert_test.843373132
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/31.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_bijection.2551801892
Short name T847
Test name
Test status
Simulation time 100696581583 ps
CPU time 2442.54 seconds
Started Sep 24 11:35:01 AM UTC 24
Finished Sep 24 12:16:12 PM UTC 24
Peak memory 213960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551801892 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection.2551801892
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/31.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_executable.1979979735
Short name T666
Test name
Test status
Simulation time 26695388096 ps
CPU time 833.88 seconds
Started Sep 24 11:38:13 AM UTC 24
Finished Sep 24 11:52:16 AM UTC 24
Peak memory 383184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979979735 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executable.1979979735
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/31.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.2303948991
Short name T594
Test name
Test status
Simulation time 28693943913 ps
CPU time 95.79 seconds
Started Sep 24 11:37:53 AM UTC 24
Finished Sep 24 11:39:31 AM UTC 24
Peak memory 222676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303948991 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_escalation.2303948991
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/31.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.1811275152
Short name T582
Test name
Test status
Simulation time 723137854 ps
CPU time 10.01 seconds
Started Sep 24 11:37:41 AM UTC 24
Finished Sep 24 11:37:52 AM UTC 24
Peak memory 229532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1811275152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_
max_throughput.1811275152
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/31.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.118765554
Short name T597
Test name
Test status
Simulation time 2467732985 ps
CPU time 83.12 seconds
Started Sep 24 11:38:40 AM UTC 24
Finished Sep 24 11:40:05 AM UTC 24
Peak memory 222672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118765554 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_mem_partial_access.118765554
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/31.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.59857378
Short name T606
Test name
Test status
Simulation time 15756485474 ps
CPU time 236.6 seconds
Started Sep 24 11:38:37 AM UTC 24
Finished Sep 24 11:42:37 AM UTC 24
Peak memory 222776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59857378 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_mem_walk.59857378
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/31.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.1233485640
Short name T712
Test name
Test status
Simulation time 41380225080 ps
CPU time 1386.41 seconds
Started Sep 24 11:34:45 AM UTC 24
Finished Sep 24 11:58:06 AM UTC 24
Peak memory 388864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233485640 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multiple_keys.1233485640
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/31.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access.1283584678
Short name T579
Test name
Test status
Simulation time 942917130 ps
CPU time 11.1 seconds
Started Sep 24 11:37:14 AM UTC 24
Finished Sep 24 11:37:26 AM UTC 24
Peak memory 212484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283584678 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_partial_access.1283584678
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/31.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.3169077806
Short name T624
Test name
Test status
Simulation time 29406337994 ps
CPU time 539.69 seconds
Started Sep 24 11:37:27 AM UTC 24
Finished Sep 24 11:46:34 AM UTC 24
Peak memory 212428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169077806 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_partial_a
ccess_b2b.3169077806
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/31.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.606938769
Short name T587
Test name
Test status
Simulation time 2243403856 ps
CPU time 6.7 seconds
Started Sep 24 11:38:28 AM UTC 24
Finished Sep 24 11:38:35 AM UTC 24
Peak memory 212628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606938769 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.606938769
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/31.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_regwen.982701521
Short name T663
Test name
Test status
Simulation time 13328268146 ps
CPU time 797.04 seconds
Started Sep 24 11:38:25 AM UTC 24
Finished Sep 24 11:51:51 AM UTC 24
Peak memory 391432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982701521 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.982701521
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/31.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_smoke.3186645279
Short name T575
Test name
Test status
Simulation time 3905447143 ps
CPU time 40.68 seconds
Started Sep 24 11:34:02 AM UTC 24
Finished Sep 24 11:34:44 AM UTC 24
Peak memory 293080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186645279 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.3186645279
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/31.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.3826252741
Short name T590
Test name
Test status
Simulation time 1676470781 ps
CPU time 23.98 seconds
Started Sep 24 11:38:42 AM UTC 24
Finished Sep 24 11:39:07 AM UTC 24
Peak memory 222772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826252741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.3826252741
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/31.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.335778981
Short name T591
Test name
Test status
Simulation time 16262942655 ps
CPU time 251.48 seconds
Started Sep 24 11:35:08 AM UTC 24
Finished Sep 24 11:39:23 AM UTC 24
Peak memory 212628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335778981 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_pipeline.335778981
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/31.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.3217914205
Short name T586
Test name
Test status
Simulation time 3189561063 ps
CPU time 35.85 seconds
Started Sep 24 11:37:49 AM UTC 24
Finished Sep 24 11:38:26 AM UTC 24
Peak memory 303216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3217914205 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl
_throughput_w_partial_write.3217914205
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/31.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.2282815791
Short name T689
Test name
Test status
Simulation time 47007208399 ps
CPU time 735.92 seconds
Started Sep 24 11:42:05 AM UTC 24
Finished Sep 24 11:54:30 AM UTC 24
Peak memory 389308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282815791 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_access_duri
ng_key_req.2282815791
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/32.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_alert_test.2948150706
Short name T610
Test name
Test status
Simulation time 18147715 ps
CPU time 1.09 seconds
Started Sep 24 11:43:04 AM UTC 24
Finished Sep 24 11:43:06 AM UTC 24
Peak memory 210884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948150706
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_alert_test.2948150706
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/32.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_bijection.2475601924
Short name T769
Test name
Test status
Simulation time 20004672113 ps
CPU time 1549.52 seconds
Started Sep 24 11:39:32 AM UTC 24
Finished Sep 24 12:05:40 PM UTC 24
Peak memory 213948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475601924 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection.2475601924
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/32.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_executable.2519378279
Short name T680
Test name
Test status
Simulation time 95634380460 ps
CPU time 681.85 seconds
Started Sep 24 11:42:09 AM UTC 24
Finished Sep 24 11:53:40 AM UTC 24
Peak memory 379240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519378279 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executable.2519378279
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/32.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.3160281321
Short name T604
Test name
Test status
Simulation time 5689838156 ps
CPU time 71.09 seconds
Started Sep 24 11:41:06 AM UTC 24
Finished Sep 24 11:42:20 AM UTC 24
Peak memory 222648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160281321 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_escalation.3160281321
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/32.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.2043299959
Short name T603
Test name
Test status
Simulation time 3189089719 ps
CPU time 88.94 seconds
Started Sep 24 11:40:44 AM UTC 24
Finished Sep 24 11:42:15 AM UTC 24
Peak memory 381148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2043299959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_
max_throughput.2043299959
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/32.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.2225083260
Short name T621
Test name
Test status
Simulation time 4850765729 ps
CPU time 187.65 seconds
Started Sep 24 11:42:38 AM UTC 24
Finished Sep 24 11:45:49 AM UTC 24
Peak memory 222712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225083260 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_mem_partial_access.2225083260
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/32.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.1659209956
Short name T620
Test name
Test status
Simulation time 2634785478 ps
CPU time 190.94 seconds
Started Sep 24 11:42:28 AM UTC 24
Finished Sep 24 11:45:42 AM UTC 24
Peak memory 222692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659209956 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_mem_walk.1659209956
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/32.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.3569129818
Short name T693
Test name
Test status
Simulation time 87307918226 ps
CPU time 936.25 seconds
Started Sep 24 11:39:28 AM UTC 24
Finished Sep 24 11:55:15 AM UTC 24
Peak memory 366808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569129818 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multiple_keys.3569129818
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/32.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access.1379383619
Short name T600
Test name
Test status
Simulation time 8410845519 ps
CPU time 75.63 seconds
Started Sep 24 11:39:48 AM UTC 24
Finished Sep 24 11:41:06 AM UTC 24
Peak memory 328132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379383619 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_partial_access.1379383619
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/32.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.3021351636
Short name T660
Test name
Test status
Simulation time 16171586703 ps
CPU time 684.49 seconds
Started Sep 24 11:40:06 AM UTC 24
Finished Sep 24 11:51:40 AM UTC 24
Peak memory 212716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021351636 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_partial_a
ccess_b2b.3021351636
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/32.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.1882301775
Short name T605
Test name
Test status
Simulation time 1534604996 ps
CPU time 5.4 seconds
Started Sep 24 11:42:20 AM UTC 24
Finished Sep 24 11:42:27 AM UTC 24
Peak memory 212296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882301775 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.1882301775
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/32.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_regwen.1471184132
Short name T611
Test name
Test status
Simulation time 9288207956 ps
CPU time 65.69 seconds
Started Sep 24 11:42:16 AM UTC 24
Finished Sep 24 11:43:24 AM UTC 24
Peak memory 293128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471184132 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.1471184132
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/32.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_smoke.3811344339
Short name T595
Test name
Test status
Simulation time 777392224 ps
CPU time 9.16 seconds
Started Sep 24 11:39:26 AM UTC 24
Finished Sep 24 11:39:37 AM UTC 24
Peak memory 212352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811344339 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.3811344339
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/32.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all.3257472699
Short name T912
Test name
Test status
Simulation time 237679496287 ps
CPU time 2697.69 seconds
Started Sep 24 11:43:03 AM UTC 24
Finished Sep 24 12:28:31 PM UTC 24
Peak memory 393064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32574726
99 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_a
ll.3257472699
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/32.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.3349931761
Short name T608
Test name
Test status
Simulation time 235093859 ps
CPU time 12.81 seconds
Started Sep 24 11:42:48 AM UTC 24
Finished Sep 24 11:43:02 AM UTC 24
Peak memory 222724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349931761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.3349931761
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/32.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.1416504432
Short name T617
Test name
Test status
Simulation time 17767352259 ps
CPU time 300.55 seconds
Started Sep 24 11:39:38 AM UTC 24
Finished Sep 24 11:44:43 AM UTC 24
Peak memory 212424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416504432 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_pipeline.1416504432
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/32.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.3956146633
Short name T607
Test name
Test status
Simulation time 782271491 ps
CPU time 109.84 seconds
Started Sep 24 11:40:55 AM UTC 24
Finished Sep 24 11:42:48 AM UTC 24
Peak memory 377252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3956146633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl
_throughput_w_partial_write.3956146633
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/32.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.600939
Short name T656
Test name
Test status
Simulation time 5256157771 ps
CPU time 338.26 seconds
Started Sep 24 11:45:19 AM UTC 24
Finished Sep 24 11:51:03 AM UTC 24
Peak memory 375004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600939 -assert nopostp
roc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_access_during_k
ey_req.600939
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/33.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_alert_test.4022878123
Short name T628
Test name
Test status
Simulation time 38605921 ps
CPU time 0.99 seconds
Started Sep 24 11:46:47 AM UTC 24
Finished Sep 24 11:46:49 AM UTC 24
Peak memory 211352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022878123
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_alert_test.4022878123
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/33.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_bijection.3817546341
Short name T691
Test name
Test status
Simulation time 63161692763 ps
CPU time 675.64 seconds
Started Sep 24 11:43:27 AM UTC 24
Finished Sep 24 11:54:51 AM UTC 24
Peak memory 212360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817546341 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection.3817546341
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/33.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_executable.1532966434
Short name T780
Test name
Test status
Simulation time 10172347503 ps
CPU time 1305.84 seconds
Started Sep 24 11:45:43 AM UTC 24
Finished Sep 24 12:07:43 PM UTC 24
Peak memory 391208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532966434 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executable.1532966434
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/33.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.1436600007
Short name T627
Test name
Test status
Simulation time 45352265907 ps
CPU time 116.51 seconds
Started Sep 24 11:44:47 AM UTC 24
Finished Sep 24 11:46:46 AM UTC 24
Peak memory 226680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436600007 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_escalation.1436600007
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/33.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.3338005943
Short name T619
Test name
Test status
Simulation time 993189945 ps
CPU time 41.51 seconds
Started Sep 24 11:44:34 AM UTC 24
Finished Sep 24 11:45:17 AM UTC 24
Peak memory 295068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3338005943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_
max_throughput.3338005943
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/33.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.745062753
Short name T643
Test name
Test status
Simulation time 22226849701 ps
CPU time 188.78 seconds
Started Sep 24 11:46:35 AM UTC 24
Finished Sep 24 11:49:47 AM UTC 24
Peak memory 222888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745062753 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_mem_partial_access.745062753
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/33.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.680185609
Short name T635
Test name
Test status
Simulation time 5370556176 ps
CPU time 143.63 seconds
Started Sep 24 11:46:29 AM UTC 24
Finished Sep 24 11:48:56 AM UTC 24
Peak memory 222948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680185609 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_mem_walk.680185609
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/33.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.3066301942
Short name T702
Test name
Test status
Simulation time 199886856613 ps
CPU time 800.5 seconds
Started Sep 24 11:43:24 AM UTC 24
Finished Sep 24 11:56:55 AM UTC 24
Peak memory 354504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066301942 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multiple_keys.3066301942
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/33.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access.1957904634
Short name T615
Test name
Test status
Simulation time 1134085064 ps
CPU time 19.81 seconds
Started Sep 24 11:44:00 AM UTC 24
Finished Sep 24 11:44:21 AM UTC 24
Peak memory 212540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957904634 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_partial_access.1957904634
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/33.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.1993846198
Short name T647
Test name
Test status
Simulation time 20819264549 ps
CPU time 329.42 seconds
Started Sep 24 11:44:22 AM UTC 24
Finished Sep 24 11:49:56 AM UTC 24
Peak memory 212400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993846198 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_partial_a
ccess_b2b.1993846198
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/33.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.2366282081
Short name T623
Test name
Test status
Simulation time 1404127783 ps
CPU time 6.36 seconds
Started Sep 24 11:46:21 AM UTC 24
Finished Sep 24 11:46:29 AM UTC 24
Peak memory 212372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366282081 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.2366282081
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/33.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_regwen.1323805237
Short name T678
Test name
Test status
Simulation time 13956534978 ps
CPU time 440.1 seconds
Started Sep 24 11:45:50 AM UTC 24
Finished Sep 24 11:53:16 AM UTC 24
Peak memory 387288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323805237 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.1323805237
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/33.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_smoke.1642740934
Short name T616
Test name
Test status
Simulation time 2165828478 ps
CPU time 84.35 seconds
Started Sep 24 11:43:07 AM UTC 24
Finished Sep 24 11:44:34 AM UTC 24
Peak memory 340184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642740934 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.1642740934
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/33.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all.1533034264
Short name T808
Test name
Test status
Simulation time 45933133234 ps
CPU time 1469.66 seconds
Started Sep 24 11:46:46 AM UTC 24
Finished Sep 24 12:11:33 PM UTC 24
Peak memory 384784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15330342
64 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_a
ll.1533034264
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/33.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.766544733
Short name T631
Test name
Test status
Simulation time 2168591852 ps
CPU time 30.39 seconds
Started Sep 24 11:46:37 AM UTC 24
Finished Sep 24 11:47:09 AM UTC 24
Peak memory 229804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766544733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.766544733
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/33.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.2035512839
Short name T634
Test name
Test status
Simulation time 16112653285 ps
CPU time 269.61 seconds
Started Sep 24 11:43:28 AM UTC 24
Finished Sep 24 11:48:01 AM UTC 24
Peak memory 212424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035512839 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_pipeline.2035512839
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/33.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.870312903
Short name T622
Test name
Test status
Simulation time 1161543031 ps
CPU time 93.88 seconds
Started Sep 24 11:44:44 AM UTC 24
Finished Sep 24 11:46:20 AM UTC 24
Peak memory 381160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=870312903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_
throughput_w_partial_write.870312903
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/33.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.3992145188
Short name T724
Test name
Test status
Simulation time 6809136400 ps
CPU time 675.6 seconds
Started Sep 24 11:48:20 AM UTC 24
Finished Sep 24 11:59:46 AM UTC 24
Peak memory 389392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992145188 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_access_duri
ng_key_req.3992145188
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/34.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_alert_test.590168668
Short name T638
Test name
Test status
Simulation time 19827232 ps
CPU time 1.07 seconds
Started Sep 24 11:49:10 AM UTC 24
Finished Sep 24 11:49:13 AM UTC 24
Peak memory 211472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590168668 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_alert_test.590168668
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/34.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_bijection.1882884574
Short name T918
Test name
Test status
Simulation time 101250412230 ps
CPU time 2648.46 seconds
Started Sep 24 11:47:09 AM UTC 24
Finished Sep 24 12:31:47 PM UTC 24
Peak memory 213884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882884574 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection.1882884574
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/34.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_executable.1022083835
Short name T720
Test name
Test status
Simulation time 13543280690 ps
CPU time 631.59 seconds
Started Sep 24 11:48:34 AM UTC 24
Finished Sep 24 11:59:13 AM UTC 24
Peak memory 387360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022083835 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executable.1022083835
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/34.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.1614454280
Short name T637
Test name
Test status
Simulation time 11832528298 ps
CPU time 54.54 seconds
Started Sep 24 11:48:08 AM UTC 24
Finished Sep 24 11:49:04 AM UTC 24
Peak memory 222660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614454280 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_escalation.1614454280
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/34.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.2532567502
Short name T642
Test name
Test status
Simulation time 820655003 ps
CPU time 89.95 seconds
Started Sep 24 11:48:03 AM UTC 24
Finished Sep 24 11:49:35 AM UTC 24
Peak memory 381152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2532567502 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_
max_throughput.2532567502
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/34.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.4222705004
Short name T675
Test name
Test status
Simulation time 36551309321 ps
CPU time 238.39 seconds
Started Sep 24 11:49:06 AM UTC 24
Finished Sep 24 11:53:08 AM UTC 24
Peak memory 222708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222705004 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_mem_partial_access.4222705004
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/34.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.2950633621
Short name T694
Test name
Test status
Simulation time 71842224309 ps
CPU time 383.81 seconds
Started Sep 24 11:49:03 AM UTC 24
Finished Sep 24 11:55:32 AM UTC 24
Peak memory 222772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950633621 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_mem_walk.2950633621
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/34.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.3187190670
Short name T790
Test name
Test status
Simulation time 79845805723 ps
CPU time 1327.99 seconds
Started Sep 24 11:46:54 AM UTC 24
Finished Sep 24 12:09:17 PM UTC 24
Peak memory 389500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187190670 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multiple_keys.3187190670
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/34.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access.1692993757
Short name T633
Test name
Test status
Simulation time 1265574294 ps
CPU time 28.46 seconds
Started Sep 24 11:47:17 AM UTC 24
Finished Sep 24 11:47:47 AM UTC 24
Peak memory 212400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692993757 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_partial_access.1692993757
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/34.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.859182722
Short name T683
Test name
Test status
Simulation time 12238309948 ps
CPU time 366.3 seconds
Started Sep 24 11:47:49 AM UTC 24
Finished Sep 24 11:54:00 AM UTC 24
Peak memory 212476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859182722 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_partial_ac
cess_b2b.859182722
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/34.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.2011042384
Short name T636
Test name
Test status
Simulation time 1409869381 ps
CPU time 3.64 seconds
Started Sep 24 11:48:57 AM UTC 24
Finished Sep 24 11:49:02 AM UTC 24
Peak memory 212292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011042384 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.2011042384
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/34.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_regwen.3580329074
Short name T641
Test name
Test status
Simulation time 1173322057 ps
CPU time 50.6 seconds
Started Sep 24 11:48:39 AM UTC 24
Finished Sep 24 11:49:31 AM UTC 24
Peak memory 241832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580329074 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.3580329074
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/34.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_smoke.3779168714
Short name T632
Test name
Test status
Simulation time 1172760355 ps
CPU time 24.83 seconds
Started Sep 24 11:46:50 AM UTC 24
Finished Sep 24 11:47:17 AM UTC 24
Peak memory 212288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779168714 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.3779168714
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/34.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all.1828609873
Short name T951
Test name
Test status
Simulation time 395727021475 ps
CPU time 8840.88 seconds
Started Sep 24 11:49:10 AM UTC 24
Finished Sep 24 02:18:18 PM UTC 24
Peak memory 390944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18286098
73 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_a
ll.1828609873
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/34.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.2762688378
Short name T639
Test name
Test status
Simulation time 97407743 ps
CPU time 5.11 seconds
Started Sep 24 11:49:08 AM UTC 24
Finished Sep 24 11:49:14 AM UTC 24
Peak memory 222644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762688378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.2762688378
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/34.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.3237635105
Short name T672
Test name
Test status
Simulation time 21253950675 ps
CPU time 333.33 seconds
Started Sep 24 11:47:10 AM UTC 24
Finished Sep 24 11:52:48 AM UTC 24
Peak memory 212420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237635105 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_pipeline.3237635105
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/34.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.2778928868
Short name T644
Test name
Test status
Simulation time 1541537781 ps
CPU time 101.41 seconds
Started Sep 24 11:48:06 AM UTC 24
Finished Sep 24 11:49:50 AM UTC 24
Peak memory 381272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2778928868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl
_throughput_w_partial_write.2778928868
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/34.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.3394617811
Short name T752
Test name
Test status
Simulation time 22588423192 ps
CPU time 823.17 seconds
Started Sep 24 11:49:51 AM UTC 24
Finished Sep 24 12:03:43 PM UTC 24
Peak memory 387280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394617811 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_access_duri
ng_key_req.3394617811
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/35.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_alert_test.3424850980
Short name T651
Test name
Test status
Simulation time 37594639 ps
CPU time 1.05 seconds
Started Sep 24 11:49:59 AM UTC 24
Finished Sep 24 11:50:01 AM UTC 24
Peak memory 210884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424850980
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_alert_test.3424850980
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/35.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_bijection.1709185409
Short name T911
Test name
Test status
Simulation time 464337535839 ps
CPU time 2314.4 seconds
Started Sep 24 11:49:23 AM UTC 24
Finished Sep 24 12:28:25 PM UTC 24
Peak memory 214092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709185409 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection.1709185409
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/35.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_executable.3887746690
Short name T706
Test name
Test status
Simulation time 5878799750 ps
CPU time 456.47 seconds
Started Sep 24 11:49:51 AM UTC 24
Finished Sep 24 11:57:33 AM UTC 24
Peak memory 385184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887746690 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executable.3887746690
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/35.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.1549809226
Short name T654
Test name
Test status
Simulation time 29638081623 ps
CPU time 61.42 seconds
Started Sep 24 11:49:50 AM UTC 24
Finished Sep 24 11:50:53 AM UTC 24
Peak memory 212380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549809226 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_escalation.1549809226
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/35.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.45378276
Short name T650
Test name
Test status
Simulation time 1445628364 ps
CPU time 19.61 seconds
Started Sep 24 11:49:38 AM UTC 24
Finished Sep 24 11:49:59 AM UTC 24
Peak memory 278688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
45378276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ma
x_throughput.45378276
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/35.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.9344457
Short name T658
Test name
Test status
Simulation time 999159128 ps
CPU time 70.68 seconds
Started Sep 24 11:49:57 AM UTC 24
Finished Sep 24 11:51:10 AM UTC 24
Peak memory 222600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9344457 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_mem_partial_access.9344457
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/35.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.3695528445
Short name T674
Test name
Test status
Simulation time 27686539068 ps
CPU time 183.86 seconds
Started Sep 24 11:49:54 AM UTC 24
Finished Sep 24 11:53:01 AM UTC 24
Peak memory 222936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695528445 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_mem_walk.3695528445
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/35.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.1076266965
Short name T735
Test name
Test status
Simulation time 8239600149 ps
CPU time 704.81 seconds
Started Sep 24 11:49:15 AM UTC 24
Finished Sep 24 12:01:08 PM UTC 24
Peak memory 387264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076266965 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multiple_keys.1076266965
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/35.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access.3213800692
Short name T645
Test name
Test status
Simulation time 708154412 ps
CPU time 15.03 seconds
Started Sep 24 11:49:34 AM UTC 24
Finished Sep 24 11:49:50 AM UTC 24
Peak memory 212316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213800692 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_partial_access.3213800692
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/35.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.3707503761
Short name T708
Test name
Test status
Simulation time 6259475522 ps
CPU time 476.25 seconds
Started Sep 24 11:49:36 AM UTC 24
Finished Sep 24 11:57:38 AM UTC 24
Peak memory 212420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707503761 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_partial_a
ccess_b2b.3707503761
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/35.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.2551276594
Short name T649
Test name
Test status
Simulation time 1528340450 ps
CPU time 5.13 seconds
Started Sep 24 11:49:52 AM UTC 24
Finished Sep 24 11:49:59 AM UTC 24
Peak memory 212296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551276594 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.2551276594
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/35.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_regwen.1793195853
Short name T799
Test name
Test status
Simulation time 74975585244 ps
CPU time 1238.92 seconds
Started Sep 24 11:49:51 AM UTC 24
Finished Sep 24 12:10:44 PM UTC 24
Peak memory 391648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793195853 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.1793195853
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/35.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_smoke.3147299610
Short name T646
Test name
Test status
Simulation time 5698991432 ps
CPU time 36.98 seconds
Started Sep 24 11:49:14 AM UTC 24
Finished Sep 24 11:49:52 AM UTC 24
Peak memory 212416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147299610 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.3147299610
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/35.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all.2691560912
Short name T938
Test name
Test status
Simulation time 494826736553 ps
CPU time 4025.93 seconds
Started Sep 24 11:49:59 AM UTC 24
Finished Sep 24 12:57:51 PM UTC 24
Peak memory 393064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26915609
12 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_a
ll.2691560912
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/35.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.620078376
Short name T653
Test name
Test status
Simulation time 3900912739 ps
CPU time 27.38 seconds
Started Sep 24 11:49:57 AM UTC 24
Finished Sep 24 11:50:26 AM UTC 24
Peak memory 222736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620078376 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.620078376
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/35.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.3937848221
Short name T687
Test name
Test status
Simulation time 7748774369 ps
CPU time 286.07 seconds
Started Sep 24 11:49:32 AM UTC 24
Finished Sep 24 11:54:22 AM UTC 24
Peak memory 212344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937848221 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_pipeline.3937848221
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/35.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.192094239
Short name T648
Test name
Test status
Simulation time 697557178 ps
CPU time 7.97 seconds
Started Sep 24 11:49:48 AM UTC 24
Finished Sep 24 11:49:58 AM UTC 24
Peak memory 222344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=192094239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_
throughput_w_partial_write.192094239
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/35.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.2122018057
Short name T820
Test name
Test status
Simulation time 22282401032 ps
CPU time 1315.48 seconds
Started Sep 24 11:50:27 AM UTC 24
Finished Sep 24 12:12:37 PM UTC 24
Peak memory 389340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122018057 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_access_duri
ng_key_req.2122018057
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/36.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_alert_test.2117659092
Short name T661
Test name
Test status
Simulation time 18007456 ps
CPU time 0.91 seconds
Started Sep 24 11:51:42 AM UTC 24
Finished Sep 24 11:51:43 AM UTC 24
Peak memory 211416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117659092
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_alert_test.2117659092
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/36.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_bijection.3702992431
Short name T909
Test name
Test status
Simulation time 122008548115 ps
CPU time 2267.66 seconds
Started Sep 24 11:50:01 AM UTC 24
Finished Sep 24 12:28:15 PM UTC 24
Peak memory 213880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702992431 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection.3702992431
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/36.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_executable.459305142
Short name T800
Test name
Test status
Simulation time 17938506945 ps
CPU time 1186.66 seconds
Started Sep 24 11:50:55 AM UTC 24
Finished Sep 24 12:10:54 PM UTC 24
Peak memory 389596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459305142 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executable.459305142
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/36.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.1516090679
Short name T662
Test name
Test status
Simulation time 47782911953 ps
CPU time 81.59 seconds
Started Sep 24 11:50:26 AM UTC 24
Finished Sep 24 11:51:49 AM UTC 24
Peak memory 212372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516090679 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_escalation.1516090679
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/36.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.1630401697
Short name T668
Test name
Test status
Simulation time 767857182 ps
CPU time 116.77 seconds
Started Sep 24 11:50:21 AM UTC 24
Finished Sep 24 11:52:20 AM UTC 24
Peak memory 381344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1630401697 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_
max_throughput.1630401697
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/36.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.541476931
Short name T671
Test name
Test status
Simulation time 1013094425 ps
CPU time 87.6 seconds
Started Sep 24 11:51:06 AM UTC 24
Finished Sep 24 11:52:36 AM UTC 24
Peak memory 229760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541476931 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_mem_partial_access.541476931
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/36.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.3097301684
Short name T711
Test name
Test status
Simulation time 65958789886 ps
CPU time 414.16 seconds
Started Sep 24 11:51:04 AM UTC 24
Finished Sep 24 11:58:04 AM UTC 24
Peak memory 222740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097301684 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_mem_walk.3097301684
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/36.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.73603865
Short name T756
Test name
Test status
Simulation time 18401445543 ps
CPU time 828.37 seconds
Started Sep 24 11:50:00 AM UTC 24
Finished Sep 24 12:03:58 PM UTC 24
Peak memory 389336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73603865 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multiple_keys.73603865
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/36.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access.314414101
Short name T655
Test name
Test status
Simulation time 1047919542 ps
CPU time 40.87 seconds
Started Sep 24 11:50:12 AM UTC 24
Finished Sep 24 11:50:54 AM UTC 24
Peak memory 293096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314414101 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_partial_access.314414101
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/36.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.4198003577
Short name T707
Test name
Test status
Simulation time 14780082782 ps
CPU time 430.06 seconds
Started Sep 24 11:50:19 AM UTC 24
Finished Sep 24 11:57:35 AM UTC 24
Peak memory 212428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198003577 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_partial_a
ccess_b2b.4198003577
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/36.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.1949511018
Short name T657
Test name
Test status
Simulation time 399202456 ps
CPU time 4.54 seconds
Started Sep 24 11:50:59 AM UTC 24
Finished Sep 24 11:51:05 AM UTC 24
Peak memory 212296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949511018 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.1949511018
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/36.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_regwen.660700035
Short name T741
Test name
Test status
Simulation time 2491105053 ps
CPU time 674.88 seconds
Started Sep 24 11:50:56 AM UTC 24
Finished Sep 24 12:02:19 PM UTC 24
Peak memory 385288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660700035 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.660700035
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/36.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_smoke.816269191
Short name T652
Test name
Test status
Simulation time 1066070146 ps
CPU time 21.95 seconds
Started Sep 24 11:50:00 AM UTC 24
Finished Sep 24 11:50:23 AM UTC 24
Peak memory 212332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816269191 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.816269191
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/36.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all.3108345115
Short name T937
Test name
Test status
Simulation time 324397099483 ps
CPU time 3903.92 seconds
Started Sep 24 11:51:27 AM UTC 24
Finished Sep 24 12:57:16 PM UTC 24
Peak memory 401180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31083451
15 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_a
ll.3108345115
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/36.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.3119780237
Short name T122
Test name
Test status
Simulation time 1245041892 ps
CPU time 51.26 seconds
Started Sep 24 11:51:11 AM UTC 24
Finished Sep 24 11:52:04 AM UTC 24
Peak memory 229676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119780237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.3119780237
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/36.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.1514579807
Short name T677
Test name
Test status
Simulation time 14827109978 ps
CPU time 189 seconds
Started Sep 24 11:50:04 AM UTC 24
Finished Sep 24 11:53:15 AM UTC 24
Peak memory 212396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514579807 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_pipeline.1514579807
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/36.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.3590957868
Short name T665
Test name
Test status
Simulation time 1574266786 ps
CPU time 97.6 seconds
Started Sep 24 11:50:24 AM UTC 24
Finished Sep 24 11:52:04 AM UTC 24
Peak memory 366820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3590957868 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl
_throughput_w_partial_write.3590957868
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/36.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.2339026479
Short name T742
Test name
Test status
Simulation time 11072080787 ps
CPU time 588.78 seconds
Started Sep 24 11:52:26 AM UTC 24
Finished Sep 24 12:02:22 PM UTC 24
Peak memory 352532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339026479 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_access_duri
ng_key_req.2339026479
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/37.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_alert_test.3988860527
Short name T679
Test name
Test status
Simulation time 36146103 ps
CPU time 1.01 seconds
Started Sep 24 11:53:16 AM UTC 24
Finished Sep 24 11:53:18 AM UTC 24
Peak memory 211352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988860527
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_alert_test.3988860527
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/37.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_bijection.2873761328
Short name T916
Test name
Test status
Simulation time 91137071642 ps
CPU time 2259.57 seconds
Started Sep 24 11:51:52 AM UTC 24
Finished Sep 24 12:29:59 PM UTC 24
Peak memory 214140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873761328 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection.2873761328
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/37.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_executable.2028023093
Short name T772
Test name
Test status
Simulation time 6836793740 ps
CPU time 828.1 seconds
Started Sep 24 11:52:30 AM UTC 24
Finished Sep 24 12:06:28 PM UTC 24
Peak memory 387288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028023093 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executable.2028023093
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/37.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.1407717219
Short name T686
Test name
Test status
Simulation time 24036894577 ps
CPU time 117.81 seconds
Started Sep 24 11:52:21 AM UTC 24
Finished Sep 24 11:54:21 AM UTC 24
Peak memory 212660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407717219 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_escalation.1407717219
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/37.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.1739383648
Short name T670
Test name
Test status
Simulation time 711831476 ps
CPU time 10.74 seconds
Started Sep 24 11:52:17 AM UTC 24
Finished Sep 24 11:52:29 AM UTC 24
Peak memory 222536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1739383648 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_
max_throughput.1739383648
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/37.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.1051731566
Short name T690
Test name
Test status
Simulation time 4387985631 ps
CPU time 100.61 seconds
Started Sep 24 11:53:01 AM UTC 24
Finished Sep 24 11:54:45 AM UTC 24
Peak memory 222712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051731566 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_mem_partial_access.1051731566
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/37.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.2459733574
Short name T713
Test name
Test status
Simulation time 27647868316 ps
CPU time 305.32 seconds
Started Sep 24 11:52:57 AM UTC 24
Finished Sep 24 11:58:07 AM UTC 24
Peak memory 222804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459733574 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_mem_walk.2459733574
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/37.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.1068530590
Short name T810
Test name
Test status
Simulation time 17315368907 ps
CPU time 1174.55 seconds
Started Sep 24 11:51:50 AM UTC 24
Finished Sep 24 12:11:38 PM UTC 24
Peak memory 385180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068530590 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multiple_keys.1068530590
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/37.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access.1021135346
Short name T669
Test name
Test status
Simulation time 909054333 ps
CPU time 17.87 seconds
Started Sep 24 11:52:05 AM UTC 24
Finished Sep 24 11:52:25 AM UTC 24
Peak memory 212240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021135346 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_partial_access.1021135346
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/37.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.1250960595
Short name T722
Test name
Test status
Simulation time 19228554003 ps
CPU time 441.93 seconds
Started Sep 24 11:52:05 AM UTC 24
Finished Sep 24 11:59:33 AM UTC 24
Peak memory 212428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250960595 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_partial_a
ccess_b2b.1250960595
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/37.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.4149319270
Short name T673
Test name
Test status
Simulation time 1349220027 ps
CPU time 5.97 seconds
Started Sep 24 11:52:49 AM UTC 24
Finished Sep 24 11:52:56 AM UTC 24
Peak memory 212564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149319270 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.4149319270
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/37.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_regwen.1679598464
Short name T738
Test name
Test status
Simulation time 3076907084 ps
CPU time 535.36 seconds
Started Sep 24 11:52:36 AM UTC 24
Finished Sep 24 12:01:40 PM UTC 24
Peak memory 387360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679598464 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.1679598464
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/37.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_smoke.4199164435
Short name T667
Test name
Test status
Simulation time 5623972739 ps
CPU time 31.64 seconds
Started Sep 24 11:51:45 AM UTC 24
Finished Sep 24 11:52:18 AM UTC 24
Peak memory 212396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199164435 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.4199164435
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/37.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all.1741591596
Short name T950
Test name
Test status
Simulation time 358937715548 ps
CPU time 8058.97 seconds
Started Sep 24 11:53:11 AM UTC 24
Finished Sep 24 02:09:01 PM UTC 24
Peak memory 391016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17415915
96 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_a
ll.1741591596
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/37.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.2906985090
Short name T710
Test name
Test status
Simulation time 9798848767 ps
CPU time 272.8 seconds
Started Sep 24 11:53:10 AM UTC 24
Finished Sep 24 11:57:46 AM UTC 24
Peak memory 395696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906985090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.2906985090
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/37.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.699409163
Short name T700
Test name
Test status
Simulation time 35191584816 ps
CPU time 259.63 seconds
Started Sep 24 11:51:55 AM UTC 24
Finished Sep 24 11:56:18 AM UTC 24
Peak memory 212344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699409163 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_pipeline.699409163
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/37.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.1702207954
Short name T682
Test name
Test status
Simulation time 786856286 ps
CPU time 88.38 seconds
Started Sep 24 11:52:19 AM UTC 24
Finished Sep 24 11:53:49 AM UTC 24
Peak memory 352412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1702207954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl
_throughput_w_partial_write.1702207954
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/37.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.1525818865
Short name T746
Test name
Test status
Simulation time 58925736888 ps
CPU time 521.5 seconds
Started Sep 24 11:54:23 AM UTC 24
Finished Sep 24 12:03:11 PM UTC 24
Peak memory 340400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525818865 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_access_duri
ng_key_req.1525818865
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/38.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_alert_test.601823934
Short name T696
Test name
Test status
Simulation time 24856524 ps
CPU time 0.97 seconds
Started Sep 24 11:55:39 AM UTC 24
Finished Sep 24 11:55:41 AM UTC 24
Peak memory 211472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601823934 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_alert_test.601823934
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/38.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_bijection.693247953
Short name T855
Test name
Test status
Simulation time 115418535015 ps
CPU time 1417.03 seconds
Started Sep 24 11:53:41 AM UTC 24
Finished Sep 24 12:17:35 PM UTC 24
Peak memory 212404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693247953 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection.693247953
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/38.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_executable.3003364338
Short name T737
Test name
Test status
Simulation time 23679684383 ps
CPU time 423.26 seconds
Started Sep 24 11:54:28 AM UTC 24
Finished Sep 24 12:01:37 PM UTC 24
Peak memory 370980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003364338 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executable.3003364338
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/38.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.2874474604
Short name T695
Test name
Test status
Simulation time 14173696350 ps
CPU time 73.79 seconds
Started Sep 24 11:54:22 AM UTC 24
Finished Sep 24 11:55:38 AM UTC 24
Peak memory 226676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874474604 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_escalation.2874474604
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/38.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.972049678
Short name T688
Test name
Test status
Simulation time 1616536736 ps
CPU time 16.2 seconds
Started Sep 24 11:54:10 AM UTC 24
Finished Sep 24 11:54:27 AM UTC 24
Peak memory 249992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
972049678 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_m
ax_throughput.972049678
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/38.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.2903526182
Short name T703
Test name
Test status
Simulation time 9867563720 ps
CPU time 125.15 seconds
Started Sep 24 11:54:54 AM UTC 24
Finished Sep 24 11:57:01 AM UTC 24
Peak memory 222712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903526182 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_mem_partial_access.2903526182
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/38.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.2017249586
Short name T721
Test name
Test status
Simulation time 5715928981 ps
CPU time 258.62 seconds
Started Sep 24 11:54:52 AM UTC 24
Finished Sep 24 11:59:15 AM UTC 24
Peak memory 222756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017249586 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_mem_walk.2017249586
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/38.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.307100941
Short name T750
Test name
Test status
Simulation time 19406667894 ps
CPU time 592.25 seconds
Started Sep 24 11:53:19 AM UTC 24
Finished Sep 24 12:03:19 PM UTC 24
Peak memory 383436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307100941 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multiple_keys.307100941
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/38.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access.2661037083
Short name T685
Test name
Test status
Simulation time 4747152643 ps
CPU time 20.11 seconds
Started Sep 24 11:53:50 AM UTC 24
Finished Sep 24 11:54:12 AM UTC 24
Peak memory 212604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661037083 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_partial_access.2661037083
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/38.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.961981668
Short name T726
Test name
Test status
Simulation time 10741377387 ps
CPU time 373.47 seconds
Started Sep 24 11:54:01 AM UTC 24
Finished Sep 24 12:00:20 PM UTC 24
Peak memory 212664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961981668 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_partial_ac
cess_b2b.961981668
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/38.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.403307827
Short name T692
Test name
Test status
Simulation time 1397468790 ps
CPU time 6.5 seconds
Started Sep 24 11:54:45 AM UTC 24
Finished Sep 24 11:54:53 AM UTC 24
Peak memory 212364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403307827 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.403307827
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/38.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_regwen.181430799
Short name T865
Test name
Test status
Simulation time 142463586320 ps
CPU time 1477.96 seconds
Started Sep 24 11:54:31 AM UTC 24
Finished Sep 24 12:19:27 PM UTC 24
Peak memory 387292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181430799 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.181430799
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/38.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_smoke.1779436643
Short name T684
Test name
Test status
Simulation time 761165649 ps
CPU time 49.65 seconds
Started Sep 24 11:53:17 AM UTC 24
Finished Sep 24 11:54:09 AM UTC 24
Peak memory 299228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779436643 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.1779436643
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/38.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all.3585893793
Short name T936
Test name
Test status
Simulation time 204107989407 ps
CPU time 3520.88 seconds
Started Sep 24 11:55:33 AM UTC 24
Finished Sep 24 12:54:52 PM UTC 24
Peak memory 394972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35858937
93 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_a
ll.3585893793
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/38.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.862658330
Short name T123
Test name
Test status
Simulation time 982927306 ps
CPU time 31.45 seconds
Started Sep 24 11:55:16 AM UTC 24
Finished Sep 24 11:55:49 AM UTC 24
Peak memory 222776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862658330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.862658330
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/38.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.2535597829
Short name T718
Test name
Test status
Simulation time 4716331595 ps
CPU time 298.61 seconds
Started Sep 24 11:53:44 AM UTC 24
Finished Sep 24 11:58:47 AM UTC 24
Peak memory 212472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535597829 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_pipeline.2535597829
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/38.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.2839507784
Short name T697
Test name
Test status
Simulation time 3085162766 ps
CPU time 86.68 seconds
Started Sep 24 11:54:13 AM UTC 24
Finished Sep 24 11:55:42 AM UTC 24
Peak memory 367076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2839507784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl
_throughput_w_partial_write.2839507784
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/38.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.3063088239
Short name T729
Test name
Test status
Simulation time 3064969619 ps
CPU time 202.36 seconds
Started Sep 24 11:57:05 AM UTC 24
Finished Sep 24 12:00:30 PM UTC 24
Peak memory 381416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063088239 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_access_duri
ng_key_req.3063088239
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/39.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_alert_test.1062929507
Short name T716
Test name
Test status
Simulation time 20174902 ps
CPU time 0.96 seconds
Started Sep 24 11:58:07 AM UTC 24
Finished Sep 24 11:58:09 AM UTC 24
Peak memory 211352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062929507
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_alert_test.1062929507
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/39.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_bijection.1543715910
Short name T903
Test name
Test status
Simulation time 164480664502 ps
CPU time 1795.08 seconds
Started Sep 24 11:55:50 AM UTC 24
Finished Sep 24 12:26:06 PM UTC 24
Peak memory 213896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543715910 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection.1543715910
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/39.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_executable.3762020570
Short name T805
Test name
Test status
Simulation time 6500922556 ps
CPU time 823.28 seconds
Started Sep 24 11:57:12 AM UTC 24
Finished Sep 24 12:11:05 PM UTC 24
Peak memory 387344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762020570 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executable.3762020570
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/39.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.2459688708
Short name T715
Test name
Test status
Simulation time 14511627700 ps
CPU time 64.65 seconds
Started Sep 24 11:57:03 AM UTC 24
Finished Sep 24 11:58:09 AM UTC 24
Peak memory 222620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459688708 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_escalation.2459688708
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/39.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.3468010572
Short name T704
Test name
Test status
Simulation time 766089114 ps
CPU time 39.62 seconds
Started Sep 24 11:56:23 AM UTC 24
Finished Sep 24 11:57:04 AM UTC 24
Peak memory 303524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3468010572 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_
max_throughput.3468010572
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/39.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.515164248
Short name T727
Test name
Test status
Simulation time 2536736275 ps
CPU time 158.33 seconds
Started Sep 24 11:57:45 AM UTC 24
Finished Sep 24 12:00:26 PM UTC 24
Peak memory 229628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515164248 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_mem_partial_access.515164248
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/39.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.250106134
Short name T745
Test name
Test status
Simulation time 5473704086 ps
CPU time 314.01 seconds
Started Sep 24 11:57:40 AM UTC 24
Finished Sep 24 12:02:59 PM UTC 24
Peak memory 222616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250106134 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_mem_walk.250106134
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/39.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.1988905957
Short name T775
Test name
Test status
Simulation time 36357359930 ps
CPU time 669.88 seconds
Started Sep 24 11:55:43 AM UTC 24
Finished Sep 24 12:07:01 PM UTC 24
Peak memory 383184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988905957 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multiple_keys.1988905957
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/39.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access.1316980533
Short name T701
Test name
Test status
Simulation time 487540781 ps
CPU time 15.08 seconds
Started Sep 24 11:56:06 AM UTC 24
Finished Sep 24 11:56:22 AM UTC 24
Peak memory 245904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316980533 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_partial_access.1316980533
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/39.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.533626604
Short name T764
Test name
Test status
Simulation time 80736635430 ps
CPU time 517.99 seconds
Started Sep 24 11:56:20 AM UTC 24
Finished Sep 24 12:05:04 PM UTC 24
Peak memory 212340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533626604 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_partial_ac
cess_b2b.533626604
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/39.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.4152752549
Short name T709
Test name
Test status
Simulation time 1165711814 ps
CPU time 6.45 seconds
Started Sep 24 11:57:36 AM UTC 24
Finished Sep 24 11:57:43 AM UTC 24
Peak memory 212296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152752549 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.4152752549
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/39.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_regwen.294618027
Short name T768
Test name
Test status
Simulation time 4689370760 ps
CPU time 478.48 seconds
Started Sep 24 11:57:34 AM UTC 24
Finished Sep 24 12:05:39 PM UTC 24
Peak memory 383188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294618027 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.294618027
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/39.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_smoke.4184198653
Short name T698
Test name
Test status
Simulation time 674780601 ps
CPU time 9.07 seconds
Started Sep 24 11:55:42 AM UTC 24
Finished Sep 24 11:55:52 AM UTC 24
Peak memory 212164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184198653 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.4184198653
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/39.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all.2585768406
Short name T944
Test name
Test status
Simulation time 294532822336 ps
CPU time 4616.82 seconds
Started Sep 24 11:58:06 AM UTC 24
Finished Sep 24 01:15:54 PM UTC 24
Peak memory 392984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25857684
06 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_a
ll.2585768406
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/39.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.1763572569
Short name T714
Test name
Test status
Simulation time 4744631855 ps
CPU time 19.18 seconds
Started Sep 24 11:57:48 AM UTC 24
Finished Sep 24 11:58:08 AM UTC 24
Peak memory 222804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763572569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.1763572569
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/39.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.1684272482
Short name T728
Test name
Test status
Simulation time 3522716423 ps
CPU time 271.32 seconds
Started Sep 24 11:55:53 AM UTC 24
Finished Sep 24 12:00:28 PM UTC 24
Peak memory 212396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684272482 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_pipeline.1684272482
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/39.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.133261876
Short name T705
Test name
Test status
Simulation time 678792143 ps
CPU time 12.89 seconds
Started Sep 24 11:56:56 AM UTC 24
Finished Sep 24 11:57:11 AM UTC 24
Peak memory 229628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=133261876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_
throughput_w_partial_write.133261876
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/39.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.4280809051
Short name T39
Test name
Test status
Simulation time 2780130110 ps
CPU time 194.88 seconds
Started Sep 24 09:52:16 AM UTC 24
Finished Sep 24 09:55:35 AM UTC 24
Peak memory 379424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280809051 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_access_durin
g_key_req.4280809051
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/4.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_alert_test.145160865
Short name T162
Test name
Test status
Simulation time 54243726 ps
CPU time 1.04 seconds
Started Sep 24 09:54:05 AM UTC 24
Finished Sep 24 09:54:07 AM UTC 24
Peak memory 211228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145160865 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_alert_test.145160865
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/4.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_bijection.3702736513
Short name T264
Test name
Test status
Simulation time 25278456414 ps
CPU time 1923.02 seconds
Started Sep 24 09:51:32 AM UTC 24
Finished Sep 24 10:24:01 AM UTC 24
Peak memory 214092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702736513 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection.3702736513
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/4.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_executable.128140285
Short name T147
Test name
Test status
Simulation time 14138968705 ps
CPU time 596.28 seconds
Started Sep 24 09:52:24 AM UTC 24
Finished Sep 24 10:02:28 AM UTC 24
Peak memory 379176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128140285 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executable.128140285
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/4.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.2689923526
Short name T67
Test name
Test status
Simulation time 15297174807 ps
CPU time 72.12 seconds
Started Sep 24 09:52:14 AM UTC 24
Finished Sep 24 09:53:28 AM UTC 24
Peak memory 212360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689923526 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_escalation.2689923526
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/4.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.3087605075
Short name T159
Test name
Test status
Simulation time 2778541047 ps
CPU time 23.41 seconds
Started Sep 24 09:51:59 AM UTC 24
Finished Sep 24 09:52:24 AM UTC 24
Peak memory 262636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3087605075 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_m
ax_throughput.3087605075
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/4.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.3214049840
Short name T85
Test name
Test status
Simulation time 38377540391 ps
CPU time 220.44 seconds
Started Sep 24 09:53:29 AM UTC 24
Finished Sep 24 09:57:13 AM UTC 24
Peak memory 227008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214049840 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_mem_partial_access.3214049840
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/4.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.3113161443
Short name T47
Test name
Test status
Simulation time 21305183718 ps
CPU time 493.92 seconds
Started Sep 24 09:53:20 AM UTC 24
Finished Sep 24 10:01:41 AM UTC 24
Peak memory 212644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113161443 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_mem_walk.3113161443
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/4.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.499517853
Short name T267
Test name
Test status
Simulation time 119422169847 ps
CPU time 1981.22 seconds
Started Sep 24 09:51:32 AM UTC 24
Finished Sep 24 10:24:55 AM UTC 24
Peak memory 388876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499517853 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multiple_keys.499517853
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/4.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access.3391502549
Short name T158
Test name
Test status
Simulation time 641742082 ps
CPU time 31.82 seconds
Started Sep 24 09:51:40 AM UTC 24
Finished Sep 24 09:52:13 AM UTC 24
Peak memory 272792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391502549 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_partial_access.3391502549
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/4.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.2645950929
Short name T176
Test name
Test status
Simulation time 32248347343 ps
CPU time 454.11 seconds
Started Sep 24 09:51:43 AM UTC 24
Finished Sep 24 09:59:23 AM UTC 24
Peak memory 212636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645950929 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_partial_ac
cess_b2b.2645950929
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/4.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.1724317190
Short name T160
Test name
Test status
Simulation time 4804251255 ps
CPU time 6.92 seconds
Started Sep 24 09:53:11 AM UTC 24
Finished Sep 24 09:53:19 AM UTC 24
Peak memory 212428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724317190 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.1724317190
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/4.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_regwen.1617639470
Short name T142
Test name
Test status
Simulation time 4782076721 ps
CPU time 666.52 seconds
Started Sep 24 09:52:59 AM UTC 24
Finished Sep 24 10:04:14 AM UTC 24
Peak memory 385572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617639470 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.1617639470
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/4.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.3325311036
Short name T33
Test name
Test status
Simulation time 135669544 ps
CPU time 3.04 seconds
Started Sep 24 09:54:00 AM UTC 24
Finished Sep 24 09:54:04 AM UTC 24
Peak memory 248456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325311036 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_sec_cm.3325311036
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/4.sram_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_smoke.3233040982
Short name T157
Test name
Test status
Simulation time 773783948 ps
CPU time 5.9 seconds
Started Sep 24 09:51:32 AM UTC 24
Finished Sep 24 09:51:39 AM UTC 24
Peak memory 212024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233040982 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.3233040982
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/4.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all.4202723532
Short name T333
Test name
Test status
Simulation time 364231749770 ps
CPU time 2749.87 seconds
Started Sep 24 09:53:53 AM UTC 24
Finished Sep 24 10:40:15 AM UTC 24
Peak memory 388964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42027235
32 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all.4202723532
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/4.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.1286434570
Short name T61
Test name
Test status
Simulation time 2012956264 ps
CPU time 15.84 seconds
Started Sep 24 09:53:47 AM UTC 24
Finished Sep 24 09:54:04 AM UTC 24
Peak memory 224712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286434570 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.1286434570
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/4.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.2495130475
Short name T179
Test name
Test status
Simulation time 4865539199 ps
CPU time 484.79 seconds
Started Sep 24 09:51:33 AM UTC 24
Finished Sep 24 09:59:44 AM UTC 24
Peak memory 212340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495130475 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_pipeline.2495130475
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/4.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.54353179
Short name T161
Test name
Test status
Simulation time 1635582366 ps
CPU time 101.31 seconds
Started Sep 24 09:52:03 AM UTC 24
Finished Sep 24 09:53:47 AM UTC 24
Peak memory 381084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=54353179 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_th
roughput_w_partial_write.54353179
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/4.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.1621677385
Short name T831
Test name
Test status
Simulation time 87537567868 ps
CPU time 867.86 seconds
Started Sep 24 11:59:27 AM UTC 24
Finished Sep 24 12:14:05 PM UTC 24
Peak memory 387380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621677385 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_access_duri
ng_key_req.1621677385
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/40.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_alert_test.4048721417
Short name T730
Test name
Test status
Simulation time 31955643 ps
CPU time 1.02 seconds
Started Sep 24 12:00:32 PM UTC 24
Finished Sep 24 12:00:34 PM UTC 24
Peak memory 211352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048721417
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_alert_test.4048721417
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/40.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_bijection.1041709770
Short name T907
Test name
Test status
Simulation time 138425075216 ps
CPU time 1767.79 seconds
Started Sep 24 11:58:11 AM UTC 24
Finished Sep 24 12:27:59 PM UTC 24
Peak memory 212532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041709770 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection.1041709770
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/40.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_executable.3680180535
Short name T881
Test name
Test status
Simulation time 74538357991 ps
CPU time 1278.44 seconds
Started Sep 24 11:59:34 AM UTC 24
Finished Sep 24 12:21:07 PM UTC 24
Peak memory 389412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680180535 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executable.3680180535
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/40.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.85770647
Short name T733
Test name
Test status
Simulation time 18992805003 ps
CPU time 90.71 seconds
Started Sep 24 11:59:16 AM UTC 24
Finished Sep 24 12:00:49 PM UTC 24
Peak memory 212336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85770647 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_escalation.85770647
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/40.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.1098228471
Short name T731
Test name
Test status
Simulation time 1592410023 ps
CPU time 91.78 seconds
Started Sep 24 11:59:02 AM UTC 24
Finished Sep 24 12:00:36 PM UTC 24
Peak memory 383140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1098228471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_
max_throughput.1098228471
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/40.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.3176391190
Short name T754
Test name
Test status
Simulation time 18313540066 ps
CPU time 201.24 seconds
Started Sep 24 12:00:22 PM UTC 24
Finished Sep 24 12:03:47 PM UTC 24
Peak memory 222780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176391190 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_mem_partial_access.3176391190
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/40.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.3335907431
Short name T744
Test name
Test status
Simulation time 2689046588 ps
CPU time 164.12 seconds
Started Sep 24 11:59:55 AM UTC 24
Finished Sep 24 12:02:42 PM UTC 24
Peak memory 222880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335907431 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_mem_walk.3335907431
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/40.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.1059443169
Short name T821
Test name
Test status
Simulation time 9759177308 ps
CPU time 862.24 seconds
Started Sep 24 11:58:11 AM UTC 24
Finished Sep 24 12:12:43 PM UTC 24
Peak memory 389320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059443169 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multiple_keys.1059443169
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/40.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access.2876082962
Short name T719
Test name
Test status
Simulation time 13764099129 ps
CPU time 18.38 seconds
Started Sep 24 11:58:41 AM UTC 24
Finished Sep 24 11:59:01 AM UTC 24
Peak memory 212412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876082962 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_partial_access.2876082962
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/40.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.2607681766
Short name T763
Test name
Test status
Simulation time 44248255996 ps
CPU time 358.56 seconds
Started Sep 24 11:58:49 AM UTC 24
Finished Sep 24 12:04:53 PM UTC 24
Peak memory 212684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607681766 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_partial_a
ccess_b2b.2607681766
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/40.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.2936385233
Short name T725
Test name
Test status
Simulation time 2404259911 ps
CPU time 5.88 seconds
Started Sep 24 11:59:46 AM UTC 24
Finished Sep 24 11:59:53 AM UTC 24
Peak memory 212628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936385233 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.2936385233
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/40.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_regwen.745812018
Short name T749
Test name
Test status
Simulation time 2702386050 ps
CPU time 216.45 seconds
Started Sep 24 11:59:36 AM UTC 24
Finished Sep 24 12:03:16 PM UTC 24
Peak memory 375008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745812018 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.745812018
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/40.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_smoke.1303021685
Short name T717
Test name
Test status
Simulation time 2886703885 ps
CPU time 31.7 seconds
Started Sep 24 11:58:07 AM UTC 24
Finished Sep 24 11:58:41 AM UTC 24
Peak memory 212364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303021685 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.1303021685
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/40.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all.3439848171
Short name T946
Test name
Test status
Simulation time 238154981496 ps
CPU time 4908.6 seconds
Started Sep 24 12:00:29 PM UTC 24
Finished Sep 24 01:23:12 PM UTC 24
Peak memory 388888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34398481
71 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_a
ll.3439848171
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/40.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.3189875398
Short name T732
Test name
Test status
Simulation time 1447770191 ps
CPU time 18.1 seconds
Started Sep 24 12:00:27 PM UTC 24
Finished Sep 24 12:00:46 PM UTC 24
Peak memory 222976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189875398 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.3189875398
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/40.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.737676522
Short name T757
Test name
Test status
Simulation time 7398983214 ps
CPU time 355.2 seconds
Started Sep 24 11:58:12 AM UTC 24
Finished Sep 24 12:04:12 PM UTC 24
Peak memory 212392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737676522 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_pipeline.737676522
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/40.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.2437761159
Short name T723
Test name
Test status
Simulation time 723290664 ps
CPU time 19.49 seconds
Started Sep 24 11:59:14 AM UTC 24
Finished Sep 24 11:59:35 AM UTC 24
Peak memory 262564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2437761159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl
_throughput_w_partial_write.2437761159
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/40.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.3763384109
Short name T875
Test name
Test status
Simulation time 36614747967 ps
CPU time 1081.61 seconds
Started Sep 24 12:02:15 PM UTC 24
Finished Sep 24 12:20:32 PM UTC 24
Peak memory 387192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763384109 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_access_duri
ng_key_req.3763384109
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/41.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_alert_test.838472680
Short name T748
Test name
Test status
Simulation time 30059159 ps
CPU time 0.93 seconds
Started Sep 24 12:03:12 PM UTC 24
Finished Sep 24 12:03:14 PM UTC 24
Peak memory 210880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838472680 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_alert_test.838472680
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/41.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_bijection.19670961
Short name T860
Test name
Test status
Simulation time 205745530291 ps
CPU time 1083.62 seconds
Started Sep 24 12:00:47 PM UTC 24
Finished Sep 24 12:19:05 PM UTC 24
Peak memory 212468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19670961 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection.19670961
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/41.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_executable.2744837309
Short name T844
Test name
Test status
Simulation time 43658102080 ps
CPU time 797.81 seconds
Started Sep 24 12:02:17 PM UTC 24
Finished Sep 24 12:15:44 PM UTC 24
Peak memory 387288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744837309 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executable.2744837309
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/41.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.2616977294
Short name T761
Test name
Test status
Simulation time 17861513804 ps
CPU time 173.21 seconds
Started Sep 24 12:01:41 PM UTC 24
Finished Sep 24 12:04:38 PM UTC 24
Peak memory 222600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616977294 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_escalation.2616977294
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/41.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.87928025
Short name T739
Test name
Test status
Simulation time 1511603476 ps
CPU time 44.83 seconds
Started Sep 24 12:01:27 PM UTC 24
Finished Sep 24 12:02:13 PM UTC 24
Peak memory 311524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
87928025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ma
x_throughput.87928025
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/41.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.317276931
Short name T759
Test name
Test status
Simulation time 26214180094 ps
CPU time 92.92 seconds
Started Sep 24 12:02:43 PM UTC 24
Finished Sep 24 12:04:18 PM UTC 24
Peak memory 222724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317276931 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_mem_partial_access.317276931
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/41.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.2273991369
Short name T793
Test name
Test status
Simulation time 89991774328 ps
CPU time 426.69 seconds
Started Sep 24 12:02:31 PM UTC 24
Finished Sep 24 12:09:44 PM UTC 24
Peak memory 222620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273991369 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_mem_walk.2273991369
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/41.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.3145070306
Short name T838
Test name
Test status
Simulation time 46614654430 ps
CPU time 845.57 seconds
Started Sep 24 12:00:37 PM UTC 24
Finished Sep 24 12:14:53 PM UTC 24
Peak memory 383188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145070306 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multiple_keys.3145070306
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/41.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access.41774332
Short name T736
Test name
Test status
Simulation time 907857455 ps
CPU time 26.44 seconds
Started Sep 24 12:00:58 PM UTC 24
Finished Sep 24 12:01:26 PM UTC 24
Peak memory 212332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41774332 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_partial_access.41774332
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/41.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.2889766767
Short name T796
Test name
Test status
Simulation time 49008946317 ps
CPU time 522.03 seconds
Started Sep 24 12:01:08 PM UTC 24
Finished Sep 24 12:09:58 PM UTC 24
Peak memory 212388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889766767 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_partial_a
ccess_b2b.2889766767
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/41.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.2175604878
Short name T743
Test name
Test status
Simulation time 1350416627 ps
CPU time 5.12 seconds
Started Sep 24 12:02:23 PM UTC 24
Finished Sep 24 12:02:29 PM UTC 24
Peak memory 212564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175604878 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.2175604878
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/41.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_regwen.3994706965
Short name T884
Test name
Test status
Simulation time 15287591734 ps
CPU time 1181.58 seconds
Started Sep 24 12:02:20 PM UTC 24
Finished Sep 24 12:22:15 PM UTC 24
Peak memory 389336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994706965 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.3994706965
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/41.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_smoke.3468484380
Short name T734
Test name
Test status
Simulation time 520132816 ps
CPU time 21.23 seconds
Started Sep 24 12:00:35 PM UTC 24
Finished Sep 24 12:00:57 PM UTC 24
Peak memory 212296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468484380 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.3468484380
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/41.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all.646477263
Short name T942
Test name
Test status
Simulation time 210608464497 ps
CPU time 4053.67 seconds
Started Sep 24 12:03:12 PM UTC 24
Finished Sep 24 01:11:36 PM UTC 24
Peak memory 388864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64647726
3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all.646477263
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/41.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.2142240080
Short name T751
Test name
Test status
Simulation time 683328907 ps
CPU time 27.07 seconds
Started Sep 24 12:03:00 PM UTC 24
Finished Sep 24 12:03:29 PM UTC 24
Peak memory 222668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142240080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.2142240080
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/41.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.2235854608
Short name T781
Test name
Test status
Simulation time 14974603074 ps
CPU time 415.76 seconds
Started Sep 24 12:00:51 PM UTC 24
Finished Sep 24 12:07:52 PM UTC 24
Peak memory 212584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235854608 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_pipeline.2235854608
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/41.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.533691712
Short name T747
Test name
Test status
Simulation time 958342536 ps
CPU time 91.39 seconds
Started Sep 24 12:01:38 PM UTC 24
Finished Sep 24 12:03:12 PM UTC 24
Peak memory 352436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=533691712 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_
throughput_w_partial_write.533691712
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/41.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.2342961102
Short name T786
Test name
Test status
Simulation time 6060487676 ps
CPU time 258.69 seconds
Started Sep 24 12:04:13 PM UTC 24
Finished Sep 24 12:08:35 PM UTC 24
Peak memory 375008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342961102 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_access_duri
ng_key_req.2342961102
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/42.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_alert_test.3872398499
Short name T766
Test name
Test status
Simulation time 22388911 ps
CPU time 0.91 seconds
Started Sep 24 12:05:15 PM UTC 24
Finished Sep 24 12:05:18 PM UTC 24
Peak memory 211352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872398499
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_alert_test.3872398499
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/42.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_bijection.3508557486
Short name T873
Test name
Test status
Simulation time 15384255783 ps
CPU time 994.22 seconds
Started Sep 24 12:03:20 PM UTC 24
Finished Sep 24 12:20:06 PM UTC 24
Peak memory 212608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3508557486 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection.3508557486
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/42.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_executable.3309456984
Short name T807
Test name
Test status
Simulation time 78816606518 ps
CPU time 418.87 seconds
Started Sep 24 12:04:16 PM UTC 24
Finished Sep 24 12:11:20 PM UTC 24
Peak memory 350440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309456984 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executable.3309456984
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/42.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.1634535524
Short name T770
Test name
Test status
Simulation time 26913352503 ps
CPU time 109.06 seconds
Started Sep 24 12:04:00 PM UTC 24
Finished Sep 24 12:05:51 PM UTC 24
Peak memory 226708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634535524 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_escalation.1634535524
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/42.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.2552890451
Short name T765
Test name
Test status
Simulation time 3400829092 ps
CPU time 84.48 seconds
Started Sep 24 12:03:48 PM UTC 24
Finished Sep 24 12:05:15 PM UTC 24
Peak memory 358752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2552890451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_
max_throughput.2552890451
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/42.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.3920097169
Short name T777
Test name
Test status
Simulation time 6372860045 ps
CPU time 158.67 seconds
Started Sep 24 12:04:43 PM UTC 24
Finished Sep 24 12:07:24 PM UTC 24
Peak memory 222640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920097169 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_mem_partial_access.3920097169
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/42.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.2010078850
Short name T817
Test name
Test status
Simulation time 24651365682 ps
CPU time 467.16 seconds
Started Sep 24 12:04:39 PM UTC 24
Finished Sep 24 12:12:33 PM UTC 24
Peak memory 222724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010078850 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_mem_walk.2010078850
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/42.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.1787860776
Short name T782
Test name
Test status
Simulation time 2591176459 ps
CPU time 279.72 seconds
Started Sep 24 12:03:17 PM UTC 24
Finished Sep 24 12:08:01 PM UTC 24
Peak memory 387560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787860776 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multiple_keys.1787860776
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/42.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access.3827522033
Short name T758
Test name
Test status
Simulation time 2981829503 ps
CPU time 29.02 seconds
Started Sep 24 12:03:45 PM UTC 24
Finished Sep 24 12:04:15 PM UTC 24
Peak memory 212064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827522033 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_partial_access.3827522033
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/42.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.3671796255
Short name T823
Test name
Test status
Simulation time 36480191371 ps
CPU time 552.99 seconds
Started Sep 24 12:03:45 PM UTC 24
Finished Sep 24 12:13:06 PM UTC 24
Peak memory 212476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671796255 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_partial_a
ccess_b2b.3671796255
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/42.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.3104703148
Short name T762
Test name
Test status
Simulation time 350404916 ps
CPU time 4.55 seconds
Started Sep 24 12:04:36 PM UTC 24
Finished Sep 24 12:04:41 PM UTC 24
Peak memory 212296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104703148 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.3104703148
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/42.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_regwen.2719032961
Short name T900
Test name
Test status
Simulation time 6528424512 ps
CPU time 1227.68 seconds
Started Sep 24 12:04:19 PM UTC 24
Finished Sep 24 12:25:00 PM UTC 24
Peak memory 387284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719032961 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.2719032961
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/42.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_smoke.4128952577
Short name T753
Test name
Test status
Simulation time 592274953 ps
CPU time 27.14 seconds
Started Sep 24 12:03:16 PM UTC 24
Finished Sep 24 12:03:44 PM UTC 24
Peak memory 212404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128952577 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.4128952577
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/42.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all.1428774799
Short name T948
Test name
Test status
Simulation time 303306092214 ps
CPU time 4926.22 seconds
Started Sep 24 12:05:05 PM UTC 24
Finished Sep 24 01:28:09 PM UTC 24
Peak memory 399024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14287747
99 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_a
ll.1428774799
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/42.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3525674513
Short name T767
Test name
Test status
Simulation time 1660809761 ps
CPU time 27.45 seconds
Started Sep 24 12:04:54 PM UTC 24
Finished Sep 24 12:05:23 PM UTC 24
Peak memory 222964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525674513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.3525674513
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/42.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.1066759854
Short name T787
Test name
Test status
Simulation time 18175942337 ps
CPU time 309.81 seconds
Started Sep 24 12:03:30 PM UTC 24
Finished Sep 24 12:08:44 PM UTC 24
Peak memory 212404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066759854 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_pipeline.1066759854
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/42.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.365799743
Short name T760
Test name
Test status
Simulation time 756913207 ps
CPU time 41.15 seconds
Started Sep 24 12:03:52 PM UTC 24
Finished Sep 24 12:04:35 PM UTC 24
Peak memory 313768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=365799743 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_
throughput_w_partial_write.365799743
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/42.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.616610145
Short name T908
Test name
Test status
Simulation time 90389690351 ps
CPU time 1268.21 seconds
Started Sep 24 12:06:48 PM UTC 24
Finished Sep 24 12:28:12 PM UTC 24
Peak memory 381340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616610145 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_access_durin
g_key_req.616610145
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/43.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_alert_test.2678733287
Short name T783
Test name
Test status
Simulation time 38351865 ps
CPU time 1.16 seconds
Started Sep 24 12:08:01 PM UTC 24
Finished Sep 24 12:08:04 PM UTC 24
Peak memory 210884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678733287
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_alert_test.2678733287
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/43.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_bijection.2609778468
Short name T902
Test name
Test status
Simulation time 660424315204 ps
CPU time 1193.47 seconds
Started Sep 24 12:05:40 PM UTC 24
Finished Sep 24 12:25:48 PM UTC 24
Peak memory 212468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609778468 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection.2609778468
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/43.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_executable.517172345
Short name T858
Test name
Test status
Simulation time 8966958572 ps
CPU time 661.96 seconds
Started Sep 24 12:07:02 PM UTC 24
Finished Sep 24 12:18:13 PM UTC 24
Peak memory 385308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517172345 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executable.517172345
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/43.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.1463217681
Short name T774
Test name
Test status
Simulation time 7147245179 ps
CPU time 11.59 seconds
Started Sep 24 12:06:34 PM UTC 24
Finished Sep 24 12:06:47 PM UTC 24
Peak memory 222868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463217681 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_escalation.1463217681
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/43.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.1445064451
Short name T773
Test name
Test status
Simulation time 2797069144 ps
CPU time 15.86 seconds
Started Sep 24 12:06:15 PM UTC 24
Finished Sep 24 12:06:32 PM UTC 24
Peak memory 264676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1445064451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_
max_throughput.1445064451
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/43.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.2657018471
Short name T798
Test name
Test status
Simulation time 10212196359 ps
CPU time 170.34 seconds
Started Sep 24 12:07:36 PM UTC 24
Finished Sep 24 12:10:30 PM UTC 24
Peak memory 222788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657018471 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_mem_partial_access.2657018471
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/43.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.3247549577
Short name T828
Test name
Test status
Simulation time 21012225112 ps
CPU time 364.83 seconds
Started Sep 24 12:07:33 PM UTC 24
Finished Sep 24 12:13:43 PM UTC 24
Peak memory 222884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247549577 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_mem_walk.3247549577
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/43.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.1805702439
Short name T794
Test name
Test status
Simulation time 14873818765 ps
CPU time 260.05 seconds
Started Sep 24 12:05:24 PM UTC 24
Finished Sep 24 12:09:48 PM UTC 24
Peak memory 385316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805702439 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multiple_keys.1805702439
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/43.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access.3176916524
Short name T771
Test name
Test status
Simulation time 1062975955 ps
CPU time 19.67 seconds
Started Sep 24 12:05:52 PM UTC 24
Finished Sep 24 12:06:13 PM UTC 24
Peak memory 212636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176916524 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_partial_access.3176916524
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/43.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.2662798787
Short name T803
Test name
Test status
Simulation time 11327299139 ps
CPU time 285 seconds
Started Sep 24 12:06:14 PM UTC 24
Finished Sep 24 12:11:03 PM UTC 24
Peak memory 212372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662798787 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_partial_a
ccess_b2b.2662798787
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/43.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.882828743
Short name T778
Test name
Test status
Simulation time 1461909004 ps
CPU time 6.12 seconds
Started Sep 24 12:07:25 PM UTC 24
Finished Sep 24 12:07:32 PM UTC 24
Peak memory 212372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882828743 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.882828743
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/43.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_regwen.545022085
Short name T818
Test name
Test status
Simulation time 4770332813 ps
CPU time 317.43 seconds
Started Sep 24 12:07:11 PM UTC 24
Finished Sep 24 12:12:34 PM UTC 24
Peak memory 379044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545022085 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.545022085
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/43.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_smoke.1403133175
Short name T776
Test name
Test status
Simulation time 1934220120 ps
CPU time 109.24 seconds
Started Sep 24 12:05:19 PM UTC 24
Finished Sep 24 12:07:10 PM UTC 24
Peak memory 377056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403133175 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.1403133175
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/43.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all.1611978802
Short name T924
Test name
Test status
Simulation time 111976541294 ps
CPU time 1625.01 seconds
Started Sep 24 12:07:53 PM UTC 24
Finished Sep 24 12:35:17 PM UTC 24
Peak memory 397696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16119788
02 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_a
ll.1611978802
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/43.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.315563652
Short name T784
Test name
Test status
Simulation time 556533309 ps
CPU time 20.71 seconds
Started Sep 24 12:07:44 PM UTC 24
Finished Sep 24 12:08:06 PM UTC 24
Peak memory 222992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315563652 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.315563652
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/43.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.1504972559
Short name T813
Test name
Test status
Simulation time 5726294263 ps
CPU time 375.03 seconds
Started Sep 24 12:05:40 PM UTC 24
Finished Sep 24 12:12:01 PM UTC 24
Peak memory 212476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504972559 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_pipeline.1504972559
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/43.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.492971975
Short name T785
Test name
Test status
Simulation time 2530608587 ps
CPU time 113.74 seconds
Started Sep 24 12:06:29 PM UTC 24
Finished Sep 24 12:08:26 PM UTC 24
Peak memory 383112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=492971975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_
throughput_w_partial_write.492971975
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/43.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.2713516444
Short name T901
Test name
Test status
Simulation time 8573698480 ps
CPU time 924.02 seconds
Started Sep 24 12:09:34 PM UTC 24
Finished Sep 24 12:25:10 PM UTC 24
Peak memory 389560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713516444 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_access_duri
ng_key_req.2713516444
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/44.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_alert_test.1124000595
Short name T802
Test name
Test status
Simulation time 31421952 ps
CPU time 0.92 seconds
Started Sep 24 12:10:56 PM UTC 24
Finished Sep 24 12:10:58 PM UTC 24
Peak memory 210884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124000595
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_alert_test.1124000595
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/44.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_bijection.583961362
Short name T934
Test name
Test status
Simulation time 165044092799 ps
CPU time 2610.45 seconds
Started Sep 24 12:08:27 PM UTC 24
Finished Sep 24 12:52:29 PM UTC 24
Peak memory 213960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583961362 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection.583961362
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/44.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_executable.4125416034
Short name T806
Test name
Test status
Simulation time 25890965057 ps
CPU time 80.07 seconds
Started Sep 24 12:09:45 PM UTC 24
Finished Sep 24 12:11:07 PM UTC 24
Peak memory 330212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125416034 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executable.4125416034
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/44.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.2756303667
Short name T795
Test name
Test status
Simulation time 21046933936 ps
CPU time 29.49 seconds
Started Sep 24 12:09:27 PM UTC 24
Finished Sep 24 12:09:58 PM UTC 24
Peak memory 212420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756303667 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_escalation.2756303667
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/44.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.1873823556
Short name T791
Test name
Test status
Simulation time 2790910036 ps
CPU time 8.56 seconds
Started Sep 24 12:09:17 PM UTC 24
Finished Sep 24 12:09:26 PM UTC 24
Peak memory 212092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1873823556 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_
max_throughput.1873823556
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/44.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.3005895856
Short name T814
Test name
Test status
Simulation time 2862829403 ps
CPU time 119.32 seconds
Started Sep 24 12:10:06 PM UTC 24
Finished Sep 24 12:12:08 PM UTC 24
Peak memory 229524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005895856 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_mem_partial_access.3005895856
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/44.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.1017151066
Short name T846
Test name
Test status
Simulation time 42217183256 ps
CPU time 353.52 seconds
Started Sep 24 12:09:59 PM UTC 24
Finished Sep 24 12:15:58 PM UTC 24
Peak memory 212684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017151066 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_mem_walk.1017151066
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/44.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.4216015592
Short name T870
Test name
Test status
Simulation time 26767941623 ps
CPU time 703.5 seconds
Started Sep 24 12:08:06 PM UTC 24
Finished Sep 24 12:19:58 PM UTC 24
Peak memory 389412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216015592 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multiple_keys.4216015592
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/44.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access.1256770702
Short name T789
Test name
Test status
Simulation time 2329040640 ps
CPU time 29.25 seconds
Started Sep 24 12:08:45 PM UTC 24
Finished Sep 24 12:09:16 PM UTC 24
Peak memory 212428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256770702 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_partial_access.1256770702
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/44.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.53569079
Short name T839
Test name
Test status
Simulation time 4154311890 ps
CPU time 351.76 seconds
Started Sep 24 12:09:05 PM UTC 24
Finished Sep 24 12:15:03 PM UTC 24
Peak memory 212732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53569079 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_partial_acc
ess_b2b.53569079
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/44.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.1191724954
Short name T797
Test name
Test status
Simulation time 350112258 ps
CPU time 4.11 seconds
Started Sep 24 12:09:59 PM UTC 24
Finished Sep 24 12:10:04 PM UTC 24
Peak memory 212628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191724954 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.1191724954
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/44.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_regwen.843423102
Short name T804
Test name
Test status
Simulation time 2039204825 ps
CPU time 74.1 seconds
Started Sep 24 12:09:49 PM UTC 24
Finished Sep 24 12:11:05 PM UTC 24
Peak memory 315592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843423102 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.843423102
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/44.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_smoke.1228803050
Short name T788
Test name
Test status
Simulation time 768918397 ps
CPU time 57.08 seconds
Started Sep 24 12:08:05 PM UTC 24
Finished Sep 24 12:09:04 PM UTC 24
Peak memory 332200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228803050 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.1228803050
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/44.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all.2649606912
Short name T940
Test name
Test status
Simulation time 443001689250 ps
CPU time 3142.96 seconds
Started Sep 24 12:10:44 PM UTC 24
Finished Sep 24 01:03:42 PM UTC 24
Peak memory 393056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26496069
12 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_a
ll.2649606912
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/44.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.607386169
Short name T801
Test name
Test status
Simulation time 952111734 ps
CPU time 24.42 seconds
Started Sep 24 12:10:31 PM UTC 24
Finished Sep 24 12:10:57 PM UTC 24
Peak memory 222928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607386169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.607386169
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/44.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.2390560174
Short name T833
Test name
Test status
Simulation time 15056170730 ps
CPU time 328.45 seconds
Started Sep 24 12:08:36 PM UTC 24
Finished Sep 24 12:14:09 PM UTC 24
Peak memory 212436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390560174 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_pipeline.2390560174
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/44.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.2976779130
Short name T792
Test name
Test status
Simulation time 802642455 ps
CPU time 14.1 seconds
Started Sep 24 12:09:18 PM UTC 24
Finished Sep 24 12:09:33 PM UTC 24
Peak memory 229532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2976779130 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl
_throughput_w_partial_write.2976779130
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/44.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.1267147622
Short name T921
Test name
Test status
Simulation time 63257188508 ps
CPU time 1288.5 seconds
Started Sep 24 12:11:39 PM UTC 24
Finished Sep 24 12:33:24 PM UTC 24
Peak memory 389340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267147622 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_access_duri
ng_key_req.1267147622
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/45.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_alert_test.2363268113
Short name T819
Test name
Test status
Simulation time 29412642 ps
CPU time 1.04 seconds
Started Sep 24 12:12:33 PM UTC 24
Finished Sep 24 12:12:36 PM UTC 24
Peak memory 210884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363268113
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_alert_test.2363268113
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/45.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_bijection.1950483574
Short name T915
Test name
Test status
Simulation time 56013405982 ps
CPU time 1109.92 seconds
Started Sep 24 12:11:04 PM UTC 24
Finished Sep 24 12:29:48 PM UTC 24
Peak memory 212492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950483574 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection.1950483574
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/45.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_executable.503836597
Short name T887
Test name
Test status
Simulation time 5061793817 ps
CPU time 628.25 seconds
Started Sep 24 12:11:55 PM UTC 24
Finished Sep 24 12:22:31 PM UTC 24
Peak memory 383240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503836597 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executable.503836597
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/45.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.3801255795
Short name T825
Test name
Test status
Simulation time 49273173050 ps
CPU time 105.48 seconds
Started Sep 24 12:11:38 PM UTC 24
Finished Sep 24 12:13:26 PM UTC 24
Peak memory 226752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801255795 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_escalation.3801255795
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/45.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.1804485405
Short name T811
Test name
Test status
Simulation time 3018789555 ps
CPU time 30.41 seconds
Started Sep 24 12:11:22 PM UTC 24
Finished Sep 24 12:11:53 PM UTC 24
Peak memory 311588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1804485405 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_
max_throughput.1804485405
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/45.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.906224338
Short name T826
Test name
Test status
Simulation time 5774160044 ps
CPU time 81.95 seconds
Started Sep 24 12:12:09 PM UTC 24
Finished Sep 24 12:13:33 PM UTC 24
Peak memory 222728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906224338 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_mem_partial_access.906224338
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/45.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.3594217974
Short name T862
Test name
Test status
Simulation time 86134358848 ps
CPU time 426.04 seconds
Started Sep 24 12:12:09 PM UTC 24
Finished Sep 24 12:19:20 PM UTC 24
Peak memory 212504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594217974 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_mem_walk.3594217974
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/45.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.2784570221
Short name T816
Test name
Test status
Simulation time 15480107431 ps
CPU time 72.99 seconds
Started Sep 24 12:10:59 PM UTC 24
Finished Sep 24 12:12:14 PM UTC 24
Peak memory 212576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784570221 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multiple_keys.2784570221
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/45.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access.3268206626
Short name T822
Test name
Test status
Simulation time 3999000645 ps
CPU time 115.12 seconds
Started Sep 24 12:11:07 PM UTC 24
Finished Sep 24 12:13:05 PM UTC 24
Peak memory 377304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268206626 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_partial_access.3268206626
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/45.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.2312407251
Short name T842
Test name
Test status
Simulation time 37390348464 ps
CPU time 256.08 seconds
Started Sep 24 12:11:07 PM UTC 24
Finished Sep 24 12:15:27 PM UTC 24
Peak memory 212408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312407251 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_partial_a
ccess_b2b.2312407251
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/45.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.1149999708
Short name T815
Test name
Test status
Simulation time 361134676 ps
CPU time 4.8 seconds
Started Sep 24 12:12:02 PM UTC 24
Finished Sep 24 12:12:08 PM UTC 24
Peak memory 212372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149999708 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.1149999708
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/45.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_regwen.1896482987
Short name T917
Test name
Test status
Simulation time 3256097830 ps
CPU time 1071.33 seconds
Started Sep 24 12:12:02 PM UTC 24
Finished Sep 24 12:30:06 PM UTC 24
Peak memory 387616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896482987 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.1896482987
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/45.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_smoke.1630830687
Short name T809
Test name
Test status
Simulation time 1091540837 ps
CPU time 38.34 seconds
Started Sep 24 12:10:58 PM UTC 24
Finished Sep 24 12:11:38 PM UTC 24
Peak memory 307324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630830687 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.1630830687
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/45.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all.2957955287
Short name T830
Test name
Test status
Simulation time 15645870475 ps
CPU time 94.67 seconds
Started Sep 24 12:12:27 PM UTC 24
Finished Sep 24 12:14:04 PM UTC 24
Peak memory 231620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29579552
87 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_a
ll.2957955287
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/45.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1779278837
Short name T124
Test name
Test status
Simulation time 455518512 ps
CPU time 9.18 seconds
Started Sep 24 12:12:15 PM UTC 24
Finished Sep 24 12:12:26 PM UTC 24
Peak memory 229596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779278837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.1779278837
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/45.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.1830103203
Short name T859
Test name
Test status
Simulation time 10186151393 ps
CPU time 447.8 seconds
Started Sep 24 12:11:06 PM UTC 24
Finished Sep 24 12:18:40 PM UTC 24
Peak memory 212396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830103203 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_pipeline.1830103203
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/45.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.88948192
Short name T812
Test name
Test status
Simulation time 2913358325 ps
CPU time 24.11 seconds
Started Sep 24 12:11:35 PM UTC 24
Finished Sep 24 12:12:00 PM UTC 24
Peak memory 262444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=88948192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_t
hroughput_w_partial_write.88948192
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/45.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.3985927874
Short name T868
Test name
Test status
Simulation time 6579484833 ps
CPU time 355.82 seconds
Started Sep 24 12:13:44 PM UTC 24
Finished Sep 24 12:19:45 PM UTC 24
Peak memory 383224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985927874 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_access_duri
ng_key_req.3985927874
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/46.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_alert_test.3030524104
Short name T836
Test name
Test status
Simulation time 14032249 ps
CPU time 0.97 seconds
Started Sep 24 12:14:19 PM UTC 24
Finished Sep 24 12:14:21 PM UTC 24
Peak memory 210884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030524104
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_alert_test.3030524104
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/46.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_bijection.475833848
Short name T920
Test name
Test status
Simulation time 105957940108 ps
CPU time 1216.7 seconds
Started Sep 24 12:12:38 PM UTC 24
Finished Sep 24 12:33:09 PM UTC 24
Peak memory 212336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475833848 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection.475833848
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/46.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_executable.3373407126
Short name T888
Test name
Test status
Simulation time 8737700440 ps
CPU time 545.37 seconds
Started Sep 24 12:13:44 PM UTC 24
Finished Sep 24 12:22:57 PM UTC 24
Peak memory 381224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373407126 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executable.3373407126
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/46.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.1741456472
Short name T840
Test name
Test status
Simulation time 36239855833 ps
CPU time 91.04 seconds
Started Sep 24 12:13:34 PM UTC 24
Finished Sep 24 12:15:07 PM UTC 24
Peak memory 227020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741456472 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_escalation.1741456472
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/46.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.542804988
Short name T829
Test name
Test status
Simulation time 753671339 ps
CPU time 31.97 seconds
Started Sep 24 12:13:27 PM UTC 24
Finished Sep 24 12:14:00 PM UTC 24
Peak memory 299172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
542804988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_m
ax_throughput.542804988
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/46.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.2364085211
Short name T851
Test name
Test status
Simulation time 16356003678 ps
CPU time 184.41 seconds
Started Sep 24 12:14:10 PM UTC 24
Finished Sep 24 12:17:17 PM UTC 24
Peak memory 222680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364085211 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_mem_partial_access.2364085211
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/46.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.149231287
Short name T869
Test name
Test status
Simulation time 81540388077 ps
CPU time 337.76 seconds
Started Sep 24 12:14:06 PM UTC 24
Finished Sep 24 12:19:49 PM UTC 24
Peak memory 222740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149231287 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_mem_walk.149231287
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/46.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.29826773
Short name T905
Test name
Test status
Simulation time 18369031796 ps
CPU time 832.74 seconds
Started Sep 24 12:12:37 PM UTC 24
Finished Sep 24 12:26:40 PM UTC 24
Peak memory 385312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29826773 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multiple_keys.29826773
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/46.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access.21492967
Short name T827
Test name
Test status
Simulation time 3309071887 ps
CPU time 35.28 seconds
Started Sep 24 12:13:06 PM UTC 24
Finished Sep 24 12:13:43 PM UTC 24
Peak memory 212360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21492967 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_partial_access.21492967
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/46.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.691601435
Short name T892
Test name
Test status
Simulation time 51250945347 ps
CPU time 604.96 seconds
Started Sep 24 12:13:07 PM UTC 24
Finished Sep 24 12:23:20 PM UTC 24
Peak memory 212620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691601435 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_partial_ac
cess_b2b.691601435
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/46.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.4002253490
Short name T834
Test name
Test status
Simulation time 741833819 ps
CPU time 3.71 seconds
Started Sep 24 12:14:05 PM UTC 24
Finished Sep 24 12:14:10 PM UTC 24
Peak memory 212292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002253490 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.4002253490
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/46.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_regwen.339740026
Short name T894
Test name
Test status
Simulation time 11362825078 ps
CPU time 584.56 seconds
Started Sep 24 12:14:01 PM UTC 24
Finished Sep 24 12:23:53 PM UTC 24
Peak memory 366788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339740026 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.339740026
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/46.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_smoke.1033518101
Short name T824
Test name
Test status
Simulation time 19842485305 ps
CPU time 49.28 seconds
Started Sep 24 12:12:34 PM UTC 24
Finished Sep 24 12:13:26 PM UTC 24
Peak memory 299152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033518101 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.1033518101
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/46.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all.4036424860
Short name T941
Test name
Test status
Simulation time 61095797190 ps
CPU time 3395.99 seconds
Started Sep 24 12:14:11 PM UTC 24
Finished Sep 24 01:11:26 PM UTC 24
Peak memory 390988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40364248
60 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_a
ll.4036424860
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/46.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3313956189
Short name T835
Test name
Test status
Simulation time 774530418 ps
CPU time 7.47 seconds
Started Sep 24 12:14:10 PM UTC 24
Finished Sep 24 12:14:18 PM UTC 24
Peak memory 222668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313956189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.3313956189
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/46.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.316829543
Short name T853
Test name
Test status
Simulation time 32005622631 ps
CPU time 279.36 seconds
Started Sep 24 12:12:45 PM UTC 24
Finished Sep 24 12:17:28 PM UTC 24
Peak memory 212568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316829543 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_pipeline.316829543
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/46.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.3103517396
Short name T837
Test name
Test status
Simulation time 1636349910 ps
CPU time 55.61 seconds
Started Sep 24 12:13:27 PM UTC 24
Finished Sep 24 12:14:24 PM UTC 24
Peak memory 319644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3103517396 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl
_throughput_w_partial_write.3103517396
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/46.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.2754994965
Short name T896
Test name
Test status
Simulation time 75831611655 ps
CPU time 504.24 seconds
Started Sep 24 12:15:56 PM UTC 24
Finished Sep 24 12:24:27 PM UTC 24
Peak memory 362720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754994965 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_access_duri
ng_key_req.2754994965
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/47.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_alert_test.2167954670
Short name T854
Test name
Test status
Simulation time 39438801 ps
CPU time 1.07 seconds
Started Sep 24 12:17:29 PM UTC 24
Finished Sep 24 12:17:32 PM UTC 24
Peak memory 211352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167954670
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_alert_test.2167954670
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/47.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_bijection.2330163440
Short name T935
Test name
Test status
Simulation time 99676615227 ps
CPU time 2360.43 seconds
Started Sep 24 12:14:54 PM UTC 24
Finished Sep 24 12:54:44 PM UTC 24
Peak memory 214068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330163440 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection.2330163440
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/47.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_executable.1322025866
Short name T906
Test name
Test status
Simulation time 37314810357 ps
CPU time 650.67 seconds
Started Sep 24 12:15:58 PM UTC 24
Finished Sep 24 12:26:57 PM UTC 24
Peak memory 383264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322025866 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executable.1322025866
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/47.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.3822403876
Short name T852
Test name
Test status
Simulation time 59875288158 ps
CPU time 92.31 seconds
Started Sep 24 12:15:45 PM UTC 24
Finished Sep 24 12:17:19 PM UTC 24
Peak memory 226752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822403876 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_escalation.3822403876
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/47.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.937939664
Short name T843
Test name
Test status
Simulation time 698489254 ps
CPU time 8.16 seconds
Started Sep 24 12:15:28 PM UTC 24
Finished Sep 24 12:15:38 PM UTC 24
Peak memory 222356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
937939664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_m
ax_throughput.937939664
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/47.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.2147765403
Short name T876
Test name
Test status
Simulation time 25843039319 ps
CPU time 219.12 seconds
Started Sep 24 12:16:53 PM UTC 24
Finished Sep 24 12:20:36 PM UTC 24
Peak memory 222596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147765403 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_mem_partial_access.2147765403
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/47.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.4006058217
Short name T864
Test name
Test status
Simulation time 23887194325 ps
CPU time 170.78 seconds
Started Sep 24 12:16:32 PM UTC 24
Finished Sep 24 12:19:26 PM UTC 24
Peak memory 222616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006058217 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_mem_walk.4006058217
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/47.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_multiple_keys.3312458945
Short name T925
Test name
Test status
Simulation time 52482003746 ps
CPU time 1240.02 seconds
Started Sep 24 12:14:26 PM UTC 24
Finished Sep 24 12:35:20 PM UTC 24
Peak memory 381164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312458945 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multiple_keys.3312458945
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/47.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access.4217177096
Short name T848
Test name
Test status
Simulation time 3354453144 ps
CPU time 74.12 seconds
Started Sep 24 12:15:08 PM UTC 24
Finished Sep 24 12:16:25 PM UTC 24
Peak memory 338208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217177096 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_partial_access.4217177096
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/47.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.3754744954
Short name T880
Test name
Test status
Simulation time 13502180898 ps
CPU time 344.25 seconds
Started Sep 24 12:15:12 PM UTC 24
Finished Sep 24 12:21:01 PM UTC 24
Peak memory 212372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754744954 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_partial_a
ccess_b2b.3754744954
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/47.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.147094315
Short name T849
Test name
Test status
Simulation time 668165413 ps
CPU time 4.48 seconds
Started Sep 24 12:16:26 PM UTC 24
Finished Sep 24 12:16:32 PM UTC 24
Peak memory 212296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147094315 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.147094315
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/47.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_regwen.3152387659
Short name T914
Test name
Test status
Simulation time 9155910945 ps
CPU time 775.25 seconds
Started Sep 24 12:16:13 PM UTC 24
Finished Sep 24 12:29:17 PM UTC 24
Peak memory 373108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152387659 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.3152387659
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/47.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_smoke.489172821
Short name T841
Test name
Test status
Simulation time 4436221627 ps
CPU time 45.84 seconds
Started Sep 24 12:14:22 PM UTC 24
Finished Sep 24 12:15:11 PM UTC 24
Peak memory 303592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489172821 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.489172821
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/47.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all.2867553957
Short name T947
Test name
Test status
Simulation time 61399246648 ps
CPU time 3913.81 seconds
Started Sep 24 12:17:20 PM UTC 24
Finished Sep 24 01:23:15 PM UTC 24
Peak memory 392872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28675539
57 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_a
ll.2867553957
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/47.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3063110757
Short name T144
Test name
Test status
Simulation time 4896218802 ps
CPU time 87.32 seconds
Started Sep 24 12:17:18 PM UTC 24
Finished Sep 24 12:18:47 PM UTC 24
Peak memory 224760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063110757 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.3063110757
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/47.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.3169744609
Short name T856
Test name
Test status
Simulation time 23395826356 ps
CPU time 151.72 seconds
Started Sep 24 12:15:04 PM UTC 24
Finished Sep 24 12:17:39 PM UTC 24
Peak memory 212444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169744609 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_pipeline.3169744609
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/47.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.2454219703
Short name T845
Test name
Test status
Simulation time 2812551995 ps
CPU time 15.03 seconds
Started Sep 24 12:15:39 PM UTC 24
Finished Sep 24 12:15:55 PM UTC 24
Peak memory 262604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2454219703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl
_throughput_w_partial_write.2454219703
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/47.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.2831829897
Short name T919
Test name
Test status
Simulation time 7735201504 ps
CPU time 783.05 seconds
Started Sep 24 12:19:22 PM UTC 24
Finished Sep 24 12:32:34 PM UTC 24
Peak memory 387272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831829897 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_access_duri
ng_key_req.2831829897
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/48.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_alert_test.631225283
Short name T871
Test name
Test status
Simulation time 73395340 ps
CPU time 1.12 seconds
Started Sep 24 12:19:59 PM UTC 24
Finished Sep 24 12:20:01 PM UTC 24
Peak memory 211472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631225283 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_alert_test.631225283
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/48.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_bijection.3498678597
Short name T923
Test name
Test status
Simulation time 14010869986 ps
CPU time 1038.89 seconds
Started Sep 24 12:17:40 PM UTC 24
Finished Sep 24 12:35:12 PM UTC 24
Peak memory 212492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498678597 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection.3498678597
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/48.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_executable.3408322160
Short name T931
Test name
Test status
Simulation time 29582110130 ps
CPU time 1226.48 seconds
Started Sep 24 12:19:27 PM UTC 24
Finished Sep 24 12:40:09 PM UTC 24
Peak memory 369100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408322160 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executable.3408322160
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/48.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.2533680248
Short name T872
Test name
Test status
Simulation time 5777411689 ps
CPU time 38.88 seconds
Started Sep 24 12:19:20 PM UTC 24
Finished Sep 24 12:20:01 PM UTC 24
Peak memory 222880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533680248 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_escalation.2533680248
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/48.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.2371766892
Short name T867
Test name
Test status
Simulation time 1448281621 ps
CPU time 49.15 seconds
Started Sep 24 12:18:48 PM UTC 24
Finished Sep 24 12:19:39 PM UTC 24
Peak memory 311428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2371766892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_
max_throughput.2371766892
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/48.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.140373898
Short name T886
Test name
Test status
Simulation time 21424278837 ps
CPU time 162.46 seconds
Started Sep 24 12:19:40 PM UTC 24
Finished Sep 24 12:22:25 PM UTC 24
Peak memory 222648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140373898 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_mem_partial_access.140373898
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/48.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.3463761855
Short name T893
Test name
Test status
Simulation time 25609148469 ps
CPU time 231.69 seconds
Started Sep 24 12:19:37 PM UTC 24
Finished Sep 24 12:23:32 PM UTC 24
Peak memory 212412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463761855 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_mem_walk.3463761855
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/48.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.2031022560
Short name T930
Test name
Test status
Simulation time 12006562416 ps
CPU time 1318.92 seconds
Started Sep 24 12:17:37 PM UTC 24
Finished Sep 24 12:39:51 PM UTC 24
Peak memory 389340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031022560 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multiple_keys.2031022560
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/48.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access.2019618941
Short name T863
Test name
Test status
Simulation time 996583497 ps
CPU time 69.67 seconds
Started Sep 24 12:18:14 PM UTC 24
Finished Sep 24 12:19:26 PM UTC 24
Peak memory 342216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019618941 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_partial_access.2019618941
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/48.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.703250739
Short name T895
Test name
Test status
Simulation time 4188559097 ps
CPU time 325.86 seconds
Started Sep 24 12:18:42 PM UTC 24
Finished Sep 24 12:24:12 PM UTC 24
Peak memory 212476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703250739 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_partial_ac
cess_b2b.703250739
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/48.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.2301279176
Short name T866
Test name
Test status
Simulation time 1353486521 ps
CPU time 6.15 seconds
Started Sep 24 12:19:28 PM UTC 24
Finished Sep 24 12:19:36 PM UTC 24
Peak memory 212436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301279176 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.2301279176
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/48.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_regwen.599968951
Short name T928
Test name
Test status
Simulation time 13825467929 ps
CPU time 995.91 seconds
Started Sep 24 12:19:27 PM UTC 24
Finished Sep 24 12:36:14 PM UTC 24
Peak memory 389548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599968951 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.599968951
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/48.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_smoke.3182065545
Short name T857
Test name
Test status
Simulation time 500783310 ps
CPU time 15.1 seconds
Started Sep 24 12:17:32 PM UTC 24
Finished Sep 24 12:17:49 PM UTC 24
Peak memory 212296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182065545 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.3182065545
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/48.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all.2303365872
Short name T945
Test name
Test status
Simulation time 126501956359 ps
CPU time 3488.98 seconds
Started Sep 24 12:19:49 PM UTC 24
Finished Sep 24 01:18:40 PM UTC 24
Peak memory 391008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23033658
72 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_a
ll.2303365872
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/48.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1768998495
Short name T874
Test name
Test status
Simulation time 788955333 ps
CPU time 26.59 seconds
Started Sep 24 12:19:46 PM UTC 24
Finished Sep 24 12:20:14 PM UTC 24
Peak memory 222708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768998495 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.1768998495
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/48.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.508740302
Short name T897
Test name
Test status
Simulation time 9846218198 ps
CPU time 406.57 seconds
Started Sep 24 12:17:50 PM UTC 24
Finished Sep 24 12:24:43 PM UTC 24
Peak memory 212344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508740302 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_pipeline.508740302
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/48.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.2020253040
Short name T861
Test name
Test status
Simulation time 3234069371 ps
CPU time 13.44 seconds
Started Sep 24 12:19:05 PM UTC 24
Finished Sep 24 12:19:20 PM UTC 24
Peak memory 229580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2020253040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl
_throughput_w_partial_write.2020253040
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/48.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.587228142
Short name T929
Test name
Test status
Simulation time 15630064705 ps
CPU time 949.25 seconds
Started Sep 24 12:21:03 PM UTC 24
Finished Sep 24 12:37:03 PM UTC 24
Peak memory 387336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587228142 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_access_durin
g_key_req.587228142
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/49.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_alert_test.3803571247
Short name T889
Test name
Test status
Simulation time 12701176 ps
CPU time 1.03 seconds
Started Sep 24 12:22:58 PM UTC 24
Finished Sep 24 12:23:00 PM UTC 24
Peak memory 211352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803571247
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_alert_test.3803571247
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/49.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_bijection.411687256
Short name T939
Test name
Test status
Simulation time 454210324112 ps
CPU time 2542.36 seconds
Started Sep 24 12:20:07 PM UTC 24
Finished Sep 24 01:03:02 PM UTC 24
Peak memory 214024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411687256 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection.411687256
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/49.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_executable.1219238327
Short name T922
Test name
Test status
Simulation time 6872502601 ps
CPU time 796.09 seconds
Started Sep 24 12:21:08 PM UTC 24
Finished Sep 24 12:34:34 PM UTC 24
Peak memory 387204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219238327 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executable.1219238327
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/49.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.3796810648
Short name T891
Test name
Test status
Simulation time 15311992146 ps
CPU time 132.36 seconds
Started Sep 24 12:20:59 PM UTC 24
Finished Sep 24 12:23:15 PM UTC 24
Peak memory 222624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796810648 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_escalation.3796810648
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/49.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.2471081936
Short name T883
Test name
Test status
Simulation time 776096998 ps
CPU time 87.72 seconds
Started Sep 24 12:20:41 PM UTC 24
Finished Sep 24 12:22:11 PM UTC 24
Peak memory 360600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2471081936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_
max_throughput.2471081936
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/49.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.3368944984
Short name T899
Test name
Test status
Simulation time 1639553026 ps
CPU time 154.4 seconds
Started Sep 24 12:22:21 PM UTC 24
Finished Sep 24 12:24:58 PM UTC 24
Peak memory 222572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368944984 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_mem_partial_access.3368944984
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/49.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.265392427
Short name T898
Test name
Test status
Simulation time 10962425052 ps
CPU time 149.02 seconds
Started Sep 24 12:22:16 PM UTC 24
Finished Sep 24 12:24:48 PM UTC 24
Peak memory 222700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265392427 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_mem_walk.265392427
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/49.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.1603964769
Short name T882
Test name
Test status
Simulation time 12080588652 ps
CPU time 102.55 seconds
Started Sep 24 12:20:02 PM UTC 24
Finished Sep 24 12:21:47 PM UTC 24
Peak memory 291032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603964769 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multiple_keys.1603964769
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/49.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access.89096255
Short name T878
Test name
Test status
Simulation time 847426789 ps
CPU time 11.76 seconds
Started Sep 24 12:20:34 PM UTC 24
Finished Sep 24 12:20:46 PM UTC 24
Peak memory 212596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89096255 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_partial_access.89096255
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/49.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.2589484583
Short name T910
Test name
Test status
Simulation time 21166796115 ps
CPU time 451.46 seconds
Started Sep 24 12:20:37 PM UTC 24
Finished Sep 24 12:28:16 PM UTC 24
Peak memory 212412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589484583 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_partial_a
ccess_b2b.2589484583
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/49.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.554450831
Short name T885
Test name
Test status
Simulation time 679609387 ps
CPU time 6.08 seconds
Started Sep 24 12:22:13 PM UTC 24
Finished Sep 24 12:22:20 PM UTC 24
Peak memory 212556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554450831 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.554450831
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/49.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_regwen.2659735365
Short name T926
Test name
Test status
Simulation time 88302134558 ps
CPU time 808.67 seconds
Started Sep 24 12:21:48 PM UTC 24
Finished Sep 24 12:35:26 PM UTC 24
Peak memory 389596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659735365 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.2659735365
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/49.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_smoke.3489228241
Short name T877
Test name
Test status
Simulation time 5740268623 ps
CPU time 36.76 seconds
Started Sep 24 12:20:02 PM UTC 24
Finished Sep 24 12:20:40 PM UTC 24
Peak memory 212352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489228241 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.3489228241
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/49.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all.2934907865
Short name T952
Test name
Test status
Simulation time 1309143348768 ps
CPU time 8259.2 seconds
Started Sep 24 12:22:32 PM UTC 24
Finished Sep 24 02:41:46 PM UTC 24
Peak memory 390936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29349078
65 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_a
ll.2934907865
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/49.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.947988624
Short name T890
Test name
Test status
Simulation time 2359421343 ps
CPU time 32.03 seconds
Started Sep 24 12:22:26 PM UTC 24
Finished Sep 24 12:23:00 PM UTC 24
Peak memory 222792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947988624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.947988624
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/49.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.2814439162
Short name T904
Test name
Test status
Simulation time 4848373620 ps
CPU time 360.8 seconds
Started Sep 24 12:20:15 PM UTC 24
Finished Sep 24 12:26:21 PM UTC 24
Peak memory 212352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814439162 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_pipeline.2814439162
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/49.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.1778227334
Short name T879
Test name
Test status
Simulation time 2795826044 ps
CPU time 10.37 seconds
Started Sep 24 12:20:47 PM UTC 24
Finished Sep 24 12:20:59 PM UTC 24
Peak memory 222584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1778227334 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl
_throughput_w_partial_write.1778227334
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/49.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.4009564866
Short name T238
Test name
Test status
Simulation time 30722364413 ps
CPU time 1243.85 seconds
Started Sep 24 09:55:31 AM UTC 24
Finished Sep 24 10:16:30 AM UTC 24
Peak memory 389384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009564866 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_access_durin
g_key_req.4009564866
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/5.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_alert_test.3830631735
Short name T169
Test name
Test status
Simulation time 15249135 ps
CPU time 1.11 seconds
Started Sep 24 09:56:30 AM UTC 24
Finished Sep 24 09:56:32 AM UTC 24
Peak memory 211416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830631735
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_alert_test.3830631735
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/5.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_bijection.2813351772
Short name T338
Test name
Test status
Simulation time 320767185325 ps
CPU time 2795.12 seconds
Started Sep 24 09:54:12 AM UTC 24
Finished Sep 24 10:41:20 AM UTC 24
Peak memory 213944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813351772 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.2813351772
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/5.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_executable.4243481895
Short name T146
Test name
Test status
Simulation time 23903153436 ps
CPU time 318.63 seconds
Started Sep 24 09:55:34 AM UTC 24
Finished Sep 24 10:00:58 AM UTC 24
Peak memory 381208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243481895 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executable.4243481895
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/5.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.1066704462
Short name T20
Test name
Test status
Simulation time 52335001170 ps
CPU time 147.91 seconds
Started Sep 24 09:55:04 AM UTC 24
Finished Sep 24 09:57:35 AM UTC 24
Peak memory 222652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066704462 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_escalation.1066704462
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/5.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.954505884
Short name T168
Test name
Test status
Simulation time 780048793 ps
CPU time 106.1 seconds
Started Sep 24 09:54:41 AM UTC 24
Finished Sep 24 09:56:29 AM UTC 24
Peak memory 370852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
954505884 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ma
x_throughput.954505884
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/5.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.2442081310
Short name T46
Test name
Test status
Simulation time 2525037285 ps
CPU time 151.19 seconds
Started Sep 24 09:55:49 AM UTC 24
Finished Sep 24 09:58:23 AM UTC 24
Peak memory 222648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442081310 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_mem_partial_access.2442081310
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/5.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.2086534722
Short name T186
Test name
Test status
Simulation time 21539135914 ps
CPU time 353.31 seconds
Started Sep 24 09:55:46 AM UTC 24
Finished Sep 24 10:01:44 AM UTC 24
Peak memory 222752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086534722 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_mem_walk.2086534722
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/5.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.2040035233
Short name T193
Test name
Test status
Simulation time 10524276967 ps
CPU time 578.8 seconds
Started Sep 24 09:54:09 AM UTC 24
Finished Sep 24 10:03:55 AM UTC 24
Peak memory 387548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040035233 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multiple_keys.2040035233
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/5.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access.283146558
Short name T165
Test name
Test status
Simulation time 4838319651 ps
CPU time 62.56 seconds
Started Sep 24 09:54:40 AM UTC 24
Finished Sep 24 09:55:44 AM UTC 24
Peak memory 336164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283146558 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_partial_access.283146558
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/5.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.1599689436
Short name T151
Test name
Test status
Simulation time 14098637858 ps
CPU time 417.54 seconds
Started Sep 24 09:54:40 AM UTC 24
Finished Sep 24 10:01:43 AM UTC 24
Peak memory 212424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599689436 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_partial_ac
cess_b2b.1599689436
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/5.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.665119758
Short name T167
Test name
Test status
Simulation time 346332365 ps
CPU time 5.44 seconds
Started Sep 24 09:55:45 AM UTC 24
Finished Sep 24 09:55:51 AM UTC 24
Peak memory 212284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665119758 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.665119758
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/5.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_smoke.1379277634
Short name T163
Test name
Test status
Simulation time 1333459585 ps
CPU time 32.25 seconds
Started Sep 24 09:54:05 AM UTC 24
Finished Sep 24 09:54:39 AM UTC 24
Peak memory 212404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379277634 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.1379277634
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/5.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all.421770282
Short name T482
Test name
Test status
Simulation time 305166182114 ps
CPU time 4384.22 seconds
Started Sep 24 09:56:03 AM UTC 24
Finished Sep 24 11:09:57 AM UTC 24
Peak memory 392980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42177028
2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all.421770282
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/5.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3282428852
Short name T62
Test name
Test status
Simulation time 501718900 ps
CPU time 9.63 seconds
Started Sep 24 09:55:52 AM UTC 24
Finished Sep 24 09:56:03 AM UTC 24
Peak memory 224720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282428852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.3282428852
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/5.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.869010301
Short name T174
Test name
Test status
Simulation time 14248535326 ps
CPU time 274.2 seconds
Started Sep 24 09:54:27 AM UTC 24
Finished Sep 24 09:59:05 AM UTC 24
Peak memory 212472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869010301 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_pipeline.869010301
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/5.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.194298344
Short name T166
Test name
Test status
Simulation time 1516441449 ps
CPU time 48.6 seconds
Started Sep 24 09:54:55 AM UTC 24
Finished Sep 24 09:55:45 AM UTC 24
Peak memory 342440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=194298344 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_t
hroughput_w_partial_write.194298344
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/5.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.4079549454
Short name T97
Test name
Test status
Simulation time 6381915082 ps
CPU time 302.34 seconds
Started Sep 24 09:58:50 AM UTC 24
Finished Sep 24 10:03:56 AM UTC 24
Peak memory 370904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079549454 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_access_durin
g_key_req.4079549454
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/6.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_alert_test.3924134922
Short name T180
Test name
Test status
Simulation time 14935635 ps
CPU time 1 seconds
Started Sep 24 10:00:00 AM UTC 24
Finished Sep 24 10:00:02 AM UTC 24
Peak memory 210884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924134922
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_alert_test.3924134922
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/6.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_bijection.204170871
Short name T271
Test name
Test status
Simulation time 45405056030 ps
CPU time 1704.49 seconds
Started Sep 24 09:56:45 AM UTC 24
Finished Sep 24 10:25:30 AM UTC 24
Peak memory 212336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204170871 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.204170871
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/6.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_executable.3453423895
Short name T152
Test name
Test status
Simulation time 14393928211 ps
CPU time 767.6 seconds
Started Sep 24 09:59:06 AM UTC 24
Finished Sep 24 10:12:03 AM UTC 24
Peak memory 389336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453423895 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executable.3453423895
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/6.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.3232884345
Short name T177
Test name
Test status
Simulation time 4643413776 ps
CPU time 42.77 seconds
Started Sep 24 09:58:39 AM UTC 24
Finished Sep 24 09:59:23 AM UTC 24
Peak memory 212428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232884345 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_escalation.3232884345
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/6.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.2317049588
Short name T175
Test name
Test status
Simulation time 1998776962 ps
CPU time 52.22 seconds
Started Sep 24 09:58:24 AM UTC 24
Finished Sep 24 09:59:18 AM UTC 24
Peak memory 338060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2317049588 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_m
ax_throughput.2317049588
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/6.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.1246099102
Short name T96
Test name
Test status
Simulation time 4387724617 ps
CPU time 187.28 seconds
Started Sep 24 09:59:33 AM UTC 24
Finished Sep 24 10:02:44 AM UTC 24
Peak memory 222988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246099102 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_mem_partial_access.1246099102
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/6.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.3849122760
Short name T189
Test name
Test status
Simulation time 27728358155 ps
CPU time 176.39 seconds
Started Sep 24 09:59:25 AM UTC 24
Finished Sep 24 10:02:24 AM UTC 24
Peak memory 222672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849122760 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_mem_walk.3849122760
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/6.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.2856776957
Short name T184
Test name
Test status
Simulation time 6002976729 ps
CPU time 300.93 seconds
Started Sep 24 09:56:33 AM UTC 24
Finished Sep 24 10:01:38 AM UTC 24
Peak memory 387264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856776957 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multiple_keys.2856776957
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/6.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access.884517082
Short name T171
Test name
Test status
Simulation time 3548744404 ps
CPU time 23.27 seconds
Started Sep 24 09:57:36 AM UTC 24
Finished Sep 24 09:58:00 AM UTC 24
Peak memory 212396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884517082 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_partial_access.884517082
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/6.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.2558113885
Short name T198
Test name
Test status
Simulation time 23238120783 ps
CPU time 383.31 seconds
Started Sep 24 09:58:01 AM UTC 24
Finished Sep 24 10:04:29 AM UTC 24
Peak memory 212420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558113885 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_partial_ac
cess_b2b.2558113885
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/6.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.854989693
Short name T178
Test name
Test status
Simulation time 3354386481 ps
CPU time 6.23 seconds
Started Sep 24 09:59:25 AM UTC 24
Finished Sep 24 09:59:32 AM UTC 24
Peak memory 212352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854989693 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.854989693
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/6.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_regwen.2028877032
Short name T219
Test name
Test status
Simulation time 3331032745 ps
CPU time 673.32 seconds
Started Sep 24 09:59:18 AM UTC 24
Finished Sep 24 10:10:41 AM UTC 24
Peak memory 389332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028877032 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.2028877032
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/6.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_smoke.4288298818
Short name T170
Test name
Test status
Simulation time 2793629381 ps
CPU time 12.71 seconds
Started Sep 24 09:56:30 AM UTC 24
Finished Sep 24 09:56:44 AM UTC 24
Peak memory 252008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288298818 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.4288298818
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/6.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all.432714595
Short name T527
Test name
Test status
Simulation time 250076734826 ps
CPU time 4709.5 seconds
Started Sep 24 09:59:51 AM UTC 24
Finished Sep 24 11:19:11 AM UTC 24
Peak memory 393060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43271459
5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all.432714595
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/6.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3289264517
Short name T63
Test name
Test status
Simulation time 797361401 ps
CPU time 13.63 seconds
Started Sep 24 09:59:45 AM UTC 24
Finished Sep 24 10:00:00 AM UTC 24
Peak memory 222612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289264517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.3289264517
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/6.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.2275240895
Short name T190
Test name
Test status
Simulation time 17931019747 ps
CPU time 316.58 seconds
Started Sep 24 09:57:14 AM UTC 24
Finished Sep 24 10:02:35 AM UTC 24
Peak memory 212416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275240895 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_pipeline.2275240895
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/6.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.747275976
Short name T181
Test name
Test status
Simulation time 3224438600 ps
CPU time 96.6 seconds
Started Sep 24 09:58:28 AM UTC 24
Finished Sep 24 10:00:07 AM UTC 24
Peak memory 372956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=747275976 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_t
hroughput_w_partial_write.747275976
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/6.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.1936357085
Short name T260
Test name
Test status
Simulation time 78371421488 ps
CPU time 1207.24 seconds
Started Sep 24 10:01:42 AM UTC 24
Finished Sep 24 10:22:03 AM UTC 24
Peak memory 387472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936357085 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_access_durin
g_key_req.1936357085
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/7.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_alert_test.3088026047
Short name T191
Test name
Test status
Simulation time 16785638 ps
CPU time 1.04 seconds
Started Sep 24 10:02:36 AM UTC 24
Finished Sep 24 10:02:38 AM UTC 24
Peak memory 211416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088026047
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_alert_test.3088026047
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/7.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_bijection.3783578192
Short name T256
Test name
Test status
Simulation time 171200917055 ps
CPU time 1187.3 seconds
Started Sep 24 10:00:29 AM UTC 24
Finished Sep 24 10:20:32 AM UTC 24
Peak memory 212380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783578192 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.3783578192
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/7.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_executable.3517072538
Short name T247
Test name
Test status
Simulation time 19990373581 ps
CPU time 975.7 seconds
Started Sep 24 10:01:44 AM UTC 24
Finished Sep 24 10:18:12 AM UTC 24
Peak memory 389388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517072538 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executable.3517072538
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/7.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.3864026853
Short name T194
Test name
Test status
Simulation time 49505776341 ps
CPU time 138.35 seconds
Started Sep 24 10:01:41 AM UTC 24
Finished Sep 24 10:04:02 AM UTC 24
Peak memory 212464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864026853 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_escalation.3864026853
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/7.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.4033560812
Short name T185
Test name
Test status
Simulation time 2853446220 ps
CPU time 14.67 seconds
Started Sep 24 10:01:25 AM UTC 24
Finished Sep 24 10:01:41 AM UTC 24
Peak memory 233696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
4033560812 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_m
ax_throughput.4033560812
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/7.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.726301071
Short name T201
Test name
Test status
Simulation time 6574708032 ps
CPU time 162.58 seconds
Started Sep 24 10:02:15 AM UTC 24
Finished Sep 24 10:05:01 AM UTC 24
Peak memory 222624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726301071 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_mem_partial_access.726301071
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/7.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.2956283182
Short name T209
Test name
Test status
Simulation time 28261055239 ps
CPU time 335.53 seconds
Started Sep 24 10:01:59 AM UTC 24
Finished Sep 24 10:07:40 AM UTC 24
Peak memory 222744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956283182 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_mem_walk.2956283182
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/7.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.1730094426
Short name T227
Test name
Test status
Simulation time 51741130544 ps
CPU time 701.83 seconds
Started Sep 24 10:00:07 AM UTC 24
Finished Sep 24 10:11:58 AM UTC 24
Peak memory 364808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730094426 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multiple_keys.1730094426
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/7.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access.2400944273
Short name T183
Test name
Test status
Simulation time 426290575 ps
CPU time 7.76 seconds
Started Sep 24 10:00:59 AM UTC 24
Finished Sep 24 10:01:07 AM UTC 24
Peak memory 212296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400944273 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_partial_access.2400944273
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/7.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.1116507879
Short name T207
Test name
Test status
Simulation time 21784396306 ps
CPU time 342.81 seconds
Started Sep 24 10:01:09 AM UTC 24
Finished Sep 24 10:06:56 AM UTC 24
Peak memory 212372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116507879 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_partial_ac
cess_b2b.1116507879
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/7.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.1323829515
Short name T187
Test name
Test status
Simulation time 348459090 ps
CPU time 5.4 seconds
Started Sep 24 10:01:52 AM UTC 24
Finished Sep 24 10:01:59 AM UTC 24
Peak memory 212380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323829515 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.1323829515
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/7.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_regwen.1124355696
Short name T148
Test name
Test status
Simulation time 16055671562 ps
CPU time 753.81 seconds
Started Sep 24 10:01:45 AM UTC 24
Finished Sep 24 10:14:27 AM UTC 24
Peak memory 385208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124355696 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.1124355696
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/7.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_smoke.75480758
Short name T182
Test name
Test status
Simulation time 3616669708 ps
CPU time 21.08 seconds
Started Sep 24 10:00:06 AM UTC 24
Finished Sep 24 10:00:28 AM UTC 24
Peak memory 252092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75480758 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.75480758
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/7.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all.3627525386
Short name T552
Test name
Test status
Simulation time 406466676938 ps
CPU time 4878.4 seconds
Started Sep 24 10:02:29 AM UTC 24
Finished Sep 24 11:24:49 AM UTC 24
Peak memory 292704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36275253
86 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all.3627525386
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/7.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1750083601
Short name T64
Test name
Test status
Simulation time 279387674 ps
CPU time 13.9 seconds
Started Sep 24 10:02:25 AM UTC 24
Finished Sep 24 10:02:40 AM UTC 24
Peak memory 222696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750083601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.1750083601
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/7.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.2421009010
Short name T197
Test name
Test status
Simulation time 12635152353 ps
CPU time 208.44 seconds
Started Sep 24 10:00:53 AM UTC 24
Finished Sep 24 10:04:25 AM UTC 24
Peak memory 212416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421009010 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_pipeline.2421009010
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/7.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.3393719497
Short name T188
Test name
Test status
Simulation time 729357928 ps
CPU time 32.89 seconds
Started Sep 24 10:01:39 AM UTC 24
Finished Sep 24 10:02:13 AM UTC 24
Peak memory 283052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3393719497 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_
throughput_w_partial_write.3393719497
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/7.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.1948748145
Short name T225
Test name
Test status
Simulation time 17572464668 ps
CPU time 430 seconds
Started Sep 24 10:04:18 AM UTC 24
Finished Sep 24 10:11:34 AM UTC 24
Peak memory 336164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948748145 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_access_durin
g_key_req.1948748145
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/8.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_alert_test.4264788754
Short name T203
Test name
Test status
Simulation time 14609240 ps
CPU time 1.02 seconds
Started Sep 24 10:05:36 AM UTC 24
Finished Sep 24 10:05:38 AM UTC 24
Peak memory 210884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264788754
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_alert_test.4264788754
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/8.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_bijection.352050749
Short name T387
Test name
Test status
Simulation time 165341532236 ps
CPU time 2729.01 seconds
Started Sep 24 10:02:44 AM UTC 24
Finished Sep 24 10:48:45 AM UTC 24
Peak memory 213884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352050749 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection.352050749
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/8.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_executable.919886503
Short name T243
Test name
Test status
Simulation time 21641813961 ps
CPU time 783.7 seconds
Started Sep 24 10:04:20 AM UTC 24
Finished Sep 24 10:17:35 AM UTC 24
Peak memory 387420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919886503 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executable.919886503
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/8.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.4102615146
Short name T154
Test name
Test status
Simulation time 24945394673 ps
CPU time 149.65 seconds
Started Sep 24 10:04:15 AM UTC 24
Finished Sep 24 10:06:48 AM UTC 24
Peak memory 212376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102615146 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_escalation.4102615146
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/8.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.4167204117
Short name T200
Test name
Test status
Simulation time 1436459520 ps
CPU time 41.04 seconds
Started Sep 24 10:04:03 AM UTC 24
Finished Sep 24 10:04:45 AM UTC 24
Peak memory 299436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
4167204117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_m
ax_throughput.4167204117
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/8.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.2856239821
Short name T53
Test name
Test status
Simulation time 13354577161 ps
CPU time 102.89 seconds
Started Sep 24 10:04:46 AM UTC 24
Finished Sep 24 10:06:32 AM UTC 24
Peak memory 222592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856239821 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_mem_partial_access.2856239821
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/8.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.1559846573
Short name T212
Test name
Test status
Simulation time 5058761385 ps
CPU time 195.05 seconds
Started Sep 24 10:04:38 AM UTC 24
Finished Sep 24 10:07:57 AM UTC 24
Peak memory 222620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559846573 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_mem_walk.1559846573
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/8.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.692811627
Short name T218
Test name
Test status
Simulation time 16646267485 ps
CPU time 443.23 seconds
Started Sep 24 10:02:41 AM UTC 24
Finished Sep 24 10:10:11 AM UTC 24
Peak memory 383464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692811627 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multiple_keys.692811627
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/8.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access.2718803569
Short name T196
Test name
Test status
Simulation time 1795966946 ps
CPU time 22.49 seconds
Started Sep 24 10:03:56 AM UTC 24
Finished Sep 24 10:04:20 AM UTC 24
Peak memory 212324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718803569 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_partial_access.2718803569
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/8.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.1436599140
Short name T205
Test name
Test status
Simulation time 5485622297 ps
CPU time 171.64 seconds
Started Sep 24 10:03:58 AM UTC 24
Finished Sep 24 10:06:52 AM UTC 24
Peak memory 212344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436599140 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_partial_ac
cess_b2b.1436599140
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/8.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.1882180676
Short name T199
Test name
Test status
Simulation time 678749350 ps
CPU time 6.31 seconds
Started Sep 24 10:04:30 AM UTC 24
Finished Sep 24 10:04:38 AM UTC 24
Peak memory 212292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882180676 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.1882180676
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/8.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_regwen.1977246674
Short name T16
Test name
Test status
Simulation time 49810482253 ps
CPU time 631.65 seconds
Started Sep 24 10:04:26 AM UTC 24
Finished Sep 24 10:15:06 AM UTC 24
Peak memory 377312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977246674 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.1977246674
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/8.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_smoke.240416201
Short name T192
Test name
Test status
Simulation time 1271696136 ps
CPU time 30.55 seconds
Started Sep 24 10:02:39 AM UTC 24
Finished Sep 24 10:03:11 AM UTC 24
Peak memory 212328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240416201 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.240416201
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/8.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all.2212288263
Short name T404
Test name
Test status
Simulation time 50710594583 ps
CPU time 2883.9 seconds
Started Sep 24 10:05:04 AM UTC 24
Finished Sep 24 10:53:37 AM UTC 24
Peak memory 388860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22122882
63 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all.2212288263
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/8.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2643440331
Short name T65
Test name
Test status
Simulation time 2333199026 ps
CPU time 31.83 seconds
Started Sep 24 10:05:02 AM UTC 24
Finished Sep 24 10:05:35 AM UTC 24
Peak memory 229792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643440331 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.2643440331
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/8.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.2155874739
Short name T211
Test name
Test status
Simulation time 13669400525 ps
CPU time 276.48 seconds
Started Sep 24 10:03:12 AM UTC 24
Finished Sep 24 10:07:53 AM UTC 24
Peak memory 212364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155874739 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_pipeline.2155874739
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/8.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.4208907126
Short name T202
Test name
Test status
Simulation time 2953022008 ps
CPU time 57.36 seconds
Started Sep 24 10:04:04 AM UTC 24
Finished Sep 24 10:05:03 AM UTC 24
Peak memory 307476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=4208907126 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_
throughput_w_partial_write.4208907126
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/8.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.3160293106
Short name T220
Test name
Test status
Simulation time 4739569942 ps
CPU time 190.67 seconds
Started Sep 24 10:07:38 AM UTC 24
Finished Sep 24 10:10:52 AM UTC 24
Peak memory 379092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160293106 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_access_durin
g_key_req.3160293106
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/9.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_alert_test.1474196335
Short name T215
Test name
Test status
Simulation time 18381137 ps
CPU time 1.13 seconds
Started Sep 24 10:09:32 AM UTC 24
Finished Sep 24 10:09:34 AM UTC 24
Peak memory 211416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474196335
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_alert_test.1474196335
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/9.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_bijection.2051974542
Short name T391
Test name
Test status
Simulation time 137946226890 ps
CPU time 2600.23 seconds
Started Sep 24 10:06:07 AM UTC 24
Finished Sep 24 10:49:58 AM UTC 24
Peak memory 213888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051974542 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.2051974542
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/9.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_executable.4237284243
Short name T252
Test name
Test status
Simulation time 6059856990 ps
CPU time 687.18 seconds
Started Sep 24 10:07:40 AM UTC 24
Finished Sep 24 10:19:16 AM UTC 24
Peak memory 387304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237284243 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executable.4237284243
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/9.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.897928176
Short name T216
Test name
Test status
Simulation time 13240354605 ps
CPU time 143.21 seconds
Started Sep 24 10:07:20 AM UTC 24
Finished Sep 24 10:09:46 AM UTC 24
Peak memory 226704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897928176 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_escalation.897928176
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/9.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.3773879019
Short name T208
Test name
Test status
Simulation time 2937123834 ps
CPU time 20.89 seconds
Started Sep 24 10:06:57 AM UTC 24
Finished Sep 24 10:07:19 AM UTC 24
Peak memory 270612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3773879019 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_m
ax_throughput.3773879019
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/9.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.4120384340
Short name T214
Test name
Test status
Simulation time 9850478717 ps
CPU time 88.3 seconds
Started Sep 24 10:08:00 AM UTC 24
Finished Sep 24 10:09:31 AM UTC 24
Peak memory 229816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120384340 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_mem_partial_access.4120384340
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/9.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.2598677375
Short name T224
Test name
Test status
Simulation time 6916830447 ps
CPU time 210.68 seconds
Started Sep 24 10:07:57 AM UTC 24
Finished Sep 24 10:11:32 AM UTC 24
Peak memory 222740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598677375 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_mem_walk.2598677375
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/9.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.3576163171
Short name T234
Test name
Test status
Simulation time 70551980809 ps
CPU time 565.89 seconds
Started Sep 24 10:05:53 AM UTC 24
Finished Sep 24 10:15:26 AM UTC 24
Peak memory 389600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576163171 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multiple_keys.3576163171
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/9.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access.1792517887
Short name T206
Test name
Test status
Simulation time 372455812 ps
CPU time 5.92 seconds
Started Sep 24 10:06:48 AM UTC 24
Finished Sep 24 10:06:55 AM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792517887 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_partial_access.1792517887
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/9.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.291025789
Short name T230
Test name
Test status
Simulation time 13388754496 ps
CPU time 403.82 seconds
Started Sep 24 10:06:54 AM UTC 24
Finished Sep 24 10:13:43 AM UTC 24
Peak memory 212476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291025789 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_partial_acc
ess_b2b.291025789
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/9.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.720667393
Short name T213
Test name
Test status
Simulation time 1342071052 ps
CPU time 4.29 seconds
Started Sep 24 10:07:54 AM UTC 24
Finished Sep 24 10:08:00 AM UTC 24
Peak memory 212556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720667393 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.720667393
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/9.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_regwen.12002077
Short name T245
Test name
Test status
Simulation time 3628449187 ps
CPU time 604.64 seconds
Started Sep 24 10:07:45 AM UTC 24
Finished Sep 24 10:17:58 AM UTC 24
Peak memory 383268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12002077 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.12002077
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/9.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_smoke.24558827
Short name T204
Test name
Test status
Simulation time 1630090643 ps
CPU time 12.53 seconds
Started Sep 24 10:05:39 AM UTC 24
Finished Sep 24 10:05:53 AM UTC 24
Peak memory 212328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24558827 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.24558827
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/9.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all.993877009
Short name T430
Test name
Test status
Simulation time 101456152647 ps
CPU time 3024.15 seconds
Started Sep 24 10:08:28 AM UTC 24
Finished Sep 24 10:59:24 AM UTC 24
Peak memory 390928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99387700
9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all.993877009
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/9.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.718385332
Short name T66
Test name
Test status
Simulation time 736095043 ps
CPU time 6.16 seconds
Started Sep 24 10:08:19 AM UTC 24
Finished Sep 24 10:08:27 AM UTC 24
Peak memory 222908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718385332 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.718385332
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/9.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.2224863135
Short name T236
Test name
Test status
Simulation time 6732504132 ps
CPU time 553.55 seconds
Started Sep 24 10:06:32 AM UTC 24
Finished Sep 24 10:15:53 AM UTC 24
Peak memory 212392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224863135 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_pipeline.2224863135
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/9.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.3594493935
Short name T210
Test name
Test status
Simulation time 3833779907 ps
CPU time 45.95 seconds
Started Sep 24 10:06:57 AM UTC 24
Finished Sep 24 10:07:44 AM UTC 24
Peak memory 301248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3594493935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_
throughput_w_partial_write.3594493935
Directory /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_main-sim-vcs/9.sram_ctrl_throughput_w_partial_write/latest
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