| T310 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_smoke.1010149526 |
|
|
Oct 02 11:44:47 PM UTC 24 |
Oct 02 11:45:05 PM UTC 24 |
916850734 ps |
| T311 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.1433679201 |
|
|
Oct 02 11:43:31 PM UTC 24 |
Oct 02 11:45:41 PM UTC 24 |
13753424157 ps |
| T312 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.687422536 |
|
|
Oct 02 11:42:07 PM UTC 24 |
Oct 02 11:45:43 PM UTC 24 |
8142798012 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.1404735117 |
|
|
Oct 02 11:38:42 PM UTC 24 |
Oct 02 11:46:09 PM UTC 24 |
181961214976 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.2653333140 |
|
|
Oct 02 11:38:38 PM UTC 24 |
Oct 02 11:46:34 PM UTC 24 |
11725660128 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access.143162453 |
|
|
Oct 02 11:46:10 PM UTC 24 |
Oct 02 11:46:42 PM UTC 24 |
4401696774 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.3312956257 |
|
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Oct 02 11:42:46 PM UTC 24 |
Oct 02 11:46:45 PM UTC 24 |
2872065374 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.1943332205 |
|
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Oct 02 11:44:42 PM UTC 24 |
Oct 02 11:46:52 PM UTC 24 |
5580151713 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.1180727226 |
|
|
Oct 02 11:40:52 PM UTC 24 |
Oct 02 11:46:55 PM UTC 24 |
4529766415 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.4146517672 |
|
|
Oct 02 11:39:14 PM UTC 24 |
Oct 02 11:47:03 PM UTC 24 |
23100820556 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all.2054740825 |
|
|
Oct 02 11:27:24 PM UTC 24 |
Oct 02 11:47:08 PM UTC 24 |
40979807843 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.4251404254 |
|
|
Oct 02 11:46:53 PM UTC 24 |
Oct 02 11:47:09 PM UTC 24 |
1773468962 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.1155775190 |
|
|
Oct 02 11:47:10 PM UTC 24 |
Oct 02 11:47:16 PM UTC 24 |
362421781 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.254228210 |
|
|
Oct 02 11:42:03 PM UTC 24 |
Oct 02 11:47:21 PM UTC 24 |
21001690366 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.4104191668 |
|
|
Oct 02 11:44:15 PM UTC 24 |
Oct 02 11:47:29 PM UTC 24 |
11437286165 ps |
| T45 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.2819782140 |
|
|
Oct 02 11:44:42 PM UTC 24 |
Oct 02 11:47:35 PM UTC 24 |
11567673665 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.142903777 |
|
|
Oct 02 11:38:27 PM UTC 24 |
Oct 02 11:47:38 PM UTC 24 |
24242680906 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.1109216475 |
|
|
Oct 02 11:40:56 PM UTC 24 |
Oct 02 11:47:38 PM UTC 24 |
64818371507 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_alert_test.2631757582 |
|
|
Oct 02 11:47:39 PM UTC 24 |
Oct 02 11:47:41 PM UTC 24 |
20422933 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.2475291766 |
|
|
Oct 02 11:46:43 PM UTC 24 |
Oct 02 11:47:44 PM UTC 24 |
5650795431 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.2045157075 |
|
|
Oct 02 11:47:30 PM UTC 24 |
Oct 02 11:47:57 PM UTC 24 |
401015426 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_smoke.1174263810 |
|
|
Oct 02 11:47:39 PM UTC 24 |
Oct 02 11:47:57 PM UTC 24 |
471496099 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.2640801780 |
|
|
Oct 02 11:37:01 PM UTC 24 |
Oct 02 11:48:06 PM UTC 24 |
12321891717 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_executable.2589641912 |
|
|
Oct 02 11:37:03 PM UTC 24 |
Oct 02 11:48:14 PM UTC 24 |
11885303477 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.1053684728 |
|
|
Oct 02 11:46:46 PM UTC 24 |
Oct 02 11:48:15 PM UTC 24 |
1071079980 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access.2693418065 |
|
|
Oct 02 11:47:59 PM UTC 24 |
Oct 02 11:48:22 PM UTC 24 |
3503591798 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.2256868461 |
|
|
Oct 02 11:48:23 PM UTC 24 |
Oct 02 11:48:32 PM UTC 24 |
742603519 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.4022910197 |
|
|
Oct 02 11:48:15 PM UTC 24 |
Oct 02 11:48:56 PM UTC 24 |
755403910 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.3255945089 |
|
|
Oct 02 11:48:16 PM UTC 24 |
Oct 02 11:49:54 PM UTC 24 |
3210201351 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_bijection.2330016662 |
|
|
Oct 02 11:21:58 PM UTC 24 |
Oct 02 11:50:10 PM UTC 24 |
52041503550 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.2784990077 |
|
|
Oct 02 11:50:11 PM UTC 24 |
Oct 02 11:50:17 PM UTC 24 |
354621958 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.519855399 |
|
|
Oct 02 11:47:22 PM UTC 24 |
Oct 02 11:50:25 PM UTC 24 |
7170665585 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.2482324675 |
|
|
Oct 02 11:47:58 PM UTC 24 |
Oct 02 11:50:44 PM UTC 24 |
9201090856 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.2550874518 |
|
|
Oct 02 11:42:55 PM UTC 24 |
Oct 02 11:50:48 PM UTC 24 |
6407615070 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.296634308 |
|
|
Oct 02 11:45:43 PM UTC 24 |
Oct 02 11:50:49 PM UTC 24 |
13892431081 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_alert_test.62587790 |
|
|
Oct 02 11:50:50 PM UTC 24 |
Oct 02 11:50:52 PM UTC 24 |
14094359 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.401950817 |
|
|
Oct 02 11:42:40 PM UTC 24 |
Oct 02 11:51:15 PM UTC 24 |
15326640407 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_executable.1742798662 |
|
|
Oct 02 11:34:26 PM UTC 24 |
Oct 02 11:51:21 PM UTC 24 |
71953907691 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_regwen.2093457881 |
|
|
Oct 02 11:30:35 PM UTC 24 |
Oct 02 11:51:21 PM UTC 24 |
54912061276 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_smoke.2766335263 |
|
|
Oct 02 11:50:53 PM UTC 24 |
Oct 02 11:51:30 PM UTC 24 |
2178172189 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_executable.43948924 |
|
|
Oct 02 11:39:17 PM UTC 24 |
Oct 02 11:51:39 PM UTC 24 |
23744520048 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access.2853251601 |
|
|
Oct 02 11:51:31 PM UTC 24 |
Oct 02 11:51:45 PM UTC 24 |
1880064692 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.3686351086 |
|
|
Oct 02 11:50:45 PM UTC 24 |
Oct 02 11:52:02 PM UTC 24 |
6411450511 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.2475752661 |
|
|
Oct 02 11:51:46 PM UTC 24 |
Oct 02 11:52:05 PM UTC 24 |
1880113466 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_bijection.1811690797 |
|
|
Oct 02 11:20:21 PM UTC 24 |
Oct 02 11:52:16 PM UTC 24 |
27106967381 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_executable.2328925842 |
|
|
Oct 02 11:26:40 PM UTC 24 |
Oct 02 11:52:33 PM UTC 24 |
131706025557 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_regwen.2008546324 |
|
|
Oct 02 11:39:20 PM UTC 24 |
Oct 02 11:52:38 PM UTC 24 |
36336443655 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.1199790051 |
|
|
Oct 02 11:47:18 PM UTC 24 |
Oct 02 11:52:53 PM UTC 24 |
21877005457 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.3705295916 |
|
|
Oct 02 11:52:54 PM UTC 24 |
Oct 02 11:53:01 PM UTC 24 |
1410918299 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.3600250946 |
|
|
Oct 02 11:50:26 PM UTC 24 |
Oct 02 11:53:15 PM UTC 24 |
23161116249 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.2906785843 |
|
|
Oct 02 11:52:03 PM UTC 24 |
Oct 02 11:53:24 PM UTC 24 |
811434879 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.3467352709 |
|
|
Oct 02 11:50:17 PM UTC 24 |
Oct 02 11:53:27 PM UTC 24 |
10189971479 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.631708679 |
|
|
Oct 02 11:40:43 PM UTC 24 |
Oct 02 11:54:02 PM UTC 24 |
14675762776 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_alert_test.2231795071 |
|
|
Oct 02 11:54:03 PM UTC 24 |
Oct 02 11:54:06 PM UTC 24 |
41458429 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_smoke.627396352 |
|
|
Oct 02 11:54:06 PM UTC 24 |
Oct 02 11:54:19 PM UTC 24 |
2695667520 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_bijection.646736546 |
|
|
Oct 02 11:19:05 PM UTC 24 |
Oct 02 11:54:10 PM UTC 24 |
110994248755 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.1322487128 |
|
|
Oct 02 11:52:06 PM UTC 24 |
Oct 02 11:54:14 PM UTC 24 |
97559707658 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_bijection.2748544759 |
|
|
Oct 02 11:29:48 PM UTC 24 |
Oct 02 11:54:22 PM UTC 24 |
80007639591 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access.879883558 |
|
|
Oct 02 11:54:23 PM UTC 24 |
Oct 02 11:54:36 PM UTC 24 |
3225793962 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all.1208195343 |
|
|
Oct 02 11:32:49 PM UTC 24 |
Oct 02 11:55:17 PM UTC 24 |
32194681624 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_regwen.2172705635 |
|
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Oct 02 11:44:03 PM UTC 24 |
Oct 02 11:55:21 PM UTC 24 |
23837673697 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_executable.2027797839 |
|
|
Oct 02 11:41:55 PM UTC 24 |
Oct 02 11:55:22 PM UTC 24 |
55877358895 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.2548965598 |
|
|
Oct 02 11:53:25 PM UTC 24 |
Oct 02 11:55:34 PM UTC 24 |
1084802679 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.918002255 |
|
|
Oct 02 11:53:02 PM UTC 24 |
Oct 02 11:55:49 PM UTC 24 |
7209126536 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_bijection.3081419647 |
|
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Oct 02 11:40:48 PM UTC 24 |
Oct 02 11:55:51 PM UTC 24 |
45121337771 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.3431293875 |
|
|
Oct 02 11:55:22 PM UTC 24 |
Oct 02 11:55:52 PM UTC 24 |
2950697431 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_executable.2458497315 |
|
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Oct 02 11:47:04 PM UTC 24 |
Oct 02 11:55:54 PM UTC 24 |
23174830494 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.902169858 |
|
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Oct 02 11:55:53 PM UTC 24 |
Oct 02 11:55:59 PM UTC 24 |
1206371810 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.3905085197 |
|
|
Oct 02 11:55:23 PM UTC 24 |
Oct 02 11:56:16 PM UTC 24 |
18964845077 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_bijection.1157061040 |
|
|
Oct 02 11:26:06 PM UTC 24 |
Oct 02 11:56:17 PM UTC 24 |
111567577705 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_alert_test.3467111462 |
|
|
Oct 02 11:56:17 PM UTC 24 |
Oct 02 11:56:19 PM UTC 24 |
33370538 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.374484315 |
|
|
Oct 02 11:55:18 PM UTC 24 |
Oct 02 11:56:21 PM UTC 24 |
1531255630 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_regwen.1390163341 |
|
|
Oct 02 11:37:10 PM UTC 24 |
Oct 02 11:56:33 PM UTC 24 |
16750838324 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_smoke.108801939 |
|
|
Oct 02 11:56:18 PM UTC 24 |
Oct 02 11:56:44 PM UTC 24 |
863456222 ps |
| T88 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.863181335 |
|
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Oct 02 11:53:16 PM UTC 24 |
Oct 02 11:56:50 PM UTC 24 |
10446583198 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access.34528261 |
|
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Oct 02 11:56:45 PM UTC 24 |
Oct 02 11:56:55 PM UTC 24 |
1389275531 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.4044653689 |
|
|
Oct 02 11:56:00 PM UTC 24 |
Oct 02 11:57:00 PM UTC 24 |
1073819411 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.4023494794 |
|
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Oct 02 11:47:42 PM UTC 24 |
Oct 02 11:57:01 PM UTC 24 |
4806319983 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.730420141 |
|
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Oct 02 11:51:41 PM UTC 24 |
Oct 02 11:57:12 PM UTC 24 |
27040740241 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.676830323 |
|
|
Oct 02 11:48:07 PM UTC 24 |
Oct 02 11:57:21 PM UTC 24 |
21792431076 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.2987369476 |
|
|
Oct 02 11:43:40 PM UTC 24 |
Oct 02 11:57:23 PM UTC 24 |
17247913422 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.3492680161 |
|
|
Oct 02 11:56:56 PM UTC 24 |
Oct 02 11:57:25 PM UTC 24 |
721530514 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_executable.3152709632 |
|
|
Oct 02 11:52:34 PM UTC 24 |
Oct 02 11:57:30 PM UTC 24 |
14364518192 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.3811447435 |
|
|
Oct 02 11:57:26 PM UTC 24 |
Oct 02 11:57:32 PM UTC 24 |
2801915132 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.2040258189 |
|
|
Oct 02 11:55:57 PM UTC 24 |
Oct 02 11:57:35 PM UTC 24 |
2443356967 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.861655572 |
|
|
Oct 02 11:51:22 PM UTC 24 |
Oct 02 11:57:40 PM UTC 24 |
8845826024 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.211797712 |
|
|
Oct 02 11:57:01 PM UTC 24 |
Oct 02 11:57:45 PM UTC 24 |
5330905671 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.4094789752 |
|
|
Oct 02 11:57:36 PM UTC 24 |
Oct 02 11:57:47 PM UTC 24 |
914751514 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_alert_test.2638608306 |
|
|
Oct 02 11:57:46 PM UTC 24 |
Oct 02 11:57:48 PM UTC 24 |
21921624 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.3379408500 |
|
|
Oct 02 11:57:00 PM UTC 24 |
Oct 02 11:57:55 PM UTC 24 |
872425343 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_executable.3194193510 |
|
|
Oct 02 11:30:33 PM UTC 24 |
Oct 02 11:58:04 PM UTC 24 |
122195772306 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.1866002610 |
|
|
Oct 02 11:46:36 PM UTC 24 |
Oct 02 11:58:16 PM UTC 24 |
84524976101 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.521408855 |
|
|
Oct 02 11:54:20 PM UTC 24 |
Oct 02 11:58:26 PM UTC 24 |
3826106699 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access.3474685893 |
|
|
Oct 02 11:58:17 PM UTC 24 |
Oct 02 11:58:26 PM UTC 24 |
1159013475 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_smoke.2653739286 |
|
|
Oct 02 11:57:48 PM UTC 24 |
Oct 02 11:58:47 PM UTC 24 |
2943158637 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_executable.4276443458 |
|
|
Oct 02 11:43:46 PM UTC 24 |
Oct 02 11:58:54 PM UTC 24 |
27247391578 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_bijection.3206024852 |
|
|
Oct 02 11:35:32 PM UTC 24 |
Oct 02 11:58:54 PM UTC 24 |
40630282557 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.410582706 |
|
|
Oct 02 11:57:33 PM UTC 24 |
Oct 02 11:58:57 PM UTC 24 |
1010400665 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all.1591597905 |
|
|
Oct 02 11:29:38 PM UTC 24 |
Oct 02 11:59:13 PM UTC 24 |
102239141019 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.4119852239 |
|
|
Oct 02 11:58:27 PM UTC 24 |
Oct 02 11:59:19 PM UTC 24 |
1544386357 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.1336897112 |
|
|
Oct 02 11:59:20 PM UTC 24 |
Oct 02 11:59:26 PM UTC 24 |
1401437165 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.3647952516 |
|
|
Oct 02 11:58:48 PM UTC 24 |
Oct 02 11:59:41 PM UTC 24 |
1493262708 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.2089606333 |
|
|
Oct 02 11:56:20 PM UTC 24 |
Oct 02 11:59:45 PM UTC 24 |
8164779695 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.155333728 |
|
|
Oct 02 11:57:31 PM UTC 24 |
Oct 03 12:00:05 AM UTC 24 |
6750515742 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.2798795176 |
|
|
Oct 02 11:55:56 PM UTC 24 |
Oct 03 12:00:12 AM UTC 24 |
43121800607 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.3108461125 |
|
|
Oct 02 11:58:55 PM UTC 24 |
Oct 03 12:00:14 AM UTC 24 |
65378423931 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_alert_test.142008410 |
|
|
Oct 03 12:00:13 AM UTC 24 |
Oct 03 12:00:16 AM UTC 24 |
34479209 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_regwen.2631730018 |
|
|
Oct 02 11:57:23 PM UTC 24 |
Oct 03 12:00:21 AM UTC 24 |
1248688627 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_smoke.2502111893 |
|
|
Oct 03 12:00:14 AM UTC 24 |
Oct 03 12:00:42 AM UTC 24 |
1041911854 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.3997531238 |
|
|
Oct 02 11:59:46 PM UTC 24 |
Oct 03 12:00:46 AM UTC 24 |
8422034721 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.3515804738 |
|
|
Oct 02 11:54:37 PM UTC 24 |
Oct 03 12:00:59 AM UTC 24 |
77332851604 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.583144590 |
|
|
Oct 02 11:59:42 PM UTC 24 |
Oct 03 12:01:12 AM UTC 24 |
9732454845 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.1321056581 |
|
|
Oct 03 12:01:13 AM UTC 24 |
Oct 03 12:01:35 AM UTC 24 |
1466651180 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.168904754 |
|
|
Oct 02 11:58:05 PM UTC 24 |
Oct 03 12:01:44 AM UTC 24 |
2561984137 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.1512001830 |
|
|
Oct 02 11:56:51 PM UTC 24 |
Oct 03 12:02:09 AM UTC 24 |
15554052072 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.3549340571 |
|
|
Oct 02 11:57:49 PM UTC 24 |
Oct 03 12:02:10 AM UTC 24 |
4028757227 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.4006389544 |
|
|
Oct 03 12:01:35 AM UTC 24 |
Oct 03 12:02:12 AM UTC 24 |
1565983933 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.1586463827 |
|
|
Oct 02 11:51:16 PM UTC 24 |
Oct 03 12:02:14 AM UTC 24 |
18694572387 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.952042269 |
|
|
Oct 03 12:02:15 AM UTC 24 |
Oct 03 12:02:21 AM UTC 24 |
1398005292 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.3958488644 |
|
|
Oct 02 11:56:34 PM UTC 24 |
Oct 03 12:02:22 AM UTC 24 |
4717577080 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_bijection.1562411718 |
|
|
Oct 02 11:27:43 PM UTC 24 |
Oct 03 12:02:34 AM UTC 24 |
92187131201 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.948144980 |
|
|
Oct 02 11:59:27 PM UTC 24 |
Oct 03 12:02:35 AM UTC 24 |
14117427338 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access.3529729417 |
|
|
Oct 03 12:00:47 AM UTC 24 |
Oct 03 12:02:36 AM UTC 24 |
1383832079 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.4143248017 |
|
|
Oct 03 12:01:45 AM UTC 24 |
Oct 03 12:02:37 AM UTC 24 |
5996629088 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_alert_test.4251987910 |
|
|
Oct 03 12:02:37 AM UTC 24 |
Oct 03 12:02:39 AM UTC 24 |
40216494 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_regwen.3622576345 |
|
|
Oct 02 11:49:56 PM UTC 24 |
Oct 03 12:02:58 AM UTC 24 |
3907808815 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_smoke.3209009909 |
|
|
Oct 03 12:02:39 AM UTC 24 |
Oct 03 12:03:14 AM UTC 24 |
948459566 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.1683906778 |
|
|
Oct 03 12:00:17 AM UTC 24 |
Oct 03 12:03:15 AM UTC 24 |
1878212818 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.2497689679 |
|
|
Oct 02 11:45:06 PM UTC 24 |
Oct 03 12:03:23 AM UTC 24 |
18750458180 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.482358052 |
|
|
Oct 03 12:02:35 AM UTC 24 |
Oct 03 12:03:29 AM UTC 24 |
5624787453 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_smoke.277043876 |
|
|
Oct 03 12:04:40 AM UTC 24 |
Oct 03 12:04:53 AM UTC 24 |
501599899 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_bijection.862267885 |
|
|
Oct 02 11:45:42 PM UTC 24 |
Oct 03 12:03:30 AM UTC 24 |
162124135877 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.1277838650 |
|
|
Oct 03 12:03:30 AM UTC 24 |
Oct 03 12:03:53 AM UTC 24 |
2772155715 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.3360754431 |
|
|
Oct 03 12:02:22 AM UTC 24 |
Oct 03 12:03:58 AM UTC 24 |
5542150633 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.370352157 |
|
|
Oct 03 12:00:43 AM UTC 24 |
Oct 03 12:04:02 AM UTC 24 |
2513171055 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.1164335778 |
|
|
Oct 03 12:03:30 AM UTC 24 |
Oct 03 12:04:03 AM UTC 24 |
1482451261 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.2512678017 |
|
|
Oct 02 11:54:11 PM UTC 24 |
Oct 03 12:04:06 AM UTC 24 |
36598041390 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.3636019825 |
|
|
Oct 03 12:04:07 AM UTC 24 |
Oct 03 12:04:13 AM UTC 24 |
1406214097 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all.1035599286 |
|
|
Oct 02 11:19:21 PM UTC 24 |
Oct 03 12:04:14 AM UTC 24 |
132540029794 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_executable.2009357706 |
|
|
Oct 02 11:55:50 PM UTC 24 |
Oct 03 12:04:29 AM UTC 24 |
10757653665 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_bijection.721856272 |
|
|
Oct 02 11:19:06 PM UTC 24 |
Oct 03 12:04:33 AM UTC 24 |
140266985262 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.478466016 |
|
|
Oct 02 11:48:32 PM UTC 24 |
Oct 03 12:04:37 AM UTC 24 |
63984633860 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_alert_test.696355288 |
|
|
Oct 03 12:04:37 AM UTC 24 |
Oct 03 12:04:39 AM UTC 24 |
19617132 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.1245869248 |
|
|
Oct 02 11:52:17 PM UTC 24 |
Oct 03 12:04:40 AM UTC 24 |
53344114823 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access.4283393751 |
|
|
Oct 03 12:03:16 AM UTC 24 |
Oct 03 12:04:58 AM UTC 24 |
2154589634 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_executable.938607074 |
|
|
Oct 02 11:57:22 PM UTC 24 |
Oct 03 12:05:04 AM UTC 24 |
18507861629 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.4231601589 |
|
|
Oct 02 11:58:55 PM UTC 24 |
Oct 03 12:05:13 AM UTC 24 |
7899648052 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access.2908704881 |
|
|
Oct 03 12:05:05 AM UTC 24 |
Oct 03 12:05:31 AM UTC 24 |
2669072387 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.3411827709 |
|
|
Oct 03 12:03:54 AM UTC 24 |
Oct 03 12:05:33 AM UTC 24 |
18503114446 ps |
| T46 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.637946481 |
|
|
Oct 03 12:04:30 AM UTC 24 |
Oct 03 12:05:56 AM UTC 24 |
1745294940 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.1006557680 |
|
|
Oct 03 12:04:14 AM UTC 24 |
Oct 03 12:06:02 AM UTC 24 |
13813243143 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.1713619884 |
|
|
Oct 02 11:41:42 PM UTC 24 |
Oct 03 12:06:18 AM UTC 24 |
82171644259 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.3086760699 |
|
|
Oct 02 11:58:27 PM UTC 24 |
Oct 03 12:06:41 AM UTC 24 |
27394516043 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_regwen.1128870192 |
|
|
Oct 02 11:47:08 PM UTC 24 |
Oct 03 12:06:56 AM UTC 24 |
20231068595 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_bijection.1442724031 |
|
|
Oct 02 11:33:16 PM UTC 24 |
Oct 03 12:06:57 AM UTC 24 |
383656391861 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.1410386050 |
|
|
Oct 03 12:05:32 AM UTC 24 |
Oct 03 12:06:59 AM UTC 24 |
772406186 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_bijection.3247538116 |
|
|
Oct 02 11:42:41 PM UTC 24 |
Oct 03 12:07:02 AM UTC 24 |
37432168419 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.909732506 |
|
|
Oct 03 12:05:33 AM UTC 24 |
Oct 03 12:07:02 AM UTC 24 |
812888643 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.3287746071 |
|
|
Oct 03 12:06:57 AM UTC 24 |
Oct 03 12:07:04 AM UTC 24 |
689178670 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all.1137725124 |
|
|
Oct 02 11:18:44 PM UTC 24 |
Oct 03 12:07:06 AM UTC 24 |
201764401386 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_alert_test.3125599107 |
|
|
Oct 03 12:07:05 AM UTC 24 |
Oct 03 12:07:07 AM UTC 24 |
47263241 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.1171365480 |
|
|
Oct 03 12:07:03 AM UTC 24 |
Oct 03 12:07:23 AM UTC 24 |
479651274 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_smoke.739218156 |
|
|
Oct 03 12:07:08 AM UTC 24 |
Oct 03 12:07:28 AM UTC 24 |
1658009414 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.1065358145 |
|
|
Oct 03 12:05:57 AM UTC 24 |
Oct 03 12:07:31 AM UTC 24 |
21982054168 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.2475962939 |
|
|
Oct 03 12:03:15 AM UTC 24 |
Oct 03 12:07:31 AM UTC 24 |
4642227136 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_regwen.4220480479 |
|
|
Oct 03 12:04:04 AM UTC 24 |
Oct 03 12:07:38 AM UTC 24 |
1000308454 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.2095027104 |
|
|
Oct 03 12:01:00 AM UTC 24 |
Oct 03 12:07:44 AM UTC 24 |
39248896280 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all.3844834194 |
|
|
Oct 02 11:42:07 PM UTC 24 |
Oct 03 12:07:50 AM UTC 24 |
63964032843 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.698541599 |
|
|
Oct 02 11:55:36 PM UTC 24 |
Oct 03 12:07:51 AM UTC 24 |
45968337863 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.3482698064 |
|
|
Oct 03 12:07:38 AM UTC 24 |
Oct 03 12:07:55 AM UTC 24 |
747527313 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access.3197552403 |
|
|
Oct 03 12:07:32 AM UTC 24 |
Oct 03 12:08:08 AM UTC 24 |
15543975826 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.1416157213 |
|
|
Oct 02 11:57:13 PM UTC 24 |
Oct 03 12:08:58 AM UTC 24 |
15796195362 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.110168117 |
|
|
Oct 03 12:07:00 AM UTC 24 |
Oct 03 12:09:03 AM UTC 24 |
6851269411 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.3559563908 |
|
|
Oct 03 12:08:59 AM UTC 24 |
Oct 03 12:09:06 AM UTC 24 |
1349901750 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_regwen.3302053861 |
|
|
Oct 02 11:55:52 PM UTC 24 |
Oct 03 12:09:14 AM UTC 24 |
9540904225 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.3067344969 |
|
|
Oct 03 12:07:45 AM UTC 24 |
Oct 03 12:09:16 AM UTC 24 |
3532964898 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.469860291 |
|
|
Oct 03 12:03:23 AM UTC 24 |
Oct 03 12:09:32 AM UTC 24 |
24590507947 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_alert_test.3923467014 |
|
|
Oct 03 12:09:33 AM UTC 24 |
Oct 03 12:09:35 AM UTC 24 |
18546592 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.1729416200 |
|
|
Oct 03 12:05:14 AM UTC 24 |
Oct 03 12:09:47 AM UTC 24 |
21088976569 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.3827580949 |
|
|
Oct 03 12:04:59 AM UTC 24 |
Oct 03 12:09:49 AM UTC 24 |
3352721621 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.2692220235 |
|
|
Oct 03 12:07:50 AM UTC 24 |
Oct 03 12:09:49 AM UTC 24 |
90098998885 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.4244552799 |
|
|
Oct 03 12:09:15 AM UTC 24 |
Oct 03 12:09:55 AM UTC 24 |
840832288 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_smoke.2992807250 |
|
|
Oct 03 12:09:36 AM UTC 24 |
Oct 03 12:09:59 AM UTC 24 |
6205071307 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all.1252360614 |
|
|
Oct 02 11:35:18 PM UTC 24 |
Oct 03 12:10:10 AM UTC 24 |
98081534529 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.258397189 |
|
|
Oct 03 12:02:22 AM UTC 24 |
Oct 03 12:10:16 AM UTC 24 |
94078698125 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access.3677234221 |
|
|
Oct 03 12:09:55 AM UTC 24 |
Oct 03 12:10:20 AM UTC 24 |
1929397273 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_regwen.3716022638 |
|
|
Oct 03 12:06:42 AM UTC 24 |
Oct 03 12:10:23 AM UTC 24 |
11140491320 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.444233484 |
|
|
Oct 03 12:03:59 AM UTC 24 |
Oct 03 12:10:25 AM UTC 24 |
17498526708 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.776353961 |
|
|
Oct 03 12:07:08 AM UTC 24 |
Oct 03 12:10:29 AM UTC 24 |
8161903472 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.1408841687 |
|
|
Oct 03 12:10:11 AM UTC 24 |
Oct 03 12:10:34 AM UTC 24 |
774024169 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.2958813235 |
|
|
Oct 03 12:09:07 AM UTC 24 |
Oct 03 12:10:37 AM UTC 24 |
2393226520 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.1221428501 |
|
|
Oct 03 12:07:29 AM UTC 24 |
Oct 03 12:10:41 AM UTC 24 |
9496629032 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.4166279153 |
|
|
Oct 03 12:10:35 AM UTC 24 |
Oct 03 12:10:42 AM UTC 24 |
764872897 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all.2360305539 |
|
|
Oct 02 11:31:05 PM UTC 24 |
Oct 03 12:10:57 AM UTC 24 |
920961579535 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.3861951813 |
|
|
Oct 02 11:46:55 PM UTC 24 |
Oct 03 12:11:00 AM UTC 24 |
333525174315 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_alert_test.4175414507 |
|
|
Oct 03 12:11:01 AM UTC 24 |
Oct 03 12:11:03 AM UTC 24 |
28726899 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.737354965 |
|
|
Oct 03 12:10:17 AM UTC 24 |
Oct 03 12:11:05 AM UTC 24 |
2759541587 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_smoke.990606263 |
|
|
Oct 03 12:11:04 AM UTC 24 |
Oct 03 12:11:25 AM UTC 24 |
1084313534 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.131985920 |
|
|
Oct 03 12:04:14 AM UTC 24 |
Oct 03 12:11:27 AM UTC 24 |
14133444361 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.4928720 |
|
|
Oct 03 12:07:32 AM UTC 24 |
Oct 03 12:11:30 AM UTC 24 |
4745227737 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.1552644637 |
|
|
Oct 03 12:10:21 AM UTC 24 |
Oct 03 12:11:41 AM UTC 24 |
9237603124 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access.3601279304 |
|
|
Oct 03 12:11:30 AM UTC 24 |
Oct 03 12:11:58 AM UTC 24 |
5940002926 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.1958410344 |
|
|
Oct 03 12:06:58 AM UTC 24 |
Oct 03 12:12:10 AM UTC 24 |
21875936535 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.3272615581 |
|
|
Oct 03 12:10:41 AM UTC 24 |
Oct 03 12:12:19 AM UTC 24 |
2479024210 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_regwen.3562749595 |
|
|
Oct 02 11:52:39 PM UTC 24 |
Oct 03 12:12:20 AM UTC 24 |
96936920261 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_bijection.4227552162 |
|
|
Oct 02 11:31:31 PM UTC 24 |
Oct 03 12:12:40 AM UTC 24 |
194828753884 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.4129834003 |
|
|
Oct 03 12:10:43 AM UTC 24 |
Oct 03 12:12:21 AM UTC 24 |
4899357833 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.3916688109 |
|
|
Oct 03 12:11:59 AM UTC 24 |
Oct 03 12:12:40 AM UTC 24 |
757320615 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.385870033 |
|
|
Oct 03 12:12:41 AM UTC 24 |
Oct 03 12:12:48 AM UTC 24 |
357020576 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.2170607687 |
|
|
Oct 03 12:12:11 AM UTC 24 |
Oct 03 12:12:49 AM UTC 24 |
777803943 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_regwen.3602084677 |
|
|
Oct 02 11:59:15 PM UTC 24 |
Oct 03 12:13:21 AM UTC 24 |
3670296055 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.310106194 |
|
|
Oct 03 12:12:20 AM UTC 24 |
Oct 03 12:13:31 AM UTC 24 |
62140772972 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.3446084895 |
|
|
Oct 03 12:09:50 AM UTC 24 |
Oct 03 12:13:33 AM UTC 24 |
24767188560 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_alert_test.165175382 |
|
|
Oct 03 12:13:34 AM UTC 24 |
Oct 03 12:13:36 AM UTC 24 |
49044607 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_executable.1721497750 |
|
|
Oct 02 11:48:58 PM UTC 24 |
Oct 03 12:13:39 AM UTC 24 |
119028342318 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.2549334039 |
|
|
Oct 03 12:13:23 AM UTC 24 |
Oct 03 12:13:44 AM UTC 24 |
535781247 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.683879301 |
|
|
Oct 03 12:09:04 AM UTC 24 |
Oct 03 12:13:56 AM UTC 24 |
172513028528 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_smoke.4244226276 |
|
|
Oct 03 12:13:37 AM UTC 24 |
Oct 03 12:13:59 AM UTC 24 |
386718213 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access.1720329834 |
|
|
Oct 03 12:13:59 AM UTC 24 |
Oct 03 12:14:11 AM UTC 24 |
411666188 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all.1112768316 |
|
|
Oct 02 11:19:02 PM UTC 24 |
Oct 03 12:14:27 AM UTC 24 |
67563235349 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.3515240350 |
|
|
Oct 03 12:14:28 AM UTC 24 |
Oct 03 12:14:43 AM UTC 24 |
689254564 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_bijection.430338343 |
|
|
Oct 02 11:51:22 PM UTC 24 |
Oct 03 12:15:02 AM UTC 24 |
19287212326 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.2093614153 |
|
|
Oct 03 12:02:10 AM UTC 24 |
Oct 03 12:15:07 AM UTC 24 |
44871560066 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_executable.700367163 |
|
|
Oct 03 12:02:11 AM UTC 24 |
Oct 03 12:15:17 AM UTC 24 |
15905651429 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.2050996876 |
|
|
Oct 03 12:10:00 AM UTC 24 |
Oct 03 12:15:19 AM UTC 24 |
23683596701 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_executable.2389565803 |
|
|
Oct 03 12:04:04 AM UTC 24 |
Oct 03 12:15:30 AM UTC 24 |
13739716238 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_executable.3033241225 |
|
|
Oct 03 12:06:19 AM UTC 24 |
Oct 03 12:15:39 AM UTC 24 |
32605487953 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.162779093 |
|
|
Oct 03 12:15:30 AM UTC 24 |
Oct 03 12:15:40 AM UTC 24 |
4178935355 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.3202901797 |
|
|
Oct 03 12:14:43 AM UTC 24 |
Oct 03 12:15:50 AM UTC 24 |
1536948099 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.3914304879 |
|
|
Oct 03 12:12:50 AM UTC 24 |
Oct 03 12:15:56 AM UTC 24 |
19729739102 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_bijection.2097682864 |
|
|
Oct 02 11:38:27 PM UTC 24 |
Oct 03 12:16:06 AM UTC 24 |
112240232037 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_alert_test.3539534720 |
|
|
Oct 03 12:16:06 AM UTC 24 |
Oct 03 12:16:08 AM UTC 24 |
35496430 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.3722507966 |
|
|
Oct 03 12:15:03 AM UTC 24 |
Oct 03 12:16:28 AM UTC 24 |
40225593980 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1092188242 |
|
|
Oct 03 12:15:51 AM UTC 24 |
Oct 03 12:16:38 AM UTC 24 |
1059404848 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_smoke.3563334489 |
|
|
Oct 03 12:16:09 AM UTC 24 |
Oct 03 12:17:04 AM UTC 24 |
751967795 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.1028735267 |
|
|
Oct 03 12:02:40 AM UTC 24 |
Oct 03 12:17:13 AM UTC 24 |
78710810114 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access.3267813881 |
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|
Oct 03 12:17:15 AM UTC 24 |
Oct 03 12:17:45 AM UTC 24 |
1270861349 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.1581129390 |
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Oct 03 12:06:04 AM UTC 24 |
Oct 03 12:17:54 AM UTC 24 |
70117514526 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.3332594609 |
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Oct 03 12:10:37 AM UTC 24 |
Oct 03 12:18:00 AM UTC 24 |
20694243861 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.1199001229 |
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Oct 03 12:15:41 AM UTC 24 |
Oct 03 12:18:06 AM UTC 24 |
2562984343 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.2638590009 |
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Oct 03 12:04:42 AM UTC 24 |
Oct 03 12:18:10 AM UTC 24 |
89988570222 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.1026895004 |
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Oct 03 12:18:01 AM UTC 24 |
Oct 03 12:18:12 AM UTC 24 |
669100024 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.600744308 |
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Oct 03 12:15:40 AM UTC 24 |
Oct 03 12:18:19 AM UTC 24 |
6993548461 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.2754359383 |
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Oct 03 12:13:57 AM UTC 24 |
Oct 03 12:18:19 AM UTC 24 |
9828455132 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.723700885 |
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Oct 03 12:18:20 AM UTC 24 |
Oct 03 12:18:26 AM UTC 24 |
1355998516 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.484138839 |
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Oct 03 12:18:07 AM UTC 24 |
Oct 03 12:18:31 AM UTC 24 |
6864305919 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_executable.2369646092 |
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Oct 02 11:58:57 PM UTC 24 |
Oct 03 12:18:39 AM UTC 24 |
179484685145 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.2921608822 |
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Oct 03 12:09:48 AM UTC 24 |
Oct 03 12:18:52 AM UTC 24 |
65180037167 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.2627275958 |
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Oct 03 12:12:49 AM UTC 24 |
Oct 03 12:18:55 AM UTC 24 |
42307580034 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_alert_test.1865548535 |
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Oct 03 12:18:56 AM UTC 24 |
Oct 03 12:18:59 AM UTC 24 |
69433618 ps |