| T799 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.638801300 |
|
|
Oct 03 12:48:40 AM UTC 24 |
Oct 03 12:52:06 AM UTC 24 |
5238608063 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_smoke.2285112256 |
|
|
Oct 03 12:51:43 AM UTC 24 |
Oct 03 12:52:07 AM UTC 24 |
1820877794 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all.3512166307 |
|
|
Oct 02 11:56:06 PM UTC 24 |
Oct 03 12:52:28 AM UTC 24 |
63494820122 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all.1396130880 |
|
|
Oct 02 11:53:28 PM UTC 24 |
Oct 03 12:52:40 AM UTC 24 |
435360998443 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_executable.1058721163 |
|
|
Oct 03 12:38:26 AM UTC 24 |
Oct 03 12:52:47 AM UTC 24 |
53372365880 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_bijection.1277628253 |
|
|
Oct 03 12:13:44 AM UTC 24 |
Oct 03 12:52:52 AM UTC 24 |
131127956374 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_regwen.3266941323 |
|
|
Oct 03 12:42:01 AM UTC 24 |
Oct 03 12:52:55 AM UTC 24 |
121488944269 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.3394766455 |
|
|
Oct 03 12:49:07 AM UTC 24 |
Oct 03 12:52:56 AM UTC 24 |
2774352622 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access.2735427309 |
|
|
Oct 03 12:52:41 AM UTC 24 |
Oct 03 12:52:58 AM UTC 24 |
3348032582 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.4195924577 |
|
|
Oct 03 12:46:38 AM UTC 24 |
Oct 03 12:53:01 AM UTC 24 |
10505444323 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.3286941024 |
|
|
Oct 03 12:48:37 AM UTC 24 |
Oct 03 12:53:08 AM UTC 24 |
5255705369 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3934450818 |
|
|
Oct 03 12:51:11 AM UTC 24 |
Oct 03 12:53:08 AM UTC 24 |
7174533107 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.1168053459 |
|
|
Oct 03 12:53:09 AM UTC 24 |
Oct 03 12:53:16 AM UTC 24 |
356253245 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.3898764842 |
|
|
Oct 03 12:45:16 AM UTC 24 |
Oct 03 12:53:16 AM UTC 24 |
66399574118 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.1598299963 |
|
|
Oct 03 12:52:52 AM UTC 24 |
Oct 03 12:53:19 AM UTC 24 |
2927140116 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.1041441500 |
|
|
Oct 03 12:52:56 AM UTC 24 |
Oct 03 12:53:23 AM UTC 24 |
838382376 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.1335664626 |
|
|
Oct 03 12:51:09 AM UTC 24 |
Oct 03 12:53:48 AM UTC 24 |
9880772181 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_alert_test.866103122 |
|
|
Oct 03 12:53:50 AM UTC 24 |
Oct 03 12:53:52 AM UTC 24 |
37984887 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_regwen.4192693791 |
|
|
Oct 03 12:44:05 AM UTC 24 |
Oct 03 12:53:58 AM UTC 24 |
10973193097 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.326198648 |
|
|
Oct 03 12:51:04 AM UTC 24 |
Oct 03 12:53:59 AM UTC 24 |
9543014448 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_smoke.921940523 |
|
|
Oct 03 12:53:53 AM UTC 24 |
Oct 03 12:54:01 AM UTC 24 |
456064350 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.3221800064 |
|
|
Oct 03 12:52:57 AM UTC 24 |
Oct 03 12:54:01 AM UTC 24 |
37714885854 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.3538967912 |
|
|
Oct 03 12:47:51 AM UTC 24 |
Oct 03 12:54:13 AM UTC 24 |
30845519266 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_bijection.1257240608 |
|
|
Oct 03 12:28:10 AM UTC 24 |
Oct 03 12:54:14 AM UTC 24 |
95732833659 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_bijection.1033249070 |
|
|
Oct 03 12:16:38 AM UTC 24 |
Oct 03 12:54:28 AM UTC 24 |
65019032698 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.2933972835 |
|
|
Oct 03 12:54:15 AM UTC 24 |
Oct 03 12:54:31 AM UTC 24 |
1332167583 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.2640185553 |
|
|
Oct 03 12:53:17 AM UTC 24 |
Oct 03 12:54:39 AM UTC 24 |
1409773836 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.4039180171 |
|
|
Oct 03 12:50:03 AM UTC 24 |
Oct 03 12:54:43 AM UTC 24 |
31168708434 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access.2796173471 |
|
|
Oct 03 12:54:02 AM UTC 24 |
Oct 03 12:54:46 AM UTC 24 |
1507160091 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.201614487 |
|
|
Oct 03 12:54:32 AM UTC 24 |
Oct 03 12:55:01 AM UTC 24 |
2935625660 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.3563072472 |
|
|
Oct 03 12:55:02 AM UTC 24 |
Oct 03 12:55:09 AM UTC 24 |
787965231 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.2118365186 |
|
|
Oct 03 12:54:29 AM UTC 24 |
Oct 03 12:55:19 AM UTC 24 |
798258902 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1321544083 |
|
|
Oct 03 12:53:19 AM UTC 24 |
Oct 03 12:55:21 AM UTC 24 |
7308226910 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all.1207361691 |
|
|
Oct 03 12:40:23 AM UTC 24 |
Oct 03 12:55:36 AM UTC 24 |
174282089370 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_bijection.773360965 |
|
|
Oct 03 12:44:52 AM UTC 24 |
Oct 03 12:55:36 AM UTC 24 |
335243635886 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_alert_test.2571725010 |
|
|
Oct 03 12:55:38 AM UTC 24 |
Oct 03 12:55:40 AM UTC 24 |
14835495 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_regwen.566300597 |
|
|
Oct 03 12:53:09 AM UTC 24 |
Oct 03 12:55:51 AM UTC 24 |
1222983432 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.3089753232 |
|
|
Oct 03 12:53:59 AM UTC 24 |
Oct 03 12:55:58 AM UTC 24 |
3846192337 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_smoke.3890658717 |
|
|
Oct 03 12:55:41 AM UTC 24 |
Oct 03 12:56:04 AM UTC 24 |
11226946297 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3771886580 |
|
|
Oct 03 12:55:23 AM UTC 24 |
Oct 03 12:56:25 AM UTC 24 |
3826772352 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.4272598073 |
|
|
Oct 03 12:53:16 AM UTC 24 |
Oct 03 12:56:29 AM UTC 24 |
22455913850 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.3691259603 |
|
|
Oct 03 12:41:06 AM UTC 24 |
Oct 03 12:56:36 AM UTC 24 |
15288644758 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.4261915208 |
|
|
Oct 03 12:56:37 AM UTC 24 |
Oct 03 12:56:59 AM UTC 24 |
709749151 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.3564082343 |
|
|
Oct 03 12:52:29 AM UTC 24 |
Oct 03 12:57:15 AM UTC 24 |
3053955707 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.3815579234 |
|
|
Oct 03 12:43:58 AM UTC 24 |
Oct 03 12:57:19 AM UTC 24 |
18880409483 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_executable.1207807073 |
|
|
Oct 03 12:44:02 AM UTC 24 |
Oct 03 12:58:00 AM UTC 24 |
9741580003 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.463837551 |
|
|
Oct 03 12:55:19 AM UTC 24 |
Oct 03 12:58:12 AM UTC 24 |
1597156279 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_regwen.2852818270 |
|
|
Oct 03 12:50:58 AM UTC 24 |
Oct 03 12:58:23 AM UTC 24 |
36162818839 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.2602705275 |
|
|
Oct 03 12:57:00 AM UTC 24 |
Oct 03 12:58:26 AM UTC 24 |
1364561659 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access.3532527788 |
|
|
Oct 03 12:56:25 AM UTC 24 |
Oct 03 12:58:31 AM UTC 24 |
1309854600 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.129741684 |
|
|
Oct 03 12:58:25 AM UTC 24 |
Oct 03 12:58:32 AM UTC 24 |
705215755 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.2440226869 |
|
|
Oct 03 12:52:48 AM UTC 24 |
Oct 03 12:58:37 AM UTC 24 |
25437367774 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_bijection.3330369534 |
|
|
Oct 03 12:49:07 AM UTC 24 |
Oct 03 12:58:47 AM UTC 24 |
17117673728 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.4136761447 |
|
|
Oct 03 12:54:02 AM UTC 24 |
Oct 03 12:58:48 AM UTC 24 |
6134257319 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_alert_test.2600073746 |
|
|
Oct 03 12:58:48 AM UTC 24 |
Oct 03 12:58:50 AM UTC 24 |
25027495 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3169207409 |
|
|
Oct 03 12:58:33 AM UTC 24 |
Oct 03 12:58:51 AM UTC 24 |
282233616 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_smoke.1685367910 |
|
|
Oct 03 12:58:48 AM UTC 24 |
Oct 03 12:58:59 AM UTC 24 |
1381941209 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_regwen.3663435585 |
|
|
Oct 03 12:48:25 AM UTC 24 |
Oct 03 12:59:02 AM UTC 24 |
22704299278 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.2772772957 |
|
|
Oct 03 12:57:16 AM UTC 24 |
Oct 03 12:59:06 AM UTC 24 |
10139651718 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.4159355350 |
|
|
Oct 03 12:56:05 AM UTC 24 |
Oct 03 12:59:23 AM UTC 24 |
4652449499 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.2277844155 |
|
|
Oct 03 12:54:14 AM UTC 24 |
Oct 03 12:59:33 AM UTC 24 |
9899422480 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access.3975674778 |
|
|
Oct 03 12:59:03 AM UTC 24 |
Oct 03 12:59:33 AM UTC 24 |
16765116867 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.1684692713 |
|
|
Oct 03 12:49:00 AM UTC 24 |
Oct 03 12:59:38 AM UTC 24 |
103530689017 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.1398072943 |
|
|
Oct 03 12:56:30 AM UTC 24 |
Oct 03 01:00:02 AM UTC 24 |
4376022862 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.1790890820 |
|
|
Oct 03 12:47:07 AM UTC 24 |
Oct 03 01:00:29 AM UTC 24 |
88257247110 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.3479753276 |
|
|
Oct 03 12:55:10 AM UTC 24 |
Oct 03 01:00:33 AM UTC 24 |
5256962113 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.3640305419 |
|
|
Oct 03 12:59:24 AM UTC 24 |
Oct 03 01:00:37 AM UTC 24 |
3008181246 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.3622803613 |
|
|
Oct 03 12:59:34 AM UTC 24 |
Oct 03 01:00:40 AM UTC 24 |
22751906386 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.1771804620 |
|
|
Oct 03 01:00:34 AM UTC 24 |
Oct 03 01:00:40 AM UTC 24 |
358363647 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.3144118573 |
|
|
Oct 03 12:59:33 AM UTC 24 |
Oct 03 01:00:55 AM UTC 24 |
3190345945 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3314621870 |
|
|
Oct 03 01:00:41 AM UTC 24 |
Oct 03 01:00:56 AM UTC 24 |
2097040296 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_alert_test.2579573326 |
|
|
Oct 03 01:00:55 AM UTC 24 |
Oct 03 01:00:58 AM UTC 24 |
15141528 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.1631922068 |
|
|
Oct 03 12:44:27 AM UTC 24 |
Oct 03 01:01:05 AM UTC 24 |
19615390694 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_regwen.3603416700 |
|
|
Oct 03 01:00:31 AM UTC 24 |
Oct 03 01:01:07 AM UTC 24 |
8897801301 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_smoke.4012769302 |
|
|
Oct 03 01:00:58 AM UTC 24 |
Oct 03 01:01:15 AM UTC 24 |
4159550350 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access.2195965008 |
|
|
Oct 03 01:01:15 AM UTC 24 |
Oct 03 01:01:25 AM UTC 24 |
770732038 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.3639968343 |
|
|
Oct 03 12:58:32 AM UTC 24 |
Oct 03 01:01:59 AM UTC 24 |
17494947063 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.3047781002 |
|
|
Oct 03 01:02:01 AM UTC 24 |
Oct 03 01:02:17 AM UTC 24 |
712254555 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.3833838531 |
|
|
Oct 03 12:58:27 AM UTC 24 |
Oct 03 01:02:50 AM UTC 24 |
8212205854 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.3186428288 |
|
|
Oct 03 12:54:40 AM UTC 24 |
Oct 03 01:02:56 AM UTC 24 |
6789422298 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.3146387769 |
|
|
Oct 03 12:59:07 AM UTC 24 |
Oct 03 01:03:22 AM UTC 24 |
9485460750 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.2512382686 |
|
|
Oct 03 01:02:51 AM UTC 24 |
Oct 03 01:03:25 AM UTC 24 |
17948875358 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_bijection.556631070 |
|
|
Oct 03 12:43:14 AM UTC 24 |
Oct 03 01:03:27 AM UTC 24 |
105818383306 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.4177998656 |
|
|
Oct 03 01:03:27 AM UTC 24 |
Oct 03 01:03:32 AM UTC 24 |
368458417 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.324861572 |
|
|
Oct 03 01:02:18 AM UTC 24 |
Oct 03 01:03:36 AM UTC 24 |
817950802 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all.208459354 |
|
|
Oct 03 12:15:56 AM UTC 24 |
Oct 03 01:03:57 AM UTC 24 |
52938626530 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.3084595050 |
|
|
Oct 03 01:00:40 AM UTC 24 |
Oct 03 01:04:07 AM UTC 24 |
25922453589 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.1840358888 |
|
|
Oct 03 01:00:38 AM UTC 24 |
Oct 03 01:04:08 AM UTC 24 |
13835161982 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_alert_test.2606423867 |
|
|
Oct 03 01:04:09 AM UTC 24 |
Oct 03 01:04:11 AM UTC 24 |
21806229 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_executable.501219355 |
|
|
Oct 03 01:03:23 AM UTC 24 |
Oct 03 01:04:17 AM UTC 24 |
1300692359 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all.1102814713 |
|
|
Oct 02 11:38:07 PM UTC 24 |
Oct 03 01:04:46 AM UTC 24 |
58146717048 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.2010911763 |
|
|
Oct 03 12:59:00 AM UTC 24 |
Oct 03 01:04:57 AM UTC 24 |
16648284625 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_executable.3057147991 |
|
|
Oct 03 12:53:02 AM UTC 24 |
Oct 03 01:04:59 AM UTC 24 |
9318154669 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_regwen.3833249636 |
|
|
Oct 03 12:54:47 AM UTC 24 |
Oct 03 01:05:00 AM UTC 24 |
6570288816 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.812668690 |
|
|
Oct 03 01:01:08 AM UTC 24 |
Oct 03 01:05:17 AM UTC 24 |
15198497841 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.3272131746 |
|
|
Oct 03 12:52:59 AM UTC 24 |
Oct 03 01:05:20 AM UTC 24 |
25215837040 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_bijection.467521940 |
|
|
Oct 03 12:39:07 AM UTC 24 |
Oct 03 01:05:41 AM UTC 24 |
62449425932 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.2048471353 |
|
|
Oct 03 01:03:58 AM UTC 24 |
Oct 03 01:05:43 AM UTC 24 |
2862192154 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.2059429795 |
|
|
Oct 03 12:57:19 AM UTC 24 |
Oct 03 01:05:59 AM UTC 24 |
20574808880 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.3781711239 |
|
|
Oct 03 01:03:37 AM UTC 24 |
Oct 03 01:06:25 AM UTC 24 |
11653661364 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all.137461623 |
|
|
Oct 02 11:19:05 PM UTC 24 |
Oct 03 01:06:28 AM UTC 24 |
397757466745 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all.917684262 |
|
|
Oct 03 12:00:06 AM UTC 24 |
Oct 03 01:07:00 AM UTC 24 |
164585099757 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_bijection.2737884697 |
|
|
Oct 03 12:25:59 AM UTC 24 |
Oct 03 01:07:14 AM UTC 24 |
137989111958 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_bijection.303937594 |
|
|
Oct 03 12:24:23 AM UTC 24 |
Oct 03 01:07:15 AM UTC 24 |
747310886764 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.4136641872 |
|
|
Oct 03 01:00:59 AM UTC 24 |
Oct 03 01:07:34 AM UTC 24 |
56465084863 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_bijection.1728934130 |
|
|
Oct 03 12:52:08 AM UTC 24 |
Oct 03 01:07:37 AM UTC 24 |
56807615413 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_bijection.2278585667 |
|
|
Oct 03 12:47:08 AM UTC 24 |
Oct 03 01:07:46 AM UTC 24 |
14761489409 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.1594414782 |
|
|
Oct 03 01:03:34 AM UTC 24 |
Oct 03 01:07:47 AM UTC 24 |
17909446563 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.3152594464 |
|
|
Oct 03 12:52:07 AM UTC 24 |
Oct 03 01:08:15 AM UTC 24 |
9892183429 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_executable.3656826181 |
|
|
Oct 03 12:50:35 AM UTC 24 |
Oct 03 01:09:05 AM UTC 24 |
75555203220 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.1283108472 |
|
|
Oct 03 01:01:25 AM UTC 24 |
Oct 03 01:09:18 AM UTC 24 |
15005101956 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_executable.2760057023 |
|
|
Oct 03 12:47:53 AM UTC 24 |
Oct 03 01:09:26 AM UTC 24 |
82903722734 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.508547497 |
|
|
Oct 03 12:58:52 AM UTC 24 |
Oct 03 01:09:55 AM UTC 24 |
49764303842 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.664761069 |
|
|
Oct 03 12:50:28 AM UTC 24 |
Oct 03 01:10:31 AM UTC 24 |
21602531673 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_regwen.965843808 |
|
|
Oct 03 12:58:13 AM UTC 24 |
Oct 03 01:10:44 AM UTC 24 |
22378299762 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_bijection.754788592 |
|
|
Oct 03 12:33:56 AM UTC 24 |
Oct 03 01:12:44 AM UTC 24 |
127187301591 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.2081890834 |
|
|
Oct 03 12:59:38 AM UTC 24 |
Oct 03 01:13:32 AM UTC 24 |
44944992661 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_executable.305926736 |
|
|
Oct 03 01:00:07 AM UTC 24 |
Oct 03 01:13:43 AM UTC 24 |
7023073937 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_regwen.3424527149 |
|
|
Oct 03 01:03:25 AM UTC 24 |
Oct 03 01:15:03 AM UTC 24 |
24860981859 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_bijection.543040259 |
|
|
Oct 03 12:53:59 AM UTC 24 |
Oct 03 01:15:58 AM UTC 24 |
115395100305 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_executable.1121463823 |
|
|
Oct 03 12:54:44 AM UTC 24 |
Oct 03 01:17:20 AM UTC 24 |
22586508094 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.1446456195 |
|
|
Oct 03 01:02:57 AM UTC 24 |
Oct 03 01:17:47 AM UTC 24 |
16371428148 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_bijection.3450251617 |
|
|
Oct 03 12:41:10 AM UTC 24 |
Oct 03 01:17:51 AM UTC 24 |
138928772068 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_bijection.2073444770 |
|
|
Oct 03 12:36:41 AM UTC 24 |
Oct 03 01:18:23 AM UTC 24 |
127376074369 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_executable.3143234631 |
|
|
Oct 03 12:58:01 AM UTC 24 |
Oct 03 01:18:24 AM UTC 24 |
95200367537 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all.2321077121 |
|
|
Oct 03 12:10:58 AM UTC 24 |
Oct 03 01:21:11 AM UTC 24 |
217336091791 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all.892516415 |
|
|
Oct 03 12:36:37 AM UTC 24 |
Oct 03 01:25:14 AM UTC 24 |
231221737828 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_all.2126566446 |
|
|
Oct 03 12:21:31 AM UTC 24 |
Oct 03 01:26:54 AM UTC 24 |
167897609737 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all.3506794094 |
|
|
Oct 03 12:44:16 AM UTC 24 |
Oct 03 01:27:07 AM UTC 24 |
363217684142 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_bijection.1078592062 |
|
|
Oct 03 12:55:59 AM UTC 24 |
Oct 03 01:28:02 AM UTC 24 |
101727761233 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all.2065429974 |
|
|
Oct 03 12:27:58 AM UTC 24 |
Oct 03 01:29:40 AM UTC 24 |
72991691276 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all.1721106829 |
|
|
Oct 03 12:09:17 AM UTC 24 |
Oct 03 01:30:52 AM UTC 24 |
337307355004 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all.1059976138 |
|
|
Oct 03 12:25:41 AM UTC 24 |
Oct 03 01:32:34 AM UTC 24 |
563936235439 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all.237959452 |
|
|
Oct 03 12:46:51 AM UTC 24 |
Oct 03 01:37:01 AM UTC 24 |
193284012224 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_bijection.2926263319 |
|
|
Oct 03 12:58:53 AM UTC 24 |
Oct 03 01:38:35 AM UTC 24 |
95960234272 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_bijection.1479620257 |
|
|
Oct 03 01:01:07 AM UTC 24 |
Oct 03 01:39:21 AM UTC 24 |
469359790288 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all.3590368190 |
|
|
Oct 03 12:48:44 AM UTC 24 |
Oct 03 01:42:45 AM UTC 24 |
68340039464 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all.596192595 |
|
|
Oct 03 12:02:35 AM UTC 24 |
Oct 03 01:44:44 AM UTC 24 |
111868995467 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all.1542042203 |
|
|
Oct 03 12:07:03 AM UTC 24 |
Oct 03 01:46:26 AM UTC 24 |
972788733305 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all.3117880201 |
|
|
Oct 03 01:00:41 AM UTC 24 |
Oct 03 01:47:57 AM UTC 24 |
506849207029 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all.658280984 |
|
|
Oct 03 12:42:49 AM UTC 24 |
Oct 03 01:56:02 AM UTC 24 |
116388499353 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all.956972968 |
|
|
Oct 03 12:30:41 AM UTC 24 |
Oct 03 01:57:57 AM UTC 24 |
62354653098 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all.1861721545 |
|
|
Oct 03 12:51:34 AM UTC 24 |
Oct 03 01:58:14 AM UTC 24 |
668308191468 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all.1050063536 |
|
|
Oct 03 01:04:08 AM UTC 24 |
Oct 03 02:00:05 AM UTC 24 |
371587443862 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all.3202464902 |
|
|
Oct 03 12:58:38 AM UTC 24 |
Oct 03 02:17:36 AM UTC 24 |
65070278443 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all.2194801973 |
|
|
Oct 03 12:33:38 AM UTC 24 |
Oct 03 02:20:40 AM UTC 24 |
496845727542 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all.3761808176 |
|
|
Oct 02 11:50:49 PM UTC 24 |
Oct 03 02:28:35 AM UTC 24 |
2599123491482 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all.2061781006 |
|
|
Oct 03 12:53:24 AM UTC 24 |
Oct 03 02:59:10 AM UTC 24 |
240895459765 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all.1558273065 |
|
|
Oct 03 12:55:37 AM UTC 24 |
Oct 03 03:02:44 AM UTC 24 |
704974559725 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all.342757866 |
|
|
Oct 03 12:39:01 AM UTC 24 |
Oct 03 03:23:56 AM UTC 24 |
483619638800 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1006951017 |
|
|
Oct 03 01:04:18 AM UTC 24 |
Oct 03 01:04:22 AM UTC 24 |
79197301 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1697979153 |
|
|
Oct 03 01:04:23 AM UTC 24 |
Oct 03 01:04:28 AM UTC 24 |
1239354385 ps |
| T67 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.4049712122 |
|
|
Oct 03 01:04:29 AM UTC 24 |
Oct 03 01:04:32 AM UTC 24 |
16540356 ps |
| T68 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1269522277 |
|
|
Oct 03 01:04:32 AM UTC 24 |
Oct 03 01:04:34 AM UTC 24 |
38634470 ps |
| T69 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2488085994 |
|
|
Oct 03 01:04:36 AM UTC 24 |
Oct 03 01:04:40 AM UTC 24 |
709220788 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3983213671 |
|
|
Oct 03 01:04:41 AM UTC 24 |
Oct 03 01:04:43 AM UTC 24 |
22489486 ps |
| T95 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1722043626 |
|
|
Oct 03 01:04:44 AM UTC 24 |
Oct 03 01:04:46 AM UTC 24 |
23242195 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2004696410 |
|
|
Oct 03 01:04:47 AM UTC 24 |
Oct 03 01:04:53 AM UTC 24 |
352630964 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2722767548 |
|
|
Oct 03 01:04:54 AM UTC 24 |
Oct 03 01:05:02 AM UTC 24 |
117505974 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.212218727 |
|
|
Oct 03 01:05:00 AM UTC 24 |
Oct 03 01:05:02 AM UTC 24 |
22336019 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.612418180 |
|
|
Oct 03 01:05:00 AM UTC 24 |
Oct 03 01:05:02 AM UTC 24 |
41227153 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.98681754 |
|
|
Oct 03 01:04:58 AM UTC 24 |
Oct 03 01:05:04 AM UTC 24 |
304224715 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1103495017 |
|
|
Oct 03 01:05:04 AM UTC 24 |
Oct 03 01:05:06 AM UTC 24 |
12374197 ps |
| T96 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3990721162 |
|
|
Oct 03 01:05:04 AM UTC 24 |
Oct 03 01:05:06 AM UTC 24 |
66208388 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.99346315 |
|
|
Oct 03 01:05:02 AM UTC 24 |
Oct 03 01:05:06 AM UTC 24 |
152810386 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.970660181 |
|
|
Oct 03 01:05:07 AM UTC 24 |
Oct 03 01:05:10 AM UTC 24 |
232874868 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1151067519 |
|
|
Oct 03 01:05:05 AM UTC 24 |
Oct 03 01:05:12 AM UTC 24 |
1389448600 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1888152922 |
|
|
Oct 03 01:05:07 AM UTC 24 |
Oct 03 01:05:13 AM UTC 24 |
153426398 ps |
| T72 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2031675686 |
|
|
Oct 03 01:05:11 AM UTC 24 |
Oct 03 01:05:13 AM UTC 24 |
40658436 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3023635282 |
|
|
Oct 03 01:05:12 AM UTC 24 |
Oct 03 01:05:14 AM UTC 24 |
20266280 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2812096768 |
|
|
Oct 03 01:05:14 AM UTC 24 |
Oct 03 01:05:16 AM UTC 24 |
16133358 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3266496801 |
|
|
Oct 03 01:05:13 AM UTC 24 |
Oct 03 01:05:17 AM UTC 24 |
120450187 ps |
| T97 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1455387086 |
|
|
Oct 03 01:05:15 AM UTC 24 |
Oct 03 01:05:18 AM UTC 24 |
45915682 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1847484722 |
|
|
Oct 03 01:04:12 AM UTC 24 |
Oct 03 01:05:18 AM UTC 24 |
7328002518 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2858232517 |
|
|
Oct 03 01:05:19 AM UTC 24 |
Oct 03 01:05:21 AM UTC 24 |
14406284 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2788175131 |
|
|
Oct 03 01:05:19 AM UTC 24 |
Oct 03 01:05:23 AM UTC 24 |
873239874 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.878482322 |
|
|
Oct 03 01:05:21 AM UTC 24 |
Oct 03 01:05:23 AM UTC 24 |
15827082 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.234031204 |
|
|
Oct 03 01:05:19 AM UTC 24 |
Oct 03 01:05:24 AM UTC 24 |
224460702 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1277874926 |
|
|
Oct 03 01:05:18 AM UTC 24 |
Oct 03 01:05:26 AM UTC 24 |
1423968834 ps |
| T98 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.845790704 |
|
|
Oct 03 01:05:24 AM UTC 24 |
Oct 03 01:05:27 AM UTC 24 |
43133857 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1856159583 |
|
|
Oct 03 01:05:24 AM UTC 24 |
Oct 03 01:05:27 AM UTC 24 |
50718063 ps |
| T89 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.163924749 |
|
|
Oct 03 01:05:22 AM UTC 24 |
Oct 03 01:05:27 AM UTC 24 |
867421723 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2159350917 |
|
|
Oct 03 01:05:28 AM UTC 24 |
Oct 03 01:05:31 AM UTC 24 |
40170127 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1555066900 |
|
|
Oct 03 01:05:26 AM UTC 24 |
Oct 03 01:05:32 AM UTC 24 |
364137524 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.678597880 |
|
|
Oct 03 01:05:28 AM UTC 24 |
Oct 03 01:05:34 AM UTC 24 |
684679276 ps |
| T99 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.677415442 |
|
|
Oct 03 01:05:32 AM UTC 24 |
Oct 03 01:05:34 AM UTC 24 |
40931569 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1134858726 |
|
|
Oct 03 01:05:28 AM UTC 24 |
Oct 03 01:05:35 AM UTC 24 |
280299608 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2602552950 |
|
|
Oct 03 01:05:33 AM UTC 24 |
Oct 03 01:05:37 AM UTC 24 |
425839467 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1783170075 |
|
|
Oct 03 01:05:35 AM UTC 24 |
Oct 03 01:05:37 AM UTC 24 |
22241076 ps |
| T100 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2846073185 |
|
|
Oct 03 01:05:35 AM UTC 24 |
Oct 03 01:05:38 AM UTC 24 |
89624949 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2851741884 |
|
|
Oct 03 01:05:39 AM UTC 24 |
Oct 03 01:05:43 AM UTC 24 |
265422338 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.843849844 |
|
|
Oct 03 01:05:39 AM UTC 24 |
Oct 03 01:05:43 AM UTC 24 |
58658286 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3067896195 |
|
|
Oct 03 01:05:42 AM UTC 24 |
Oct 03 01:05:44 AM UTC 24 |
13338977 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3909951130 |
|
|
Oct 03 01:05:36 AM UTC 24 |
Oct 03 01:05:46 AM UTC 24 |
2822877678 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1659874254 |
|
|
Oct 03 01:05:43 AM UTC 24 |
Oct 03 01:05:46 AM UTC 24 |
39776706 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.4187642747 |
|
|
Oct 03 01:05:46 AM UTC 24 |
Oct 03 01:05:49 AM UTC 24 |
36734401 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1206928820 |
|
|
Oct 03 01:05:46 AM UTC 24 |
Oct 03 01:05:50 AM UTC 24 |
162181696 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1636749542 |
|
|
Oct 03 01:05:45 AM UTC 24 |
Oct 03 01:05:50 AM UTC 24 |
332957755 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.499823535 |
|
|
Oct 03 01:05:50 AM UTC 24 |
Oct 03 01:05:52 AM UTC 24 |
22788021 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1189138443 |
|
|
Oct 03 01:05:44 AM UTC 24 |
Oct 03 01:05:53 AM UTC 24 |
1640855158 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3168498357 |
|
|
Oct 03 01:05:54 AM UTC 24 |
Oct 03 01:05:58 AM UTC 24 |
112969435 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.46758628 |
|
|
Oct 03 01:05:53 AM UTC 24 |
Oct 03 01:05:59 AM UTC 24 |
600647336 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1924284509 |
|
|
Oct 03 01:05:51 AM UTC 24 |
Oct 03 01:05:59 AM UTC 24 |
2934830129 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3862905283 |
|
|
Oct 03 01:04:47 AM UTC 24 |
Oct 03 01:05:59 AM UTC 24 |
29457028408 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.185145772 |
|
|
Oct 03 01:05:18 AM UTC 24 |
Oct 03 01:05:59 AM UTC 24 |
7674754514 ps |
| T90 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2921484401 |
|
|
Oct 03 01:05:58 AM UTC 24 |
Oct 03 01:06:00 AM UTC 24 |
38896513 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2108785277 |
|
|
Oct 03 01:05:59 AM UTC 24 |
Oct 03 01:06:01 AM UTC 24 |
39942644 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1821736309 |
|
|
Oct 03 01:06:01 AM UTC 24 |
Oct 03 01:06:03 AM UTC 24 |
50542287 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3307637870 |
|
|
Oct 03 01:06:02 AM UTC 24 |
Oct 03 01:06:04 AM UTC 24 |
22935177 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1939517670 |
|
|
Oct 03 01:06:01 AM UTC 24 |
Oct 03 01:06:05 AM UTC 24 |
33808556 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2241080323 |
|
|
Oct 03 01:06:01 AM UTC 24 |
Oct 03 01:06:05 AM UTC 24 |
206723200 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3451489357 |
|
|
Oct 03 01:05:59 AM UTC 24 |
Oct 03 01:06:07 AM UTC 24 |
699593266 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.427282600 |
|
|
Oct 03 01:06:07 AM UTC 24 |
Oct 03 01:06:09 AM UTC 24 |
74950815 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1878582405 |
|
|
Oct 03 01:06:06 AM UTC 24 |
Oct 03 01:06:11 AM UTC 24 |
209846343 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2853521575 |
|
|
Oct 03 01:06:06 AM UTC 24 |
Oct 03 01:06:11 AM UTC 24 |
65844488 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3073006767 |
|
|
Oct 03 01:05:38 AM UTC 24 |
Oct 03 01:06:13 AM UTC 24 |
4323750837 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1488207192 |
|
|
Oct 03 01:06:04 AM UTC 24 |
Oct 03 01:06:13 AM UTC 24 |
353116370 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.434207334 |
|
|
Oct 03 01:06:11 AM UTC 24 |
Oct 03 01:06:13 AM UTC 24 |
45932876 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1971764261 |
|
|
Oct 03 01:06:14 AM UTC 24 |
Oct 03 01:06:16 AM UTC 24 |
72820658 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2056839409 |
|
|
Oct 03 01:06:14 AM UTC 24 |
Oct 03 01:06:18 AM UTC 24 |
318258725 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1287562527 |
|
|
Oct 03 01:06:14 AM UTC 24 |
Oct 03 01:06:19 AM UTC 24 |
81736958 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.4135373016 |
|
|
Oct 03 01:06:17 AM UTC 24 |
Oct 03 01:06:19 AM UTC 24 |
139834991 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.159585992 |
|
|
Oct 03 01:06:12 AM UTC 24 |
Oct 03 01:06:20 AM UTC 24 |
1577712459 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3261696299 |
|
|
Oct 03 01:05:07 AM UTC 24 |
Oct 03 01:06:22 AM UTC 24 |
19592915593 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1578379614 |
|
|
Oct 03 01:06:21 AM UTC 24 |
Oct 03 01:06:25 AM UTC 24 |
217503445 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2250082074 |
|
|
Oct 03 01:06:20 AM UTC 24 |
Oct 03 01:06:25 AM UTC 24 |
27623738 ps |
| T91 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.289159245 |
|
|
Oct 03 01:06:23 AM UTC 24 |
Oct 03 01:06:25 AM UTC 24 |
18151450 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3388251509 |
|
|
Oct 03 01:06:19 AM UTC 24 |
Oct 03 01:06:26 AM UTC 24 |
446059537 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.847285500 |
|
|
Oct 03 01:06:24 AM UTC 24 |
Oct 03 01:06:26 AM UTC 24 |
15734004 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3493135872 |
|
|
Oct 03 01:06:27 AM UTC 24 |
Oct 03 01:06:29 AM UTC 24 |
33603778 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.488943314 |
|
|
Oct 03 01:06:27 AM UTC 24 |
Oct 03 01:06:29 AM UTC 24 |
41167633 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.684158370 |
|
|
Oct 03 01:06:26 AM UTC 24 |
Oct 03 01:06:30 AM UTC 24 |
54586058 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2866102300 |
|
|
Oct 03 01:06:26 AM UTC 24 |
Oct 03 01:06:31 AM UTC 24 |
897573620 ps |
| T92 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3203493378 |
|
|
Oct 03 01:05:51 AM UTC 24 |
Oct 03 01:06:32 AM UTC 24 |
3853842302 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.4083712058 |
|
|
Oct 03 01:06:26 AM UTC 24 |
Oct 03 01:06:33 AM UTC 24 |
619310412 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2466680680 |
|
|
Oct 03 01:06:32 AM UTC 24 |
Oct 03 01:06:34 AM UTC 24 |
31377946 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.4289539953 |
|
|
Oct 03 01:06:28 AM UTC 24 |
Oct 03 01:06:35 AM UTC 24 |
1424532322 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1308792241 |
|
|
Oct 03 01:06:33 AM UTC 24 |
Oct 03 01:06:35 AM UTC 24 |
41656709 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3491851891 |
|
|
Oct 03 01:06:31 AM UTC 24 |
Oct 03 01:06:36 AM UTC 24 |
2799871882 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2884329723 |
|
|
Oct 03 01:06:31 AM UTC 24 |
Oct 03 01:06:38 AM UTC 24 |
136859751 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3139450468 |
|
|
Oct 03 01:06:36 AM UTC 24 |
Oct 03 01:06:39 AM UTC 24 |
154037974 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2832499899 |
|
|
Oct 03 01:06:37 AM UTC 24 |
Oct 03 01:06:39 AM UTC 24 |
14025572 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1071594621 |
|
|
Oct 03 01:06:33 AM UTC 24 |
Oct 03 01:06:40 AM UTC 24 |
928429830 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1724950723 |
|
|
Oct 03 01:06:38 AM UTC 24 |
Oct 03 01:06:41 AM UTC 24 |
73895119 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2942922741 |
|
|
Oct 03 01:06:36 AM UTC 24 |
Oct 03 01:06:42 AM UTC 24 |
129015629 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.4201398740 |
|
|
Oct 03 01:06:43 AM UTC 24 |
Oct 03 01:06:45 AM UTC 24 |
22592729 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.301921113 |
|
|
Oct 03 01:06:42 AM UTC 24 |
Oct 03 01:06:46 AM UTC 24 |
385796498 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3782571438 |
|
|
Oct 03 01:06:41 AM UTC 24 |
Oct 03 01:06:46 AM UTC 24 |
243611603 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1251595406 |
|
|
Oct 03 01:06:40 AM UTC 24 |
Oct 03 01:06:47 AM UTC 24 |
1378845460 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3416304753 |
|
|
Oct 03 01:06:47 AM UTC 24 |
Oct 03 01:06:48 AM UTC 24 |
44574079 ps |