| T552 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.881315488 |
|
|
Oct 03 12:11:28 AM UTC 24 |
Oct 03 12:19:00 AM UTC 24 |
5627457096 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_regwen.1128899937 |
|
|
Oct 03 12:02:13 AM UTC 24 |
Oct 03 12:19:04 AM UTC 24 |
69918516778 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_smoke.3569395066 |
|
|
Oct 03 12:18:59 AM UTC 24 |
Oct 03 12:19:26 AM UTC 24 |
1117084297 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.757835966 |
|
|
Oct 03 12:17:55 AM UTC 24 |
Oct 03 12:19:40 AM UTC 24 |
3614617152 ps |
| T47 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.2088047053 |
|
|
Oct 03 12:18:40 AM UTC 24 |
Oct 03 12:19:59 AM UTC 24 |
8985952387 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.2217622237 |
|
|
Oct 03 12:14:12 AM UTC 24 |
Oct 03 12:20:01 AM UTC 24 |
59121255578 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_regwen.385125415 |
|
|
Oct 03 12:12:41 AM UTC 24 |
Oct 03 12:20:05 AM UTC 24 |
2117860722 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.1477717609 |
|
|
Oct 03 12:10:24 AM UTC 24 |
Oct 03 12:20:10 AM UTC 24 |
5993315674 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access.950522243 |
|
|
Oct 03 12:19:41 AM UTC 24 |
Oct 03 12:20:16 AM UTC 24 |
1862726231 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.1874228102 |
|
|
Oct 03 12:20:02 AM UTC 24 |
Oct 03 12:20:25 AM UTC 24 |
712591547 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.2031898538 |
|
|
Oct 03 12:20:10 AM UTC 24 |
Oct 03 12:20:34 AM UTC 24 |
2624470704 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_regwen.926238665 |
|
|
Oct 03 12:08:09 AM UTC 24 |
Oct 03 12:20:39 AM UTC 24 |
23674283306 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.359407938 |
|
|
Oct 03 12:20:40 AM UTC 24 |
Oct 03 12:20:46 AM UTC 24 |
366965266 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all.1020910216 |
|
|
Oct 02 11:25:20 PM UTC 24 |
Oct 03 12:20:59 AM UTC 24 |
84364924942 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.2688970318 |
|
|
Oct 03 12:11:06 AM UTC 24 |
Oct 03 12:21:24 AM UTC 24 |
8405561467 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.4267755412 |
|
|
Oct 03 12:12:21 AM UTC 24 |
Oct 03 12:21:30 AM UTC 24 |
12767063322 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.2133717342 |
|
|
Oct 03 12:20:05 AM UTC 24 |
Oct 03 12:21:32 AM UTC 24 |
3355784756 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_executable.954979336 |
|
|
Oct 03 12:12:22 AM UTC 24 |
Oct 03 12:21:34 AM UTC 24 |
36512909581 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_alert_test.3382747294 |
|
|
Oct 03 12:21:34 AM UTC 24 |
Oct 03 12:21:36 AM UTC 24 |
15241214 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_smoke.947627839 |
|
|
Oct 03 12:21:35 AM UTC 24 |
Oct 03 12:21:59 AM UTC 24 |
2307646819 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.2801886249 |
|
|
Oct 03 12:18:32 AM UTC 24 |
Oct 03 12:22:07 AM UTC 24 |
8772086378 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.4117805568 |
|
|
Oct 03 12:17:05 AM UTC 24 |
Oct 03 12:22:10 AM UTC 24 |
20729467843 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all.4124890905 |
|
|
Oct 02 11:44:43 PM UTC 24 |
Oct 03 12:22:19 AM UTC 24 |
46249327135 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.1459513310 |
|
|
Oct 03 12:21:24 AM UTC 24 |
Oct 03 12:22:23 AM UTC 24 |
4501618782 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access.2454130924 |
|
|
Oct 03 12:22:10 AM UTC 24 |
Oct 03 12:22:28 AM UTC 24 |
2173641181 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.1311631179 |
|
|
Oct 03 12:18:10 AM UTC 24 |
Oct 03 12:22:50 AM UTC 24 |
6320079971 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.3974586758 |
|
|
Oct 03 12:19:27 AM UTC 24 |
Oct 03 12:22:57 AM UTC 24 |
4604487098 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_regwen.542433626 |
|
|
Oct 03 12:10:30 AM UTC 24 |
Oct 03 12:23:06 AM UTC 24 |
2725678616 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_executable.3221393569 |
|
|
Oct 03 12:15:18 AM UTC 24 |
Oct 03 12:23:07 AM UTC 24 |
11724768130 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.1744190206 |
|
|
Oct 03 12:20:47 AM UTC 24 |
Oct 03 12:23:10 AM UTC 24 |
4029331818 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.2963103009 |
|
|
Oct 03 12:23:11 AM UTC 24 |
Oct 03 12:23:18 AM UTC 24 |
659954014 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.2924842129 |
|
|
Oct 03 12:22:30 AM UTC 24 |
Oct 03 12:23:52 AM UTC 24 |
780269629 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.2249519452 |
|
|
Oct 03 12:21:00 AM UTC 24 |
Oct 03 12:23:59 AM UTC 24 |
6310837063 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.1505725011 |
|
|
Oct 03 12:21:37 AM UTC 24 |
Oct 03 12:24:02 AM UTC 24 |
4864019517 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_executable.3450753783 |
|
|
Oct 03 12:23:06 AM UTC 24 |
Oct 03 12:24:07 AM UTC 24 |
8633638667 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_alert_test.579946160 |
|
|
Oct 03 12:24:08 AM UTC 24 |
Oct 03 12:24:10 AM UTC 24 |
38229353 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.340520419 |
|
|
Oct 03 12:22:52 AM UTC 24 |
Oct 03 12:24:13 AM UTC 24 |
50700838003 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.541476401 |
|
|
Oct 03 12:24:00 AM UTC 24 |
Oct 03 12:24:22 AM UTC 24 |
925292776 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_smoke.1050236289 |
|
|
Oct 03 12:24:11 AM UTC 24 |
Oct 03 12:24:26 AM UTC 24 |
692463904 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.1063774680 |
|
|
Oct 03 12:22:24 AM UTC 24 |
Oct 03 12:24:27 AM UTC 24 |
7645106384 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.1968973293 |
|
|
Oct 03 12:07:52 AM UTC 24 |
Oct 03 12:24:33 AM UTC 24 |
49004800431 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access.3775856201 |
|
|
Oct 03 12:24:28 AM UTC 24 |
Oct 03 12:24:37 AM UTC 24 |
2300146472 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all.1392333769 |
|
|
Oct 02 11:21:34 PM UTC 24 |
Oct 03 12:24:40 AM UTC 24 |
42705811935 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.308477842 |
|
|
Oct 03 12:23:53 AM UTC 24 |
Oct 03 12:25:08 AM UTC 24 |
2893137625 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.1855191937 |
|
|
Oct 03 12:18:27 AM UTC 24 |
Oct 03 12:25:14 AM UTC 24 |
92461208394 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.2455517142 |
|
|
Oct 03 12:22:08 AM UTC 24 |
Oct 03 12:25:19 AM UTC 24 |
4886469222 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.4002244460 |
|
|
Oct 03 12:16:29 AM UTC 24 |
Oct 03 12:25:23 AM UTC 24 |
11399795790 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.2407672451 |
|
|
Oct 03 12:11:43 AM UTC 24 |
Oct 03 12:25:28 AM UTC 24 |
103661510732 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_bijection.2003752138 |
|
|
Oct 03 12:09:50 AM UTC 24 |
Oct 03 12:25:30 AM UTC 24 |
28033693650 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_regwen.2657284710 |
|
|
Oct 03 12:18:20 AM UTC 24 |
Oct 03 12:25:31 AM UTC 24 |
1337354069 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.2817283425 |
|
|
Oct 03 12:25:30 AM UTC 24 |
Oct 03 12:25:37 AM UTC 24 |
709357259 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.3901420167 |
|
|
Oct 03 12:25:09 AM UTC 24 |
Oct 03 12:25:40 AM UTC 24 |
3824280610 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_regwen.4062651329 |
|
|
Oct 03 12:20:35 AM UTC 24 |
Oct 03 12:25:55 AM UTC 24 |
32270436722 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.3818759592 |
|
|
Oct 03 12:19:00 AM UTC 24 |
Oct 03 12:25:56 AM UTC 24 |
23581280819 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.3412074569 |
|
|
Oct 03 12:23:19 AM UTC 24 |
Oct 03 12:25:56 AM UTC 24 |
5198475299 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_alert_test.473278546 |
|
|
Oct 03 12:25:56 AM UTC 24 |
Oct 03 12:25:58 AM UTC 24 |
14228620 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.1634817996 |
|
|
Oct 03 12:24:38 AM UTC 24 |
Oct 03 12:25:59 AM UTC 24 |
1440835698 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.1890211778 |
|
|
Oct 03 12:20:17 AM UTC 24 |
Oct 03 12:26:00 AM UTC 24 |
7736694830 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_bijection.3194761630 |
|
|
Oct 02 11:54:15 PM UTC 24 |
Oct 03 12:26:05 AM UTC 24 |
165843397454 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access.3586747573 |
|
|
Oct 03 12:26:01 AM UTC 24 |
Oct 03 12:26:08 AM UTC 24 |
676362964 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.1871131813 |
|
|
Oct 03 12:24:41 AM UTC 24 |
Oct 03 12:26:20 AM UTC 24 |
1590563322 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_smoke.2991533466 |
|
|
Oct 03 12:25:57 AM UTC 24 |
Oct 03 12:26:24 AM UTC 24 |
9394756471 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.3842067063 |
|
|
Oct 03 12:26:21 AM UTC 24 |
Oct 03 12:26:34 AM UTC 24 |
693077331 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_bijection.1909278124 |
|
|
Oct 02 11:47:45 PM UTC 24 |
Oct 03 12:26:40 AM UTC 24 |
278017384665 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1234340270 |
|
|
Oct 03 12:25:38 AM UTC 24 |
Oct 03 12:27:24 AM UTC 24 |
2616709674 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.2394667089 |
|
|
Oct 03 12:27:25 AM UTC 24 |
Oct 03 12:27:30 AM UTC 24 |
366527014 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.921022010 |
|
|
Oct 03 12:25:32 AM UTC 24 |
Oct 03 12:27:47 AM UTC 24 |
3140960875 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_regwen.2857025372 |
|
|
Oct 03 12:15:19 AM UTC 24 |
Oct 03 12:27:57 AM UTC 24 |
14749005985 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.3395862032 |
|
|
Oct 03 12:24:34 AM UTC 24 |
Oct 03 12:27:57 AM UTC 24 |
6643739174 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_regwen.3078103349 |
|
|
Oct 03 12:26:41 AM UTC 24 |
Oct 03 12:28:02 AM UTC 24 |
3206763563 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.2488929379 |
|
|
Oct 03 12:26:09 AM UTC 24 |
Oct 03 12:28:05 AM UTC 24 |
1559545855 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_alert_test.3711321692 |
|
|
Oct 03 12:28:03 AM UTC 24 |
Oct 03 12:28:05 AM UTC 24 |
34899643 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.2147445157 |
|
|
Oct 03 12:27:58 AM UTC 24 |
Oct 03 12:28:10 AM UTC 24 |
386347049 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_executable.430240861 |
|
|
Oct 03 12:10:26 AM UTC 24 |
Oct 03 12:28:14 AM UTC 24 |
10090144393 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.2053027499 |
|
|
Oct 03 12:25:32 AM UTC 24 |
Oct 03 12:28:27 AM UTC 24 |
14453340179 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_smoke.3310927227 |
|
|
Oct 03 12:28:05 AM UTC 24 |
Oct 03 12:28:47 AM UTC 24 |
3274121034 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access.207547630 |
|
|
Oct 03 12:28:29 AM UTC 24 |
Oct 03 12:28:50 AM UTC 24 |
869869390 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.1198044981 |
|
|
Oct 03 12:13:40 AM UTC 24 |
Oct 03 12:28:58 AM UTC 24 |
18803634911 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.3187335409 |
|
|
Oct 03 12:17:46 AM UTC 24 |
Oct 03 12:29:14 AM UTC 24 |
112519250197 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.3626744928 |
|
|
Oct 03 12:28:51 AM UTC 24 |
Oct 03 12:30:01 AM UTC 24 |
8219865243 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.2015135302 |
|
|
Oct 03 12:28:58 AM UTC 24 |
Oct 03 12:30:05 AM UTC 24 |
4151253778 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.3955935870 |
|
|
Oct 03 12:26:25 AM UTC 24 |
Oct 03 12:30:06 AM UTC 24 |
75244362419 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.2810193218 |
|
|
Oct 03 12:24:26 AM UTC 24 |
Oct 03 12:30:10 AM UTC 24 |
33078080640 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.4228205333 |
|
|
Oct 03 12:30:11 AM UTC 24 |
Oct 03 12:30:18 AM UTC 24 |
3720024539 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.246660204 |
|
|
Oct 03 12:27:48 AM UTC 24 |
Oct 03 12:30:24 AM UTC 24 |
17588874572 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_executable.4172046196 |
|
|
Oct 03 12:07:57 AM UTC 24 |
Oct 03 12:30:35 AM UTC 24 |
25877934549 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.670914470 |
|
|
Oct 03 12:20:00 AM UTC 24 |
Oct 03 12:30:40 AM UTC 24 |
59476523332 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.2490112002 |
|
|
Oct 03 12:30:36 AM UTC 24 |
Oct 03 12:31:06 AM UTC 24 |
1184667025 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_alert_test.659130562 |
|
|
Oct 03 12:31:06 AM UTC 24 |
Oct 03 12:31:08 AM UTC 24 |
37062964 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.197701984 |
|
|
Oct 03 12:26:34 AM UTC 24 |
Oct 03 12:31:10 AM UTC 24 |
19545654888 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.826110302 |
|
|
Oct 03 12:22:19 AM UTC 24 |
Oct 03 12:31:16 AM UTC 24 |
50028434240 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.2108970614 |
|
|
Oct 03 12:29:14 AM UTC 24 |
Oct 03 12:31:18 AM UTC 24 |
14225552293 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.893077416 |
|
|
Oct 03 12:27:31 AM UTC 24 |
Oct 03 12:31:22 AM UTC 24 |
86809847252 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_smoke.1730598773 |
|
|
Oct 03 12:31:10 AM UTC 24 |
Oct 03 12:31:45 AM UTC 24 |
915909247 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all.1909283439 |
|
|
Oct 02 11:23:51 PM UTC 24 |
Oct 03 12:31:51 AM UTC 24 |
132970764500 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access.1625761739 |
|
|
Oct 03 12:31:23 AM UTC 24 |
Oct 03 12:32:01 AM UTC 24 |
4402465668 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_bijection.4014282499 |
|
|
Oct 03 12:04:55 AM UTC 24 |
Oct 03 12:32:26 AM UTC 24 |
83776156635 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.1437984783 |
|
|
Oct 03 12:31:52 AM UTC 24 |
Oct 03 12:32:34 AM UTC 24 |
1480187283 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.547721801 |
|
|
Oct 03 12:30:25 AM UTC 24 |
Oct 03 12:32:38 AM UTC 24 |
61371149775 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.2840687248 |
|
|
Oct 03 12:32:27 AM UTC 24 |
Oct 03 12:32:49 AM UTC 24 |
1999419968 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_executable.3544994349 |
|
|
Oct 03 12:25:20 AM UTC 24 |
Oct 03 12:32:57 AM UTC 24 |
9186267587 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.3663130631 |
|
|
Oct 03 12:32:57 AM UTC 24 |
Oct 03 12:33:04 AM UTC 24 |
5565673402 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_executable.1592441345 |
|
|
Oct 03 12:26:41 AM UTC 24 |
Oct 03 12:33:05 AM UTC 24 |
16459607850 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all.3124525210 |
|
|
Oct 02 11:57:41 PM UTC 24 |
Oct 03 12:33:28 AM UTC 24 |
69992400939 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.2445876292 |
|
|
Oct 03 12:32:01 AM UTC 24 |
Oct 03 12:33:37 AM UTC 24 |
1569580391 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_bijection.1093436819 |
|
|
Oct 02 11:56:23 PM UTC 24 |
Oct 03 12:33:39 AM UTC 24 |
383728242660 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_alert_test.881459443 |
|
|
Oct 03 12:33:41 AM UTC 24 |
Oct 03 12:33:43 AM UTC 24 |
53470472 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_executable.790590595 |
|
|
Oct 03 12:18:13 AM UTC 24 |
Oct 03 12:33:52 AM UTC 24 |
15291434243 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.3177129922 |
|
|
Oct 03 12:28:48 AM UTC 24 |
Oct 03 12:33:55 AM UTC 24 |
22134571229 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.2713391875 |
|
|
Oct 03 12:26:00 AM UTC 24 |
Oct 03 12:33:56 AM UTC 24 |
5352418748 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_smoke.2693254298 |
|
|
Oct 03 12:33:44 AM UTC 24 |
Oct 03 12:34:04 AM UTC 24 |
1556520740 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.463932062 |
|
|
Oct 03 12:33:29 AM UTC 24 |
Oct 03 12:34:10 AM UTC 24 |
4006909841 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.3155561224 |
|
|
Oct 03 12:26:06 AM UTC 24 |
Oct 03 12:34:35 AM UTC 24 |
6989388021 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.2088822216 |
|
|
Oct 03 12:30:19 AM UTC 24 |
Oct 03 12:34:43 AM UTC 24 |
24629409962 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.805939983 |
|
|
Oct 03 12:34:36 AM UTC 24 |
Oct 03 12:34:47 AM UTC 24 |
1401499498 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.2945684601 |
|
|
Oct 03 12:34:48 AM UTC 24 |
Oct 03 12:35:21 AM UTC 24 |
5131262006 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_executable.2834181543 |
|
|
Oct 03 12:20:26 AM UTC 24 |
Oct 03 12:35:50 AM UTC 24 |
7194384726 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access.2791398020 |
|
|
Oct 03 12:34:04 AM UTC 24 |
Oct 03 12:35:52 AM UTC 24 |
6116047080 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.789067269 |
|
|
Oct 03 12:31:11 AM UTC 24 |
Oct 03 12:35:58 AM UTC 24 |
6630489736 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.2068803729 |
|
|
Oct 03 12:33:05 AM UTC 24 |
Oct 03 12:36:02 AM UTC 24 |
6849647771 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.743546484 |
|
|
Oct 03 12:35:59 AM UTC 24 |
Oct 03 12:36:06 AM UTC 24 |
676200762 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_all.2525216373 |
|
|
Oct 02 11:39:44 PM UTC 24 |
Oct 03 12:36:19 AM UTC 24 |
247253865218 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_bijection.1337489909 |
|
|
Oct 03 12:02:59 AM UTC 24 |
Oct 03 12:36:35 AM UTC 24 |
248637470116 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_bijection.3223150884 |
|
|
Oct 03 12:11:26 AM UTC 24 |
Oct 03 12:36:37 AM UTC 24 |
258385636163 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.3352284508 |
|
|
Oct 03 12:22:58 AM UTC 24 |
Oct 03 12:36:38 AM UTC 24 |
22961125767 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.194484526 |
|
|
Oct 03 12:28:15 AM UTC 24 |
Oct 03 12:36:40 AM UTC 24 |
10842031587 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_alert_test.3981147395 |
|
|
Oct 03 12:36:38 AM UTC 24 |
Oct 03 12:36:40 AM UTC 24 |
22699802 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.3857212345 |
|
|
Oct 03 12:34:44 AM UTC 24 |
Oct 03 12:36:41 AM UTC 24 |
3128303629 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_smoke.2831235897 |
|
|
Oct 03 12:36:39 AM UTC 24 |
Oct 03 12:36:55 AM UTC 24 |
760587119 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_bijection.2544724989 |
|
|
Oct 02 11:57:56 PM UTC 24 |
Oct 03 12:37:10 AM UTC 24 |
236897205783 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access.3246196714 |
|
|
Oct 03 12:36:56 AM UTC 24 |
Oct 03 12:37:12 AM UTC 24 |
1532137851 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.1610045325 |
|
|
Oct 03 12:33:53 AM UTC 24 |
Oct 03 12:38:06 AM UTC 24 |
5467246183 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.1748190766 |
|
|
Oct 03 12:33:57 AM UTC 24 |
Oct 03 12:38:20 AM UTC 24 |
20473673330 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.3760102566 |
|
|
Oct 03 12:36:20 AM UTC 24 |
Oct 03 12:38:21 AM UTC 24 |
1391002462 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.517270577 |
|
|
Oct 03 12:31:19 AM UTC 24 |
Oct 03 12:38:25 AM UTC 24 |
5313539330 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.1265254593 |
|
|
Oct 03 12:38:07 AM UTC 24 |
Oct 03 12:38:42 AM UTC 24 |
1431784886 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.1503771255 |
|
|
Oct 03 12:38:21 AM UTC 24 |
Oct 03 12:38:42 AM UTC 24 |
2232505074 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.1167688376 |
|
|
Oct 03 12:36:03 AM UTC 24 |
Oct 03 12:38:46 AM UTC 24 |
1977229342 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.1681043305 |
|
|
Oct 03 12:38:43 AM UTC 24 |
Oct 03 12:38:49 AM UTC 24 |
347129158 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.1837808325 |
|
|
Oct 03 12:32:35 AM UTC 24 |
Oct 03 12:38:54 AM UTC 24 |
6650304365 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.2632811198 |
|
|
Oct 03 12:36:06 AM UTC 24 |
Oct 03 12:39:00 AM UTC 24 |
2520560592 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.3486738631 |
|
|
Oct 03 12:15:08 AM UTC 24 |
Oct 03 12:39:02 AM UTC 24 |
22355551286 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.3081375601 |
|
|
Oct 03 12:37:13 AM UTC 24 |
Oct 03 12:39:05 AM UTC 24 |
1593931961 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all.4222358378 |
|
|
Oct 02 11:20:13 PM UTC 24 |
Oct 03 12:39:06 AM UTC 24 |
190420393686 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_alert_test.2450381314 |
|
|
Oct 03 12:39:03 AM UTC 24 |
Oct 03 12:39:06 AM UTC 24 |
18968865 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_smoke.1341356910 |
|
|
Oct 03 12:39:05 AM UTC 24 |
Oct 03 12:39:16 AM UTC 24 |
1585099605 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.802337493 |
|
|
Oct 03 12:36:40 AM UTC 24 |
Oct 03 12:39:18 AM UTC 24 |
12332411332 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_executable.2560937442 |
|
|
Oct 03 12:32:39 AM UTC 24 |
Oct 03 12:39:19 AM UTC 24 |
4355011531 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.2350621505 |
|
|
Oct 03 12:25:15 AM UTC 24 |
Oct 03 12:39:35 AM UTC 24 |
31001985391 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_bijection.1802887865 |
|
|
Oct 03 12:00:22 AM UTC 24 |
Oct 03 12:39:46 AM UTC 24 |
460570686014 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.4145984765 |
|
|
Oct 03 12:38:55 AM UTC 24 |
Oct 03 12:39:50 AM UTC 24 |
5962304902 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.2768314164 |
|
|
Oct 03 12:39:36 AM UTC 24 |
Oct 03 12:39:51 AM UTC 24 |
1454809638 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_bijection.4213571900 |
|
|
Oct 03 12:19:05 AM UTC 24 |
Oct 03 12:40:01 AM UTC 24 |
18106695958 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_regwen.3854608721 |
|
|
Oct 03 12:23:08 AM UTC 24 |
Oct 03 12:40:10 AM UTC 24 |
11509484273 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.3942741714 |
|
|
Oct 03 12:38:50 AM UTC 24 |
Oct 03 12:40:13 AM UTC 24 |
3081808731 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all.1575465526 |
|
|
Oct 03 12:24:03 AM UTC 24 |
Oct 03 12:40:17 AM UTC 24 |
72606155181 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.3281165543 |
|
|
Oct 03 12:40:14 AM UTC 24 |
Oct 03 12:40:19 AM UTC 24 |
360437237 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.3752333555 |
|
|
Oct 03 12:38:21 AM UTC 24 |
Oct 03 12:40:20 AM UTC 24 |
10112580884 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access.4284079589 |
|
|
Oct 03 12:39:19 AM UTC 24 |
Oct 03 12:40:23 AM UTC 24 |
3817677149 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.2812145066 |
|
|
Oct 03 12:33:05 AM UTC 24 |
Oct 03 12:40:25 AM UTC 24 |
276420240101 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_alert_test.1411005953 |
|
|
Oct 03 12:40:26 AM UTC 24 |
Oct 03 12:40:29 AM UTC 24 |
17813956 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.2718045963 |
|
|
Oct 03 12:40:21 AM UTC 24 |
Oct 03 12:41:05 AM UTC 24 |
1439015542 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.3137641648 |
|
|
Oct 03 12:39:47 AM UTC 24 |
Oct 03 12:41:09 AM UTC 24 |
3293135945 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.354712634 |
|
|
Oct 03 12:39:51 AM UTC 24 |
Oct 03 12:41:13 AM UTC 24 |
66113044186 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_bijection.2636449934 |
|
|
Oct 03 12:22:00 AM UTC 24 |
Oct 03 12:41:13 AM UTC 24 |
46260641707 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access.1154724785 |
|
|
Oct 03 12:41:14 AM UTC 24 |
Oct 03 12:41:25 AM UTC 24 |
386598094 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_smoke.1846500415 |
|
|
Oct 03 12:40:30 AM UTC 24 |
Oct 03 12:41:25 AM UTC 24 |
9230094147 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.3425656717 |
|
|
Oct 03 12:30:02 AM UTC 24 |
Oct 03 12:41:31 AM UTC 24 |
109139675803 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.2929079824 |
|
|
Oct 03 12:24:14 AM UTC 24 |
Oct 03 12:41:39 AM UTC 24 |
9867051063 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.2763838600 |
|
|
Oct 03 12:41:32 AM UTC 24 |
Oct 03 12:41:41 AM UTC 24 |
3030124270 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_regwen.2907206879 |
|
|
Oct 03 12:40:12 AM UTC 24 |
Oct 03 12:41:48 AM UTC 24 |
13024731629 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.2604022422 |
|
|
Oct 03 12:40:20 AM UTC 24 |
Oct 03 12:42:00 AM UTC 24 |
16819286658 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.1091979280 |
|
|
Oct 03 12:41:27 AM UTC 24 |
Oct 03 12:42:05 AM UTC 24 |
1460588791 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.2335183561 |
|
|
Oct 03 12:42:05 AM UTC 24 |
Oct 03 12:42:12 AM UTC 24 |
1408094822 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_executable.818501692 |
|
|
Oct 03 12:41:49 AM UTC 24 |
Oct 03 12:42:34 AM UTC 24 |
6726223863 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.3263881183 |
|
|
Oct 03 12:37:11 AM UTC 24 |
Oct 03 12:42:39 AM UTC 24 |
10849846320 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.142571949 |
|
|
Oct 03 12:36:41 AM UTC 24 |
Oct 03 12:42:48 AM UTC 24 |
5519500960 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.3002857905 |
|
|
Oct 03 12:40:18 AM UTC 24 |
Oct 03 12:42:52 AM UTC 24 |
6912820876 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_alert_test.3685784539 |
|
|
Oct 03 12:42:53 AM UTC 24 |
Oct 03 12:42:55 AM UTC 24 |
15273164 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_smoke.776278695 |
|
|
Oct 03 12:42:56 AM UTC 24 |
Oct 03 12:43:03 AM UTC 24 |
2721961292 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.1856504553 |
|
|
Oct 03 12:31:45 AM UTC 24 |
Oct 03 12:43:13 AM UTC 24 |
92195129419 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_bijection.3710488705 |
|
|
Oct 03 12:07:24 AM UTC 24 |
Oct 03 12:43:17 AM UTC 24 |
121583815706 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.2505553754 |
|
|
Oct 03 12:42:41 AM UTC 24 |
Oct 03 12:43:36 AM UTC 24 |
692217759 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all.2121410533 |
|
|
Oct 03 12:13:32 AM UTC 24 |
Oct 03 12:43:41 AM UTC 24 |
26836212954 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_regwen.1641520412 |
|
|
Oct 03 12:38:43 AM UTC 24 |
Oct 03 12:43:41 AM UTC 24 |
21424880373 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all.1193698236 |
|
|
Oct 02 11:47:36 PM UTC 24 |
Oct 03 12:43:42 AM UTC 24 |
176277477251 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_executable.2803114096 |
|
|
Oct 03 12:35:51 AM UTC 24 |
Oct 03 12:43:55 AM UTC 24 |
6399121001 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_regwen.1682233157 |
|
|
Oct 03 12:32:50 AM UTC 24 |
Oct 03 12:43:57 AM UTC 24 |
11824806718 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_executable.1857898730 |
|
|
Oct 03 12:30:06 AM UTC 24 |
Oct 03 12:44:02 AM UTC 24 |
17555256754 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.2225703853 |
|
|
Oct 03 12:39:17 AM UTC 24 |
Oct 03 12:44:04 AM UTC 24 |
3178072159 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.402665625 |
|
|
Oct 03 12:43:43 AM UTC 24 |
Oct 03 12:44:05 AM UTC 24 |
1407312656 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access.1489891163 |
|
|
Oct 03 12:43:37 AM UTC 24 |
Oct 03 12:44:07 AM UTC 24 |
10723368489 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.1089505672 |
|
|
Oct 03 12:42:36 AM UTC 24 |
Oct 03 12:44:08 AM UTC 24 |
959953952 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.79466196 |
|
|
Oct 03 12:44:06 AM UTC 24 |
Oct 03 12:44:13 AM UTC 24 |
1512382461 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_regwen.1163430054 |
|
|
Oct 03 12:35:52 AM UTC 24 |
Oct 03 12:44:15 AM UTC 24 |
4935646837 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.1085321693 |
|
|
Oct 03 12:43:42 AM UTC 24 |
Oct 03 12:44:15 AM UTC 24 |
6489813876 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_alert_test.451321582 |
|
|
Oct 03 12:44:16 AM UTC 24 |
Oct 03 12:44:18 AM UTC 24 |
13744854 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.3344784695 |
|
|
Oct 03 12:38:47 AM UTC 24 |
Oct 03 12:44:26 AM UTC 24 |
21538310267 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.2020647172 |
|
|
Oct 03 12:43:56 AM UTC 24 |
Oct 03 12:44:50 AM UTC 24 |
24763571612 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_smoke.3376001617 |
|
|
Oct 03 12:44:19 AM UTC 24 |
Oct 03 12:44:56 AM UTC 24 |
7206315409 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.3189665605 |
|
|
Oct 03 12:34:10 AM UTC 24 |
Oct 03 12:45:05 AM UTC 24 |
96483347807 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access.1533717990 |
|
|
Oct 03 12:45:06 AM UTC 24 |
Oct 03 12:45:15 AM UTC 24 |
573687069 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.3248285157 |
|
|
Oct 03 12:41:40 AM UTC 24 |
Oct 03 12:45:19 AM UTC 24 |
252969372452 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.484732748 |
|
|
Oct 03 12:44:13 AM UTC 24 |
Oct 03 12:45:21 AM UTC 24 |
1894890423 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.1195260776 |
|
|
Oct 03 12:45:20 AM UTC 24 |
Oct 03 12:45:42 AM UTC 24 |
741252031 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.1958392364 |
|
|
Oct 03 12:45:22 AM UTC 24 |
Oct 03 12:45:43 AM UTC 24 |
3638998973 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.3823171297 |
|
|
Oct 03 12:42:12 AM UTC 24 |
Oct 03 12:45:43 AM UTC 24 |
27663162800 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.460498223 |
|
|
Oct 03 12:25:57 AM UTC 24 |
Oct 03 12:45:51 AM UTC 24 |
55867573561 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_regwen.202979145 |
|
|
Oct 03 12:25:24 AM UTC 24 |
Oct 03 12:46:30 AM UTC 24 |
20778757955 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.1046637929 |
|
|
Oct 03 12:46:31 AM UTC 24 |
Oct 03 12:46:38 AM UTC 24 |
679527652 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.1228969792 |
|
|
Oct 03 12:45:43 AM UTC 24 |
Oct 03 12:46:41 AM UTC 24 |
6450292060 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.2446907968 |
|
|
Oct 03 12:41:26 AM UTC 24 |
Oct 03 12:46:45 AM UTC 24 |
20053428355 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.3254422827 |
|
|
Oct 03 12:43:04 AM UTC 24 |
Oct 03 12:46:50 AM UTC 24 |
4612368781 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.1343368923 |
|
|
Oct 03 12:44:09 AM UTC 24 |
Oct 03 12:46:51 AM UTC 24 |
20830890551 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_alert_test.2598026983 |
|
|
Oct 03 12:46:52 AM UTC 24 |
Oct 03 12:46:54 AM UTC 24 |
34598104 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.3024032185 |
|
|
Oct 03 12:41:14 AM UTC 24 |
Oct 03 12:47:05 AM UTC 24 |
7899721840 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_smoke.1556895148 |
|
|
Oct 03 12:46:55 AM UTC 24 |
Oct 03 12:47:06 AM UTC 24 |
442656474 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.2991614669 |
|
|
Oct 03 12:41:42 AM UTC 24 |
Oct 03 12:47:10 AM UTC 24 |
6334086154 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all.2348117415 |
|
|
Oct 03 12:04:33 AM UTC 24 |
Oct 03 12:47:10 AM UTC 24 |
351170154061 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.1760468395 |
|
|
Oct 03 12:46:46 AM UTC 24 |
Oct 03 12:47:11 AM UTC 24 |
2223423733 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.3730814564 |
|
|
Oct 03 12:39:20 AM UTC 24 |
Oct 03 12:47:30 AM UTC 24 |
14187388085 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access.96005683 |
|
|
Oct 03 12:47:11 AM UTC 24 |
Oct 03 12:47:36 AM UTC 24 |
4304353028 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_regwen.4271164765 |
|
|
Oct 03 12:30:08 AM UTC 24 |
Oct 03 12:47:40 AM UTC 24 |
22268879435 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.2988800581 |
|
|
Oct 03 12:43:18 AM UTC 24 |
Oct 03 12:47:50 AM UTC 24 |
4182507418 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.4029803172 |
|
|
Oct 03 12:47:37 AM UTC 24 |
Oct 03 12:47:52 AM UTC 24 |
1401091078 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.1184427531 |
|
|
Oct 03 12:39:52 AM UTC 24 |
Oct 03 12:48:30 AM UTC 24 |
22771961533 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.3766059775 |
|
|
Oct 03 12:48:31 AM UTC 24 |
Oct 03 12:48:36 AM UTC 24 |
354412732 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.191555444 |
|
|
Oct 03 12:46:42 AM UTC 24 |
Oct 03 12:48:39 AM UTC 24 |
5903109697 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.2082123826 |
|
|
Oct 03 12:43:42 AM UTC 24 |
Oct 03 12:48:41 AM UTC 24 |
8372813901 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.1150931569 |
|
|
Oct 03 12:47:41 AM UTC 24 |
Oct 03 12:48:43 AM UTC 24 |
9717693355 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.2040581841 |
|
|
Oct 03 12:44:08 AM UTC 24 |
Oct 03 12:48:56 AM UTC 24 |
5255100340 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.4029920575 |
|
|
Oct 03 12:44:58 AM UTC 24 |
Oct 03 12:48:56 AM UTC 24 |
8017623739 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_alert_test.3669472601 |
|
|
Oct 03 12:48:57 AM UTC 24 |
Oct 03 12:48:59 AM UTC 24 |
60413728 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_smoke.947587633 |
|
|
Oct 03 12:48:57 AM UTC 24 |
Oct 03 12:49:06 AM UTC 24 |
1400868497 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.1306531256 |
|
|
Oct 03 12:47:31 AM UTC 24 |
Oct 03 12:49:06 AM UTC 24 |
763661536 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.1925447069 |
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Oct 03 12:48:42 AM UTC 24 |
Oct 03 12:49:21 AM UTC 24 |
919888780 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.4151229120 |
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Oct 03 12:47:12 AM UTC 24 |
Oct 03 12:50:02 AM UTC 24 |
3917021070 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.4193089981 |
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Oct 03 12:35:22 AM UTC 24 |
Oct 03 12:50:04 AM UTC 24 |
12033192703 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.2375580388 |
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Oct 03 12:50:05 AM UTC 24 |
Oct 03 12:50:18 AM UTC 24 |
9579066134 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.3767119828 |
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Oct 03 12:39:07 AM UTC 24 |
Oct 03 12:50:24 AM UTC 24 |
164341338882 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.4248535185 |
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Oct 03 12:50:18 AM UTC 24 |
Oct 03 12:50:28 AM UTC 24 |
709583449 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_executable.3712110214 |
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Oct 03 12:40:02 AM UTC 24 |
Oct 03 12:50:35 AM UTC 24 |
12751862260 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.783403159 |
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Oct 03 12:45:44 AM UTC 24 |
Oct 03 12:50:57 AM UTC 24 |
31555952011 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access.2836918071 |
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Oct 03 12:49:22 AM UTC 24 |
Oct 03 12:51:00 AM UTC 24 |
4203535608 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.215615546 |
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Oct 03 12:47:11 AM UTC 24 |
Oct 03 12:51:03 AM UTC 24 |
11421703928 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.1077432848 |
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Oct 03 12:51:01 AM UTC 24 |
Oct 03 12:51:08 AM UTC 24 |
1251491044 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.4011671490 |
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Oct 03 12:28:06 AM UTC 24 |
Oct 03 12:51:10 AM UTC 24 |
18567641552 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_regwen.3332573032 |
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Oct 03 12:45:53 AM UTC 24 |
Oct 03 12:51:33 AM UTC 24 |
2658601739 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.2757013635 |
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Oct 03 12:50:24 AM UTC 24 |
Oct 03 12:51:39 AM UTC 24 |
7096925918 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_alert_test.2221664383 |
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Oct 03 12:51:40 AM UTC 24 |
Oct 03 12:51:43 AM UTC 24 |
16845363 ps |