| T311 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.1719803694 |
|
|
Oct 09 12:59:49 PM UTC 24 |
Oct 09 01:01:28 PM UTC 24 |
49995883914 ps |
| T312 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.2649008347 |
|
|
Oct 09 01:00:37 PM UTC 24 |
Oct 09 01:01:43 PM UTC 24 |
960483247 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access.855530677 |
|
|
Oct 09 01:01:25 PM UTC 24 |
Oct 09 01:01:46 PM UTC 24 |
1078466817 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.3606569395 |
|
|
Oct 09 01:01:30 PM UTC 24 |
Oct 09 01:01:58 PM UTC 24 |
1479315628 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1658361054 |
|
|
Oct 09 01:00:41 PM UTC 24 |
Oct 09 01:02:07 PM UTC 24 |
5315149226 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.580191563 |
|
|
Oct 09 12:58:49 PM UTC 24 |
Oct 09 01:02:11 PM UTC 24 |
5649007722 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.1763937315 |
|
|
Oct 09 01:01:47 PM UTC 24 |
Oct 09 01:02:24 PM UTC 24 |
2851925541 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_bijection.3739291750 |
|
|
Oct 09 12:37:35 PM UTC 24 |
Oct 09 01:02:26 PM UTC 24 |
66741107148 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.482396729 |
|
|
Oct 09 01:02:25 PM UTC 24 |
Oct 09 01:02:31 PM UTC 24 |
1773816113 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.1674369479 |
|
|
Oct 09 01:01:44 PM UTC 24 |
Oct 09 01:02:38 PM UTC 24 |
3202355139 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_smoke.844535966 |
|
|
Oct 09 01:00:51 PM UTC 24 |
Oct 09 01:02:46 PM UTC 24 |
3813889330 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_readback_err.3897380148 |
|
|
Oct 09 01:02:39 PM UTC 24 |
Oct 09 01:02:48 PM UTC 24 |
971718326 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.2588490324 |
|
|
Oct 09 01:00:56 PM UTC 24 |
Oct 09 01:03:20 PM UTC 24 |
12260986215 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_alert_test.133891580 |
|
|
Oct 09 01:03:22 PM UTC 24 |
Oct 09 01:03:24 PM UTC 24 |
27293802 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.4086072939 |
|
|
Oct 09 12:56:10 PM UTC 24 |
Oct 09 01:03:24 PM UTC 24 |
5505289528 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.2216316117 |
|
|
Oct 09 01:02:46 PM UTC 24 |
Oct 09 01:03:25 PM UTC 24 |
8095651213 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_regwen.3011745003 |
|
|
Oct 09 12:51:14 PM UTC 24 |
Oct 09 01:04:02 PM UTC 24 |
2957245701 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.1833143634 |
|
|
Oct 09 12:50:13 PM UTC 24 |
Oct 09 01:04:02 PM UTC 24 |
6167865368 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.2253745935 |
|
|
Oct 09 12:52:13 PM UTC 24 |
Oct 09 01:04:08 PM UTC 24 |
44240923021 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.3798146143 |
|
|
Oct 09 12:34:56 PM UTC 24 |
Oct 09 01:04:12 PM UTC 24 |
47669039355 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_smoke.2220081032 |
|
|
Oct 09 01:03:25 PM UTC 24 |
Oct 09 01:04:14 PM UTC 24 |
1637434727 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.248464205 |
|
|
Oct 09 01:04:13 PM UTC 24 |
Oct 09 01:04:33 PM UTC 24 |
2944576061 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access.3700291158 |
|
|
Oct 09 01:04:03 PM UTC 24 |
Oct 09 01:05:02 PM UTC 24 |
1127420843 ps |
| T87 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.3035264724 |
|
|
Oct 09 01:02:31 PM UTC 24 |
Oct 09 01:05:50 PM UTC 24 |
4855743611 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.3338152190 |
|
|
Oct 09 01:02:27 PM UTC 24 |
Oct 09 01:06:00 PM UTC 24 |
18788640435 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.636099460 |
|
|
Oct 09 01:06:01 PM UTC 24 |
Oct 09 01:06:08 PM UTC 24 |
371812475 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.1510502078 |
|
|
Oct 09 01:04:15 PM UTC 24 |
Oct 09 01:06:08 PM UTC 24 |
848377612 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.85794617 |
|
|
Oct 09 12:56:21 PM UTC 24 |
Oct 09 01:06:09 PM UTC 24 |
20286725676 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_readback_err.3819679222 |
|
|
Oct 09 01:06:10 PM UTC 24 |
Oct 09 01:06:23 PM UTC 24 |
4699423399 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.699748128 |
|
|
Oct 09 01:04:34 PM UTC 24 |
Oct 09 01:06:39 PM UTC 24 |
140936022521 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_bijection.3547276451 |
|
|
Oct 09 12:18:19 PM UTC 24 |
Oct 09 01:06:41 PM UTC 24 |
230209032680 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_alert_test.3424623039 |
|
|
Oct 09 01:06:42 PM UTC 24 |
Oct 09 01:06:44 PM UTC 24 |
40972540 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.38771028 |
|
|
Oct 09 01:06:23 PM UTC 24 |
Oct 09 01:07:02 PM UTC 24 |
4445978335 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_smoke.956717682 |
|
|
Oct 09 01:06:45 PM UTC 24 |
Oct 09 01:07:04 PM UTC 24 |
1114868314 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_bijection.362467284 |
|
|
Oct 09 12:52:35 PM UTC 24 |
Oct 09 01:07:15 PM UTC 24 |
154552443928 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.2950748727 |
|
|
Oct 09 01:00:25 PM UTC 24 |
Oct 09 01:07:30 PM UTC 24 |
39012256477 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.3615066568 |
|
|
Oct 09 12:59:28 PM UTC 24 |
Oct 09 01:07:50 PM UTC 24 |
20915894890 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access.3217654851 |
|
|
Oct 09 01:07:30 PM UTC 24 |
Oct 09 01:07:51 PM UTC 24 |
1163370386 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.3754327568 |
|
|
Oct 09 01:06:09 PM UTC 24 |
Oct 09 01:07:58 PM UTC 24 |
40989110770 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_executable.4102975167 |
|
|
Oct 09 12:54:07 PM UTC 24 |
Oct 09 01:08:02 PM UTC 24 |
8981575814 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.4205249403 |
|
|
Oct 09 01:07:53 PM UTC 24 |
Oct 09 01:08:09 PM UTC 24 |
2894861198 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.880770559 |
|
|
Oct 09 01:03:25 PM UTC 24 |
Oct 09 01:08:39 PM UTC 24 |
31762029047 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_executable.1939743350 |
|
|
Oct 09 01:05:03 PM UTC 24 |
Oct 09 01:08:40 PM UTC 24 |
4310021744 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_executable.2289936234 |
|
|
Oct 09 12:51:13 PM UTC 24 |
Oct 09 01:08:44 PM UTC 24 |
19195567225 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.2883655923 |
|
|
Oct 09 01:08:45 PM UTC 24 |
Oct 09 01:08:52 PM UTC 24 |
1403433181 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.1168837789 |
|
|
Oct 09 01:04:02 PM UTC 24 |
Oct 09 01:08:56 PM UTC 24 |
2721772039 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.2028511621 |
|
|
Oct 09 01:08:03 PM UTC 24 |
Oct 09 01:09:09 PM UTC 24 |
21524071822 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_readback_err.2413425435 |
|
|
Oct 09 01:09:11 PM UTC 24 |
Oct 09 01:09:24 PM UTC 24 |
1419383034 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_bijection.203248631 |
|
|
Oct 09 12:35:07 PM UTC 24 |
Oct 09 01:09:29 PM UTC 24 |
37996187174 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.759891078 |
|
|
Oct 09 01:07:59 PM UTC 24 |
Oct 09 01:09:30 PM UTC 24 |
2973510039 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_alert_test.1147331785 |
|
|
Oct 09 01:09:32 PM UTC 24 |
Oct 09 01:09:34 PM UTC 24 |
24430328 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_bijection.570724847 |
|
|
Oct 09 12:20:14 PM UTC 24 |
Oct 09 01:09:43 PM UTC 24 |
524261788869 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.2574504958 |
|
|
Oct 09 01:00:51 PM UTC 24 |
Oct 09 01:10:05 PM UTC 24 |
10780019754 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.3648630840 |
|
|
Oct 09 01:08:57 PM UTC 24 |
Oct 09 01:10:08 PM UTC 24 |
1033333078 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_smoke.3405265143 |
|
|
Oct 09 01:09:35 PM UTC 24 |
Oct 09 01:10:29 PM UTC 24 |
15845748810 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_bijection.3083576266 |
|
|
Oct 09 12:58:45 PM UTC 24 |
Oct 09 01:11:05 PM UTC 24 |
36214940161 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_bijection.938362602 |
|
|
Oct 09 12:32:27 PM UTC 24 |
Oct 09 01:11:08 PM UTC 24 |
33236099217 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_smoke.132199132 |
|
|
Oct 09 01:12:28 PM UTC 24 |
Oct 09 01:12:48 PM UTC 24 |
1616906908 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.2120839005 |
|
|
Oct 09 01:11:06 PM UTC 24 |
Oct 09 01:11:21 PM UTC 24 |
681154613 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.3323164731 |
|
|
Oct 09 01:11:09 PM UTC 24 |
Oct 09 01:11:24 PM UTC 24 |
1449144740 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.968311077 |
|
|
Oct 09 01:07:16 PM UTC 24 |
Oct 09 01:11:27 PM UTC 24 |
13991279046 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_regwen.3305077396 |
|
|
Oct 09 01:00:16 PM UTC 24 |
Oct 09 01:11:39 PM UTC 24 |
56192916653 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access.1705211472 |
|
|
Oct 09 01:10:09 PM UTC 24 |
Oct 09 01:11:39 PM UTC 24 |
870905235 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.3434899781 |
|
|
Oct 09 01:04:10 PM UTC 24 |
Oct 09 01:11:40 PM UTC 24 |
21913920671 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.590645392 |
|
|
Oct 09 01:11:40 PM UTC 24 |
Oct 09 01:11:47 PM UTC 24 |
377275150 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.4235117709 |
|
|
Oct 09 01:06:09 PM UTC 24 |
Oct 09 01:11:53 PM UTC 24 |
20730750350 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_readback_err.2579481883 |
|
|
Oct 09 01:11:54 PM UTC 24 |
Oct 09 01:12:05 PM UTC 24 |
1171165749 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.1158813598 |
|
|
Oct 09 01:11:22 PM UTC 24 |
Oct 09 01:12:22 PM UTC 24 |
10399985471 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.3203865979 |
|
|
Oct 09 01:12:06 PM UTC 24 |
Oct 09 01:12:23 PM UTC 24 |
1204482051 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_alert_test.3569946963 |
|
|
Oct 09 01:12:25 PM UTC 24 |
Oct 09 01:12:27 PM UTC 24 |
17149687 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.4248014912 |
|
|
Oct 09 01:09:26 PM UTC 24 |
Oct 09 01:12:30 PM UTC 24 |
16823829950 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.1713912020 |
|
|
Oct 09 01:01:29 PM UTC 24 |
Oct 09 01:12:31 PM UTC 24 |
23143062113 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.2984351512 |
|
|
Oct 09 01:07:03 PM UTC 24 |
Oct 09 01:12:55 PM UTC 24 |
6293420367 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_regwen.3760646217 |
|
|
Oct 09 01:05:51 PM UTC 24 |
Oct 09 01:13:18 PM UTC 24 |
10408681847 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access.4159460942 |
|
|
Oct 09 01:12:55 PM UTC 24 |
Oct 09 01:13:26 PM UTC 24 |
5441887390 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_executable.4085129634 |
|
|
Oct 09 01:02:08 PM UTC 24 |
Oct 09 01:13:57 PM UTC 24 |
16835388161 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.928331534 |
|
|
Oct 09 01:08:53 PM UTC 24 |
Oct 09 01:13:58 PM UTC 24 |
3947959546 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.1444777990 |
|
|
Oct 09 01:08:10 PM UTC 24 |
Oct 09 01:14:09 PM UTC 24 |
27981758341 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.3663871360 |
|
|
Oct 09 01:13:59 PM UTC 24 |
Oct 09 01:14:16 PM UTC 24 |
4212949998 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.1998260157 |
|
|
Oct 09 01:13:58 PM UTC 24 |
Oct 09 01:14:25 PM UTC 24 |
731520296 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.2417804192 |
|
|
Oct 09 01:13:28 PM UTC 24 |
Oct 09 01:14:40 PM UTC 24 |
3112534202 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.2782252316 |
|
|
Oct 09 01:11:48 PM UTC 24 |
Oct 09 01:14:45 PM UTC 24 |
20914768298 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.3135281578 |
|
|
Oct 09 01:14:41 PM UTC 24 |
Oct 09 01:14:47 PM UTC 24 |
1349221566 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.2049986303 |
|
|
Oct 09 01:10:06 PM UTC 24 |
Oct 09 01:15:14 PM UTC 24 |
4255253091 ps |
| T152 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_executable.842678599 |
|
|
Oct 09 12:57:20 PM UTC 24 |
Oct 09 01:15:17 PM UTC 24 |
254520171099 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_executable.313672549 |
|
|
Oct 09 12:59:54 PM UTC 24 |
Oct 09 01:15:20 PM UTC 24 |
34563739696 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_readback_err.2123330939 |
|
|
Oct 09 01:15:14 PM UTC 24 |
Oct 09 01:15:25 PM UTC 24 |
2642073342 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_alert_test.773652763 |
|
|
Oct 09 01:15:26 PM UTC 24 |
Oct 09 01:15:28 PM UTC 24 |
15273095 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_smoke.3488889629 |
|
|
Oct 09 01:15:29 PM UTC 24 |
Oct 09 01:16:15 PM UTC 24 |
16224192053 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.129534516 |
|
|
Oct 09 01:14:48 PM UTC 24 |
Oct 09 01:16:24 PM UTC 24 |
16731554657 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.846022014 |
|
|
Oct 09 01:07:51 PM UTC 24 |
Oct 09 01:16:35 PM UTC 24 |
16803367326 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.3262266412 |
|
|
Oct 09 12:58:42 PM UTC 24 |
Oct 09 01:17:20 PM UTC 24 |
76913726583 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.441279415 |
|
|
Oct 09 01:11:41 PM UTC 24 |
Oct 09 01:17:42 PM UTC 24 |
21886461053 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.796134371 |
|
|
Oct 09 01:14:46 PM UTC 24 |
Oct 09 01:17:47 PM UTC 24 |
18702556657 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.1054484584 |
|
|
Oct 09 01:15:18 PM UTC 24 |
Oct 09 01:18:01 PM UTC 24 |
4587041796 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.639291973 |
|
|
Oct 09 01:10:30 PM UTC 24 |
Oct 09 01:18:07 PM UTC 24 |
28556793501 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access.229873568 |
|
|
Oct 09 01:17:21 PM UTC 24 |
Oct 09 01:18:08 PM UTC 24 |
7082674077 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.1273295806 |
|
|
Oct 09 01:18:09 PM UTC 24 |
Oct 09 01:18:14 PM UTC 24 |
717384058 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.579188301 |
|
|
Oct 09 01:17:48 PM UTC 24 |
Oct 09 01:18:20 PM UTC 24 |
7040188662 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_readback_err.498604025 |
|
|
Oct 09 01:18:21 PM UTC 24 |
Oct 09 01:18:30 PM UTC 24 |
684981590 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_executable.2438450101 |
|
|
Oct 09 01:11:28 PM UTC 24 |
Oct 09 01:18:30 PM UTC 24 |
15785487711 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_alert_test.318925373 |
|
|
Oct 09 01:18:30 PM UTC 24 |
Oct 09 01:18:32 PM UTC 24 |
37812867 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.401057634 |
|
|
Oct 09 01:12:49 PM UTC 24 |
Oct 09 01:18:34 PM UTC 24 |
19759118535 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.22868925 |
|
|
Oct 09 01:18:01 PM UTC 24 |
Oct 09 01:18:42 PM UTC 24 |
6087844084 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3656125894 |
|
|
Oct 09 01:18:27 PM UTC 24 |
Oct 09 01:18:59 PM UTC 24 |
2108747239 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_bijection.995908162 |
|
|
Oct 09 12:50:15 PM UTC 24 |
Oct 09 01:19:13 PM UTC 24 |
116799799811 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.3902300523 |
|
|
Oct 09 01:17:51 PM UTC 24 |
Oct 09 01:19:23 PM UTC 24 |
3211663977 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_smoke.1080803819 |
|
|
Oct 09 01:18:33 PM UTC 24 |
Oct 09 01:19:25 PM UTC 24 |
1087482322 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.2881893982 |
|
|
Oct 09 01:19:25 PM UTC 24 |
Oct 09 01:19:32 PM UTC 24 |
357039612 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.1564200039 |
|
|
Oct 09 01:18:48 PM UTC 24 |
Oct 09 01:19:33 PM UTC 24 |
3074904884 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access.3470870361 |
|
|
Oct 09 01:18:42 PM UTC 24 |
Oct 09 01:19:34 PM UTC 24 |
2040779035 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.481774887 |
|
|
Oct 09 01:14:10 PM UTC 24 |
Oct 09 01:19:40 PM UTC 24 |
19689395504 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_readback_err.926147183 |
|
|
Oct 09 01:19:34 PM UTC 24 |
Oct 09 01:19:46 PM UTC 24 |
1362422769 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.1446347906 |
|
|
Oct 09 01:19:00 PM UTC 24 |
Oct 09 01:19:46 PM UTC 24 |
43970757087 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_alert_test.1064801051 |
|
|
Oct 09 01:19:45 PM UTC 24 |
Oct 09 01:19:47 PM UTC 24 |
15713640 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.536802619 |
|
|
Oct 09 01:19:35 PM UTC 24 |
Oct 09 01:20:16 PM UTC 24 |
2147970012 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_smoke.1663360457 |
|
|
Oct 09 01:19:46 PM UTC 24 |
Oct 09 01:20:19 PM UTC 24 |
5823059932 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.1931837852 |
|
|
Oct 09 01:20:21 PM UTC 24 |
Oct 09 01:20:34 PM UTC 24 |
6041302369 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access.400811841 |
|
|
Oct 09 01:20:15 PM UTC 24 |
Oct 09 01:20:36 PM UTC 24 |
2169449820 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.388759586 |
|
|
Oct 09 01:18:15 PM UTC 24 |
Oct 09 01:20:44 PM UTC 24 |
11628553163 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.1789573997 |
|
|
Oct 09 01:20:21 PM UTC 24 |
Oct 09 01:20:52 PM UTC 24 |
709157736 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.387007306 |
|
|
Oct 09 01:20:46 PM UTC 24 |
Oct 09 01:20:53 PM UTC 24 |
1305156683 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.1231782179 |
|
|
Oct 09 01:18:45 PM UTC 24 |
Oct 09 01:21:01 PM UTC 24 |
12690265967 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_regwen.723440151 |
|
|
Oct 09 01:02:13 PM UTC 24 |
Oct 09 01:21:06 PM UTC 24 |
84672638065 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_readback_err.3897832021 |
|
|
Oct 09 01:21:03 PM UTC 24 |
Oct 09 01:21:13 PM UTC 24 |
2870910171 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.3675266050 |
|
|
Oct 09 01:19:33 PM UTC 24 |
Oct 09 01:21:20 PM UTC 24 |
10714053284 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_alert_test.689851467 |
|
|
Oct 09 01:21:20 PM UTC 24 |
Oct 09 01:21:22 PM UTC 24 |
24950231 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.3419369423 |
|
|
Oct 09 01:18:35 PM UTC 24 |
Oct 09 01:21:33 PM UTC 24 |
5813330118 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.632026948 |
|
|
Oct 09 01:04:36 PM UTC 24 |
Oct 09 01:21:42 PM UTC 24 |
56593184323 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.4252304314 |
|
|
Oct 09 01:21:07 PM UTC 24 |
Oct 09 01:21:53 PM UTC 24 |
1366639848 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_smoke.1795804757 |
|
|
Oct 09 01:21:21 PM UTC 24 |
Oct 09 01:21:53 PM UTC 24 |
5632638119 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.56441068 |
|
|
Oct 09 01:17:43 PM UTC 24 |
Oct 09 01:22:02 PM UTC 24 |
22643776365 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.437982412 |
|
|
Oct 09 01:19:47 PM UTC 24 |
Oct 09 01:23:00 PM UTC 24 |
15192230181 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access.2135820783 |
|
|
Oct 09 01:21:54 PM UTC 24 |
Oct 09 01:22:14 PM UTC 24 |
419813389 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.1529461621 |
|
|
Oct 09 01:16:36 PM UTC 24 |
Oct 09 01:22:20 PM UTC 24 |
17248068936 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.2233747004 |
|
|
Oct 09 01:22:14 PM UTC 24 |
Oct 09 01:22:26 PM UTC 24 |
3022869125 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.3904633110 |
|
|
Oct 09 01:20:29 PM UTC 24 |
Oct 09 01:22:38 PM UTC 24 |
12202268142 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.4283046853 |
|
|
Oct 09 01:13:19 PM UTC 24 |
Oct 09 01:22:43 PM UTC 24 |
22730916182 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.3753301572 |
|
|
Oct 09 01:23:00 PM UTC 24 |
Oct 09 01:23:06 PM UTC 24 |
354397314 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_regwen.598173548 |
|
|
Oct 09 01:20:36 PM UTC 24 |
Oct 09 01:23:24 PM UTC 24 |
17782719387 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.2699859185 |
|
|
Oct 09 01:22:03 PM UTC 24 |
Oct 09 01:23:34 PM UTC 24 |
1534602855 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.1603865637 |
|
|
Oct 09 01:19:06 PM UTC 24 |
Oct 09 01:23:36 PM UTC 24 |
6793251160 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_readback_err.3584536669 |
|
|
Oct 09 01:23:35 PM UTC 24 |
Oct 09 01:23:47 PM UTC 24 |
680564625 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.2795297381 |
|
|
Oct 09 01:20:55 PM UTC 24 |
Oct 09 01:23:54 PM UTC 24 |
10269696054 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_alert_test.2403116789 |
|
|
Oct 09 01:23:54 PM UTC 24 |
Oct 09 01:23:56 PM UTC 24 |
79105671 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.409265706 |
|
|
Oct 09 01:09:36 PM UTC 24 |
Oct 09 01:23:57 PM UTC 24 |
99944938037 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.1766860441 |
|
|
Oct 09 01:19:30 PM UTC 24 |
Oct 09 01:24:03 PM UTC 24 |
4109907552 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.893076762 |
|
|
Oct 09 01:18:11 PM UTC 24 |
Oct 09 01:24:06 PM UTC 24 |
82760795829 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.2313430676 |
|
|
Oct 09 01:21:43 PM UTC 24 |
Oct 09 01:24:33 PM UTC 24 |
18923877460 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_smoke.1595192989 |
|
|
Oct 09 01:23:57 PM UTC 24 |
Oct 09 01:24:48 PM UTC 24 |
3652721454 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access.1412570910 |
|
|
Oct 09 01:24:34 PM UTC 24 |
Oct 09 01:24:49 PM UTC 24 |
741310964 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.2281926948 |
|
|
Oct 09 01:22:20 PM UTC 24 |
Oct 09 01:24:53 PM UTC 24 |
218238590706 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.1240849072 |
|
|
Oct 09 01:19:54 PM UTC 24 |
Oct 09 01:25:04 PM UTC 24 |
11946047882 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.3575016472 |
|
|
Oct 09 01:24:54 PM UTC 24 |
Oct 09 01:25:07 PM UTC 24 |
1583105494 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.2423267363 |
|
|
Oct 09 01:01:59 PM UTC 24 |
Oct 09 01:25:08 PM UTC 24 |
69318534342 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.1404946210 |
|
|
Oct 09 01:23:37 PM UTC 24 |
Oct 09 01:25:11 PM UTC 24 |
2677050922 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.2162925352 |
|
|
Oct 09 01:24:50 PM UTC 24 |
Oct 09 01:25:53 PM UTC 24 |
768876397 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.2394716610 |
|
|
Oct 09 01:20:16 PM UTC 24 |
Oct 09 01:26:01 PM UTC 24 |
44875119628 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.1113482470 |
|
|
Oct 09 01:25:53 PM UTC 24 |
Oct 09 01:26:01 PM UTC 24 |
4770214634 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_regwen.2906621060 |
|
|
Oct 09 01:11:40 PM UTC 24 |
Oct 09 01:26:03 PM UTC 24 |
42693601840 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.1779018471 |
|
|
Oct 09 01:25:05 PM UTC 24 |
Oct 09 01:26:13 PM UTC 24 |
6454054929 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_readback_err.3662995881 |
|
|
Oct 09 01:26:04 PM UTC 24 |
Oct 09 01:26:14 PM UTC 24 |
706062041 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all.3200845729 |
|
|
Oct 09 12:24:24 PM UTC 24 |
Oct 09 01:26:23 PM UTC 24 |
269165146058 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_alert_test.184435478 |
|
|
Oct 09 01:26:23 PM UTC 24 |
Oct 09 01:26:25 PM UTC 24 |
40638347 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.3350173032 |
|
|
Oct 09 01:26:14 PM UTC 24 |
Oct 09 01:26:27 PM UTC 24 |
1271980662 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.3276562162 |
|
|
Oct 09 01:23:26 PM UTC 24 |
Oct 09 01:26:42 PM UTC 24 |
19376341848 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_regwen.1250213904 |
|
|
Oct 09 01:19:24 PM UTC 24 |
Oct 09 01:26:47 PM UTC 24 |
17346805286 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_smoke.1381179945 |
|
|
Oct 09 01:26:27 PM UTC 24 |
Oct 09 01:26:50 PM UTC 24 |
8588714121 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all.298665005 |
|
|
Oct 09 12:34:24 PM UTC 24 |
Oct 09 01:26:51 PM UTC 24 |
51697481893 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_executable.2637899157 |
|
|
Oct 09 01:14:16 PM UTC 24 |
Oct 09 01:27:05 PM UTC 24 |
17630660023 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.3489415227 |
|
|
Oct 09 01:18:03 PM UTC 24 |
Oct 09 01:27:06 PM UTC 24 |
7467943641 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access.2309232482 |
|
|
Oct 09 01:26:51 PM UTC 24 |
Oct 09 01:27:09 PM UTC 24 |
531224848 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.1878511778 |
|
|
Oct 09 01:26:03 PM UTC 24 |
Oct 09 01:27:30 PM UTC 24 |
6032135519 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.4002278828 |
|
|
Oct 09 01:27:07 PM UTC 24 |
Oct 09 01:27:41 PM UTC 24 |
2940342499 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.2741305137 |
|
|
Oct 09 01:23:06 PM UTC 24 |
Oct 09 01:27:44 PM UTC 24 |
33302342903 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.678849540 |
|
|
Oct 09 01:27:07 PM UTC 24 |
Oct 09 01:28:00 PM UTC 24 |
1544634795 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.1914971839 |
|
|
Oct 09 01:28:01 PM UTC 24 |
Oct 09 01:28:08 PM UTC 24 |
941877301 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.2042497970 |
|
|
Oct 09 01:26:01 PM UTC 24 |
Oct 09 01:28:12 PM UTC 24 |
2023178462 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.4193998893 |
|
|
Oct 09 01:27:10 PM UTC 24 |
Oct 09 01:28:16 PM UTC 24 |
21855442974 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_readback_err.2755881007 |
|
|
Oct 09 01:28:18 PM UTC 24 |
Oct 09 01:28:28 PM UTC 24 |
1384663922 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.2566670984 |
|
|
Oct 09 01:20:53 PM UTC 24 |
Oct 09 01:28:34 PM UTC 24 |
36339570788 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.3353551966 |
|
|
Oct 09 01:28:29 PM UTC 24 |
Oct 09 01:28:42 PM UTC 24 |
1288312754 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_alert_test.363915246 |
|
|
Oct 09 01:28:43 PM UTC 24 |
Oct 09 01:28:45 PM UTC 24 |
37668093 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_smoke.1797324538 |
|
|
Oct 09 01:28:46 PM UTC 24 |
Oct 09 01:29:07 PM UTC 24 |
3469182938 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.3327045574 |
|
|
Oct 09 01:24:49 PM UTC 24 |
Oct 09 01:29:25 PM UTC 24 |
25916519265 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_regwen.4056931932 |
|
|
Oct 09 01:14:25 PM UTC 24 |
Oct 09 01:29:34 PM UTC 24 |
25315296595 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.2600152609 |
|
|
Oct 09 01:18:42 PM UTC 24 |
Oct 09 01:29:34 PM UTC 24 |
81623102672 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_bijection.1132590672 |
|
|
Oct 09 01:12:32 PM UTC 24 |
Oct 09 01:29:45 PM UTC 24 |
28020095971 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access.3354794623 |
|
|
Oct 09 01:29:35 PM UTC 24 |
Oct 09 01:29:53 PM UTC 24 |
392502466 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.2341905134 |
|
|
Oct 09 01:24:07 PM UTC 24 |
Oct 09 01:30:18 PM UTC 24 |
8738989395 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_regwen.2009411146 |
|
|
Oct 09 01:27:45 PM UTC 24 |
Oct 09 01:30:18 PM UTC 24 |
14514518908 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.1618835901 |
|
|
Oct 09 01:30:18 PM UTC 24 |
Oct 09 01:30:31 PM UTC 24 |
2713838203 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.3728233675 |
|
|
Oct 09 01:29:54 PM UTC 24 |
Oct 09 01:30:43 PM UTC 24 |
725287995 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_executable.2309966342 |
|
|
Oct 09 01:08:40 PM UTC 24 |
Oct 09 01:30:53 PM UTC 24 |
12540003165 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.3984671951 |
|
|
Oct 09 01:21:54 PM UTC 24 |
Oct 09 01:30:57 PM UTC 24 |
150309161999 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.306778451 |
|
|
Oct 09 01:30:58 PM UTC 24 |
Oct 09 01:31:04 PM UTC 24 |
347292880 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.1941018362 |
|
|
Oct 09 01:28:13 PM UTC 24 |
Oct 09 01:31:05 PM UTC 24 |
4919846834 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.2530433192 |
|
|
Oct 09 01:23:57 PM UTC 24 |
Oct 09 01:31:15 PM UTC 24 |
29006116835 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.307761452 |
|
|
Oct 09 01:26:48 PM UTC 24 |
Oct 09 01:31:24 PM UTC 24 |
31059576437 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_readback_err.3346899986 |
|
|
Oct 09 01:31:17 PM UTC 24 |
Oct 09 01:31:29 PM UTC 24 |
681900249 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.2710515330 |
|
|
Oct 09 01:30:20 PM UTC 24 |
Oct 09 01:32:05 PM UTC 24 |
17464863659 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_alert_test.136279172 |
|
|
Oct 09 01:32:06 PM UTC 24 |
Oct 09 01:32:08 PM UTC 24 |
20412674 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_smoke.4182851450 |
|
|
Oct 09 01:32:09 PM UTC 24 |
Oct 09 01:32:21 PM UTC 24 |
1770771756 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_bijection.2493175647 |
|
|
Oct 09 01:03:26 PM UTC 24 |
Oct 09 01:32:27 PM UTC 24 |
193407604673 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.924317494 |
|
|
Oct 09 01:31:26 PM UTC 24 |
Oct 09 01:32:27 PM UTC 24 |
7876020009 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.3090925697 |
|
|
Oct 09 01:31:06 PM UTC 24 |
Oct 09 01:33:00 PM UTC 24 |
2769205672 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.635198170 |
|
|
Oct 09 01:22:27 PM UTC 24 |
Oct 09 01:33:02 PM UTC 24 |
49328064727 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_executable.2110402530 |
|
|
Oct 09 01:25:09 PM UTC 24 |
Oct 09 01:33:20 PM UTC 24 |
14093469524 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_executable.2001003542 |
|
|
Oct 09 01:30:44 PM UTC 24 |
Oct 09 01:33:29 PM UTC 24 |
3954543758 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.4222881967 |
|
|
Oct 09 01:12:31 PM UTC 24 |
Oct 09 01:33:32 PM UTC 24 |
7598312066 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.4120791181 |
|
|
Oct 09 01:33:21 PM UTC 24 |
Oct 09 01:33:41 PM UTC 24 |
710986918 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.434158181 |
|
|
Oct 09 01:18:34 PM UTC 24 |
Oct 09 01:33:49 PM UTC 24 |
68563903236 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all.1919714224 |
|
|
Oct 09 01:06:40 PM UTC 24 |
Oct 09 01:33:56 PM UTC 24 |
56670847279 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.417228273 |
|
|
Oct 09 01:27:32 PM UTC 24 |
Oct 09 01:33:57 PM UTC 24 |
8104953019 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.1087361415 |
|
|
Oct 09 01:31:05 PM UTC 24 |
Oct 09 01:34:01 PM UTC 24 |
4034039196 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.3646098517 |
|
|
Oct 09 01:33:58 PM UTC 24 |
Oct 09 01:34:05 PM UTC 24 |
353944103 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.3026747374 |
|
|
Oct 09 01:26:51 PM UTC 24 |
Oct 09 01:34:07 PM UTC 24 |
28983464035 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_bijection.1683703536 |
|
|
Oct 09 01:21:34 PM UTC 24 |
Oct 09 01:34:14 PM UTC 24 |
328319644944 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_readback_err.298845608 |
|
|
Oct 09 01:34:09 PM UTC 24 |
Oct 09 01:34:20 PM UTC 24 |
1376035041 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.2232216359 |
|
|
Oct 09 01:34:15 PM UTC 24 |
Oct 09 01:34:32 PM UTC 24 |
603564127 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_alert_test.1943173546 |
|
|
Oct 09 01:34:33 PM UTC 24 |
Oct 09 01:34:36 PM UTC 24 |
19729074 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access.3283685727 |
|
|
Oct 09 01:33:01 PM UTC 24 |
Oct 09 01:34:44 PM UTC 24 |
1898197239 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_smoke.2104333118 |
|
|
Oct 09 01:34:36 PM UTC 24 |
Oct 09 01:34:49 PM UTC 24 |
402850749 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.3205409251 |
|
|
Oct 09 01:33:32 PM UTC 24 |
Oct 09 01:34:51 PM UTC 24 |
10126197117 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.3912743858 |
|
|
Oct 09 01:29:08 PM UTC 24 |
Oct 09 01:34:56 PM UTC 24 |
3514870638 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.1173991535 |
|
|
Oct 09 01:29:35 PM UTC 24 |
Oct 09 01:35:08 PM UTC 24 |
8998753128 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.4285149667 |
|
|
Oct 09 01:33:29 PM UTC 24 |
Oct 09 01:35:12 PM UTC 24 |
789107389 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.3787762848 |
|
|
Oct 09 01:11:25 PM UTC 24 |
Oct 09 01:35:16 PM UTC 24 |
16002570186 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.1474279386 |
|
|
Oct 09 01:28:09 PM UTC 24 |
Oct 09 01:35:16 PM UTC 24 |
37372771671 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access.3848550342 |
|
|
Oct 09 01:34:57 PM UTC 24 |
Oct 09 01:35:19 PM UTC 24 |
1942007058 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_bijection.1335826320 |
|
|
Oct 09 01:00:55 PM UTC 24 |
Oct 09 01:35:26 PM UTC 24 |
33565815909 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.94487761 |
|
|
Oct 09 01:29:46 PM UTC 24 |
Oct 09 01:35:32 PM UTC 24 |
56248948816 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_executable.512146617 |
|
|
Oct 09 01:19:14 PM UTC 24 |
Oct 09 01:35:34 PM UTC 24 |
21301598771 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.3283154644 |
|
|
Oct 09 01:35:34 PM UTC 24 |
Oct 09 01:35:41 PM UTC 24 |
351719022 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all.3144713485 |
|
|
Oct 09 12:44:13 PM UTC 24 |
Oct 09 01:35:42 PM UTC 24 |
122678633695 ps |
| T88 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.1800698412 |
|
|
Oct 09 01:34:05 PM UTC 24 |
Oct 09 01:35:45 PM UTC 24 |
2666297479 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.1073183259 |
|
|
Oct 09 01:32:28 PM UTC 24 |
Oct 09 01:35:48 PM UTC 24 |
2459401330 ps |
| T34 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_readback_err.3171474523 |
|
|
Oct 09 01:35:46 PM UTC 24 |
Oct 09 01:35:56 PM UTC 24 |
2754234532 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_bijection.3526848623 |
|
|
Oct 09 01:18:34 PM UTC 24 |
Oct 09 01:36:13 PM UTC 24 |
15288665856 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_alert_test.1198405241 |
|
|
Oct 09 01:36:14 PM UTC 24 |
Oct 09 01:36:17 PM UTC 24 |
14479632 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.1836795659 |
|
|
Oct 09 01:35:17 PM UTC 24 |
Oct 09 01:36:18 PM UTC 24 |
1547480248 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all.1857385962 |
|
|
Oct 09 12:41:12 PM UTC 24 |
Oct 09 01:36:31 PM UTC 24 |
102196379827 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_bijection.117732389 |
|
|
Oct 09 12:56:08 PM UTC 24 |
Oct 09 01:36:34 PM UTC 24 |
149355677636 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.2154933570 |
|
|
Oct 09 01:35:17 PM UTC 24 |
Oct 09 01:36:35 PM UTC 24 |
12542079661 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access.3195779877 |
|
|
Oct 09 01:36:36 PM UTC 24 |
Oct 09 01:36:44 PM UTC 24 |
1471747060 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.1054289384 |
|
|
Oct 09 01:35:12 PM UTC 24 |
Oct 09 01:36:54 PM UTC 24 |
2314280709 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.692877332 |
|
|
Oct 09 01:35:49 PM UTC 24 |
Oct 09 01:37:01 PM UTC 24 |
4186514751 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.2129235477 |
|
|
Oct 09 01:35:43 PM UTC 24 |
Oct 09 01:37:09 PM UTC 24 |
6239192404 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_smoke.2954513013 |
|
|
Oct 09 01:36:17 PM UTC 24 |
Oct 09 01:37:20 PM UTC 24 |
4782310405 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.3637964955 |
|
|
Oct 09 01:20:34 PM UTC 24 |
Oct 09 01:37:20 PM UTC 24 |
44943893103 ps |