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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.64 99.50 96.05 99.72 100.00 97.34 99.13 98.72


Total test records in report: 1083
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1017 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3829518795 Oct 09 10:10:02 AM UTC 24 Oct 09 10:10:05 AM UTC 24 187971830 ps
T136 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3617171327 Oct 09 10:10:02 AM UTC 24 Oct 09 10:10:07 AM UTC 24 328563513 ps
T1018 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.641867704 Oct 09 10:10:05 AM UTC 24 Oct 09 10:10:07 AM UTC 24 26761921 ps
T1019 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2150492146 Oct 09 10:10:02 AM UTC 24 Oct 09 10:10:08 AM UTC 24 140921441 ps
T1020 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1656703668 Oct 09 10:10:03 AM UTC 24 Oct 09 10:10:09 AM UTC 24 343805055 ps
T141 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.996520004 Oct 09 10:10:05 AM UTC 24 Oct 09 10:10:10 AM UTC 24 642893691 ps
T1021 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.100702783 Oct 09 10:10:09 AM UTC 24 Oct 09 10:10:11 AM UTC 24 16535271 ps
T1022 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2807990673 Oct 09 10:10:12 AM UTC 24 Oct 09 10:10:14 AM UTC 24 13516754 ps
T1023 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.4214343831 Oct 09 10:10:05 AM UTC 24 Oct 09 10:10:14 AM UTC 24 473316906 ps
T1024 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3279829348 Oct 09 10:10:09 AM UTC 24 Oct 09 10:10:14 AM UTC 24 706235468 ps
T1025 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1742890441 Oct 09 10:10:10 AM UTC 24 Oct 09 10:10:15 AM UTC 24 256874634 ps
T139 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.4276213026 Oct 09 10:10:11 AM UTC 24 Oct 09 10:10:15 AM UTC 24 143940945 ps
T1026 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1844218162 Oct 09 10:10:15 AM UTC 24 Oct 09 10:10:17 AM UTC 24 27157311 ps
T80 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3323368548 Oct 09 10:09:41 AM UTC 24 Oct 09 10:10:18 AM UTC 24 3958653570 ps
T1027 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1664045756 Oct 09 10:10:18 AM UTC 24 Oct 09 10:10:20 AM UTC 24 24048291 ps
T1028 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1762106153 Oct 09 10:10:20 AM UTC 24 Oct 09 10:10:22 AM UTC 24 16086625 ps
T1029 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1776798575 Oct 09 10:10:15 AM UTC 24 Oct 09 10:10:22 AM UTC 24 1045866224 ps
T1030 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.542465941 Oct 09 10:10:16 AM UTC 24 Oct 09 10:10:23 AM UTC 24 71236300 ps
T81 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1378274002 Oct 09 10:09:29 AM UTC 24 Oct 09 10:10:26 AM UTC 24 7417222654 ps
T1031 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3177054894 Oct 09 10:10:24 AM UTC 24 Oct 09 10:10:26 AM UTC 24 35076625 ps
T1032 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.786648023 Oct 09 10:10:24 AM UTC 24 Oct 09 10:10:26 AM UTC 24 50693699 ps
T142 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1386368646 Oct 09 10:10:23 AM UTC 24 Oct 09 10:10:26 AM UTC 24 349631499 ps
T1033 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.4142240092 Oct 09 10:10:21 AM UTC 24 Oct 09 10:10:26 AM UTC 24 379364081 ps
T1034 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.4290190131 Oct 09 10:10:23 AM UTC 24 Oct 09 10:10:27 AM UTC 24 68012348 ps
T1035 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1403899382 Oct 09 10:10:28 AM UTC 24 Oct 09 10:10:30 AM UTC 24 15540672 ps
T1036 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.698272590 Oct 09 10:10:28 AM UTC 24 Oct 09 10:10:30 AM UTC 24 64592929 ps
T140 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.663380637 Oct 09 10:10:28 AM UTC 24 Oct 09 10:10:31 AM UTC 24 125998519 ps
T1037 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3714788462 Oct 09 10:10:26 AM UTC 24 Oct 09 10:10:32 AM UTC 24 706495562 ps
T82 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2795727419 Oct 09 10:09:33 AM UTC 24 Oct 09 10:10:33 AM UTC 24 14171882555 ps
T83 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1207405401 Oct 09 10:09:37 AM UTC 24 Oct 09 10:10:35 AM UTC 24 64029497295 ps
T1038 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2988684294 Oct 09 10:10:27 AM UTC 24 Oct 09 10:10:36 AM UTC 24 49971174 ps
T1039 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1501573595 Oct 09 10:10:34 AM UTC 24 Oct 09 10:10:36 AM UTC 24 27012533 ps
T90 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1473998776 Oct 09 10:10:03 AM UTC 24 Oct 09 10:10:38 AM UTC 24 15413431162 ps
T1040 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1020272231 Oct 09 10:10:31 AM UTC 24 Oct 09 10:10:38 AM UTC 24 1393631619 ps
T1041 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3535731994 Oct 09 10:10:36 AM UTC 24 Oct 09 10:10:38 AM UTC 24 47461411 ps
T143 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3348518951 Oct 09 10:10:33 AM UTC 24 Oct 09 10:10:39 AM UTC 24 2119049984 ps
T1042 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3166130129 Oct 09 10:10:32 AM UTC 24 Oct 09 10:10:39 AM UTC 24 44571436 ps
T1043 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1849677083 Oct 09 10:10:02 AM UTC 24 Oct 09 10:10:40 AM UTC 24 7578446798 ps
T1044 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3014407543 Oct 09 10:10:40 AM UTC 24 Oct 09 10:10:42 AM UTC 24 37152178 ps
T1045 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3023043768 Oct 09 10:10:40 AM UTC 24 Oct 09 10:10:42 AM UTC 24 81502142 ps
T1046 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.711406482 Oct 09 10:10:40 AM UTC 24 Oct 09 10:10:43 AM UTC 24 22173633 ps
T1047 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2776185276 Oct 09 10:10:36 AM UTC 24 Oct 09 10:10:43 AM UTC 24 1433529751 ps
T1048 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1827521790 Oct 09 10:10:40 AM UTC 24 Oct 09 10:10:44 AM UTC 24 218333560 ps
T1049 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1934130237 Oct 09 10:10:43 AM UTC 24 Oct 09 10:10:46 AM UTC 24 30502298 ps
T1050 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3423210803 Oct 09 10:10:40 AM UTC 24 Oct 09 10:10:46 AM UTC 24 655917552 ps
T1051 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1157331322 Oct 09 10:10:43 AM UTC 24 Oct 09 10:10:47 AM UTC 24 268253927 ps
T1052 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.201060318 Oct 09 10:10:44 AM UTC 24 Oct 09 10:10:47 AM UTC 24 35932526 ps
T91 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.258615662 Oct 09 10:10:09 AM UTC 24 Oct 09 10:10:47 AM UTC 24 3868419102 ps
T1053 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3435324028 Oct 09 10:10:42 AM UTC 24 Oct 09 10:10:48 AM UTC 24 39951740 ps
T137 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.472497417 Oct 09 10:10:47 AM UTC 24 Oct 09 10:10:51 AM UTC 24 1115550133 ps
T92 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2930512184 Oct 09 10:10:48 AM UTC 24 Oct 09 10:10:51 AM UTC 24 19981466 ps
T1054 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2526903326 Oct 09 10:10:48 AM UTC 24 Oct 09 10:10:51 AM UTC 24 305741484 ps
T1055 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.975959635 Oct 09 10:10:21 AM UTC 24 Oct 09 10:10:52 AM UTC 24 19474412029 ps
T1056 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3086479478 Oct 09 10:10:44 AM UTC 24 Oct 09 10:10:52 AM UTC 24 1403845673 ps
T1057 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1303043395 Oct 09 10:10:52 AM UTC 24 Oct 09 10:10:53 AM UTC 24 15895232 ps
T1058 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.493414515 Oct 09 10:10:48 AM UTC 24 Oct 09 10:10:54 AM UTC 24 713202349 ps
T1059 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1045016175 Oct 09 10:10:50 AM UTC 24 Oct 09 10:10:55 AM UTC 24 44421826 ps
T1060 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2136877368 Oct 09 10:10:53 AM UTC 24 Oct 09 10:10:55 AM UTC 24 13931919 ps
T1061 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2680605891 Oct 09 10:10:47 AM UTC 24 Oct 09 10:10:55 AM UTC 24 538964797 ps
T1062 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2593753278 Oct 09 10:10:15 AM UTC 24 Oct 09 10:10:55 AM UTC 24 3864266646 ps
T1063 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2759402331 Oct 09 10:10:51 AM UTC 24 Oct 09 10:10:56 AM UTC 24 273124904 ps
T1064 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.778259131 Oct 09 10:10:56 AM UTC 24 Oct 09 10:10:58 AM UTC 24 13651339 ps
T1065 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3834701720 Oct 09 10:10:56 AM UTC 24 Oct 09 10:10:58 AM UTC 24 13486165 ps
T93 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.662068324 Oct 09 10:09:45 AM UTC 24 Oct 09 10:10:59 AM UTC 24 11416789332 ps
T1066 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2903193145 Oct 09 10:10:55 AM UTC 24 Oct 09 10:10:59 AM UTC 24 41483957 ps
T1067 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1857461230 Oct 09 10:10:55 AM UTC 24 Oct 09 10:11:00 AM UTC 24 2121968414 ps
T1068 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3515221320 Oct 09 10:10:53 AM UTC 24 Oct 09 10:11:00 AM UTC 24 752462247 ps
T1069 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.262814051 Oct 09 10:10:58 AM UTC 24 Oct 09 10:11:01 AM UTC 24 144176481 ps
T1070 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2591074668 Oct 09 10:11:00 AM UTC 24 Oct 09 10:11:02 AM UTC 24 12970147 ps
T1071 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1463450069 Oct 09 10:10:56 AM UTC 24 Oct 09 10:11:02 AM UTC 24 356252547 ps
T1072 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1145480147 Oct 09 10:11:00 AM UTC 24 Oct 09 10:11:02 AM UTC 24 17073076 ps
T1073 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.274070381 Oct 09 10:10:57 AM UTC 24 Oct 09 10:11:03 AM UTC 24 105626568 ps
T94 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2222352368 Oct 09 10:09:56 AM UTC 24 Oct 09 10:11:07 AM UTC 24 15429980598 ps
T1074 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.551507700 Oct 09 10:11:01 AM UTC 24 Oct 09 10:11:07 AM UTC 24 1435830765 ps
T1075 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3689666415 Oct 09 10:09:55 AM UTC 24 Oct 09 10:11:09 AM UTC 24 9177519579 ps
T1076 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.4273413318 Oct 09 10:10:47 AM UTC 24 Oct 09 10:11:19 AM UTC 24 12997773820 ps
T1077 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2665283611 Oct 09 10:10:54 AM UTC 24 Oct 09 10:11:35 AM UTC 24 8032679642 ps
T1078 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.801490166 Oct 09 10:10:37 AM UTC 24 Oct 09 10:11:36 AM UTC 24 7418631892 ps
T1079 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.172364888 Oct 09 10:10:27 AM UTC 24 Oct 09 10:11:36 AM UTC 24 41469452145 ps
T1080 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.332501784 Oct 09 10:10:31 AM UTC 24 Oct 09 10:11:45 AM UTC 24 54315169664 ps
T1081 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2670516995 Oct 09 10:10:41 AM UTC 24 Oct 09 10:11:47 AM UTC 24 7903941326 ps
T1082 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.548855785 Oct 09 10:10:49 AM UTC 24 Oct 09 10:11:55 AM UTC 24 7475345585 ps
T1083 /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.961219410 Oct 09 10:10:56 AM UTC 24 Oct 09 10:12:10 AM UTC 24 58647890844 ps

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_lc_escalation.3225264152
Short name T5
Test name
Test status
Simulation time 17395898918 ps
CPU time 47.48 seconds
Started Oct 09 12:18:05 PM UTC 24
Finished Oct 09 12:18:54 PM UTC 24
Peak memory 221552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225264152 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_escalation.3225264152
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.2307627702
Short name T26
Test name
Test status
Simulation time 6833649015 ps
CPU time 56.39 seconds
Started Oct 09 12:24:20 PM UTC 24
Finished Oct 09 12:25:18 PM UTC 24
Peak memory 228704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307627702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.2307627702
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1346919198
Short name T49
Test name
Test status
Simulation time 7924220342 ps
CPU time 60.82 seconds
Started Oct 09 12:36:31 PM UTC 24
Finished Oct 09 12:37:34 PM UTC 24
Peak memory 221676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346919198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.1346919198
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_partial_access.1724692259
Short name T42
Test name
Test status
Simulation time 41724939028 ps
CPU time 209.69 seconds
Started Oct 09 12:18:05 PM UTC 24
Finished Oct 09 12:21:38 PM UTC 24
Peak memory 221532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724692259 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_mem_partial_access.1724692259
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_regwen.2512464987
Short name T20
Test name
Test status
Simulation time 8294797473 ps
CPU time 64.25 seconds
Started Oct 09 12:21:35 PM UTC 24
Finished Oct 09 12:22:41 PM UTC 24
Peak memory 271464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512464987 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.2512464987
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.890781814
Short name T118
Test name
Test status
Simulation time 621683634 ps
CPU time 3.49 seconds
Started Oct 09 10:09:31 AM UTC 24
Finished Oct 09 10:09:35 AM UTC 24
Peak memory 224336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8907
81814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_tl_i
ntg_err.890781814
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_sec_cm.7590283
Short name T30
Test name
Test status
Simulation time 1049891357 ps
CPU time 3.35 seconds
Started Oct 09 12:22:09 PM UTC 24
Finished Oct 09 12:22:13 PM UTC 24
Peak memory 247832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7590283 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_sec_cm.7590283
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_executable.1379979564
Short name T28
Test name
Test status
Simulation time 1155510832 ps
CPU time 37.8 seconds
Started Oct 09 12:18:52 PM UTC 24
Finished Oct 09 12:19:31 PM UTC 24
Peak memory 271352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379979564 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executable.1379979564
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access_b2b.2675997623
Short name T63
Test name
Test status
Simulation time 23366766525 ps
CPU time 306.51 seconds
Started Oct 09 12:18:31 PM UTC 24
Finished Oct 09 12:23:42 PM UTC 24
Peak memory 211260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675997623 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_partial_ac
cess_b2b.2675997623
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all.960063235
Short name T273
Test name
Test status
Simulation time 79762371644 ps
CPU time 2245.97 seconds
Started Oct 09 12:18:10 PM UTC 24
Finished Oct 09 12:56:01 PM UTC 24
Peak memory 390180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96006323
5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_all.960063235
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.3934216209
Short name T25
Test name
Test status
Simulation time 7539121219 ps
CPU time 100.21 seconds
Started Oct 09 12:21:59 PM UTC 24
Finished Oct 09 12:23:41 PM UTC 24
Peak memory 351476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934216209 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.3934216209
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_readback_err.3193999044
Short name T33
Test name
Test status
Simulation time 1333398107 ps
CPU time 9.91 seconds
Started Oct 09 12:43:56 PM UTC 24
Finished Oct 09 12:44:07 PM UTC 24
Peak memory 211468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193999044 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_readback_err.3193999044
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_all.4047104403
Short name T157
Test name
Test status
Simulation time 28699753705 ps
CPU time 742.2 seconds
Started Oct 09 12:36:47 PM UTC 24
Finished Oct 09 12:49:18 PM UTC 24
Peak memory 392488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40471044
03 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all.4047104403
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1520453853
Short name T71
Test name
Test status
Simulation time 22874560 ps
CPU time 0.98 seconds
Started Oct 09 10:09:32 AM UTC 24
Finished Oct 09 10:09:34 AM UTC 24
Peak memory 211924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520453
853 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_al
iasing.1520453853
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_ram_cfg.200439499
Short name T1
Test name
Test status
Simulation time 1344870878 ps
CPU time 5.19 seconds
Started Oct 09 12:18:05 PM UTC 24
Finished Oct 09 12:18:11 PM UTC 24
Peak memory 211284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200439499 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.200439499
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3348518951
Short name T143
Test name
Test status
Simulation time 2119049984 ps
CPU time 4.4 seconds
Started Oct 09 10:10:33 AM UTC 24
Finished Oct 09 10:10:39 AM UTC 24
Peak memory 214200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348
518951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl
_intg_err.3348518951
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_executable.1677372427
Short name T151
Test name
Test status
Simulation time 27249332581 ps
CPU time 760.78 seconds
Started Oct 09 12:43:29 PM UTC 24
Finished Oct 09 12:56:20 PM UTC 24
Peak memory 388216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677372427 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executable.1677372427
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_alert_test.1361126443
Short name T12
Test name
Test status
Simulation time 44029510 ps
CPU time 1.03 seconds
Started Oct 09 12:18:18 PM UTC 24
Finished Oct 09 12:18:20 PM UTC 24
Peak memory 209432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361126443
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_alert_test.1361126443
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.301428978
Short name T138
Test name
Test status
Simulation time 379775387 ps
CPU time 2.55 seconds
Started Oct 09 10:10:16 AM UTC 24
Finished Oct 09 10:10:20 AM UTC 24
Peak memory 224268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014
28978 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl_
intg_err.301428978
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_readback_err.105053325
Short name T2
Test name
Test status
Simulation time 668688209 ps
CPU time 10.99 seconds
Started Oct 09 12:18:05 PM UTC 24
Finished Oct 09 12:18:18 PM UTC 24
Peak memory 211280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105053325 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_readback_err.105053325
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1378274002
Short name T81
Test name
Test status
Simulation time 7417222654 ps
CPU time 54.34 seconds
Started Oct 09 10:09:29 AM UTC 24
Finished Oct 09 10:10:26 AM UTC 24
Peak memory 214092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1
378274002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_
passthru_mem_tl_intg_err.1378274002
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1386368646
Short name T142
Test name
Test status
Simulation time 349631499 ps
CPU time 2.2 seconds
Started Oct 09 10:10:23 AM UTC 24
Finished Oct 09 10:10:26 AM UTC 24
Peak memory 224352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386
368646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl
_intg_err.1386368646
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.125574064
Short name T144
Test name
Test status
Simulation time 5377981543 ps
CPU time 85.39 seconds
Started Oct 09 02:15:08 PM UTC 24
Finished Oct 09 02:16:36 PM UTC 24
Peak memory 225792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125574064 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.125574064
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/43.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2034153356
Short name T70
Test name
Test status
Simulation time 22456451 ps
CPU time 0.87 seconds
Started Oct 09 10:09:31 AM UTC 24
Finished Oct 09 10:09:33 AM UTC 24
Peak memory 212716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034153356 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_rw.2034153356
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.444408866
Short name T113
Test name
Test status
Simulation time 210103162 ps
CPU time 1.63 seconds
Started Oct 09 10:09:31 AM UTC 24
Finished Oct 09 10:09:34 AM UTC 24
Peak memory 212780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4444088
66 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_bit
_bash.444408866
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2342138767
Short name T112
Test name
Test status
Simulation time 42308774 ps
CPU time 0.92 seconds
Started Oct 09 10:09:31 AM UTC 24
Finished Oct 09 10:09:33 AM UTC 24
Peak memory 213132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342138
767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_hw
_reset.2342138767
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.66505225
Short name T995
Test name
Test status
Simulation time 352018905 ps
CPU time 5.81 seconds
Started Oct 09 10:09:32 AM UTC 24
Finished Oct 09 10:09:39 AM UTC 24
Peak memory 224288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000
00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=66505225 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.66505225
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3490424267
Short name T97
Test name
Test status
Simulation time 19206255 ps
CPU time 1.04 seconds
Started Oct 09 10:09:32 AM UTC 24
Finished Oct 09 10:09:34 AM UTC 24
Peak memory 212452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000
00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=3490424267 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram
_ctrl_same_csr_outstanding.3490424267
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.185598413
Short name T993
Test name
Test status
Simulation time 92499610 ps
CPU time 5.54 seconds
Started Oct 09 10:09:29 AM UTC 24
Finished Oct 09 10:09:36 AM UTC 24
Peak memory 224332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185598413 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_tl_errors.185598413
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1444967382
Short name T115
Test name
Test status
Simulation time 22763698 ps
CPU time 1.08 seconds
Started Oct 09 10:09:35 AM UTC 24
Finished Oct 09 10:09:37 AM UTC 24
Peak memory 212728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444967
382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_al
iasing.1444967382
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2945805891
Short name T994
Test name
Test status
Simulation time 374372374 ps
CPU time 2.06 seconds
Started Oct 09 10:09:35 AM UTC 24
Finished Oct 09 10:09:38 AM UTC 24
Peak memory 213984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945805
891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_bi
t_bash.2945805891
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1436522902
Short name T114
Test name
Test status
Simulation time 51024826 ps
CPU time 0.96 seconds
Started Oct 09 10:09:35 AM UTC 24
Finished Oct 09 10:09:37 AM UTC 24
Peak memory 212784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436522
902 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_hw
_reset.1436522902
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1725555156
Short name T999
Test name
Test status
Simulation time 363835139 ps
CPU time 4.21 seconds
Started Oct 09 10:09:36 AM UTC 24
Finished Oct 09 10:09:41 AM UTC 24
Peak memory 224080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000
00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=1725555156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.1725555156
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.633697829
Short name T98
Test name
Test status
Simulation time 11736559 ps
CPU time 0.86 seconds
Started Oct 09 10:09:35 AM UTC 24
Finished Oct 09 10:09:37 AM UTC 24
Peak memory 212724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633697829 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_rw.633697829
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2795727419
Short name T82
Test name
Test status
Simulation time 14171882555 ps
CPU time 58.5 seconds
Started Oct 09 10:09:33 AM UTC 24
Finished Oct 09 10:10:33 AM UTC 24
Peak memory 214156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2
795727419 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_
passthru_mem_tl_intg_err.2795727419
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.346917829
Short name T99
Test name
Test status
Simulation time 20269248 ps
CPU time 0.93 seconds
Started Oct 09 10:09:35 AM UTC 24
Finished Oct 09 10:09:37 AM UTC 24
Peak memory 212788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000
00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=346917829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_
ctrl_same_csr_outstanding.346917829
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2522519105
Short name T996
Test name
Test status
Simulation time 107836082 ps
CPU time 5.29 seconds
Started Oct 09 10:09:33 AM UTC 24
Finished Oct 09 10:09:40 AM UTC 24
Peak memory 224280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522519105 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_errors.2522519105
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2612045579
Short name T119
Test name
Test status
Simulation time 1256588679 ps
CPU time 3.12 seconds
Started Oct 09 10:09:33 AM UTC 24
Finished Oct 09 10:09:38 AM UTC 24
Peak memory 224212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612
045579 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_
intg_err.2612045579
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.4142240092
Short name T1033
Test name
Test status
Simulation time 379364081 ps
CPU time 4.59 seconds
Started Oct 09 10:10:21 AM UTC 24
Finished Oct 09 10:10:26 AM UTC 24
Peak memory 224004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000
00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=4142240092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.4142240092
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1664045756
Short name T1027
Test name
Test status
Simulation time 24048291 ps
CPU time 1.08 seconds
Started Oct 09 10:10:18 AM UTC 24
Finished Oct 09 10:10:20 AM UTC 24
Peak memory 212716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664045756 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_rw.1664045756
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2593753278
Short name T1062
Test name
Test status
Simulation time 3864266646 ps
CPU time 38.32 seconds
Started Oct 09 10:10:15 AM UTC 24
Finished Oct 09 10:10:55 AM UTC 24
Peak memory 213896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2
593753278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl
_passthru_mem_tl_intg_err.2593753278
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1762106153
Short name T1028
Test name
Test status
Simulation time 16086625 ps
CPU time 1.06 seconds
Started Oct 09 10:10:20 AM UTC 24
Finished Oct 09 10:10:22 AM UTC 24
Peak memory 212804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000
00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=1762106153 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sra
m_ctrl_same_csr_outstanding.1762106153
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_errors.542465941
Short name T1030
Test name
Test status
Simulation time 71236300 ps
CPU time 5.65 seconds
Started Oct 09 10:10:16 AM UTC 24
Finished Oct 09 10:10:23 AM UTC 24
Peak memory 224368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542465941 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_tl_errors.542465941
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3714788462
Short name T1037
Test name
Test status
Simulation time 706495562 ps
CPU time 4.77 seconds
Started Oct 09 10:10:26 AM UTC 24
Finished Oct 09 10:10:32 AM UTC 24
Peak memory 224288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000
00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=3714788462 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.3714788462
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3177054894
Short name T1031
Test name
Test status
Simulation time 35076625 ps
CPU time 0.93 seconds
Started Oct 09 10:10:24 AM UTC 24
Finished Oct 09 10:10:26 AM UTC 24
Peak memory 212796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177054894 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_rw.3177054894
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.975959635
Short name T1055
Test name
Test status
Simulation time 19474412029 ps
CPU time 29.67 seconds
Started Oct 09 10:10:21 AM UTC 24
Finished Oct 09 10:10:52 AM UTC 24
Peak memory 214184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9
75959635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_
passthru_mem_tl_intg_err.975959635
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.786648023
Short name T1032
Test name
Test status
Simulation time 50693699 ps
CPU time 0.92 seconds
Started Oct 09 10:10:24 AM UTC 24
Finished Oct 09 10:10:26 AM UTC 24
Peak memory 212784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000
00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=786648023 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram
_ctrl_same_csr_outstanding.786648023
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/11.sram_ctrl_tl_errors.4290190131
Short name T1034
Test name
Test status
Simulation time 68012348 ps
CPU time 2.91 seconds
Started Oct 09 10:10:23 AM UTC 24
Finished Oct 09 10:10:27 AM UTC 24
Peak memory 224460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290190131 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl_errors.4290190131
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1020272231
Short name T1040
Test name
Test status
Simulation time 1393631619 ps
CPU time 6.47 seconds
Started Oct 09 10:10:31 AM UTC 24
Finished Oct 09 10:10:38 AM UTC 24
Peak memory 224084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000
00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=1020272231 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.1020272231
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1403899382
Short name T1035
Test name
Test status
Simulation time 15540672 ps
CPU time 0.95 seconds
Started Oct 09 10:10:28 AM UTC 24
Finished Oct 09 10:10:30 AM UTC 24
Peak memory 212716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403899382 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_rw.1403899382
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.172364888
Short name T1079
Test name
Test status
Simulation time 41469452145 ps
CPU time 66.74 seconds
Started Oct 09 10:10:27 AM UTC 24
Finished Oct 09 10:11:36 AM UTC 24
Peak memory 214152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1
72364888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_
passthru_mem_tl_intg_err.172364888
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.698272590
Short name T1036
Test name
Test status
Simulation time 64592929 ps
CPU time 1.04 seconds
Started Oct 09 10:10:28 AM UTC 24
Finished Oct 09 10:10:30 AM UTC 24
Peak memory 212780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000
00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=698272590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram
_ctrl_same_csr_outstanding.698272590
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2988684294
Short name T1038
Test name
Test status
Simulation time 49971174 ps
CPU time 7.02 seconds
Started Oct 09 10:10:27 AM UTC 24
Finished Oct 09 10:10:36 AM UTC 24
Peak memory 224332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988684294 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl_errors.2988684294
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.663380637
Short name T140
Test name
Test status
Simulation time 125998519 ps
CPU time 2.23 seconds
Started Oct 09 10:10:28 AM UTC 24
Finished Oct 09 10:10:31 AM UTC 24
Peak memory 224416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6633
80637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_tl_
intg_err.663380637
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2776185276
Short name T1047
Test name
Test status
Simulation time 1433529751 ps
CPU time 6.03 seconds
Started Oct 09 10:10:36 AM UTC 24
Finished Oct 09 10:10:43 AM UTC 24
Peak memory 224472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000
00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=2776185276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.2776185276
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1501573595
Short name T1039
Test name
Test status
Simulation time 27012533 ps
CPU time 1.05 seconds
Started Oct 09 10:10:34 AM UTC 24
Finished Oct 09 10:10:36 AM UTC 24
Peak memory 212776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501573595 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_rw.1501573595
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.332501784
Short name T1080
Test name
Test status
Simulation time 54315169664 ps
CPU time 71.78 seconds
Started Oct 09 10:10:31 AM UTC 24
Finished Oct 09 10:11:45 AM UTC 24
Peak memory 214216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
32501784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_
passthru_mem_tl_intg_err.332501784
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3535731994
Short name T1041
Test name
Test status
Simulation time 47461411 ps
CPU time 1.05 seconds
Started Oct 09 10:10:36 AM UTC 24
Finished Oct 09 10:10:38 AM UTC 24
Peak memory 212804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000
00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=3535731994 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sra
m_ctrl_same_csr_outstanding.3535731994
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3166130129
Short name T1042
Test name
Test status
Simulation time 44571436 ps
CPU time 6.13 seconds
Started Oct 09 10:10:32 AM UTC 24
Finished Oct 09 10:10:39 AM UTC 24
Peak memory 224288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166130129 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl_errors.3166130129
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3423210803
Short name T1050
Test name
Test status
Simulation time 655917552 ps
CPU time 4.88 seconds
Started Oct 09 10:10:40 AM UTC 24
Finished Oct 09 10:10:46 AM UTC 24
Peak memory 224012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000
00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=3423210803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.3423210803
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3014407543
Short name T1044
Test name
Test status
Simulation time 37152178 ps
CPU time 0.96 seconds
Started Oct 09 10:10:40 AM UTC 24
Finished Oct 09 10:10:42 AM UTC 24
Peak memory 212776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014407543 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_rw.3014407543
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.801490166
Short name T1078
Test name
Test status
Simulation time 7418631892 ps
CPU time 56.54 seconds
Started Oct 09 10:10:37 AM UTC 24
Finished Oct 09 10:11:36 AM UTC 24
Peak memory 214160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8
01490166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_
passthru_mem_tl_intg_err.801490166
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3023043768
Short name T1045
Test name
Test status
Simulation time 81502142 ps
CPU time 1.29 seconds
Started Oct 09 10:10:40 AM UTC 24
Finished Oct 09 10:10:42 AM UTC 24
Peak memory 212804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000
00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=3023043768 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sra
m_ctrl_same_csr_outstanding.3023043768
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_errors.711406482
Short name T1046
Test name
Test status
Simulation time 22173633 ps
CPU time 2 seconds
Started Oct 09 10:10:40 AM UTC 24
Finished Oct 09 10:10:43 AM UTC 24
Peak memory 223020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711406482 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_tl_errors.711406482
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1827521790
Short name T1048
Test name
Test status
Simulation time 218333560 ps
CPU time 2.94 seconds
Started Oct 09 10:10:40 AM UTC 24
Finished Oct 09 10:10:44 AM UTC 24
Peak memory 224240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827
521790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_tl
_intg_err.1827521790
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3086479478
Short name T1056
Test name
Test status
Simulation time 1403845673 ps
CPU time 6.42 seconds
Started Oct 09 10:10:44 AM UTC 24
Finished Oct 09 10:10:52 AM UTC 24
Peak memory 224008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000
00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=3086479478 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.3086479478
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1934130237
Short name T1049
Test name
Test status
Simulation time 30502298 ps
CPU time 0.94 seconds
Started Oct 09 10:10:43 AM UTC 24
Finished Oct 09 10:10:46 AM UTC 24
Peak memory 212716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934130237 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_rw.1934130237
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2670516995
Short name T1081
Test name
Test status
Simulation time 7903941326 ps
CPU time 64.14 seconds
Started Oct 09 10:10:41 AM UTC 24
Finished Oct 09 10:11:47 AM UTC 24
Peak memory 214164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2
670516995 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl
_passthru_mem_tl_intg_err.2670516995
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.201060318
Short name T1052
Test name
Test status
Simulation time 35932526 ps
CPU time 1.1 seconds
Started Oct 09 10:10:44 AM UTC 24
Finished Oct 09 10:10:47 AM UTC 24
Peak memory 212780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000
00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=201060318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram
_ctrl_same_csr_outstanding.201060318
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3435324028
Short name T1053
Test name
Test status
Simulation time 39951740 ps
CPU time 5 seconds
Started Oct 09 10:10:42 AM UTC 24
Finished Oct 09 10:10:48 AM UTC 24
Peak memory 224284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435324028 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl_errors.3435324028
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1157331322
Short name T1051
Test name
Test status
Simulation time 268253927 ps
CPU time 2.25 seconds
Started Oct 09 10:10:43 AM UTC 24
Finished Oct 09 10:10:47 AM UTC 24
Peak memory 214036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157
331322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl
_intg_err.1157331322
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.493414515
Short name T1058
Test name
Test status
Simulation time 713202349 ps
CPU time 4.24 seconds
Started Oct 09 10:10:48 AM UTC 24
Finished Oct 09 10:10:54 AM UTC 24
Peak memory 213844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000
00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=493414515 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.493414515
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2930512184
Short name T92
Test name
Test status
Simulation time 19981466 ps
CPU time 0.99 seconds
Started Oct 09 10:10:48 AM UTC 24
Finished Oct 09 10:10:51 AM UTC 24
Peak memory 212716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930512184 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_rw.2930512184
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.4273413318
Short name T1076
Test name
Test status
Simulation time 12997773820 ps
CPU time 30.69 seconds
Started Oct 09 10:10:47 AM UTC 24
Finished Oct 09 10:11:19 AM UTC 24
Peak memory 213964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4
273413318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl
_passthru_mem_tl_intg_err.4273413318
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2526903326
Short name T1054
Test name
Test status
Simulation time 305741484 ps
CPU time 1.27 seconds
Started Oct 09 10:10:48 AM UTC 24
Finished Oct 09 10:10:51 AM UTC 24
Peak memory 212804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000
00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=2526903326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sra
m_ctrl_same_csr_outstanding.2526903326
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2680605891
Short name T1061
Test name
Test status
Simulation time 538964797 ps
CPU time 6.41 seconds
Started Oct 09 10:10:47 AM UTC 24
Finished Oct 09 10:10:55 AM UTC 24
Peak memory 224404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680605891 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl_errors.2680605891
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.472497417
Short name T137
Test name
Test status
Simulation time 1115550133 ps
CPU time 1.96 seconds
Started Oct 09 10:10:47 AM UTC 24
Finished Oct 09 10:10:51 AM UTC 24
Peak memory 212788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4724
97417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_tl_
intg_err.472497417
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3515221320
Short name T1068
Test name
Test status
Simulation time 752462247 ps
CPU time 6.33 seconds
Started Oct 09 10:10:53 AM UTC 24
Finished Oct 09 10:11:00 AM UTC 24
Peak memory 224272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000
00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=3515221320 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.3515221320
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1303043395
Short name T1057
Test name
Test status
Simulation time 15895232 ps
CPU time 1.01 seconds
Started Oct 09 10:10:52 AM UTC 24
Finished Oct 09 10:10:53 AM UTC 24
Peak memory 212796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303043395 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_rw.1303043395
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.548855785
Short name T1082
Test name
Test status
Simulation time 7475345585 ps
CPU time 63.3 seconds
Started Oct 09 10:10:49 AM UTC 24
Finished Oct 09 10:11:55 AM UTC 24
Peak memory 214236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5
48855785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_
passthru_mem_tl_intg_err.548855785
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2136877368
Short name T1060
Test name
Test status
Simulation time 13931919 ps
CPU time 0.94 seconds
Started Oct 09 10:10:53 AM UTC 24
Finished Oct 09 10:10:55 AM UTC 24
Peak memory 212804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000
00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=2136877368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sra
m_ctrl_same_csr_outstanding.2136877368
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1045016175
Short name T1059
Test name
Test status
Simulation time 44421826 ps
CPU time 2.93 seconds
Started Oct 09 10:10:50 AM UTC 24
Finished Oct 09 10:10:55 AM UTC 24
Peak memory 214036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045016175 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl_errors.1045016175
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2759402331
Short name T1063
Test name
Test status
Simulation time 273124904 ps
CPU time 3.64 seconds
Started Oct 09 10:10:51 AM UTC 24
Finished Oct 09 10:10:56 AM UTC 24
Peak memory 224308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759
402331 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_tl
_intg_err.2759402331
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1463450069
Short name T1071
Test name
Test status
Simulation time 356252547 ps
CPU time 4.45 seconds
Started Oct 09 10:10:56 AM UTC 24
Finished Oct 09 10:11:02 AM UTC 24
Peak memory 224356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000
00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=1463450069 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.1463450069
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_csr_rw.778259131
Short name T1064
Test name
Test status
Simulation time 13651339 ps
CPU time 0.88 seconds
Started Oct 09 10:10:56 AM UTC 24
Finished Oct 09 10:10:58 AM UTC 24
Peak memory 212796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778259131 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_rw.778259131
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2665283611
Short name T1077
Test name
Test status
Simulation time 8032679642 ps
CPU time 39.56 seconds
Started Oct 09 10:10:54 AM UTC 24
Finished Oct 09 10:11:35 AM UTC 24
Peak memory 213956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2
665283611 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl
_passthru_mem_tl_intg_err.2665283611
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3834701720
Short name T1065
Test name
Test status
Simulation time 13486165 ps
CPU time 1.08 seconds
Started Oct 09 10:10:56 AM UTC 24
Finished Oct 09 10:10:58 AM UTC 24
Peak memory 212780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000
00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=3834701720 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sra
m_ctrl_same_csr_outstanding.3834701720
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2903193145
Short name T1066
Test name
Test status
Simulation time 41483957 ps
CPU time 3.19 seconds
Started Oct 09 10:10:55 AM UTC 24
Finished Oct 09 10:10:59 AM UTC 24
Peak memory 214172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903193145 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_tl_errors.2903193145
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1857461230
Short name T1067
Test name
Test status
Simulation time 2121968414 ps
CPU time 3.47 seconds
Started Oct 09 10:10:55 AM UTC 24
Finished Oct 09 10:11:00 AM UTC 24
Peak memory 214248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857
461230 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_tl
_intg_err.1857461230
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.551507700
Short name T1074
Test name
Test status
Simulation time 1435830765 ps
CPU time 5.44 seconds
Started Oct 09 10:11:01 AM UTC 24
Finished Oct 09 10:11:07 AM UTC 24
Peak memory 224084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000
00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=551507700 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.551507700
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2591074668
Short name T1070
Test name
Test status
Simulation time 12970147 ps
CPU time 1.01 seconds
Started Oct 09 10:11:00 AM UTC 24
Finished Oct 09 10:11:02 AM UTC 24
Peak memory 212716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591074668 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_rw.2591074668
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.961219410
Short name T1083
Test name
Test status
Simulation time 58647890844 ps
CPU time 72.27 seconds
Started Oct 09 10:10:56 AM UTC 24
Finished Oct 09 10:12:10 AM UTC 24
Peak memory 214088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9
61219410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_
passthru_mem_tl_intg_err.961219410
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1145480147
Short name T1072
Test name
Test status
Simulation time 17073076 ps
CPU time 1.21 seconds
Started Oct 09 10:11:00 AM UTC 24
Finished Oct 09 10:11:02 AM UTC 24
Peak memory 212784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000
00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=1145480147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sra
m_ctrl_same_csr_outstanding.1145480147
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_errors.274070381
Short name T1073
Test name
Test status
Simulation time 105626568 ps
CPU time 5.01 seconds
Started Oct 09 10:10:57 AM UTC 24
Finished Oct 09 10:11:03 AM UTC 24
Peak memory 224328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274070381 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl_errors.274070381
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.262814051
Short name T1069
Test name
Test status
Simulation time 144176481 ps
CPU time 1.94 seconds
Started Oct 09 10:10:58 AM UTC 24
Finished Oct 09 10:11:01 AM UTC 24
Peak memory 223028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628
14051 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_tl_
intg_err.262814051
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2387003505
Short name T73
Test name
Test status
Simulation time 45620029 ps
CPU time 1.02 seconds
Started Oct 09 10:09:39 AM UTC 24
Finished Oct 09 10:09:41 AM UTC 24
Peak memory 212724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387003
505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_al
iasing.2387003505
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3856646672
Short name T1000
Test name
Test status
Simulation time 45938961 ps
CPU time 2.03 seconds
Started Oct 09 10:09:39 AM UTC 24
Finished Oct 09 10:09:42 AM UTC 24
Peak memory 214176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856646
672 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_bi
t_bash.3856646672
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2967025671
Short name T997
Test name
Test status
Simulation time 21507068 ps
CPU time 0.96 seconds
Started Oct 09 10:09:38 AM UTC 24
Finished Oct 09 10:09:40 AM UTC 24
Peak memory 212724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967025
671 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_hw
_reset.2967025671
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.506167649
Short name T1001
Test name
Test status
Simulation time 724886403 ps
CPU time 5.06 seconds
Started Oct 09 10:09:40 AM UTC 24
Finished Oct 09 10:09:46 AM UTC 24
Peak memory 224208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000
00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=506167649 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.506167649
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.485777188
Short name T72
Test name
Test status
Simulation time 46060737 ps
CPU time 0.93 seconds
Started Oct 09 10:09:38 AM UTC 24
Finished Oct 09 10:09:40 AM UTC 24
Peak memory 212724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485777188 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_rw.485777188
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1207405401
Short name T83
Test name
Test status
Simulation time 64029497295 ps
CPU time 56.42 seconds
Started Oct 09 10:09:37 AM UTC 24
Finished Oct 09 10:10:35 AM UTC 24
Peak memory 214100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1
207405401 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_
passthru_mem_tl_intg_err.1207405401
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.936308777
Short name T100
Test name
Test status
Simulation time 22116280 ps
CPU time 0.99 seconds
Started Oct 09 10:09:40 AM UTC 24
Finished Oct 09 10:09:42 AM UTC 24
Peak memory 212808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000
00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=936308777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_
ctrl_same_csr_outstanding.936308777
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.794717033
Short name T998
Test name
Test status
Simulation time 123376188 ps
CPU time 2.85 seconds
Started Oct 09 10:09:37 AM UTC 24
Finished Oct 09 10:09:41 AM UTC 24
Peak memory 224268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794717033 -asser
t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_errors.794717033
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.4012557481
Short name T120
Test name
Test status
Simulation time 195674919 ps
CPU time 3.06 seconds
Started Oct 09 10:09:37 AM UTC 24
Finished Oct 09 10:09:42 AM UTC 24
Peak memory 224332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012
557481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_tl_
intg_err.4012557481
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1876484718
Short name T1002
Test name
Test status
Simulation time 22805008 ps
CPU time 0.99 seconds
Started Oct 09 10:09:43 AM UTC 24
Finished Oct 09 10:09:48 AM UTC 24
Peak memory 212720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876484
718 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_al
iasing.1876484718
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1966248864
Short name T1003
Test name
Test status
Simulation time 411088620 ps
CPU time 2.17 seconds
Started Oct 09 10:09:42 AM UTC 24
Finished Oct 09 10:09:49 AM UTC 24
Peak memory 214240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966248
864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_bi
t_bash.1966248864
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3405468819
Short name T74
Test name
Test status
Simulation time 15570406 ps
CPU time 0.92 seconds
Started Oct 09 10:09:41 AM UTC 24
Finished Oct 09 10:09:46 AM UTC 24
Peak memory 212848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405468
819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_hw
_reset.3405468819
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3799817957
Short name T1006
Test name
Test status
Simulation time 1814372003 ps
CPU time 7.01 seconds
Started Oct 09 10:09:43 AM UTC 24
Finished Oct 09 10:09:54 AM UTC 24
Peak memory 224076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000
00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=3799817957 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.3799817957
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2364689593
Short name T75
Test name
Test status
Simulation time 49051947 ps
CPU time 0.96 seconds
Started Oct 09 10:09:42 AM UTC 24
Finished Oct 09 10:09:48 AM UTC 24
Peak memory 212700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364689593 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_rw.2364689593
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3323368548
Short name T80
Test name
Test status
Simulation time 3958653570 ps
CPU time 33.01 seconds
Started Oct 09 10:09:41 AM UTC 24
Finished Oct 09 10:10:18 AM UTC 24
Peak memory 213956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
323368548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_
passthru_mem_tl_intg_err.3323368548
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.98120302
Short name T101
Test name
Test status
Simulation time 42954926 ps
CPU time 1.26 seconds
Started Oct 09 10:09:43 AM UTC 24
Finished Oct 09 10:09:48 AM UTC 24
Peak memory 212776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000
00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=98120302 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_c
trl_same_csr_outstanding.98120302
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.33748730
Short name T1004
Test name
Test status
Simulation time 147823810 ps
CPU time 6.39 seconds
Started Oct 09 10:09:41 AM UTC 24
Finished Oct 09 10:09:52 AM UTC 24
Peak memory 214048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33748730 -assert
nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_errors.33748730
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.653830701
Short name T134
Test name
Test status
Simulation time 1472774562 ps
CPU time 3.35 seconds
Started Oct 09 10:09:41 AM UTC 24
Finished Oct 09 10:09:48 AM UTC 24
Peak memory 224344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6538
30701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_tl_i
ntg_err.653830701
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1528791809
Short name T1005
Test name
Test status
Simulation time 17865416 ps
CPU time 0.93 seconds
Started Oct 09 10:09:50 AM UTC 24
Finished Oct 09 10:09:54 AM UTC 24
Peak memory 212804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528791
809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_al
iasing.1528791809
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3454854929
Short name T78
Test name
Test status
Simulation time 679891566 ps
CPU time 3.14 seconds
Started Oct 09 10:09:50 AM UTC 24
Finished Oct 09 10:09:56 AM UTC 24
Peak memory 213924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454854
929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_bi
t_bash.3454854929
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.799292030
Short name T77
Test name
Test status
Simulation time 39779734 ps
CPU time 0.95 seconds
Started Oct 09 10:09:50 AM UTC 24
Finished Oct 09 10:09:54 AM UTC 24
Peak memory 212784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7992920
30 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_hw_
reset.799292030
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3560467562
Short name T1011
Test name
Test status
Simulation time 1360936859 ps
CPU time 7.02 seconds
Started Oct 09 10:09:52 AM UTC 24
Finished Oct 09 10:10:01 AM UTC 24
Peak memory 224212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000
00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=3560467562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.3560467562
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3900259730
Short name T76
Test name
Test status
Simulation time 14103940 ps
CPU time 0.98 seconds
Started Oct 09 10:09:50 AM UTC 24
Finished Oct 09 10:09:54 AM UTC 24
Peak memory 212716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900259730 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_rw.3900259730
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.662068324
Short name T93
Test name
Test status
Simulation time 11416789332 ps
CPU time 69.05 seconds
Started Oct 09 10:09:45 AM UTC 24
Finished Oct 09 10:10:59 AM UTC 24
Peak memory 214220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6
62068324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_p
assthru_mem_tl_intg_err.662068324
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.4140165279
Short name T102
Test name
Test status
Simulation time 56892773 ps
CPU time 0.93 seconds
Started Oct 09 10:09:50 AM UTC 24
Finished Oct 09 10:09:54 AM UTC 24
Peak memory 212780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000
00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=4140165279 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram
_ctrl_same_csr_outstanding.4140165279
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2818885844
Short name T1007
Test name
Test status
Simulation time 79056407 ps
CPU time 3.77 seconds
Started Oct 09 10:09:48 AM UTC 24
Finished Oct 09 10:09:55 AM UTC 24
Peak memory 224468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818885844 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_errors.2818885844
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3127319775
Short name T135
Test name
Test status
Simulation time 776141253 ps
CPU time 3.8 seconds
Started Oct 09 10:09:48 AM UTC 24
Finished Oct 09 10:09:56 AM UTC 24
Peak memory 214024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127
319775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_tl_
intg_err.3127319775
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3177565683
Short name T1014
Test name
Test status
Simulation time 1507022523 ps
CPU time 5.58 seconds
Started Oct 09 10:09:55 AM UTC 24
Finished Oct 09 10:10:02 AM UTC 24
Peak memory 224344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000
00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=3177565683 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.3177565683
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.4077131044
Short name T79
Test name
Test status
Simulation time 28731178 ps
CPU time 0.96 seconds
Started Oct 09 10:09:55 AM UTC 24
Finished Oct 09 10:09:57 AM UTC 24
Peak memory 212716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077131044 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_rw.4077131044
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3689666415
Short name T1075
Test name
Test status
Simulation time 9177519579 ps
CPU time 72.07 seconds
Started Oct 09 10:09:55 AM UTC 24
Finished Oct 09 10:11:09 AM UTC 24
Peak memory 214112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3
689666415 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_
passthru_mem_tl_intg_err.3689666415
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.9365998
Short name T103
Test name
Test status
Simulation time 35536937 ps
CPU time 0.93 seconds
Started Oct 09 10:09:55 AM UTC 24
Finished Oct 09 10:09:57 AM UTC 24
Peak memory 212776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000
00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=9365998 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ct
rl_same_csr_outstanding.9365998
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3013479674
Short name T1013
Test name
Test status
Simulation time 273628437 ps
CPU time 5.88 seconds
Started Oct 09 10:09:55 AM UTC 24
Finished Oct 09 10:10:02 AM UTC 24
Peak memory 224336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013479674 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_errors.3013479674
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1342321632
Short name T1008
Test name
Test status
Simulation time 96970661 ps
CPU time 2.06 seconds
Started Oct 09 10:09:55 AM UTC 24
Finished Oct 09 10:09:58 AM UTC 24
Peak memory 224256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342
321632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_tl_
intg_err.1342321632
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2350843688
Short name T1015
Test name
Test status
Simulation time 380071209 ps
CPU time 3.76 seconds
Started Oct 09 10:10:00 AM UTC 24
Finished Oct 09 10:10:04 AM UTC 24
Peak memory 213844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000
00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=2350843688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.2350843688
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3031886717
Short name T1009
Test name
Test status
Simulation time 62216735 ps
CPU time 0.97 seconds
Started Oct 09 10:09:58 AM UTC 24
Finished Oct 09 10:10:00 AM UTC 24
Peak memory 212716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031886717 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_rw.3031886717
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2222352368
Short name T94
Test name
Test status
Simulation time 15429980598 ps
CPU time 69.13 seconds
Started Oct 09 10:09:56 AM UTC 24
Finished Oct 09 10:11:07 AM UTC 24
Peak memory 214224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2
222352368 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_
passthru_mem_tl_intg_err.2222352368
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1960157127
Short name T104
Test name
Test status
Simulation time 15764146 ps
CPU time 1.04 seconds
Started Oct 09 10:09:58 AM UTC 24
Finished Oct 09 10:10:00 AM UTC 24
Peak memory 212780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000
00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=1960157127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram
_ctrl_same_csr_outstanding.1960157127
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.4214918514
Short name T1012
Test name
Test status
Simulation time 52796006 ps
CPU time 3.76 seconds
Started Oct 09 10:09:56 AM UTC 24
Finished Oct 09 10:10:01 AM UTC 24
Peak memory 224528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214918514 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_errors.4214918514
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3487167937
Short name T1010
Test name
Test status
Simulation time 705841140 ps
CPU time 2.6 seconds
Started Oct 09 10:09:57 AM UTC 24
Finished Oct 09 10:10:01 AM UTC 24
Peak memory 213972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487
167937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_tl_
intg_err.3487167937
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1656703668
Short name T1020
Test name
Test status
Simulation time 343805055 ps
CPU time 4.76 seconds
Started Oct 09 10:10:03 AM UTC 24
Finished Oct 09 10:10:09 AM UTC 24
Peak memory 213844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000
00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=1656703668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.1656703668
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2539730377
Short name T1016
Test name
Test status
Simulation time 29672902 ps
CPU time 0.94 seconds
Started Oct 09 10:10:02 AM UTC 24
Finished Oct 09 10:10:04 AM UTC 24
Peak memory 212716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539730377 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_rw.2539730377
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1849677083
Short name T1043
Test name
Test status
Simulation time 7578446798 ps
CPU time 36.13 seconds
Started Oct 09 10:10:02 AM UTC 24
Finished Oct 09 10:10:40 AM UTC 24
Peak memory 213972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1
849677083 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_
passthru_mem_tl_intg_err.1849677083
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3829518795
Short name T1017
Test name
Test status
Simulation time 187971830 ps
CPU time 1.14 seconds
Started Oct 09 10:10:02 AM UTC 24
Finished Oct 09 10:10:05 AM UTC 24
Peak memory 212776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000
00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=3829518795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram
_ctrl_same_csr_outstanding.3829518795
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2150492146
Short name T1019
Test name
Test status
Simulation time 140921441 ps
CPU time 4.3 seconds
Started Oct 09 10:10:02 AM UTC 24
Finished Oct 09 10:10:08 AM UTC 24
Peak memory 224152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150492146 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_tl_errors.2150492146
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3617171327
Short name T136
Test name
Test status
Simulation time 328563513 ps
CPU time 3.85 seconds
Started Oct 09 10:10:02 AM UTC 24
Finished Oct 09 10:10:07 AM UTC 24
Peak memory 224212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617
171327 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_tl_
intg_err.3617171327
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3279829348
Short name T1024
Test name
Test status
Simulation time 706235468 ps
CPU time 4.62 seconds
Started Oct 09 10:10:09 AM UTC 24
Finished Oct 09 10:10:14 AM UTC 24
Peak memory 224012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000
00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=3279829348 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.3279829348
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_csr_rw.641867704
Short name T1018
Test name
Test status
Simulation time 26761921 ps
CPU time 0.94 seconds
Started Oct 09 10:10:05 AM UTC 24
Finished Oct 09 10:10:07 AM UTC 24
Peak memory 212724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641867704 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_rw.641867704
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1473998776
Short name T90
Test name
Test status
Simulation time 15413431162 ps
CPU time 33.66 seconds
Started Oct 09 10:10:03 AM UTC 24
Finished Oct 09 10:10:38 AM UTC 24
Peak memory 214100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1
473998776 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_
passthru_mem_tl_intg_err.1473998776
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.100702783
Short name T1021
Test name
Test status
Simulation time 16535271 ps
CPU time 1.16 seconds
Started Oct 09 10:10:09 AM UTC 24
Finished Oct 09 10:10:11 AM UTC 24
Peak memory 212788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000
00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=100702783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_
ctrl_same_csr_outstanding.100702783
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_errors.4214343831
Short name T1023
Test name
Test status
Simulation time 473316906 ps
CPU time 7.76 seconds
Started Oct 09 10:10:05 AM UTC 24
Finished Oct 09 10:10:14 AM UTC 24
Peak memory 224336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214343831 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_errors.4214343831
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.996520004
Short name T141
Test name
Test status
Simulation time 642893691 ps
CPU time 3.57 seconds
Started Oct 09 10:10:05 AM UTC 24
Finished Oct 09 10:10:10 AM UTC 24
Peak memory 224488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9965
20004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_tl_i
ntg_err.996520004
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1776798575
Short name T1029
Test name
Test status
Simulation time 1045866224 ps
CPU time 6.03 seconds
Started Oct 09 10:10:15 AM UTC 24
Finished Oct 09 10:10:22 AM UTC 24
Peak memory 226452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=100000000
00 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/re
po/hw/dv/tools/sim.tcl +ntb_random_seed=1776798575 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.1776798575
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2807990673
Short name T1022
Test name
Test status
Simulation time 13516754 ps
CPU time 1.06 seconds
Started Oct 09 10:10:12 AM UTC 24
Finished Oct 09 10:10:14 AM UTC 24
Peak memory 212716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807990673 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_rw.2807990673
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.258615662
Short name T91
Test name
Test status
Simulation time 3868419102 ps
CPU time 36.69 seconds
Started Oct 09 10:10:09 AM UTC 24
Finished Oct 09 10:10:47 AM UTC 24
Peak memory 213900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2
58615662 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_p
assthru_mem_tl_intg_err.258615662
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1844218162
Short name T1026
Test name
Test status
Simulation time 27157311 ps
CPU time 0.95 seconds
Started Oct 09 10:10:15 AM UTC 24
Finished Oct 09 10:10:17 AM UTC 24
Peak memory 212804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=10000
00000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=1844218162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram
_ctrl_same_csr_outstanding.1844218162
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1742890441
Short name T1025
Test name
Test status
Simulation time 256874634 ps
CPU time 3.88 seconds
Started Oct 09 10:10:10 AM UTC 24
Finished Oct 09 10:10:15 AM UTC 24
Peak memory 224328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742890441 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_errors.1742890441
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.4276213026
Short name T139
Test name
Test status
Simulation time 143940945 ps
CPU time 3.03 seconds
Started Oct 09 10:10:11 AM UTC 24
Finished Oct 09 10:10:15 AM UTC 24
Peak memory 224212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276
213026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_tl_
intg_err.4276213026
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_access_during_key_req.1626289764
Short name T85
Test name
Test status
Simulation time 76842917087 ps
CPU time 806.39 seconds
Started Oct 09 12:18:05 PM UTC 24
Finished Oct 09 12:31:41 PM UTC 24
Peak memory 388152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626289764 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_access_durin
g_key_req.1626289764
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_bijection.3530834705
Short name T246
Test name
Test status
Simulation time 26894481128 ps
CPU time 1929.99 seconds
Started Oct 09 12:18:03 PM UTC 24
Finished Oct 09 12:50:37 PM UTC 24
Peak memory 211256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530834705 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.3530834705
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_executable.2282395184
Short name T149
Test name
Test status
Simulation time 16997138524 ps
CPU time 923.98 seconds
Started Oct 09 12:18:05 PM UTC 24
Finished Oct 09 12:33:40 PM UTC 24
Peak memory 386096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282395184 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executable.2282395184
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_max_throughput.2229183779
Short name T36
Test name
Test status
Simulation time 807529253 ps
CPU time 120.21 seconds
Started Oct 09 12:18:04 PM UTC 24
Finished Oct 09 12:20:06 PM UTC 24
Peak memory 380064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2229183779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_m
ax_throughput.2229183779
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_mem_walk.72831962
Short name T43
Test name
Test status
Simulation time 10904464098 ps
CPU time 250.52 seconds
Started Oct 09 12:18:05 PM UTC 24
Finished Oct 09 12:22:20 PM UTC 24
Peak memory 221928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72831962 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_mem_walk.72831962
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_multiple_keys.1194272685
Short name T195
Test name
Test status
Simulation time 18458400954 ps
CPU time 1058.66 seconds
Started Oct 09 12:18:03 PM UTC 24
Finished Oct 09 12:35:54 PM UTC 24
Peak memory 386168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194272685 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multiple_keys.1194272685
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access.1182091038
Short name T3
Test name
Test status
Simulation time 4255414477 ps
CPU time 13.11 seconds
Started Oct 09 12:18:03 PM UTC 24
Finished Oct 09 12:18:18 PM UTC 24
Peak memory 211020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182091038 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_partial_access.1182091038
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_partial_access_b2b.509798039
Short name T106
Test name
Test status
Simulation time 27880864331 ps
CPU time 374.47 seconds
Started Oct 09 12:18:03 PM UTC 24
Finished Oct 09 12:24:23 PM UTC 24
Peak memory 211576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509798039 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_partial_acc
ess_b2b.509798039
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_regwen.4226918557
Short name T117
Test name
Test status
Simulation time 2836043401 ps
CPU time 903.28 seconds
Started Oct 09 12:18:05 PM UTC 24
Finished Oct 09 12:33:20 PM UTC 24
Peak memory 386040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226918557 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.4226918557
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_sec_cm.2215319090
Short name T4
Test name
Test status
Simulation time 1277405717 ps
CPU time 9.55 seconds
Started Oct 09 12:18:12 PM UTC 24
Finished Oct 09 12:18:23 PM UTC 24
Peak memory 247764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215319090 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_sec_cm.2215319090
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_smoke.2271090737
Short name T6
Test name
Test status
Simulation time 1473680137 ps
CPU time 25.38 seconds
Started Oct 09 12:18:03 PM UTC 24
Finished Oct 09 12:18:30 PM UTC 24
Peak memory 211256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271090737 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.2271090737
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_pipeline.429093585
Short name T108
Test name
Test status
Simulation time 121517560777 ps
CPU time 586.1 seconds
Started Oct 09 12:18:03 PM UTC 24
Finished Oct 09 12:27:57 PM UTC 24
Peak memory 211264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429093585 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_stress_pipeline.429093585
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_throughput_w_partial_write.1485622681
Short name T11
Test name
Test status
Simulation time 1490977026 ps
CPU time 30.4 seconds
Started Oct 09 12:18:04 PM UTC 24
Finished Oct 09 12:18:36 PM UTC 24
Peak memory 295808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1485622681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_
throughput_w_partial_write.1485622681
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/0.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_access_during_key_req.1460314068
Short name T86
Test name
Test status
Simulation time 50357122510 ps
CPU time 901.26 seconds
Started Oct 09 12:18:50 PM UTC 24
Finished Oct 09 12:34:02 PM UTC 24
Peak memory 386176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460314068 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_access_durin
g_key_req.1460314068
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_alert_test.2735680643
Short name T14
Test name
Test status
Simulation time 41164389 ps
CPU time 0.99 seconds
Started Oct 09 12:20:11 PM UTC 24
Finished Oct 09 12:20:13 PM UTC 24
Peak memory 209432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735680643
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_alert_test.2735680643
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_bijection.3547276451
Short name T338
Test name
Test status
Simulation time 230209032680 ps
CPU time 2868.53 seconds
Started Oct 09 12:18:19 PM UTC 24
Finished Oct 09 01:06:41 PM UTC 24
Peak memory 211296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547276451 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection.3547276451
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_lc_escalation.1480811772
Short name T8
Test name
Test status
Simulation time 51932102234 ps
CPU time 119.22 seconds
Started Oct 09 12:18:37 PM UTC 24
Finished Oct 09 12:20:38 PM UTC 24
Peak memory 221740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1480811772 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_escalation.1480811772
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_max_throughput.3874894012
Short name T13
Test name
Test status
Simulation time 714923100 ps
CPU time 14.81 seconds
Started Oct 09 12:18:32 PM UTC 24
Finished Oct 09 12:18:48 PM UTC 24
Peak memory 232500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3874894012 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_m
ax_throughput.3874894012
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_partial_access.425686627
Short name T54
Test name
Test status
Simulation time 4495173377 ps
CPU time 150.2 seconds
Started Oct 09 12:19:25 PM UTC 24
Finished Oct 09 12:21:58 PM UTC 24
Peak memory 221604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425686627 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_mem_partial_access.425686627
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_mem_walk.2887613022
Short name T51
Test name
Test status
Simulation time 5361645068 ps
CPU time 312.78 seconds
Started Oct 09 12:19:01 PM UTC 24
Finished Oct 09 12:24:19 PM UTC 24
Peak memory 221540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887613022 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_mem_walk.2887613022
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_multiple_keys.908273339
Short name T181
Test name
Test status
Simulation time 21495972629 ps
CPU time 902.01 seconds
Started Oct 09 12:18:19 PM UTC 24
Finished Oct 09 12:33:31 PM UTC 24
Peak memory 388216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908273339 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multiple_keys.908273339
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_partial_access.3728139455
Short name T32
Test name
Test status
Simulation time 5283020397 ps
CPU time 75.18 seconds
Started Oct 09 12:18:24 PM UTC 24
Finished Oct 09 12:19:41 PM UTC 24
Peak memory 376064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728139455 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_partial_access.3728139455
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_ram_cfg.287419000
Short name T23
Test name
Test status
Simulation time 698450352 ps
CPU time 4.88 seconds
Started Oct 09 12:18:54 PM UTC 24
Finished Oct 09 12:19:00 PM UTC 24
Peak memory 211212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287419000 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.287419000
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_readback_err.4244781600
Short name T16
Test name
Test status
Simulation time 1354556664 ps
CPU time 10.37 seconds
Started Oct 09 12:19:32 PM UTC 24
Finished Oct 09 12:19:44 PM UTC 24
Peak memory 211284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244781600 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_readback_err.4244781600
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_regwen.3808193801
Short name T19
Test name
Test status
Simulation time 11786924899 ps
CPU time 142.52 seconds
Started Oct 09 12:18:53 PM UTC 24
Finished Oct 09 12:21:18 PM UTC 24
Peak memory 341308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808193801 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.3808193801
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_sec_cm.1310989693
Short name T18
Test name
Test status
Simulation time 348299421 ps
CPU time 2.45 seconds
Started Oct 09 12:20:07 PM UTC 24
Finished Oct 09 12:20:11 PM UTC 24
Peak memory 247840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310989693 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_sec_cm.1310989693
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_smoke.1843202599
Short name T10
Test name
Test status
Simulation time 715479478 ps
CPU time 12.12 seconds
Started Oct 09 12:18:18 PM UTC 24
Finished Oct 09 12:18:31 PM UTC 24
Peak memory 211152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843202599 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.1843202599
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all.1326716023
Short name T744
Test name
Test status
Simulation time 180532967524 ps
CPU time 6274.49 seconds
Started Oct 09 12:19:45 PM UTC 24
Finished Oct 09 02:05:27 PM UTC 24
Peak memory 393752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13267160
23 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all.1326716023
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.300456195
Short name T24
Test name
Test status
Simulation time 627712860 ps
CPU time 28.79 seconds
Started Oct 09 12:19:42 PM UTC 24
Finished Oct 09 12:20:12 PM UTC 24
Peak memory 221616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300456195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.300456195
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_pipeline.2907349371
Short name T62
Test name
Test status
Simulation time 3157435444 ps
CPU time 183.49 seconds
Started Oct 09 12:18:21 PM UTC 24
Finished Oct 09 12:21:27 PM UTC 24
Peak memory 211220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907349371 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_pipeline.2907349371
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_throughput_w_partial_write.2130510162
Short name T37
Test name
Test status
Simulation time 1615659000 ps
CPU time 103.66 seconds
Started Oct 09 12:18:33 PM UTC 24
Finished Oct 09 12:20:20 PM UTC 24
Peak memory 381936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2130510162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_
throughput_w_partial_write.2130510162
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/1.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.2521226017
Short name T286
Test name
Test status
Simulation time 38568912789 ps
CPU time 656.94 seconds
Started Oct 09 12:46:48 PM UTC 24
Finished Oct 09 12:57:53 PM UTC 24
Peak memory 388156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521226017 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_access_duri
ng_key_req.2521226017
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_alert_test.3721437915
Short name T242
Test name
Test status
Simulation time 23778793 ps
CPU time 0.97 seconds
Started Oct 09 12:50:09 PM UTC 24
Finished Oct 09 12:50:12 PM UTC 24
Peak memory 209432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721437915
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_alert_test.3721437915
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_bijection.360119199
Short name T295
Test name
Test status
Simulation time 124087355019 ps
CPU time 842.94 seconds
Started Oct 09 12:45:34 PM UTC 24
Finished Oct 09 12:59:48 PM UTC 24
Peak memory 211348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360119199 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection.360119199
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_executable.1763505270
Short name T249
Test name
Test status
Simulation time 7851377346 ps
CPU time 199.54 seconds
Started Oct 09 12:47:46 PM UTC 24
Finished Oct 09 12:51:08 PM UTC 24
Peak memory 320636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763505270 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executable.1763505270
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_lc_escalation.3453964077
Short name T237
Test name
Test status
Simulation time 33157411135 ps
CPU time 96.55 seconds
Started Oct 09 12:46:46 PM UTC 24
Finished Oct 09 12:48:25 PM UTC 24
Peak memory 221732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453964077 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_escalation.3453964077
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_max_throughput.7243817
Short name T233
Test name
Test status
Simulation time 718111203 ps
CPU time 26.05 seconds
Started Oct 09 12:46:18 PM UTC 24
Finished Oct 09 12:46:45 PM UTC 24
Peak memory 294076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
7243817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_max
_throughput.7243817
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_partial_access.3941846072
Short name T251
Test name
Test status
Simulation time 18838927948 ps
CPU time 150.98 seconds
Started Oct 09 12:48:39 PM UTC 24
Finished Oct 09 12:51:13 PM UTC 24
Peak memory 221768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941846072 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_mem_partial_access.3941846072
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_mem_walk.1783370739
Short name T264
Test name
Test status
Simulation time 5417964842 ps
CPU time 300.17 seconds
Started Oct 09 12:48:34 PM UTC 24
Finished Oct 09 12:53:39 PM UTC 24
Peak memory 221536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783370739 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_mem_walk.1783370739
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.2483527736
Short name T265
Test name
Test status
Simulation time 11901187878 ps
CPU time 507.21 seconds
Started Oct 09 12:45:09 PM UTC 24
Finished Oct 09 12:53:43 PM UTC 24
Peak memory 384304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483527736 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multiple_keys.2483527736
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access.214999265
Short name T231
Test name
Test status
Simulation time 907221695 ps
CPU time 37.77 seconds
Started Oct 09 12:45:37 PM UTC 24
Finished Oct 09 12:46:17 PM UTC 24
Peak memory 304112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214999265 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_partial_access.214999265
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_partial_access_b2b.1367871855
Short name T256
Test name
Test status
Simulation time 26818125646 ps
CPU time 381.83 seconds
Started Oct 09 12:45:39 PM UTC 24
Finished Oct 09 12:52:07 PM UTC 24
Peak memory 211388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367871855 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_partial_a
ccess_b2b.1367871855
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_ram_cfg.800772115
Short name T238
Test name
Test status
Simulation time 355194266 ps
CPU time 6.23 seconds
Started Oct 09 12:48:26 PM UTC 24
Finished Oct 09 12:48:34 PM UTC 24
Peak memory 211296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800772115 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.800772115
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_readback_err.215601656
Short name T240
Test name
Test status
Simulation time 2657826706 ps
CPU time 5.85 seconds
Started Oct 09 12:49:19 PM UTC 24
Finished Oct 09 12:49:26 PM UTC 24
Peak memory 211428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215601656 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_readback_err.215601656
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_regwen.389958660
Short name T277
Test name
Test status
Simulation time 3569820687 ps
CPU time 504.23 seconds
Started Oct 09 12:47:49 PM UTC 24
Finished Oct 09 12:56:20 PM UTC 24
Peak memory 388280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389958660 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.389958660
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_smoke.1333881911
Short name T230
Test name
Test status
Simulation time 1120323957 ps
CPU time 26.31 seconds
Started Oct 09 12:45:09 PM UTC 24
Finished Oct 09 12:45:37 PM UTC 24
Peak memory 211076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333881911 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.1333881911
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all.216907803
Short name T878
Test name
Test status
Simulation time 1482878266945 ps
CPU time 5611.78 seconds
Started Oct 09 12:49:27 PM UTC 24
Finished Oct 09 02:24:03 PM UTC 24
Peak memory 389648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21690780
3 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all.216907803
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3339522565
Short name T67
Test name
Test status
Simulation time 924290153 ps
CPU time 40.6 seconds
Started Oct 09 12:49:26 PM UTC 24
Finished Oct 09 12:50:08 PM UTC 24
Peak memory 221472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339522565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.3339522565
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_pipeline.3999807848
Short name T261
Test name
Test status
Simulation time 19274302801 ps
CPU time 468.17 seconds
Started Oct 09 12:45:35 PM UTC 24
Finished Oct 09 12:53:31 PM UTC 24
Peak memory 211260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999807848 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_pipeline.3999807848
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_throughput_w_partial_write.59803490
Short name T234
Test name
Test status
Simulation time 765057830 ps
CPU time 23.96 seconds
Started Oct 09 12:46:22 PM UTC 24
Finished Oct 09 12:46:47 PM UTC 24
Peak memory 300276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=59803490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_t
hroughput_w_partial_write.59803490
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/10.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.3952240373
Short name T263
Test name
Test status
Simulation time 3695843559 ps
CPU time 146.46 seconds
Started Oct 09 12:51:09 PM UTC 24
Finished Oct 09 12:53:38 PM UTC 24
Peak memory 379964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952240373 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_access_duri
ng_key_req.3952240373
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_alert_test.1554831239
Short name T259
Test name
Test status
Simulation time 36509108 ps
CPU time 0.95 seconds
Started Oct 09 12:52:10 PM UTC 24
Finished Oct 09 12:52:12 PM UTC 24
Peak memory 209012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554831239
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_alert_test.1554831239
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_bijection.995908162
Short name T408
Test name
Test status
Simulation time 116799799811 ps
CPU time 1717.4 seconds
Started Oct 09 12:50:15 PM UTC 24
Finished Oct 09 01:19:13 PM UTC 24
Peak memory 211272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995908162 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection.995908162
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_executable.2289936234
Short name T350
Test name
Test status
Simulation time 19195567225 ps
CPU time 1039.4 seconds
Started Oct 09 12:51:13 PM UTC 24
Finished Oct 09 01:08:44 PM UTC 24
Peak memory 382112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289936234 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executable.2289936234
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_lc_escalation.1558211726
Short name T250
Test name
Test status
Simulation time 6152980018 ps
CPU time 17.41 seconds
Started Oct 09 12:50:54 PM UTC 24
Finished Oct 09 12:51:12 PM UTC 24
Peak memory 211260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558211726 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_escalation.1558211726
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_max_throughput.1316681245
Short name T253
Test name
Test status
Simulation time 3401680446 ps
CPU time 63.7 seconds
Started Oct 09 12:50:38 PM UTC 24
Finished Oct 09 12:51:44 PM UTC 24
Peak memory 336928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1316681245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_
max_throughput.1316681245
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_partial_access.1320975146
Short name T59
Test name
Test status
Simulation time 40497903480 ps
CPU time 221.16 seconds
Started Oct 09 12:51:46 PM UTC 24
Finished Oct 09 12:55:30 PM UTC 24
Peak memory 221836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320975146 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_mem_partial_access.1320975146
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_mem_walk.578240824
Short name T288
Test name
Test status
Simulation time 10717505698 ps
CPU time 376.86 seconds
Started Oct 09 12:51:44 PM UTC 24
Finished Oct 09 12:58:06 PM UTC 24
Peak memory 221612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578240824 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_mem_walk.578240824
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_multiple_keys.1833143634
Short name T326
Test name
Test status
Simulation time 6167865368 ps
CPU time 819.66 seconds
Started Oct 09 12:50:13 PM UTC 24
Finished Oct 09 01:04:02 PM UTC 24
Peak memory 386096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833143634 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multiple_keys.1833143634
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access.4202054845
Short name T248
Test name
Test status
Simulation time 432317383 ps
CPU time 19.09 seconds
Started Oct 09 12:50:32 PM UTC 24
Finished Oct 09 12:50:52 PM UTC 24
Peak memory 273364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202054845 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_partial_access.4202054845
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_partial_access_b2b.1242670508
Short name T309
Test name
Test status
Simulation time 63297673644 ps
CPU time 638.53 seconds
Started Oct 09 12:50:37 PM UTC 24
Finished Oct 09 01:01:24 PM UTC 24
Peak memory 211260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242670508 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_partial_a
ccess_b2b.1242670508
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_ram_cfg.3898127958
Short name T254
Test name
Test status
Simulation time 419506792 ps
CPU time 6.22 seconds
Started Oct 09 12:51:37 PM UTC 24
Finished Oct 09 12:51:45 PM UTC 24
Peak memory 211484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898127958 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.3898127958
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_readback_err.2886136997
Short name T255
Test name
Test status
Simulation time 694031848 ps
CPU time 10.28 seconds
Started Oct 09 12:51:46 PM UTC 24
Finished Oct 09 12:51:57 PM UTC 24
Peak memory 211360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886136997 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_readback_err.2886136997
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_regwen.3011745003
Short name T325
Test name
Test status
Simulation time 2957245701 ps
CPU time 759.94 seconds
Started Oct 09 12:51:14 PM UTC 24
Finished Oct 09 01:04:02 PM UTC 24
Peak memory 381916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011745003 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.3011745003
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_smoke.586327430
Short name T245
Test name
Test status
Simulation time 1520145266 ps
CPU time 25.03 seconds
Started Oct 09 12:50:10 PM UTC 24
Finished Oct 09 12:50:36 PM UTC 24
Peak memory 211184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586327430 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.586327430
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all.1416675056
Short name T957
Test name
Test status
Simulation time 245802519281 ps
CPU time 6233.04 seconds
Started Oct 09 12:52:08 PM UTC 24
Finished Oct 09 02:37:09 PM UTC 24
Peak memory 399908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14166750
56 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_a
ll.1416675056
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3463892041
Short name T257
Test name
Test status
Simulation time 1959561441 ps
CPU time 10.29 seconds
Started Oct 09 12:51:58 PM UTC 24
Finished Oct 09 12:52:09 PM UTC 24
Peak memory 221600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463892041 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.3463892041
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_pipeline.3976511537
Short name T276
Test name
Test status
Simulation time 10730275925 ps
CPU time 334.22 seconds
Started Oct 09 12:50:30 PM UTC 24
Finished Oct 09 12:56:09 PM UTC 24
Peak memory 211420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976511537 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_pipeline.3976511537
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_throughput_w_partial_write.1579133551
Short name T252
Test name
Test status
Simulation time 3103550527 ps
CPU time 50.51 seconds
Started Oct 09 12:50:44 PM UTC 24
Finished Oct 09 12:51:36 PM UTC 24
Peak memory 320572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1579133551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl
_throughput_w_partial_write.1579133551
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/11.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.411849161
Short name T310
Test name
Test status
Simulation time 16778958439 ps
CPU time 443.05 seconds
Started Oct 09 12:53:59 PM UTC 24
Finished Oct 09 01:01:27 PM UTC 24
Peak memory 386120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411849161 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_access_durin
g_key_req.411849161
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_alert_test.684842096
Short name T274
Test name
Test status
Simulation time 25713172 ps
CPU time 0.98 seconds
Started Oct 09 12:56:02 PM UTC 24
Finished Oct 09 12:56:04 PM UTC 24
Peak memory 209432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684842096 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_alert_test.684842096
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_bijection.362467284
Short name T341
Test name
Test status
Simulation time 154552443928 ps
CPU time 869.23 seconds
Started Oct 09 12:52:35 PM UTC 24
Finished Oct 09 01:07:15 PM UTC 24
Peak memory 211464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362467284 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection.362467284
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_executable.4102975167
Short name T346
Test name
Test status
Simulation time 8981575814 ps
CPU time 825.52 seconds
Started Oct 09 12:54:07 PM UTC 24
Finished Oct 09 01:08:02 PM UTC 24
Peak memory 388160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102975167 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executable.4102975167
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_lc_escalation.2129784000
Short name T282
Test name
Test status
Simulation time 18242947216 ps
CPU time 215.33 seconds
Started Oct 09 12:53:48 PM UTC 24
Finished Oct 09 12:57:26 PM UTC 24
Peak memory 211280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129784000 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_escalation.2129784000
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_max_throughput.1335192402
Short name T269
Test name
Test status
Simulation time 982868754 ps
CPU time 35.83 seconds
Started Oct 09 12:53:40 PM UTC 24
Finished Oct 09 12:54:18 PM UTC 24
Peak memory 310512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1335192402 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_
max_throughput.1335192402
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_partial_access.2543470674
Short name T60
Test name
Test status
Simulation time 2629061071 ps
CPU time 106.51 seconds
Started Oct 09 12:55:30 PM UTC 24
Finished Oct 09 12:57:19 PM UTC 24
Peak memory 221560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543470674 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_mem_partial_access.2543470674
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_mem_walk.2398749048
Short name T285
Test name
Test status
Simulation time 98846459573 ps
CPU time 192.68 seconds
Started Oct 09 12:54:26 PM UTC 24
Finished Oct 09 12:57:42 PM UTC 24
Peak memory 221672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398749048 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_mem_walk.2398749048
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.2253745935
Short name T327
Test name
Test status
Simulation time 44240923021 ps
CPU time 705.24 seconds
Started Oct 09 12:52:13 PM UTC 24
Finished Oct 09 01:04:08 PM UTC 24
Peak memory 384092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253745935 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multiple_keys.2253745935
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access.2995378392
Short name T267
Test name
Test status
Simulation time 593838623 ps
CPU time 23.48 seconds
Started Oct 09 12:53:33 PM UTC 24
Finished Oct 09 12:53:58 PM UTC 24
Peak memory 211196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995378392 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_partial_access.2995378392
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_partial_access_b2b.2526888090
Short name T303
Test name
Test status
Simulation time 218396218852 ps
CPU time 415.38 seconds
Started Oct 09 12:53:39 PM UTC 24
Finished Oct 09 01:00:40 PM UTC 24
Peak memory 211388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526888090 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_partial_a
ccess_b2b.2526888090
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_ram_cfg.2030149913
Short name T270
Test name
Test status
Simulation time 350411227 ps
CPU time 5.75 seconds
Started Oct 09 12:54:18 PM UTC 24
Finished Oct 09 12:54:25 PM UTC 24
Peak memory 211284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030149913 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.2030149913
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_readback_err.4079991298
Short name T272
Test name
Test status
Simulation time 662002419 ps
CPU time 10.88 seconds
Started Oct 09 12:55:31 PM UTC 24
Finished Oct 09 12:55:43 PM UTC 24
Peak memory 211364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079991298 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_readback_err.4079991298
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_regwen.2798199769
Short name T133
Test name
Test status
Simulation time 8444472677 ps
CPU time 109.53 seconds
Started Oct 09 12:54:12 PM UTC 24
Finished Oct 09 12:56:04 PM UTC 24
Peak memory 343360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798199769 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.2798199769
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_smoke.2831418845
Short name T260
Test name
Test status
Simulation time 502692300 ps
CPU time 20.55 seconds
Started Oct 09 12:52:12 PM UTC 24
Finished Oct 09 12:52:34 PM UTC 24
Peak memory 211332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831418845 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.2831418845
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all.20415957
Short name T922
Test name
Test status
Simulation time 523938683516 ps
CPU time 5507.3 seconds
Started Oct 09 12:56:01 PM UTC 24
Finished Oct 09 02:28:52 PM UTC 24
Peak memory 391700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20415957
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all.20415957
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.468359913
Short name T275
Test name
Test status
Simulation time 1318553235 ps
CPU time 21.06 seconds
Started Oct 09 12:55:44 PM UTC 24
Finished Oct 09 12:56:06 PM UTC 24
Peak memory 221516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468359913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.468359913
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_pipeline.3531276263
Short name T301
Test name
Test status
Simulation time 11252501168 ps
CPU time 418.44 seconds
Started Oct 09 12:53:32 PM UTC 24
Finished Oct 09 01:00:37 PM UTC 24
Peak memory 211432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531276263 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_pipeline.3531276263
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_throughput_w_partial_write.1001821560
Short name T271
Test name
Test status
Simulation time 8620675715 ps
CPU time 102.66 seconds
Started Oct 09 12:53:43 PM UTC 24
Finished Oct 09 12:55:28 PM UTC 24
Peak memory 374068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1001821560 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl
_throughput_w_partial_write.1001821560
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/12.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.2924352275
Short name T291
Test name
Test status
Simulation time 2820915993 ps
CPU time 92.08 seconds
Started Oct 09 12:57:11 PM UTC 24
Finished Oct 09 12:58:45 PM UTC 24
Peak memory 263208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924352275 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_access_duri
ng_key_req.2924352275
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_alert_test.2393726410
Short name T289
Test name
Test status
Simulation time 34828013 ps
CPU time 1.02 seconds
Started Oct 09 12:58:07 PM UTC 24
Finished Oct 09 12:58:09 PM UTC 24
Peak memory 211336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393726410
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_alert_test.2393726410
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_bijection.117732389
Short name T543
Test name
Test status
Simulation time 149355677636 ps
CPU time 2398.33 seconds
Started Oct 09 12:56:08 PM UTC 24
Finished Oct 09 01:36:34 PM UTC 24
Peak memory 212788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117732389 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection.117732389
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_executable.842678599
Short name T152
Test name
Test status
Simulation time 254520171099 ps
CPU time 1065.27 seconds
Started Oct 09 12:57:20 PM UTC 24
Finished Oct 09 01:15:17 PM UTC 24
Peak memory 388216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842678599 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executable.842678599
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_lc_escalation.2779796125
Short name T283
Test name
Test status
Simulation time 5751859255 ps
CPU time 21.62 seconds
Started Oct 09 12:57:03 PM UTC 24
Finished Oct 09 12:57:26 PM UTC 24
Peak memory 221324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779796125 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_escalation.2779796125
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_max_throughput.1160191942
Short name T280
Test name
Test status
Simulation time 725700003 ps
CPU time 18.26 seconds
Started Oct 09 12:56:43 PM UTC 24
Finished Oct 09 12:57:03 PM UTC 24
Peak memory 251068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1160191942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_
max_throughput.1160191942
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_partial_access.1649442416
Short name T302
Test name
Test status
Simulation time 2457882985 ps
CPU time 172.87 seconds
Started Oct 09 12:57:43 PM UTC 24
Finished Oct 09 01:00:39 PM UTC 24
Peak memory 221508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649442416 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_mem_partial_access.1649442416
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_mem_walk.2913826520
Short name T294
Test name
Test status
Simulation time 4118872249 ps
CPU time 117 seconds
Started Oct 09 12:57:34 PM UTC 24
Finished Oct 09 12:59:35 PM UTC 24
Peak memory 221632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913826520 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_mem_walk.2913826520
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.440465668
Short name T308
Test name
Test status
Simulation time 3456816216 ps
CPU time 285.48 seconds
Started Oct 09 12:56:05 PM UTC 24
Finished Oct 09 01:00:55 PM UTC 24
Peak memory 379960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440465668 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multiple_keys.440465668
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access.1124366861
Short name T279
Test name
Test status
Simulation time 3500273900 ps
CPU time 28.45 seconds
Started Oct 09 12:56:21 PM UTC 24
Finished Oct 09 12:56:51 PM UTC 24
Peak memory 211236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124366861 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_partial_access.1124366861
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_partial_access_b2b.85794617
Short name T335
Test name
Test status
Simulation time 20286725676 ps
CPU time 581.01 seconds
Started Oct 09 12:56:21 PM UTC 24
Finished Oct 09 01:06:09 PM UTC 24
Peak memory 211400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85794617 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_partial_acc
ess_b2b.85794617
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_ram_cfg.532888122
Short name T284
Test name
Test status
Simulation time 431392579 ps
CPU time 5.66 seconds
Started Oct 09 12:57:27 PM UTC 24
Finished Oct 09 12:57:34 PM UTC 24
Peak memory 211296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532888122 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.532888122
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_readback_err.3385612647
Short name T287
Test name
Test status
Simulation time 1376552236 ps
CPU time 11.31 seconds
Started Oct 09 12:57:53 PM UTC 24
Finished Oct 09 12:58:06 PM UTC 24
Peak memory 211284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385612647 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_readback_err.3385612647
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_regwen.1778370040
Short name T305
Test name
Test status
Simulation time 6317680851 ps
CPU time 197.07 seconds
Started Oct 09 12:57:27 PM UTC 24
Finished Oct 09 01:00:47 PM UTC 24
Peak memory 375832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778370040 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.1778370040
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_smoke.2005508148
Short name T278
Test name
Test status
Simulation time 5809081782 ps
CPU time 36.71 seconds
Started Oct 09 12:56:04 PM UTC 24
Finished Oct 09 12:56:43 PM UTC 24
Peak memory 211308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005508148 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.2005508148
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all.2721987334
Short name T793
Test name
Test status
Simulation time 395170832421 ps
CPU time 4356.5 seconds
Started Oct 09 12:58:07 PM UTC 24
Finished Oct 09 02:11:31 PM UTC 24
Peak memory 391712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27219873
34 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_a
ll.2721987334
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.2340624646
Short name T61
Test name
Test status
Simulation time 8544988926 ps
CPU time 40.66 seconds
Started Oct 09 12:58:06 PM UTC 24
Finished Oct 09 12:58:48 PM UTC 24
Peak memory 228592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340624646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.2340624646
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_pipeline.4086072939
Short name T324
Test name
Test status
Simulation time 5505289528 ps
CPU time 428.13 seconds
Started Oct 09 12:56:10 PM UTC 24
Finished Oct 09 01:03:24 PM UTC 24
Peak memory 211624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086072939 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_pipeline.4086072939
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_throughput_w_partial_write.4242735391
Short name T281
Test name
Test status
Simulation time 2840635978 ps
CPU time 16.81 seconds
Started Oct 09 12:56:51 PM UTC 24
Finished Oct 09 12:57:10 PM UTC 24
Peak memory 234488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=4242735391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl
_throughput_w_partial_write.4242735391
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/13.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.2083880543
Short name T304
Test name
Test status
Simulation time 1635234280 ps
CPU time 49.04 seconds
Started Oct 09 12:59:53 PM UTC 24
Finished Oct 09 01:00:43 PM UTC 24
Peak memory 211140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083880543 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_access_duri
ng_key_req.2083880543
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_alert_test.877500881
Short name T306
Test name
Test status
Simulation time 38242688 ps
CPU time 1.1 seconds
Started Oct 09 01:00:48 PM UTC 24
Finished Oct 09 01:00:50 PM UTC 24
Peak memory 209432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877500881 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_alert_test.877500881
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_bijection.3083576266
Short name T362
Test name
Test status
Simulation time 36214940161 ps
CPU time 729.95 seconds
Started Oct 09 12:58:45 PM UTC 24
Finished Oct 09 01:11:05 PM UTC 24
Peak memory 211364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083576266 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection.3083576266
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_executable.313672549
Short name T390
Test name
Test status
Simulation time 34563739696 ps
CPU time 916.28 seconds
Started Oct 09 12:59:54 PM UTC 24
Finished Oct 09 01:15:20 PM UTC 24
Peak memory 388220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313672549 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executable.313672549
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_lc_escalation.1719803694
Short name T311
Test name
Test status
Simulation time 49995883914 ps
CPU time 96.97 seconds
Started Oct 09 12:59:49 PM UTC 24
Finished Oct 09 01:01:28 PM UTC 24
Peak memory 221504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719803694 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_escalation.1719803694
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_max_throughput.2717859132
Short name T299
Test name
Test status
Simulation time 767389586 ps
CPU time 44.08 seconds
Started Oct 09 12:59:31 PM UTC 24
Finished Oct 09 01:00:17 PM UTC 24
Peak memory 332720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2717859132 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_
max_throughput.2717859132
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_partial_access.2649008347
Short name T312
Test name
Test status
Simulation time 960483247 ps
CPU time 64.06 seconds
Started Oct 09 01:00:37 PM UTC 24
Finished Oct 09 01:01:43 PM UTC 24
Peak memory 228344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649008347 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_mem_partial_access.2649008347
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.2950748727
Short name T342
Test name
Test status
Simulation time 39012256477 ps
CPU time 418.71 seconds
Started Oct 09 01:00:25 PM UTC 24
Finished Oct 09 01:07:30 PM UTC 24
Peak memory 221792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950748727 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_mem_walk.2950748727
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.3262266412
Short name T396
Test name
Test status
Simulation time 76913726583 ps
CPU time 1104.65 seconds
Started Oct 09 12:58:42 PM UTC 24
Finished Oct 09 01:17:20 PM UTC 24
Peak memory 388108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262266412 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multiple_keys.3262266412
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access.1378842234
Short name T293
Test name
Test status
Simulation time 5192284190 ps
CPU time 30.73 seconds
Started Oct 09 12:58:58 PM UTC 24
Finished Oct 09 12:59:30 PM UTC 24
Peak memory 211268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378842234 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_partial_access.1378842234
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.3615066568
Short name T343
Test name
Test status
Simulation time 20915894890 ps
CPU time 495.43 seconds
Started Oct 09 12:59:28 PM UTC 24
Finished Oct 09 01:07:50 PM UTC 24
Peak memory 211260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615066568 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_partial_a
ccess_b2b.3615066568
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_ram_cfg.957155290
Short name T300
Test name
Test status
Simulation time 712916788 ps
CPU time 4.79 seconds
Started Oct 09 01:00:18 PM UTC 24
Finished Oct 09 01:00:24 PM UTC 24
Peak memory 211304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957155290 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.957155290
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_readback_err.975568144
Short name T307
Test name
Test status
Simulation time 2356798428 ps
CPU time 12.32 seconds
Started Oct 09 01:00:40 PM UTC 24
Finished Oct 09 01:00:54 PM UTC 24
Peak memory 211344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975568144 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_readback_err.975568144
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_regwen.3305077396
Short name T368
Test name
Test status
Simulation time 56192916653 ps
CPU time 674.81 seconds
Started Oct 09 01:00:16 PM UTC 24
Finished Oct 09 01:11:39 PM UTC 24
Peak memory 380224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305077396 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.3305077396
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_smoke.1539261755
Short name T297
Test name
Test status
Simulation time 790553552 ps
CPU time 100.23 seconds
Started Oct 09 12:58:10 PM UTC 24
Finished Oct 09 12:59:53 PM UTC 24
Peak memory 365556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539261755 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.1539261755
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_all.1506643624
Short name T611
Test name
Test status
Simulation time 157764004107 ps
CPU time 2680.6 seconds
Started Oct 09 01:00:45 PM UTC 24
Finished Oct 09 01:45:56 PM UTC 24
Peak memory 385640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15066436
24 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_a
ll.1506643624
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.1658361054
Short name T121
Test name
Test status
Simulation time 5315149226 ps
CPU time 83.32 seconds
Started Oct 09 01:00:41 PM UTC 24
Finished Oct 09 01:02:07 PM UTC 24
Peak memory 308396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658361054 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.1658361054
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_pipeline.580191563
Short name T315
Test name
Test status
Simulation time 5649007722 ps
CPU time 198.7 seconds
Started Oct 09 12:58:49 PM UTC 24
Finished Oct 09 01:02:11 PM UTC 24
Peak memory 211500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580191563 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_pipeline.580191563
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_throughput_w_partial_write.2668434341
Short name T296
Test name
Test status
Simulation time 737220346 ps
CPU time 15.13 seconds
Started Oct 09 12:59:35 PM UTC 24
Finished Oct 09 12:59:52 PM UTC 24
Peak memory 244652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2668434341 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl
_throughput_w_partial_write.2668434341
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/14.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.2423267363
Short name T457
Test name
Test status
Simulation time 69318534342 ps
CPU time 1369.86 seconds
Started Oct 09 01:01:59 PM UTC 24
Finished Oct 09 01:25:08 PM UTC 24
Peak memory 382080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423267363 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_access_duri
ng_key_req.2423267363
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_alert_test.133891580
Short name T323
Test name
Test status
Simulation time 27293802 ps
CPU time 1.13 seconds
Started Oct 09 01:03:22 PM UTC 24
Finished Oct 09 01:03:24 PM UTC 24
Peak memory 209428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133891580 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_alert_test.133891580
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_bijection.1335826320
Short name T533
Test name
Test status
Simulation time 33565815909 ps
CPU time 2047.55 seconds
Started Oct 09 01:00:55 PM UTC 24
Finished Oct 09 01:35:26 PM UTC 24
Peak memory 212720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335826320 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection.1335826320
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_executable.4085129634
Short name T381
Test name
Test status
Simulation time 16835388161 ps
CPU time 698.88 seconds
Started Oct 09 01:02:08 PM UTC 24
Finished Oct 09 01:13:57 PM UTC 24
Peak memory 377952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085129634 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executable.4085129634
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.1763937315
Short name T316
Test name
Test status
Simulation time 2851925541 ps
CPU time 35.24 seconds
Started Oct 09 01:01:47 PM UTC 24
Finished Oct 09 01:02:24 PM UTC 24
Peak memory 221456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763937315 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_escalation.1763937315
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.3606569395
Short name T314
Test name
Test status
Simulation time 1479315628 ps
CPU time 26.82 seconds
Started Oct 09 01:01:30 PM UTC 24
Finished Oct 09 01:01:58 PM UTC 24
Peak memory 287656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3606569395 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_
max_throughput.3606569395
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.3035264724
Short name T87
Test name
Test status
Simulation time 4855743611 ps
CPU time 195.25 seconds
Started Oct 09 01:02:31 PM UTC 24
Finished Oct 09 01:05:50 PM UTC 24
Peak memory 221616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035264724 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_mem_partial_access.3035264724
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.3338152190
Short name T332
Test name
Test status
Simulation time 18788640435 ps
CPU time 209.24 seconds
Started Oct 09 01:02:27 PM UTC 24
Finished Oct 09 01:06:00 PM UTC 24
Peak memory 221568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338152190 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_mem_walk.3338152190
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.2574504958
Short name T359
Test name
Test status
Simulation time 10780019754 ps
CPU time 547.01 seconds
Started Oct 09 01:00:51 PM UTC 24
Finished Oct 09 01:10:05 PM UTC 24
Peak memory 384284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574504958 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multiple_keys.2574504958
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access.855530677
Short name T313
Test name
Test status
Simulation time 1078466817 ps
CPU time 19.19 seconds
Started Oct 09 01:01:25 PM UTC 24
Finished Oct 09 01:01:46 PM UTC 24
Peak memory 253108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855530677 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_partial_access.855530677
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.1713912020
Short name T377
Test name
Test status
Simulation time 23143062113 ps
CPU time 653.29 seconds
Started Oct 09 01:01:29 PM UTC 24
Finished Oct 09 01:12:31 PM UTC 24
Peak memory 211532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713912020 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_partial_a
ccess_b2b.1713912020
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.482396729
Short name T318
Test name
Test status
Simulation time 1773816113 ps
CPU time 4.63 seconds
Started Oct 09 01:02:25 PM UTC 24
Finished Oct 09 01:02:31 PM UTC 24
Peak memory 211304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482396729 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.482396729
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_readback_err.3897380148
Short name T321
Test name
Test status
Simulation time 971718326 ps
CPU time 8.06 seconds
Started Oct 09 01:02:39 PM UTC 24
Finished Oct 09 01:02:48 PM UTC 24
Peak memory 211284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897380148 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_readback_err.3897380148
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_regwen.723440151
Short name T426
Test name
Test status
Simulation time 84672638065 ps
CPU time 1118.56 seconds
Started Oct 09 01:02:13 PM UTC 24
Finished Oct 09 01:21:06 PM UTC 24
Peak memory 367680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723440151 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.723440151
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_smoke.844535966
Short name T320
Test name
Test status
Simulation time 3813889330 ps
CPU time 112.37 seconds
Started Oct 09 01:00:51 PM UTC 24
Finished Oct 09 01:02:46 PM UTC 24
Peak memory 369724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844535966 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.844535966
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all.1156649936
Short name T833
Test name
Test status
Simulation time 960989284867 ps
CPU time 4471.8 seconds
Started Oct 09 01:02:50 PM UTC 24
Finished Oct 09 02:18:09 PM UTC 24
Peak memory 394028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11566499
36 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_a
ll.1156649936
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.2216316117
Short name T122
Test name
Test status
Simulation time 8095651213 ps
CPU time 37.51 seconds
Started Oct 09 01:02:46 PM UTC 24
Finished Oct 09 01:03:25 PM UTC 24
Peak memory 221988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216316117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.2216316117
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.2588490324
Short name T322
Test name
Test status
Simulation time 12260986215 ps
CPU time 141.51 seconds
Started Oct 09 01:00:56 PM UTC 24
Finished Oct 09 01:03:20 PM UTC 24
Peak memory 211336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588490324 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_pipeline.2588490324
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.1674369479
Short name T319
Test name
Test status
Simulation time 3202355139 ps
CPU time 52.29 seconds
Started Oct 09 01:01:44 PM UTC 24
Finished Oct 09 01:02:38 PM UTC 24
Peak memory 310436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1674369479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl
_throughput_w_partial_write.1674369479
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/15.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.632026948
Short name T431
Test name
Test status
Simulation time 56593184323 ps
CPU time 1013.91 seconds
Started Oct 09 01:04:36 PM UTC 24
Finished Oct 09 01:21:42 PM UTC 24
Peak memory 386116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632026948 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_access_durin
g_key_req.632026948
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_alert_test.3424623039
Short name T339
Test name
Test status
Simulation time 40972540 ps
CPU time 0.99 seconds
Started Oct 09 01:06:42 PM UTC 24
Finished Oct 09 01:06:44 PM UTC 24
Peak memory 209432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424623039
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_alert_test.3424623039
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_bijection.2493175647
Short name T506
Test name
Test status
Simulation time 193407604673 ps
CPU time 1720.26 seconds
Started Oct 09 01:03:26 PM UTC 24
Finished Oct 09 01:32:27 PM UTC 24
Peak memory 211340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493175647 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection.2493175647
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_executable.1939743350
Short name T349
Test name
Test status
Simulation time 4310021744 ps
CPU time 212.99 seconds
Started Oct 09 01:05:03 PM UTC 24
Finished Oct 09 01:08:40 PM UTC 24
Peak memory 386172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939743350 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executable.1939743350
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.699748128
Short name T337
Test name
Test status
Simulation time 140936022521 ps
CPU time 123.02 seconds
Started Oct 09 01:04:34 PM UTC 24
Finished Oct 09 01:06:39 PM UTC 24
Peak memory 221552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699748128 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_escalation.699748128
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.248464205
Short name T330
Test name
Test status
Simulation time 2944576061 ps
CPU time 19.47 seconds
Started Oct 09 01:04:13 PM UTC 24
Finished Oct 09 01:04:33 PM UTC 24
Peak memory 281592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
248464205 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_m
ax_throughput.248464205
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.3754327568
Short name T345
Test name
Test status
Simulation time 40989110770 ps
CPU time 106.61 seconds
Started Oct 09 01:06:09 PM UTC 24
Finished Oct 09 01:07:58 PM UTC 24
Peak memory 221656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754327568 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_mem_partial_access.3754327568
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.4235117709
Short name T372
Test name
Test status
Simulation time 20730750350 ps
CPU time 339.33 seconds
Started Oct 09 01:06:09 PM UTC 24
Finished Oct 09 01:11:53 PM UTC 24
Peak memory 221560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235117709 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_mem_walk.4235117709
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.880770559
Short name T348
Test name
Test status
Simulation time 31762029047 ps
CPU time 309.54 seconds
Started Oct 09 01:03:25 PM UTC 24
Finished Oct 09 01:08:39 PM UTC 24
Peak memory 386168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880770559 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multiple_keys.880770559
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access.3700291158
Short name T331
Test name
Test status
Simulation time 1127420843 ps
CPU time 56.84 seconds
Started Oct 09 01:04:03 PM UTC 24
Finished Oct 09 01:05:02 PM UTC 24
Peak memory 326636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700291158 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_partial_access.3700291158
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.3434899781
Short name T370
Test name
Test status
Simulation time 21913920671 ps
CPU time 444.32 seconds
Started Oct 09 01:04:10 PM UTC 24
Finished Oct 09 01:11:40 PM UTC 24
Peak memory 211260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434899781 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_partial_a
ccess_b2b.3434899781
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.636099460
Short name T333
Test name
Test status
Simulation time 371812475 ps
CPU time 5.99 seconds
Started Oct 09 01:06:01 PM UTC 24
Finished Oct 09 01:06:08 PM UTC 24
Peak memory 211296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636099460 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.636099460
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_readback_err.3819679222
Short name T336
Test name
Test status
Simulation time 4699423399 ps
CPU time 11.33 seconds
Started Oct 09 01:06:10 PM UTC 24
Finished Oct 09 01:06:23 PM UTC 24
Peak memory 211412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819679222 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_readback_err.3819679222
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_regwen.3760646217
Short name T379
Test name
Test status
Simulation time 10408681847 ps
CPU time 441.57 seconds
Started Oct 09 01:05:51 PM UTC 24
Finished Oct 09 01:13:18 PM UTC 24
Peak memory 359612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760646217 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.3760646217
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_smoke.2220081032
Short name T329
Test name
Test status
Simulation time 1637434727 ps
CPU time 47.28 seconds
Started Oct 09 01:03:25 PM UTC 24
Finished Oct 09 01:04:14 PM UTC 24
Peak memory 308212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220081032 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.2220081032
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all.1919714224
Short name T515
Test name
Test status
Simulation time 56670847279 ps
CPU time 1616.4 seconds
Started Oct 09 01:06:40 PM UTC 24
Finished Oct 09 01:33:56 PM UTC 24
Peak memory 388288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19197142
24 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_a
ll.1919714224
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.38771028
Short name T123
Test name
Test status
Simulation time 4445978335 ps
CPU time 37.21 seconds
Started Oct 09 01:06:23 PM UTC 24
Finished Oct 09 01:07:02 PM UTC 24
Peak memory 221856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38771028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.38771028
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.1168837789
Short name T352
Test name
Test status
Simulation time 2721772039 ps
CPU time 289.04 seconds
Started Oct 09 01:04:02 PM UTC 24
Finished Oct 09 01:08:56 PM UTC 24
Peak memory 211316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168837789 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_pipeline.1168837789
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.1510502078
Short name T334
Test name
Test status
Simulation time 848377612 ps
CPU time 110.79 seconds
Started Oct 09 01:04:15 PM UTC 24
Finished Oct 09 01:06:08 PM UTC 24
Peak memory 369652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1510502078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl
_throughput_w_partial_write.1510502078
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/16.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.1444777990
Short name T383
Test name
Test status
Simulation time 27981758341 ps
CPU time 353.45 seconds
Started Oct 09 01:08:10 PM UTC 24
Finished Oct 09 01:14:09 PM UTC 24
Peak memory 361528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444777990 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_access_duri
ng_key_req.1444777990
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_alert_test.1147331785
Short name T357
Test name
Test status
Simulation time 24430328 ps
CPU time 1.06 seconds
Started Oct 09 01:09:32 PM UTC 24
Finished Oct 09 01:09:34 PM UTC 24
Peak memory 209432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147331785
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_alert_test.1147331785
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_bijection.1211367215
Short name T607
Test name
Test status
Simulation time 100607060223 ps
CPU time 2277.83 seconds
Started Oct 09 01:07:05 PM UTC 24
Finished Oct 09 01:45:29 PM UTC 24
Peak memory 212708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211367215 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection.1211367215
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_executable.2309966342
Short name T496
Test name
Test status
Simulation time 12540003165 ps
CPU time 1318.3 seconds
Started Oct 09 01:08:40 PM UTC 24
Finished Oct 09 01:30:53 PM UTC 24
Peak memory 388156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309966342 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executable.2309966342
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.2028511621
Short name T353
Test name
Test status
Simulation time 21524071822 ps
CPU time 64.22 seconds
Started Oct 09 01:08:03 PM UTC 24
Finished Oct 09 01:09:09 PM UTC 24
Peak memory 221596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028511621 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_escalation.2028511621
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.4205249403
Short name T347
Test name
Test status
Simulation time 2894861198 ps
CPU time 15.42 seconds
Started Oct 09 01:07:53 PM UTC 24
Finished Oct 09 01:08:09 PM UTC 24
Peak memory 261040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
4205249403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_
max_throughput.4205249403
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.3648630840
Short name T360
Test name
Test status
Simulation time 1033333078 ps
CPU time 69.34 seconds
Started Oct 09 01:08:57 PM UTC 24
Finished Oct 09 01:10:08 PM UTC 24
Peak memory 221676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648630840 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_mem_partial_access.3648630840
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.928331534
Short name T382
Test name
Test status
Simulation time 3947959546 ps
CPU time 301.09 seconds
Started Oct 09 01:08:53 PM UTC 24
Finished Oct 09 01:13:58 PM UTC 24
Peak memory 221512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928331534 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_mem_walk.928331534
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.2984351512
Short name T378
Test name
Test status
Simulation time 6293420367 ps
CPU time 346.64 seconds
Started Oct 09 01:07:03 PM UTC 24
Finished Oct 09 01:12:55 PM UTC 24
Peak memory 361584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984351512 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multiple_keys.2984351512
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access.3217654851
Short name T344
Test name
Test status
Simulation time 1163370386 ps
CPU time 19.89 seconds
Started Oct 09 01:07:30 PM UTC 24
Finished Oct 09 01:07:51 PM UTC 24
Peak memory 211472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217654851 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_partial_access.3217654851
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.846022014
Short name T395
Test name
Test status
Simulation time 16803367326 ps
CPU time 516.62 seconds
Started Oct 09 01:07:51 PM UTC 24
Finished Oct 09 01:16:35 PM UTC 24
Peak memory 211276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846022014 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_partial_ac
cess_b2b.846022014
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.2883655923
Short name T351
Test name
Test status
Simulation time 1403433181 ps
CPU time 6.48 seconds
Started Oct 09 01:08:45 PM UTC 24
Finished Oct 09 01:08:52 PM UTC 24
Peak memory 211284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883655923 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.2883655923
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_readback_err.2413425435
Short name T354
Test name
Test status
Simulation time 1419383034 ps
CPU time 11.56 seconds
Started Oct 09 01:09:11 PM UTC 24
Finished Oct 09 01:09:24 PM UTC 24
Peak memory 211284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413425435 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_readback_err.2413425435
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_smoke.956717682
Short name T340
Test name
Test status
Simulation time 1114868314 ps
CPU time 18.13 seconds
Started Oct 09 01:06:45 PM UTC 24
Finished Oct 09 01:07:04 PM UTC 24
Peak memory 211160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956717682 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.956717682
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all.3997742629
Short name T775
Test name
Test status
Simulation time 35556652417 ps
CPU time 3575.33 seconds
Started Oct 09 01:09:32 PM UTC 24
Finished Oct 09 02:09:46 PM UTC 24
Peak memory 397860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39977426
29 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_a
ll.3997742629
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.4248014912
Short name T376
Test name
Test status
Simulation time 16823829950 ps
CPU time 181.33 seconds
Started Oct 09 01:09:26 PM UTC 24
Finished Oct 09 01:12:30 PM UTC 24
Peak memory 396532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248014912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.4248014912
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.968311077
Short name T367
Test name
Test status
Simulation time 13991279046 ps
CPU time 246.95 seconds
Started Oct 09 01:07:16 PM UTC 24
Finished Oct 09 01:11:27 PM UTC 24
Peak memory 211532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968311077 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_pipeline.968311077
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.759891078
Short name T356
Test name
Test status
Simulation time 2973510039 ps
CPU time 88.94 seconds
Started Oct 09 01:07:59 PM UTC 24
Finished Oct 09 01:09:30 PM UTC 24
Peak memory 365616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=759891078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_
throughput_w_partial_write.759891078
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/17.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.3787762848
Short name T530
Test name
Test status
Simulation time 16002570186 ps
CPU time 1414.6 seconds
Started Oct 09 01:11:25 PM UTC 24
Finished Oct 09 01:35:16 PM UTC 24
Peak memory 386104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787762848 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_access_duri
ng_key_req.3787762848
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_alert_test.3569946963
Short name T375
Test name
Test status
Simulation time 17149687 ps
CPU time 1.07 seconds
Started Oct 09 01:12:25 PM UTC 24
Finished Oct 09 01:12:27 PM UTC 24
Peak memory 209432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569946963
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_alert_test.3569946963
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_bijection.2711303968
Short name T727
Test name
Test status
Simulation time 119845515172 ps
CPU time 3181.17 seconds
Started Oct 09 01:09:43 PM UTC 24
Finished Oct 09 02:03:21 PM UTC 24
Peak memory 212896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711303968 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection.2711303968
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_executable.2438450101
Short name T404
Test name
Test status
Simulation time 15785487711 ps
CPU time 415.43 seconds
Started Oct 09 01:11:28 PM UTC 24
Finished Oct 09 01:18:30 PM UTC 24
Peak memory 386088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438450101 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executable.2438450101
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.1158813598
Short name T374
Test name
Test status
Simulation time 10399985471 ps
CPU time 58.47 seconds
Started Oct 09 01:11:22 PM UTC 24
Finished Oct 09 01:12:22 PM UTC 24
Peak memory 211220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158813598 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_escalation.1158813598
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.2120839005
Short name T365
Test name
Test status
Simulation time 681154613 ps
CPU time 13.64 seconds
Started Oct 09 01:11:06 PM UTC 24
Finished Oct 09 01:11:21 PM UTC 24
Peak memory 228264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2120839005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_
max_throughput.2120839005
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.2782252316
Short name T387
Test name
Test status
Simulation time 20914768298 ps
CPU time 174.28 seconds
Started Oct 09 01:11:48 PM UTC 24
Finished Oct 09 01:14:45 PM UTC 24
Peak memory 221568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782252316 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_mem_partial_access.2782252316
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.441279415
Short name T397
Test name
Test status
Simulation time 21886461053 ps
CPU time 355.33 seconds
Started Oct 09 01:11:41 PM UTC 24
Finished Oct 09 01:17:42 PM UTC 24
Peak memory 221640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441279415 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_mem_walk.441279415
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.409265706
Short name T448
Test name
Test status
Simulation time 99944938037 ps
CPU time 850.51 seconds
Started Oct 09 01:09:36 PM UTC 24
Finished Oct 09 01:23:57 PM UTC 24
Peak memory 378040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409265706 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multiple_keys.409265706
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access.1705211472
Short name T369
Test name
Test status
Simulation time 870905235 ps
CPU time 88.37 seconds
Started Oct 09 01:10:09 PM UTC 24
Finished Oct 09 01:11:39 PM UTC 24
Peak memory 378024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705211472 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_partial_access.1705211472
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.639291973
Short name T399
Test name
Test status
Simulation time 28556793501 ps
CPU time 451 seconds
Started Oct 09 01:10:30 PM UTC 24
Finished Oct 09 01:18:07 PM UTC 24
Peak memory 211332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639291973 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_partial_ac
cess_b2b.639291973
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.590645392
Short name T371
Test name
Test status
Simulation time 377275150 ps
CPU time 6.13 seconds
Started Oct 09 01:11:40 PM UTC 24
Finished Oct 09 01:11:47 PM UTC 24
Peak memory 211492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590645392 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.590645392
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_readback_err.2579481883
Short name T373
Test name
Test status
Simulation time 1171165749 ps
CPU time 9.72 seconds
Started Oct 09 01:11:54 PM UTC 24
Finished Oct 09 01:12:05 PM UTC 24
Peak memory 211620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579481883 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_readback_err.2579481883
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_regwen.2906621060
Short name T462
Test name
Test status
Simulation time 42693601840 ps
CPU time 852.77 seconds
Started Oct 09 01:11:40 PM UTC 24
Finished Oct 09 01:26:03 PM UTC 24
Peak memory 380008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906621060 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.2906621060
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_smoke.3405265143
Short name T361
Test name
Test status
Simulation time 15845748810 ps
CPU time 52.45 seconds
Started Oct 09 01:09:35 PM UTC 24
Finished Oct 09 01:10:29 PM UTC 24
Peak memory 316468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405265143 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.3405265143
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all.3312934865
Short name T835
Test name
Test status
Simulation time 243963711868 ps
CPU time 3915.46 seconds
Started Oct 09 01:12:24 PM UTC 24
Finished Oct 09 02:18:17 PM UTC 24
Peak memory 399856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33129348
65 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_a
ll.3312934865
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.3203865979
Short name T124
Test name
Test status
Simulation time 1204482051 ps
CPU time 15.34 seconds
Started Oct 09 01:12:06 PM UTC 24
Finished Oct 09 01:12:23 PM UTC 24
Peak memory 221496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203865979 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.3203865979
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.2049986303
Short name T389
Test name
Test status
Simulation time 4255253091 ps
CPU time 302.42 seconds
Started Oct 09 01:10:06 PM UTC 24
Finished Oct 09 01:15:14 PM UTC 24
Peak memory 211268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049986303 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_pipeline.2049986303
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.3323164731
Short name T366
Test name
Test status
Simulation time 1449144740 ps
CPU time 14.06 seconds
Started Oct 09 01:11:09 PM UTC 24
Finished Oct 09 01:11:24 PM UTC 24
Peak memory 228268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3323164731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl
_throughput_w_partial_write.3323164731
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/18.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.481774887
Short name T414
Test name
Test status
Simulation time 19689395504 ps
CPU time 325.36 seconds
Started Oct 09 01:14:10 PM UTC 24
Finished Oct 09 01:19:40 PM UTC 24
Peak memory 379960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481774887 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_access_durin
g_key_req.481774887
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_alert_test.773652763
Short name T392
Test name
Test status
Simulation time 15273095 ps
CPU time 0.99 seconds
Started Oct 09 01:15:26 PM UTC 24
Finished Oct 09 01:15:28 PM UTC 24
Peak memory 211152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773652763 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_alert_test.773652763
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_bijection.1132590672
Short name T490
Test name
Test status
Simulation time 28020095971 ps
CPU time 1020.4 seconds
Started Oct 09 01:12:32 PM UTC 24
Finished Oct 09 01:29:45 PM UTC 24
Peak memory 211212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132590672 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection.1132590672
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_executable.2637899157
Short name T472
Test name
Test status
Simulation time 17630660023 ps
CPU time 759.63 seconds
Started Oct 09 01:14:16 PM UTC 24
Finished Oct 09 01:27:05 PM UTC 24
Peak memory 386064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637899157 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executable.2637899157
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.3663871360
Short name T384
Test name
Test status
Simulation time 4212949998 ps
CPU time 15.59 seconds
Started Oct 09 01:13:59 PM UTC 24
Finished Oct 09 01:14:16 PM UTC 24
Peak memory 211292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663871360 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_escalation.3663871360
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.2417804192
Short name T386
Test name
Test status
Simulation time 3112534202 ps
CPU time 70.27 seconds
Started Oct 09 01:13:28 PM UTC 24
Finished Oct 09 01:14:40 PM UTC 24
Peak memory 355444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2417804192 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_
max_throughput.2417804192
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.129534516
Short name T394
Test name
Test status
Simulation time 16731554657 ps
CPU time 93.89 seconds
Started Oct 09 01:14:48 PM UTC 24
Finished Oct 09 01:16:24 PM UTC 24
Peak memory 221776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129534516 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_mem_partial_access.129534516
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.796134371
Short name T398
Test name
Test status
Simulation time 18702556657 ps
CPU time 178.22 seconds
Started Oct 09 01:14:46 PM UTC 24
Finished Oct 09 01:17:47 PM UTC 24
Peak memory 221840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796134371 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_mem_walk.796134371
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.4222881967
Short name T512
Test name
Test status
Simulation time 7598312066 ps
CPU time 1246.97 seconds
Started Oct 09 01:12:31 PM UTC 24
Finished Oct 09 01:33:32 PM UTC 24
Peak memory 388212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222881967 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multiple_keys.4222881967
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access.4159460942
Short name T380
Test name
Test status
Simulation time 5441887390 ps
CPU time 29.72 seconds
Started Oct 09 01:12:55 PM UTC 24
Finished Oct 09 01:13:26 PM UTC 24
Peak memory 211252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159460942 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_partial_access.4159460942
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.4283046853
Short name T440
Test name
Test status
Simulation time 22730916182 ps
CPU time 556.6 seconds
Started Oct 09 01:13:19 PM UTC 24
Finished Oct 09 01:22:43 PM UTC 24
Peak memory 211308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283046853 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_partial_a
ccess_b2b.4283046853
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.3135281578
Short name T388
Test name
Test status
Simulation time 1349221566 ps
CPU time 5.24 seconds
Started Oct 09 01:14:41 PM UTC 24
Finished Oct 09 01:14:47 PM UTC 24
Peak memory 211220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135281578 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.3135281578
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_readback_err.2123330939
Short name T391
Test name
Test status
Simulation time 2642073342 ps
CPU time 9.34 seconds
Started Oct 09 01:15:14 PM UTC 24
Finished Oct 09 01:15:25 PM UTC 24
Peak memory 211348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123330939 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_readback_err.2123330939
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_regwen.4056931932
Short name T488
Test name
Test status
Simulation time 25315296595 ps
CPU time 897.23 seconds
Started Oct 09 01:14:25 PM UTC 24
Finished Oct 09 01:29:34 PM UTC 24
Peak memory 388412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056931932 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.4056931932
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_smoke.132199132
Short name T364
Test name
Test status
Simulation time 1616906908 ps
CPU time 19.07 seconds
Started Oct 09 01:12:28 PM UTC 24
Finished Oct 09 01:12:48 PM UTC 24
Peak memory 211404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132199132 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.132199132
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all.4234508975
Short name T741
Test name
Test status
Simulation time 219626760039 ps
CPU time 2951.39 seconds
Started Oct 09 01:15:21 PM UTC 24
Finished Oct 09 02:05:04 PM UTC 24
Peak memory 399976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42345089
75 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_a
ll.4234508975
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.1054484584
Short name T125
Test name
Test status
Simulation time 4587041796 ps
CPU time 159.16 seconds
Started Oct 09 01:15:18 PM UTC 24
Finished Oct 09 01:18:01 PM UTC 24
Peak memory 394416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054484584 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.1054484584
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.401057634
Short name T406
Test name
Test status
Simulation time 19759118535 ps
CPU time 339.34 seconds
Started Oct 09 01:12:49 PM UTC 24
Finished Oct 09 01:18:34 PM UTC 24
Peak memory 211340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401057634 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_pipeline.401057634
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.1998260157
Short name T385
Test name
Test status
Simulation time 731520296 ps
CPU time 25.7 seconds
Started Oct 09 01:13:58 PM UTC 24
Finished Oct 09 01:14:25 PM UTC 24
Peak memory 285616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1998260157 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl
_throughput_w_partial_write.1998260157
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/19.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_access_during_key_req.130295527
Short name T41
Test name
Test status
Simulation time 25501042507 ps
CPU time 574.61 seconds
Started Oct 09 12:21:29 PM UTC 24
Finished Oct 09 12:31:12 PM UTC 24
Peak memory 386368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130295527 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_access_during
_key_req.130295527
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_alert_test.2511671178
Short name T15
Test name
Test status
Simulation time 44009613 ps
CPU time 0.99 seconds
Started Oct 09 12:22:09 PM UTC 24
Finished Oct 09 12:22:11 PM UTC 24
Peak memory 209428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511671178
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_alert_test.2511671178
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_bijection.570724847
Short name T358
Test name
Test status
Simulation time 524261788869 ps
CPU time 2933.75 seconds
Started Oct 09 12:20:14 PM UTC 24
Finished Oct 09 01:09:43 PM UTC 24
Peak memory 211356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570724847 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection.570724847
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_executable.3562119719
Short name T150
Test name
Test status
Simulation time 65226753369 ps
CPU time 907.25 seconds
Started Oct 09 12:21:33 PM UTC 24
Finished Oct 09 12:36:50 PM UTC 24
Peak memory 384036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562119719 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executable.3562119719
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_lc_escalation.2690699980
Short name T9
Test name
Test status
Simulation time 13291290009 ps
CPU time 47.39 seconds
Started Oct 09 12:21:19 PM UTC 24
Finished Oct 09 12:22:08 PM UTC 24
Peak memory 211288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690699980 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_escalation.2690699980
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_max_throughput.642706699
Short name T55
Test name
Test status
Simulation time 1585600628 ps
CPU time 91.27 seconds
Started Oct 09 12:20:39 PM UTC 24
Finished Oct 09 12:22:12 PM UTC 24
Peak memory 371712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
642706699 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ma
x_throughput.642706699
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_partial_access.2546872207
Short name T44
Test name
Test status
Simulation time 1391155342 ps
CPU time 81.53 seconds
Started Oct 09 12:21:56 PM UTC 24
Finished Oct 09 12:23:20 PM UTC 24
Peak memory 228596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546872207 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_mem_partial_access.2546872207
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_mem_walk.3631977955
Short name T52
Test name
Test status
Simulation time 24692066817 ps
CPU time 354.65 seconds
Started Oct 09 12:21:48 PM UTC 24
Finished Oct 09 12:27:48 PM UTC 24
Peak memory 221540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631977955 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_mem_walk.3631977955
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_multiple_keys.2394780541
Short name T178
Test name
Test status
Simulation time 9602277989 ps
CPU time 723.48 seconds
Started Oct 09 12:20:13 PM UTC 24
Finished Oct 09 12:32:26 PM UTC 24
Peak memory 384380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394780541 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multiple_keys.2394780541
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access.3460181885
Short name T68
Test name
Test status
Simulation time 1504742146 ps
CPU time 32.42 seconds
Started Oct 09 12:20:21 PM UTC 24
Finished Oct 09 12:20:55 PM UTC 24
Peak memory 283560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460181885 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_partial_access.3460181885
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_partial_access_b2b.639400113
Short name T107
Test name
Test status
Simulation time 13238263363 ps
CPU time 353.83 seconds
Started Oct 09 12:20:34 PM UTC 24
Finished Oct 09 12:26:33 PM UTC 24
Peak memory 211528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639400113 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_partial_acc
ess_b2b.639400113
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_ram_cfg.2926178196
Short name T29
Test name
Test status
Simulation time 1168807675 ps
CPU time 6.12 seconds
Started Oct 09 12:21:40 PM UTC 24
Finished Oct 09 12:21:48 PM UTC 24
Peak memory 211216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926178196 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.2926178196
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_readback_err.837600444
Short name T17
Test name
Test status
Simulation time 2761677286 ps
CPU time 9.84 seconds
Started Oct 09 12:21:58 PM UTC 24
Finished Oct 09 12:22:08 PM UTC 24
Peak memory 211340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837600444 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_readback_err.837600444
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_smoke.1459144460
Short name T38
Test name
Test status
Simulation time 3092661494 ps
CPU time 20.8 seconds
Started Oct 09 12:20:11 PM UTC 24
Finished Oct 09 12:20:33 PM UTC 24
Peak memory 211288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459144460 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.1459144460
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_all.2855518390
Short name T298
Test name
Test status
Simulation time 141992666154 ps
CPU time 2264.41 seconds
Started Oct 09 12:22:06 PM UTC 24
Finished Oct 09 01:00:15 PM UTC 24
Peak memory 390268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28555183
90 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all.2855518390
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_stress_pipeline.2951790352
Short name T105
Test name
Test status
Simulation time 3248076497 ps
CPU time 217.31 seconds
Started Oct 09 12:20:16 PM UTC 24
Finished Oct 09 12:23:57 PM UTC 24
Peak memory 211304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951790352 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_pipeline.2951790352
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/2.sram_ctrl_throughput_w_partial_write.4269405207
Short name T69
Test name
Test status
Simulation time 730661328 ps
CPU time 35.51 seconds
Started Oct 09 12:20:55 PM UTC 24
Finished Oct 09 12:21:32 PM UTC 24
Peak memory 298160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=4269405207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_
throughput_w_partial_write.4269405207
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/2.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.3489415227
Short name T473
Test name
Test status
Simulation time 7467943641 ps
CPU time 535.86 seconds
Started Oct 09 01:18:03 PM UTC 24
Finished Oct 09 01:27:06 PM UTC 24
Peak memory 382080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489415227 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_access_duri
ng_key_req.3489415227
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/20.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_alert_test.318925373
Short name T405
Test name
Test status
Simulation time 37812867 ps
CPU time 0.97 seconds
Started Oct 09 01:18:30 PM UTC 24
Finished Oct 09 01:18:32 PM UTC 24
Peak memory 209432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318925373 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_alert_test.318925373
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/20.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_bijection.3398764863
Short name T718
Test name
Test status
Simulation time 129445183581 ps
CPU time 2710.55 seconds
Started Oct 09 01:16:25 PM UTC 24
Finished Oct 09 02:02:08 PM UTC 24
Peak memory 212896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398764863 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection.3398764863
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/20.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_executable.2870036264
Short name T560
Test name
Test status
Simulation time 18440977926 ps
CPU time 1224.74 seconds
Started Oct 09 01:18:08 PM UTC 24
Finished Oct 09 01:38:47 PM UTC 24
Peak memory 388220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870036264 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executable.2870036264
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/20.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.22868925
Short name T407
Test name
Test status
Simulation time 6087844084 ps
CPU time 38.95 seconds
Started Oct 09 01:18:01 PM UTC 24
Finished Oct 09 01:18:42 PM UTC 24
Peak memory 221488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22868925 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_escalation.22868925
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/20.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.579188301
Short name T402
Test name
Test status
Simulation time 7040188662 ps
CPU time 30.75 seconds
Started Oct 09 01:17:48 PM UTC 24
Finished Oct 09 01:18:20 PM UTC 24
Peak memory 277684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
579188301 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_m
ax_throughput.579188301
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/20.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.388759586
Short name T422
Test name
Test status
Simulation time 11628553163 ps
CPU time 146.96 seconds
Started Oct 09 01:18:15 PM UTC 24
Finished Oct 09 01:20:44 PM UTC 24
Peak memory 221568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388759586 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_mem_partial_access.388759586
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/20.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.893076762
Short name T450
Test name
Test status
Simulation time 82760795829 ps
CPU time 349.36 seconds
Started Oct 09 01:18:11 PM UTC 24
Finished Oct 09 01:24:06 PM UTC 24
Peak memory 221836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893076762 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_mem_walk.893076762
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/20.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.4152416493
Short name T618
Test name
Test status
Simulation time 117751973633 ps
CPU time 1805.96 seconds
Started Oct 09 01:16:16 PM UTC 24
Finished Oct 09 01:46:42 PM UTC 24
Peak memory 388252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152416493 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multiple_keys.4152416493
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/20.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access.229873568
Short name T400
Test name
Test status
Simulation time 7082674077 ps
CPU time 45.63 seconds
Started Oct 09 01:17:21 PM UTC 24
Finished Oct 09 01:18:08 PM UTC 24
Peak memory 211328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229873568 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_partial_access.229873568
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/20.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.56441068
Short name T434
Test name
Test status
Simulation time 22643776365 ps
CPU time 255.21 seconds
Started Oct 09 01:17:43 PM UTC 24
Finished Oct 09 01:22:02 PM UTC 24
Peak memory 211240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56441068 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_partial_acc
ess_b2b.56441068
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/20.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.1273295806
Short name T401
Test name
Test status
Simulation time 717384058 ps
CPU time 3.47 seconds
Started Oct 09 01:18:09 PM UTC 24
Finished Oct 09 01:18:14 PM UTC 24
Peak memory 211296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273295806 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.1273295806
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/20.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_readback_err.498604025
Short name T403
Test name
Test status
Simulation time 684981590 ps
CPU time 7.5 seconds
Started Oct 09 01:18:21 PM UTC 24
Finished Oct 09 01:18:30 PM UTC 24
Peak memory 211284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498604025 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_readback_err.498604025
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/20.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_regwen.848570896
Short name T577
Test name
Test status
Simulation time 43928346111 ps
CPU time 1370.86 seconds
Started Oct 09 01:18:09 PM UTC 24
Finished Oct 09 01:41:14 PM UTC 24
Peak memory 386112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848570896 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.848570896
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/20.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_smoke.3488889629
Short name T393
Test name
Test status
Simulation time 16224192053 ps
CPU time 44.27 seconds
Started Oct 09 01:15:29 PM UTC 24
Finished Oct 09 01:16:15 PM UTC 24
Peak memory 211524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488889629 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.3488889629
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/20.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all.4246513808
Short name T721
Test name
Test status
Simulation time 307652160301 ps
CPU time 2595.14 seconds
Started Oct 09 01:18:30 PM UTC 24
Finished Oct 09 02:02:19 PM UTC 24
Peak memory 363036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42465138
08 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_a
ll.4246513808
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/20.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3656125894
Short name T126
Test name
Test status
Simulation time 2108747239 ps
CPU time 30.97 seconds
Started Oct 09 01:18:27 PM UTC 24
Finished Oct 09 01:18:59 PM UTC 24
Peak memory 221472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656125894 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.3656125894
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/20.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.1529461621
Short name T437
Test name
Test status
Simulation time 17248068936 ps
CPU time 338.6 seconds
Started Oct 09 01:16:36 PM UTC 24
Finished Oct 09 01:22:20 PM UTC 24
Peak memory 211368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529461621 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_pipeline.1529461621
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/20.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.3902300523
Short name T409
Test name
Test status
Simulation time 3211663977 ps
CPU time 89.74 seconds
Started Oct 09 01:17:51 PM UTC 24
Finished Oct 09 01:19:23 PM UTC 24
Peak memory 359668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3902300523 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl
_throughput_w_partial_write.3902300523
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/20.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.1603865637
Short name T444
Test name
Test status
Simulation time 6793251160 ps
CPU time 265.7 seconds
Started Oct 09 01:19:06 PM UTC 24
Finished Oct 09 01:23:36 PM UTC 24
Peak memory 386368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603865637 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_access_duri
ng_key_req.1603865637
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/21.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_alert_test.1064801051
Short name T417
Test name
Test status
Simulation time 15713640 ps
CPU time 1.12 seconds
Started Oct 09 01:19:45 PM UTC 24
Finished Oct 09 01:19:47 PM UTC 24
Peak memory 209432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064801051
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_alert_test.1064801051
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/21.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_bijection.3526848623
Short name T539
Test name
Test status
Simulation time 15288665856 ps
CPU time 1045.67 seconds
Started Oct 09 01:18:34 PM UTC 24
Finished Oct 09 01:36:13 PM UTC 24
Peak memory 211332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526848623 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection.3526848623
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/21.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_executable.512146617
Short name T535
Test name
Test status
Simulation time 21301598771 ps
CPU time 969.03 seconds
Started Oct 09 01:19:14 PM UTC 24
Finished Oct 09 01:35:34 PM UTC 24
Peak memory 388152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512146617 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executable.512146617
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/21.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.1446347906
Short name T416
Test name
Test status
Simulation time 43970757087 ps
CPU time 44.18 seconds
Started Oct 09 01:19:00 PM UTC 24
Finished Oct 09 01:19:46 PM UTC 24
Peak memory 221756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446347906 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_escalation.1446347906
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/21.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.1231782179
Short name T425
Test name
Test status
Simulation time 12690265967 ps
CPU time 133.99 seconds
Started Oct 09 01:18:45 PM UTC 24
Finished Oct 09 01:21:01 PM UTC 24
Peak memory 380280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1231782179 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_
max_throughput.1231782179
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/21.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.3675266050
Short name T428
Test name
Test status
Simulation time 10714053284 ps
CPU time 104.21 seconds
Started Oct 09 01:19:33 PM UTC 24
Finished Oct 09 01:21:20 PM UTC 24
Peak memory 228412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675266050 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_mem_partial_access.3675266050
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/21.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.1766860441
Short name T449
Test name
Test status
Simulation time 4109907552 ps
CPU time 267.57 seconds
Started Oct 09 01:19:30 PM UTC 24
Finished Oct 09 01:24:03 PM UTC 24
Peak memory 221500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766860441 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_mem_walk.1766860441
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/21.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.434158181
Short name T514
Test name
Test status
Simulation time 68563903236 ps
CPU time 904.27 seconds
Started Oct 09 01:18:34 PM UTC 24
Finished Oct 09 01:33:49 PM UTC 24
Peak memory 384120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434158181 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multiple_keys.434158181
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/21.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access.3470870361
Short name T413
Test name
Test status
Simulation time 2040779035 ps
CPU time 50.06 seconds
Started Oct 09 01:18:42 PM UTC 24
Finished Oct 09 01:19:34 PM UTC 24
Peak memory 296076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470870361 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_partial_access.3470870361
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/21.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.2600152609
Short name T489
Test name
Test status
Simulation time 81623102672 ps
CPU time 642.72 seconds
Started Oct 09 01:18:42 PM UTC 24
Finished Oct 09 01:29:34 PM UTC 24
Peak memory 211280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600152609 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_partial_a
ccess_b2b.2600152609
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/21.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.2881893982
Short name T411
Test name
Test status
Simulation time 357039612 ps
CPU time 5.04 seconds
Started Oct 09 01:19:25 PM UTC 24
Finished Oct 09 01:19:32 PM UTC 24
Peak memory 211488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881893982 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.2881893982
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/21.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_readback_err.926147183
Short name T415
Test name
Test status
Simulation time 1362422769 ps
CPU time 10.83 seconds
Started Oct 09 01:19:34 PM UTC 24
Finished Oct 09 01:19:46 PM UTC 24
Peak memory 211556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926147183 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_readback_err.926147183
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/21.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_regwen.1250213904
Short name T469
Test name
Test status
Simulation time 17346805286 ps
CPU time 436.94 seconds
Started Oct 09 01:19:24 PM UTC 24
Finished Oct 09 01:26:47 PM UTC 24
Peak memory 386076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250213904 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.1250213904
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/21.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_smoke.1080803819
Short name T410
Test name
Test status
Simulation time 1087482322 ps
CPU time 50.3 seconds
Started Oct 09 01:18:33 PM UTC 24
Finished Oct 09 01:19:25 PM UTC 24
Peak memory 304112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080803819 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.1080803819
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/21.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all.189808237
Short name T943
Test name
Test status
Simulation time 786781058669 ps
CPU time 4342.57 seconds
Started Oct 09 01:19:41 PM UTC 24
Finished Oct 09 02:32:56 PM UTC 24
Peak memory 223036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18980823
7 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all.189808237
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/21.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.536802619
Short name T418
Test name
Test status
Simulation time 2147970012 ps
CPU time 39.38 seconds
Started Oct 09 01:19:35 PM UTC 24
Finished Oct 09 01:20:16 PM UTC 24
Peak memory 221876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536802619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.536802619
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/21.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.3419369423
Short name T430
Test name
Test status
Simulation time 5813330118 ps
CPU time 174.28 seconds
Started Oct 09 01:18:35 PM UTC 24
Finished Oct 09 01:21:33 PM UTC 24
Peak memory 211536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419369423 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_pipeline.3419369423
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/21.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.1564200039
Short name T412
Test name
Test status
Simulation time 3074904884 ps
CPU time 43.67 seconds
Started Oct 09 01:18:48 PM UTC 24
Finished Oct 09 01:19:33 PM UTC 24
Peak memory 302276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1564200039 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl
_throughput_w_partial_write.1564200039
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/21.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.3637964955
Short name T550
Test name
Test status
Simulation time 44943893103 ps
CPU time 993.7 seconds
Started Oct 09 01:20:34 PM UTC 24
Finished Oct 09 01:37:20 PM UTC 24
Peak memory 381976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637964955 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_access_duri
ng_key_req.3637964955
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/22.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_alert_test.689851467
Short name T429
Test name
Test status
Simulation time 24950231 ps
CPU time 0.97 seconds
Started Oct 09 01:21:20 PM UTC 24
Finished Oct 09 01:21:22 PM UTC 24
Peak memory 211336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689851467 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_alert_test.689851467
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/22.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_bijection.151511993
Short name T638
Test name
Test status
Simulation time 69277704187 ps
CPU time 1748.75 seconds
Started Oct 09 01:19:48 PM UTC 24
Finished Oct 09 01:49:18 PM UTC 24
Peak memory 211392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151511993 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection.151511993
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/22.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_executable.1200654183
Short name T580
Test name
Test status
Simulation time 37351860085 ps
CPU time 1234.25 seconds
Started Oct 09 01:20:36 PM UTC 24
Finished Oct 09 01:41:24 PM UTC 24
Peak memory 386168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200654183 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executable.1200654183
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/22.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.3904633110
Short name T439
Test name
Test status
Simulation time 12202268142 ps
CPU time 126.61 seconds
Started Oct 09 01:20:29 PM UTC 24
Finished Oct 09 01:22:38 PM UTC 24
Peak memory 211592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904633110 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_escalation.3904633110
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/22.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.1789573997
Short name T423
Test name
Test status
Simulation time 709157736 ps
CPU time 30.09 seconds
Started Oct 09 01:20:21 PM UTC 24
Finished Oct 09 01:20:52 PM UTC 24
Peak memory 277500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1789573997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_
max_throughput.1789573997
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/22.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.2795297381
Short name T446
Test name
Test status
Simulation time 10269696054 ps
CPU time 175.06 seconds
Started Oct 09 01:20:55 PM UTC 24
Finished Oct 09 01:23:54 PM UTC 24
Peak memory 221692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795297381 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_mem_partial_access.2795297381
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/22.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.2566670984
Short name T483
Test name
Test status
Simulation time 36339570788 ps
CPU time 454.4 seconds
Started Oct 09 01:20:53 PM UTC 24
Finished Oct 09 01:28:34 PM UTC 24
Peak memory 221536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566670984 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_mem_walk.2566670984
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/22.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.437982412
Short name T435
Test name
Test status
Simulation time 15192230181 ps
CPU time 188.85 seconds
Started Oct 09 01:19:47 PM UTC 24
Finished Oct 09 01:23:00 PM UTC 24
Peak memory 269356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437982412 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multiple_keys.437982412
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/22.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access.400811841
Short name T421
Test name
Test status
Simulation time 2169449820 ps
CPU time 19.27 seconds
Started Oct 09 01:20:15 PM UTC 24
Finished Oct 09 01:20:36 PM UTC 24
Peak memory 211312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400811841 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_partial_access.400811841
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/22.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.2394716610
Short name T460
Test name
Test status
Simulation time 44875119628 ps
CPU time 339.49 seconds
Started Oct 09 01:20:16 PM UTC 24
Finished Oct 09 01:26:01 PM UTC 24
Peak memory 211340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394716610 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_partial_a
ccess_b2b.2394716610
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/22.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.387007306
Short name T424
Test name
Test status
Simulation time 1305156683 ps
CPU time 5.89 seconds
Started Oct 09 01:20:46 PM UTC 24
Finished Oct 09 01:20:53 PM UTC 24
Peak memory 211304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387007306 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.387007306
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/22.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_readback_err.3897832021
Short name T427
Test name
Test status
Simulation time 2870910171 ps
CPU time 8.98 seconds
Started Oct 09 01:21:03 PM UTC 24
Finished Oct 09 01:21:13 PM UTC 24
Peak memory 211428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897832021 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_readback_err.3897832021
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/22.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_regwen.598173548
Short name T442
Test name
Test status
Simulation time 17782719387 ps
CPU time 164.72 seconds
Started Oct 09 01:20:36 PM UTC 24
Finished Oct 09 01:23:24 PM UTC 24
Peak memory 384316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598173548 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.598173548
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/22.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_smoke.1663360457
Short name T419
Test name
Test status
Simulation time 5823059932 ps
CPU time 31.49 seconds
Started Oct 09 01:19:46 PM UTC 24
Finished Oct 09 01:20:19 PM UTC 24
Peak memory 211388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663360457 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.1663360457
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/22.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all.1468538528
Short name T820
Test name
Test status
Simulation time 45063609450 ps
CPU time 3230.82 seconds
Started Oct 09 01:21:15 PM UTC 24
Finished Oct 09 02:15:39 PM UTC 24
Peak memory 397876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14685385
28 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_a
ll.1468538528
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/22.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.4252304314
Short name T432
Test name
Test status
Simulation time 1366639848 ps
CPU time 43.99 seconds
Started Oct 09 01:21:07 PM UTC 24
Finished Oct 09 01:21:53 PM UTC 24
Peak memory 223648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252304314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.4252304314
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/22.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.1240849072
Short name T455
Test name
Test status
Simulation time 11946047882 ps
CPU time 304.96 seconds
Started Oct 09 01:19:54 PM UTC 24
Finished Oct 09 01:25:04 PM UTC 24
Peak memory 211368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240849072 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_pipeline.1240849072
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/22.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.1931837852
Short name T420
Test name
Test status
Simulation time 6041302369 ps
CPU time 11.86 seconds
Started Oct 09 01:20:21 PM UTC 24
Finished Oct 09 01:20:34 PM UTC 24
Peak memory 221328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1931837852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl
_throughput_w_partial_write.1931837852
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/22.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.635198170
Short name T509
Test name
Test status
Simulation time 49328064727 ps
CPU time 627.55 seconds
Started Oct 09 01:22:27 PM UTC 24
Finished Oct 09 01:33:02 PM UTC 24
Peak memory 382076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635198170 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_access_durin
g_key_req.635198170
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/23.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_alert_test.2403116789
Short name T447
Test name
Test status
Simulation time 79105671 ps
CPU time 0.9 seconds
Started Oct 09 01:23:54 PM UTC 24
Finished Oct 09 01:23:56 PM UTC 24
Peak memory 209432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403116789
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_alert_test.2403116789
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/23.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_bijection.1683703536
Short name T520
Test name
Test status
Simulation time 328319644944 ps
CPU time 751.4 seconds
Started Oct 09 01:21:34 PM UTC 24
Finished Oct 09 01:34:14 PM UTC 24
Peak memory 211500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683703536 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection.1683703536
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/23.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_executable.2776395206
Short name T589
Test name
Test status
Simulation time 38379068573 ps
CPU time 1225.18 seconds
Started Oct 09 01:22:39 PM UTC 24
Finished Oct 09 01:43:18 PM UTC 24
Peak memory 388148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776395206 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executable.2776395206
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/23.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.2281926948
Short name T454
Test name
Test status
Simulation time 218238590706 ps
CPU time 149.68 seconds
Started Oct 09 01:22:20 PM UTC 24
Finished Oct 09 01:24:53 PM UTC 24
Peak memory 211324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281926948 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_escalation.2281926948
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/23.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.2699859185
Short name T443
Test name
Test status
Simulation time 1534602855 ps
CPU time 89.02 seconds
Started Oct 09 01:22:03 PM UTC 24
Finished Oct 09 01:23:34 PM UTC 24
Peak memory 359548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2699859185 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_
max_throughput.2699859185
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/23.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.3276562162
Short name T468
Test name
Test status
Simulation time 19376341848 ps
CPU time 193.29 seconds
Started Oct 09 01:23:26 PM UTC 24
Finished Oct 09 01:26:42 PM UTC 24
Peak memory 221900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276562162 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_mem_partial_access.3276562162
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/23.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.2741305137
Short name T477
Test name
Test status
Simulation time 33302342903 ps
CPU time 272.71 seconds
Started Oct 09 01:23:06 PM UTC 24
Finished Oct 09 01:27:44 PM UTC 24
Peak memory 211472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741305137 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_mem_walk.2741305137
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/23.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.4100829727
Short name T565
Test name
Test status
Simulation time 51060970471 ps
CPU time 1064.1 seconds
Started Oct 09 01:21:23 PM UTC 24
Finished Oct 09 01:39:20 PM UTC 24
Peak memory 388152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100829727 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multiple_keys.4100829727
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/23.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access.2135820783
Short name T436
Test name
Test status
Simulation time 419813389 ps
CPU time 18.46 seconds
Started Oct 09 01:21:54 PM UTC 24
Finished Oct 09 01:22:14 PM UTC 24
Peak memory 283820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135820783 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_partial_access.2135820783
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/23.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.3984671951
Short name T497
Test name
Test status
Simulation time 150309161999 ps
CPU time 536.02 seconds
Started Oct 09 01:21:54 PM UTC 24
Finished Oct 09 01:30:57 PM UTC 24
Peak memory 211228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984671951 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_partial_a
ccess_b2b.3984671951
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/23.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.3753301572
Short name T441
Test name
Test status
Simulation time 354397314 ps
CPU time 4.4 seconds
Started Oct 09 01:23:00 PM UTC 24
Finished Oct 09 01:23:06 PM UTC 24
Peak memory 211288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753301572 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.3753301572
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/23.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_readback_err.3584536669
Short name T445
Test name
Test status
Simulation time 680564625 ps
CPU time 11.45 seconds
Started Oct 09 01:23:35 PM UTC 24
Finished Oct 09 01:23:47 PM UTC 24
Peak memory 211288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584536669 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_readback_err.3584536669
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/23.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_regwen.3330673475
Short name T551
Test name
Test status
Simulation time 12582549562 ps
CPU time 870.35 seconds
Started Oct 09 01:22:44 PM UTC 24
Finished Oct 09 01:37:24 PM UTC 24
Peak memory 384048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330673475 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.3330673475
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/23.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_smoke.1795804757
Short name T433
Test name
Test status
Simulation time 5632638119 ps
CPU time 29.92 seconds
Started Oct 09 01:21:21 PM UTC 24
Finished Oct 09 01:21:53 PM UTC 24
Peak memory 211264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795804757 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.1795804757
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/23.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all.67228823
Short name T954
Test name
Test status
Simulation time 41426963175 ps
CPU time 4334.61 seconds
Started Oct 09 01:23:48 PM UTC 24
Finished Oct 09 02:36:50 PM UTC 24
Peak memory 391728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67228823
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all.67228823
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/23.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.1404946210
Short name T458
Test name
Test status
Simulation time 2677050922 ps
CPU time 92.39 seconds
Started Oct 09 01:23:37 PM UTC 24
Finished Oct 09 01:25:11 PM UTC 24
Peak memory 370036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404946210 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.1404946210
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/23.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.2313430676
Short name T451
Test name
Test status
Simulation time 18923877460 ps
CPU time 167.02 seconds
Started Oct 09 01:21:43 PM UTC 24
Finished Oct 09 01:24:33 PM UTC 24
Peak memory 211584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313430676 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_pipeline.2313430676
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/23.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.2233747004
Short name T438
Test name
Test status
Simulation time 3022869125 ps
CPU time 10.64 seconds
Started Oct 09 01:22:14 PM UTC 24
Finished Oct 09 01:22:26 PM UTC 24
Peak memory 221260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2233747004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl
_throughput_w_partial_write.2233747004
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/23.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.1058082911
Short name T599
Test name
Test status
Simulation time 15411446518 ps
CPU time 1135.73 seconds
Started Oct 09 01:25:08 PM UTC 24
Finished Oct 09 01:44:17 PM UTC 24
Peak memory 388284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058082911 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_access_duri
ng_key_req.1058082911
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/24.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_alert_test.184435478
Short name T466
Test name
Test status
Simulation time 40638347 ps
CPU time 1.03 seconds
Started Oct 09 01:26:23 PM UTC 24
Finished Oct 09 01:26:25 PM UTC 24
Peak memory 209432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184435478 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_alert_test.184435478
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/24.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_bijection.3622667754
Short name T773
Test name
Test status
Simulation time 275892089698 ps
CPU time 2698.54 seconds
Started Oct 09 01:24:04 PM UTC 24
Finished Oct 09 02:09:32 PM UTC 24
Peak memory 212828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622667754 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection.3622667754
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/24.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_executable.2110402530
Short name T510
Test name
Test status
Simulation time 14093469524 ps
CPU time 485.25 seconds
Started Oct 09 01:25:09 PM UTC 24
Finished Oct 09 01:33:20 PM UTC 24
Peak memory 386064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110402530 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executable.2110402530
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/24.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.1779018471
Short name T463
Test name
Test status
Simulation time 6454054929 ps
CPU time 66.47 seconds
Started Oct 09 01:25:05 PM UTC 24
Finished Oct 09 01:26:13 PM UTC 24
Peak memory 225716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779018471 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_escalation.1779018471
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/24.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.2162925352
Short name T459
Test name
Test status
Simulation time 768876397 ps
CPU time 60.37 seconds
Started Oct 09 01:24:50 PM UTC 24
Finished Oct 09 01:25:53 PM UTC 24
Peak memory 367528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2162925352 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_
max_throughput.2162925352
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/24.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.1878511778
Short name T475
Test name
Test status
Simulation time 6032135519 ps
CPU time 85.62 seconds
Started Oct 09 01:26:03 PM UTC 24
Finished Oct 09 01:27:30 PM UTC 24
Peak memory 221588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878511778 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_mem_partial_access.1878511778
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/24.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.2042497970
Short name T480
Test name
Test status
Simulation time 2023178462 ps
CPU time 128.01 seconds
Started Oct 09 01:26:01 PM UTC 24
Finished Oct 09 01:28:12 PM UTC 24
Peak memory 221512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042497970 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_mem_walk.2042497970
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/24.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.2530433192
Short name T500
Test name
Test status
Simulation time 29006116835 ps
CPU time 431.97 seconds
Started Oct 09 01:23:57 PM UTC 24
Finished Oct 09 01:31:15 PM UTC 24
Peak memory 384112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530433192 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multiple_keys.2530433192
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/24.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access.1412570910
Short name T453
Test name
Test status
Simulation time 741310964 ps
CPU time 13.88 seconds
Started Oct 09 01:24:34 PM UTC 24
Finished Oct 09 01:24:49 PM UTC 24
Peak memory 211200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412570910 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_partial_access.1412570910
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/24.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.3327045574
Short name T487
Test name
Test status
Simulation time 25916519265 ps
CPU time 271.32 seconds
Started Oct 09 01:24:49 PM UTC 24
Finished Oct 09 01:29:25 PM UTC 24
Peak memory 211380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327045574 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_partial_a
ccess_b2b.3327045574
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/24.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.1113482470
Short name T461
Test name
Test status
Simulation time 4770214634 ps
CPU time 6.96 seconds
Started Oct 09 01:25:53 PM UTC 24
Finished Oct 09 01:26:01 PM UTC 24
Peak memory 211340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113482470 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.1113482470
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/24.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_readback_err.3662995881
Short name T464
Test name
Test status
Simulation time 706062041 ps
CPU time 9.23 seconds
Started Oct 09 01:26:04 PM UTC 24
Finished Oct 09 01:26:14 PM UTC 24
Peak memory 211552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662995881 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_readback_err.3662995881
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/24.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_regwen.116183509
Short name T555
Test name
Test status
Simulation time 31947610534 ps
CPU time 746.52 seconds
Started Oct 09 01:25:12 PM UTC 24
Finished Oct 09 01:37:48 PM UTC 24
Peak memory 386096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116183509 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.116183509
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/24.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_smoke.1595192989
Short name T452
Test name
Test status
Simulation time 3652721454 ps
CPU time 48.94 seconds
Started Oct 09 01:23:57 PM UTC 24
Finished Oct 09 01:24:48 PM UTC 24
Peak memory 310388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595192989 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.1595192989
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/24.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all.4009889708
Short name T964
Test name
Test status
Simulation time 499519251263 ps
CPU time 4525.91 seconds
Started Oct 09 01:26:15 PM UTC 24
Finished Oct 09 02:42:33 PM UTC 24
Peak memory 389748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40098897
08 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_a
ll.4009889708
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/24.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.3350173032
Short name T467
Test name
Test status
Simulation time 1271980662 ps
CPU time 12.17 seconds
Started Oct 09 01:26:14 PM UTC 24
Finished Oct 09 01:26:27 PM UTC 24
Peak memory 221528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350173032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.3350173032
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/24.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.2341905134
Short name T492
Test name
Test status
Simulation time 8738989395 ps
CPU time 365.59 seconds
Started Oct 09 01:24:07 PM UTC 24
Finished Oct 09 01:30:18 PM UTC 24
Peak memory 211252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341905134 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_pipeline.2341905134
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/24.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.3575016472
Short name T456
Test name
Test status
Simulation time 1583105494 ps
CPU time 10.63 seconds
Started Oct 09 01:24:54 PM UTC 24
Finished Oct 09 01:25:07 PM UTC 24
Peak memory 228548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3575016472 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl
_throughput_w_partial_write.3575016472
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/24.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_access_during_key_req.417228273
Short name T516
Test name
Test status
Simulation time 8104953019 ps
CPU time 379.97 seconds
Started Oct 09 01:27:32 PM UTC 24
Finished Oct 09 01:33:57 PM UTC 24
Peak memory 361600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417228273 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_access_durin
g_key_req.417228273
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/25.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_alert_test.363915246
Short name T485
Test name
Test status
Simulation time 37668093 ps
CPU time 0.98 seconds
Started Oct 09 01:28:43 PM UTC 24
Finished Oct 09 01:28:45 PM UTC 24
Peak memory 211336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363915246 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_alert_test.363915246
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/25.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_executable.342284185
Short name T601
Test name
Test status
Simulation time 20079230268 ps
CPU time 995.3 seconds
Started Oct 09 01:27:42 PM UTC 24
Finished Oct 09 01:44:29 PM UTC 24
Peak memory 386232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342284185 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executable.342284185
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/25.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.4193998893
Short name T481
Test name
Test status
Simulation time 21855442974 ps
CPU time 64.48 seconds
Started Oct 09 01:27:10 PM UTC 24
Finished Oct 09 01:28:16 PM UTC 24
Peak memory 221488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193998893 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_escalation.4193998893
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/25.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.4002278828
Short name T476
Test name
Test status
Simulation time 2940342499 ps
CPU time 32.57 seconds
Started Oct 09 01:27:07 PM UTC 24
Finished Oct 09 01:27:41 PM UTC 24
Peak memory 281912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
4002278828 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_
max_throughput.4002278828
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/25.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.1941018362
Short name T499
Test name
Test status
Simulation time 4919846834 ps
CPU time 168.21 seconds
Started Oct 09 01:28:13 PM UTC 24
Finished Oct 09 01:31:05 PM UTC 24
Peak memory 221784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941018362 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_mem_partial_access.1941018362
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/25.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.1474279386
Short name T531
Test name
Test status
Simulation time 37372771671 ps
CPU time 420.8 seconds
Started Oct 09 01:28:09 PM UTC 24
Finished Oct 09 01:35:16 PM UTC 24
Peak memory 221568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474279386 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_mem_walk.1474279386
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/25.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.286707692
Short name T585
Test name
Test status
Simulation time 44039664913 ps
CPU time 932.48 seconds
Started Oct 09 01:26:29 PM UTC 24
Finished Oct 09 01:42:11 PM UTC 24
Peak memory 384124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286707692 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multiple_keys.286707692
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/25.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access.2309232482
Short name T474
Test name
Test status
Simulation time 531224848 ps
CPU time 16.76 seconds
Started Oct 09 01:26:51 PM UTC 24
Finished Oct 09 01:27:09 PM UTC 24
Peak memory 211476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309232482 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_partial_access.2309232482
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/25.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.3026747374
Short name T519
Test name
Test status
Simulation time 28983464035 ps
CPU time 430.39 seconds
Started Oct 09 01:26:51 PM UTC 24
Finished Oct 09 01:34:07 PM UTC 24
Peak memory 211260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026747374 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_partial_a
ccess_b2b.3026747374
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/25.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.1914971839
Short name T479
Test name
Test status
Simulation time 941877301 ps
CPU time 6.03 seconds
Started Oct 09 01:28:01 PM UTC 24
Finished Oct 09 01:28:08 PM UTC 24
Peak memory 211284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914971839 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.1914971839
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/25.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_readback_err.2755881007
Short name T482
Test name
Test status
Simulation time 1384663922 ps
CPU time 9.44 seconds
Started Oct 09 01:28:18 PM UTC 24
Finished Oct 09 01:28:28 PM UTC 24
Peak memory 211288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755881007 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_readback_err.2755881007
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/25.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_regwen.2009411146
Short name T493
Test name
Test status
Simulation time 14514518908 ps
CPU time 150.59 seconds
Started Oct 09 01:27:45 PM UTC 24
Finished Oct 09 01:30:18 PM UTC 24
Peak memory 304292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009411146 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.2009411146
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/25.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_smoke.1381179945
Short name T470
Test name
Test status
Simulation time 8588714121 ps
CPU time 21.98 seconds
Started Oct 09 01:26:27 PM UTC 24
Finished Oct 09 01:26:50 PM UTC 24
Peak memory 211300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381179945 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.1381179945
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/25.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all.1202577977
Short name T925
Test name
Test status
Simulation time 236012077435 ps
CPU time 3606.01 seconds
Started Oct 09 01:28:35 PM UTC 24
Finished Oct 09 02:29:20 PM UTC 24
Peak memory 391708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12025779
77 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_a
ll.1202577977
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/25.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.3353551966
Short name T484
Test name
Test status
Simulation time 1288312754 ps
CPU time 12.09 seconds
Started Oct 09 01:28:29 PM UTC 24
Finished Oct 09 01:28:42 PM UTC 24
Peak memory 221544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353551966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.3353551966
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/25.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.307761452
Short name T501
Test name
Test status
Simulation time 31059576437 ps
CPU time 272.37 seconds
Started Oct 09 01:26:48 PM UTC 24
Finished Oct 09 01:31:24 PM UTC 24
Peak memory 211324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307761452 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_pipeline.307761452
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/25.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.678849540
Short name T478
Test name
Test status
Simulation time 1544634795 ps
CPU time 51.72 seconds
Started Oct 09 01:27:07 PM UTC 24
Finished Oct 09 01:28:00 PM UTC 24
Peak memory 314348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=678849540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_
throughput_w_partial_write.678849540
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/25.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.1182688524
Short name T592
Test name
Test status
Simulation time 26985498481 ps
CPU time 773.93 seconds
Started Oct 09 01:30:32 PM UTC 24
Finished Oct 09 01:43:35 PM UTC 24
Peak memory 381952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182688524 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_access_duri
ng_key_req.1182688524
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/26.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_alert_test.136279172
Short name T504
Test name
Test status
Simulation time 20412674 ps
CPU time 1.1 seconds
Started Oct 09 01:32:06 PM UTC 24
Finished Oct 09 01:32:08 PM UTC 24
Peak memory 209432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136279172 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_alert_test.136279172
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/26.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_bijection.2058770356
Short name T621
Test name
Test status
Simulation time 55380400763 ps
CPU time 1047.32 seconds
Started Oct 09 01:29:27 PM UTC 24
Finished Oct 09 01:47:07 PM UTC 24
Peak memory 211360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058770356 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection.2058770356
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/26.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_executable.2001003542
Short name T511
Test name
Test status
Simulation time 3954543758 ps
CPU time 162.12 seconds
Started Oct 09 01:30:44 PM UTC 24
Finished Oct 09 01:33:29 PM UTC 24
Peak memory 336876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001003542 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executable.2001003542
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/26.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.2710515330
Short name T503
Test name
Test status
Simulation time 17464863659 ps
CPU time 103.2 seconds
Started Oct 09 01:30:20 PM UTC 24
Finished Oct 09 01:32:05 PM UTC 24
Peak memory 211252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710515330 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_escalation.2710515330
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/26.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.3728233675
Short name T495
Test name
Test status
Simulation time 725287995 ps
CPU time 47.02 seconds
Started Oct 09 01:29:54 PM UTC 24
Finished Oct 09 01:30:43 PM UTC 24
Peak memory 302072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3728233675 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_
max_throughput.3728233675
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/26.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.3090925697
Short name T508
Test name
Test status
Simulation time 2769205672 ps
CPU time 111.24 seconds
Started Oct 09 01:31:06 PM UTC 24
Finished Oct 09 01:33:00 PM UTC 24
Peak memory 221548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090925697 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_mem_partial_access.3090925697
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/26.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.1087361415
Short name T517
Test name
Test status
Simulation time 4034039196 ps
CPU time 172.83 seconds
Started Oct 09 01:31:05 PM UTC 24
Finished Oct 09 01:34:01 PM UTC 24
Peak memory 221496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087361415 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_mem_walk.1087361415
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/26.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.3912743858
Short name T527
Test name
Test status
Simulation time 3514870638 ps
CPU time 343.3 seconds
Started Oct 09 01:29:08 PM UTC 24
Finished Oct 09 01:34:56 PM UTC 24
Peak memory 343280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912743858 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multiple_keys.3912743858
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/26.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access.3354794623
Short name T491
Test name
Test status
Simulation time 392502466 ps
CPU time 16.84 seconds
Started Oct 09 01:29:35 PM UTC 24
Finished Oct 09 01:29:53 PM UTC 24
Peak memory 248740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354794623 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_partial_access.3354794623
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/26.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.94487761
Short name T534
Test name
Test status
Simulation time 56248948816 ps
CPU time 341.37 seconds
Started Oct 09 01:29:46 PM UTC 24
Finished Oct 09 01:35:32 PM UTC 24
Peak memory 211200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94487761 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_partial_acc
ess_b2b.94487761
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/26.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.306778451
Short name T498
Test name
Test status
Simulation time 347292880 ps
CPU time 4.91 seconds
Started Oct 09 01:30:58 PM UTC 24
Finished Oct 09 01:31:04 PM UTC 24
Peak memory 211484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306778451 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.306778451
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/26.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_readback_err.3346899986
Short name T502
Test name
Test status
Simulation time 681900249 ps
CPU time 10.53 seconds
Started Oct 09 01:31:17 PM UTC 24
Finished Oct 09 01:31:29 PM UTC 24
Peak memory 211356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346899986 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_readback_err.3346899986
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/26.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_regwen.2902922737
Short name T594
Test name
Test status
Simulation time 57595693168 ps
CPU time 767.2 seconds
Started Oct 09 01:30:54 PM UTC 24
Finished Oct 09 01:43:51 PM UTC 24
Peak memory 388224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902922737 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.2902922737
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/26.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_smoke.1797324538
Short name T486
Test name
Test status
Simulation time 3469182938 ps
CPU time 19.56 seconds
Started Oct 09 01:28:46 PM UTC 24
Finished Oct 09 01:29:07 PM UTC 24
Peak memory 211196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797324538 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.1797324538
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/26.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all.2710724899
Short name T749
Test name
Test status
Simulation time 150432995416 ps
CPU time 2053.74 seconds
Started Oct 09 01:31:30 PM UTC 24
Finished Oct 09 02:06:07 PM UTC 24
Peak memory 387688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27107248
99 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_a
ll.2710724899
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/26.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.924317494
Short name T507
Test name
Test status
Simulation time 7876020009 ps
CPU time 59.74 seconds
Started Oct 09 01:31:26 PM UTC 24
Finished Oct 09 01:32:27 PM UTC 24
Peak memory 228508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924317494 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.924317494
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/26.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.1173991535
Short name T528
Test name
Test status
Simulation time 8998753128 ps
CPU time 328.45 seconds
Started Oct 09 01:29:35 PM UTC 24
Finished Oct 09 01:35:08 PM UTC 24
Peak memory 211536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173991535 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_pipeline.1173991535
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/26.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.1618835901
Short name T494
Test name
Test status
Simulation time 2713838203 ps
CPU time 11.29 seconds
Started Oct 09 01:30:18 PM UTC 24
Finished Oct 09 01:30:31 PM UTC 24
Peak memory 228212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1618835901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl
_throughput_w_partial_write.1618835901
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/26.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.578677668
Short name T643
Test name
Test status
Simulation time 13376792570 ps
CPU time 1007.24 seconds
Started Oct 09 01:33:42 PM UTC 24
Finished Oct 09 01:50:41 PM UTC 24
Peak memory 386432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578677668 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_access_durin
g_key_req.578677668
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/27.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_alert_test.1943173546
Short name T523
Test name
Test status
Simulation time 19729074 ps
CPU time 1.08 seconds
Started Oct 09 01:34:33 PM UTC 24
Finished Oct 09 01:34:36 PM UTC 24
Peak memory 209432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943173546
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_alert_test.1943173546
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/27.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_bijection.2188205498
Short name T737
Test name
Test status
Simulation time 107919643907 ps
CPU time 1893.68 seconds
Started Oct 09 01:32:28 PM UTC 24
Finished Oct 09 02:04:24 PM UTC 24
Peak memory 211592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188205498 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection.2188205498
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/27.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_executable.2311530262
Short name T569
Test name
Test status
Simulation time 5122442732 ps
CPU time 349.64 seconds
Started Oct 09 01:33:50 PM UTC 24
Finished Oct 09 01:39:45 PM UTC 24
Peak memory 384044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311530262 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executable.2311530262
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/27.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.3205409251
Short name T526
Test name
Test status
Simulation time 10126197117 ps
CPU time 76.24 seconds
Started Oct 09 01:33:32 PM UTC 24
Finished Oct 09 01:34:51 PM UTC 24
Peak memory 221564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205409251 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_escalation.3205409251
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/27.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.4120791181
Short name T513
Test name
Test status
Simulation time 710986918 ps
CPU time 18.14 seconds
Started Oct 09 01:33:21 PM UTC 24
Finished Oct 09 01:33:41 PM UTC 24
Peak memory 244988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
4120791181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_
max_throughput.4120791181
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/27.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.1800698412
Short name T88
Test name
Test status
Simulation time 2666297479 ps
CPU time 97.31 seconds
Started Oct 09 01:34:05 PM UTC 24
Finished Oct 09 01:35:45 PM UTC 24
Peak memory 228652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800698412 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_mem_partial_access.1800698412
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/27.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.3560623231
Short name T576
Test name
Test status
Simulation time 20694441849 ps
CPU time 396.54 seconds
Started Oct 09 01:34:02 PM UTC 24
Finished Oct 09 01:40:44 PM UTC 24
Peak memory 221536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560623231 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_mem_walk.3560623231
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/27.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.632432560
Short name T572
Test name
Test status
Simulation time 37488584349 ps
CPU time 460.86 seconds
Started Oct 09 01:32:22 PM UTC 24
Finished Oct 09 01:40:10 PM UTC 24
Peak memory 380028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632432560 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multiple_keys.632432560
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/27.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access.3283685727
Short name T524
Test name
Test status
Simulation time 1898197239 ps
CPU time 100.65 seconds
Started Oct 09 01:33:01 PM UTC 24
Finished Oct 09 01:34:44 PM UTC 24
Peak memory 377764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283685727 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_partial_access.3283685727
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/27.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.3652306790
Short name T562
Test name
Test status
Simulation time 18894437635 ps
CPU time 354.45 seconds
Started Oct 09 01:33:03 PM UTC 24
Finished Oct 09 01:39:03 PM UTC 24
Peak memory 211492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652306790 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_partial_a
ccess_b2b.3652306790
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/27.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.3646098517
Short name T518
Test name
Test status
Simulation time 353944103 ps
CPU time 5.44 seconds
Started Oct 09 01:33:58 PM UTC 24
Finished Oct 09 01:34:05 PM UTC 24
Peak memory 211488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646098517 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.3646098517
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/27.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_readback_err.298845608
Short name T521
Test name
Test status
Simulation time 1376035041 ps
CPU time 9.95 seconds
Started Oct 09 01:34:09 PM UTC 24
Finished Oct 09 01:34:20 PM UTC 24
Peak memory 211556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298845608 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_readback_err.298845608
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/27.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_regwen.1823971521
Short name T634
Test name
Test status
Simulation time 9310233303 ps
CPU time 896.73 seconds
Started Oct 09 01:33:57 PM UTC 24
Finished Oct 09 01:49:04 PM UTC 24
Peak memory 382008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823971521 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.1823971521
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/27.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_smoke.4182851450
Short name T505
Test name
Test status
Simulation time 1770771756 ps
CPU time 10.74 seconds
Started Oct 09 01:32:09 PM UTC 24
Finished Oct 09 01:32:21 PM UTC 24
Peak memory 226220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182851450 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.4182851450
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/27.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all.688772852
Short name T857
Test name
Test status
Simulation time 42009307874 ps
CPU time 2817.18 seconds
Started Oct 09 01:34:21 PM UTC 24
Finished Oct 09 02:21:49 PM UTC 24
Peak memory 393748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68877285
2 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all.688772852
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/27.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.2232216359
Short name T522
Test name
Test status
Simulation time 603564127 ps
CPU time 15.79 seconds
Started Oct 09 01:34:15 PM UTC 24
Finished Oct 09 01:34:32 PM UTC 24
Peak memory 221544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232216359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.2232216359
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/27.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.1073183259
Short name T538
Test name
Test status
Simulation time 2459401330 ps
CPU time 196.71 seconds
Started Oct 09 01:32:28 PM UTC 24
Finished Oct 09 01:35:48 PM UTC 24
Peak memory 211204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073183259 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_pipeline.1073183259
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/27.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.4285149667
Short name T529
Test name
Test status
Simulation time 789107389 ps
CPU time 100.51 seconds
Started Oct 09 01:33:29 PM UTC 24
Finished Oct 09 01:35:12 PM UTC 24
Peak memory 381944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=4285149667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl
_throughput_w_partial_write.4285149667
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/27.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.897334263
Short name T679
Test name
Test status
Simulation time 20311078654 ps
CPU time 1306.73 seconds
Started Oct 09 01:35:20 PM UTC 24
Finished Oct 09 01:57:21 PM UTC 24
Peak memory 388224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897334263 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_access_durin
g_key_req.897334263
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/28.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_alert_test.1198405241
Short name T540
Test name
Test status
Simulation time 14479632 ps
CPU time 1.1 seconds
Started Oct 09 01:36:14 PM UTC 24
Finished Oct 09 01:36:17 PM UTC 24
Peak memory 209432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198405241
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_alert_test.1198405241
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/28.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_executable.3955913221
Short name T628
Test name
Test status
Simulation time 92668143596 ps
CPU time 752.18 seconds
Started Oct 09 01:35:27 PM UTC 24
Finished Oct 09 01:48:08 PM UTC 24
Peak memory 374060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955913221 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executable.3955913221
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/28.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.2154933570
Short name T544
Test name
Test status
Simulation time 12542079661 ps
CPU time 76.8 seconds
Started Oct 09 01:35:17 PM UTC 24
Finished Oct 09 01:36:35 PM UTC 24
Peak memory 211516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154933570 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_escalation.2154933570
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/28.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.1054289384
Short name T546
Test name
Test status
Simulation time 2314280709 ps
CPU time 99.28 seconds
Started Oct 09 01:35:12 PM UTC 24
Finished Oct 09 01:36:54 PM UTC 24
Peak memory 380152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1054289384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_
max_throughput.1054289384
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/28.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.2129235477
Short name T548
Test name
Test status
Simulation time 6239192404 ps
CPU time 84.62 seconds
Started Oct 09 01:35:43 PM UTC 24
Finished Oct 09 01:37:09 PM UTC 24
Peak memory 221568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129235477 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_mem_partial_access.2129235477
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/28.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.3848007094
Short name T579
Test name
Test status
Simulation time 65627586980 ps
CPU time 331.92 seconds
Started Oct 09 01:35:43 PM UTC 24
Finished Oct 09 01:41:19 PM UTC 24
Peak memory 221824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848007094 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_mem_walk.3848007094
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/28.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.2021533337
Short name T661
Test name
Test status
Simulation time 126971855495 ps
CPU time 1137.86 seconds
Started Oct 09 01:34:45 PM UTC 24
Finished Oct 09 01:53:56 PM UTC 24
Peak memory 386160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021533337 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multiple_keys.2021533337
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/28.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access.3848550342
Short name T532
Test name
Test status
Simulation time 1942007058 ps
CPU time 20.49 seconds
Started Oct 09 01:34:57 PM UTC 24
Finished Oct 09 01:35:19 PM UTC 24
Peak memory 211196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848550342 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_partial_access.3848550342
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/28.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.3403550498
Short name T571
Test name
Test status
Simulation time 17177318275 ps
CPU time 292.85 seconds
Started Oct 09 01:35:09 PM UTC 24
Finished Oct 09 01:40:06 PM UTC 24
Peak memory 211580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403550498 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_partial_a
ccess_b2b.3403550498
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/28.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.3283154644
Short name T536
Test name
Test status
Simulation time 351719022 ps
CPU time 5.68 seconds
Started Oct 09 01:35:34 PM UTC 24
Finished Oct 09 01:35:41 PM UTC 24
Peak memory 211292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283154644 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.3283154644
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/28.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_readback_err.3171474523
Short name T34
Test name
Test status
Simulation time 2754234532 ps
CPU time 9.3 seconds
Started Oct 09 01:35:46 PM UTC 24
Finished Oct 09 01:35:56 PM UTC 24
Peak memory 211532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171474523 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_readback_err.3171474523
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/28.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_regwen.536458107
Short name T635
Test name
Test status
Simulation time 39925618107 ps
CPU time 804.59 seconds
Started Oct 09 01:35:33 PM UTC 24
Finished Oct 09 01:49:07 PM UTC 24
Peak memory 388452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536458107 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.536458107
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/28.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_smoke.2104333118
Short name T525
Test name
Test status
Simulation time 402850749 ps
CPU time 11.24 seconds
Started Oct 09 01:34:36 PM UTC 24
Finished Oct 09 01:34:49 PM UTC 24
Peak memory 211204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104333118 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.2104333118
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/28.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all.3403217157
Short name T895
Test name
Test status
Simulation time 352890408811 ps
CPU time 2928.6 seconds
Started Oct 09 01:35:57 PM UTC 24
Finished Oct 09 02:25:15 PM UTC 24
Peak memory 396136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34032171
57 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_a
ll.3403217157
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/28.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.692877332
Short name T547
Test name
Test status
Simulation time 4186514751 ps
CPU time 69.97 seconds
Started Oct 09 01:35:49 PM UTC 24
Finished Oct 09 01:37:01 PM UTC 24
Peak memory 228428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692877332 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.692877332
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/28.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.733572929
Short name T561
Test name
Test status
Simulation time 10387950164 ps
CPU time 241.72 seconds
Started Oct 09 01:34:52 PM UTC 24
Finished Oct 09 01:38:57 PM UTC 24
Peak memory 211272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733572929 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_pipeline.733572929
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/28.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.1836795659
Short name T541
Test name
Test status
Simulation time 1547480248 ps
CPU time 60.34 seconds
Started Oct 09 01:35:17 PM UTC 24
Finished Oct 09 01:36:18 PM UTC 24
Peak memory 340916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1836795659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl
_throughput_w_partial_write.1836795659
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/28.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.2565815203
Short name T566
Test name
Test status
Simulation time 2256371307 ps
CPU time 123.18 seconds
Started Oct 09 01:37:21 PM UTC 24
Finished Oct 09 01:39:26 PM UTC 24
Peak memory 379892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565815203 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_access_duri
ng_key_req.2565815203
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/29.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_alert_test.250880083
Short name T559
Test name
Test status
Simulation time 36977636 ps
CPU time 0.98 seconds
Started Oct 09 01:38:39 PM UTC 24
Finished Oct 09 01:38:41 PM UTC 24
Peak memory 209432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250880083 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_alert_test.250880083
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/29.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_executable.3188903474
Short name T583
Test name
Test status
Simulation time 15900977223 ps
CPU time 267.2 seconds
Started Oct 09 01:37:22 PM UTC 24
Finished Oct 09 01:41:53 PM UTC 24
Peak memory 351268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188903474 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executable.3188903474
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/29.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.1112682861
Short name T554
Test name
Test status
Simulation time 3559477188 ps
CPU time 32.61 seconds
Started Oct 09 01:37:10 PM UTC 24
Finished Oct 09 01:37:43 PM UTC 24
Peak memory 221532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112682861 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_escalation.1112682861
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/29.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.3463013974
Short name T552
Test name
Test status
Simulation time 2287337916 ps
CPU time 28.62 seconds
Started Oct 09 01:36:54 PM UTC 24
Finished Oct 09 01:37:24 PM UTC 24
Peak memory 277756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3463013974 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_
max_throughput.3463013974
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/29.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.2727192136
Short name T564
Test name
Test status
Simulation time 972440925 ps
CPU time 87 seconds
Started Oct 09 01:37:44 PM UTC 24
Finished Oct 09 01:39:13 PM UTC 24
Peak memory 221516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727192136 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_mem_partial_access.2727192136
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/29.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.198687817
Short name T574
Test name
Test status
Simulation time 1981201138 ps
CPU time 164.46 seconds
Started Oct 09 01:37:35 PM UTC 24
Finished Oct 09 01:40:23 PM UTC 24
Peak memory 221520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198687817 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_mem_walk.198687817
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/29.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.2278033193
Short name T610
Test name
Test status
Simulation time 8779494187 ps
CPU time 568.1 seconds
Started Oct 09 01:36:19 PM UTC 24
Finished Oct 09 01:45:55 PM UTC 24
Peak memory 384016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278033193 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multiple_keys.2278033193
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/29.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access.3195779877
Short name T545
Test name
Test status
Simulation time 1471747060 ps
CPU time 7.27 seconds
Started Oct 09 01:36:36 PM UTC 24
Finished Oct 09 01:36:44 PM UTC 24
Peak memory 217580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195779877 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_partial_access.3195779877
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/29.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.1373814127
Short name T588
Test name
Test status
Simulation time 6497445887 ps
CPU time 375.68 seconds
Started Oct 09 01:36:45 PM UTC 24
Finished Oct 09 01:43:06 PM UTC 24
Peak memory 211340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373814127 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_partial_a
ccess_b2b.1373814127
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/29.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.278106351
Short name T553
Test name
Test status
Simulation time 5611456309 ps
CPU time 7.57 seconds
Started Oct 09 01:37:25 PM UTC 24
Finished Oct 09 01:37:34 PM UTC 24
Peak memory 211352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278106351 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.278106351
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/29.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_readback_err.1936897087
Short name T556
Test name
Test status
Simulation time 2352309204 ps
CPU time 10.95 seconds
Started Oct 09 01:37:50 PM UTC 24
Finished Oct 09 01:38:02 PM UTC 24
Peak memory 211620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936897087 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_readback_err.1936897087
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/29.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_regwen.770043066
Short name T657
Test name
Test status
Simulation time 12772778769 ps
CPU time 894.89 seconds
Started Oct 09 01:37:25 PM UTC 24
Finished Oct 09 01:52:31 PM UTC 24
Peak memory 388144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770043066 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.770043066
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/29.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_smoke.2954513013
Short name T549
Test name
Test status
Simulation time 4782310405 ps
CPU time 60.97 seconds
Started Oct 09 01:36:17 PM UTC 24
Finished Oct 09 01:37:20 PM UTC 24
Peak memory 324916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954513013 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.2954513013
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/29.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all.1251042025
Short name T977
Test name
Test status
Simulation time 1293753676435 ps
CPU time 4255.91 seconds
Started Oct 09 01:38:17 PM UTC 24
Finished Oct 09 02:50:03 PM UTC 24
Peak memory 387608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12510420
25 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_a
ll.1251042025
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/29.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1585971131
Short name T557
Test name
Test status
Simulation time 1196209603 ps
CPU time 12.12 seconds
Started Oct 09 01:38:03 PM UTC 24
Finished Oct 09 01:38:16 PM UTC 24
Peak memory 221472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585971131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.1585971131
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/29.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.1037886974
Short name T595
Test name
Test status
Simulation time 12857154390 ps
CPU time 442.59 seconds
Started Oct 09 01:36:35 PM UTC 24
Finished Oct 09 01:44:03 PM UTC 24
Peak memory 211344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037886974 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_pipeline.1037886974
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/29.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.64999906
Short name T558
Test name
Test status
Simulation time 3268450050 ps
CPU time 94.88 seconds
Started Oct 09 01:37:01 PM UTC 24
Finished Oct 09 01:38:38 PM UTC 24
Peak memory 381936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=64999906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_t
hroughput_w_partial_write.64999906
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/29.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_access_during_key_req.1737640175
Short name T40
Test name
Test status
Simulation time 5105583896 ps
CPU time 236.03 seconds
Started Oct 09 12:23:20 PM UTC 24
Finished Oct 09 12:27:20 PM UTC 24
Peak memory 369984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737640175 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_access_durin
g_key_req.1737640175
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_alert_test.3823727275
Short name T130
Test name
Test status
Simulation time 14574048 ps
CPU time 1.01 seconds
Started Oct 09 12:24:33 PM UTC 24
Finished Oct 09 12:24:35 PM UTC 24
Peak memory 209432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823727275
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_alert_test.3823727275
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_bijection.1804783657
Short name T214
Test name
Test status
Simulation time 16477417891 ps
CPU time 1130.57 seconds
Started Oct 09 12:22:14 PM UTC 24
Finished Oct 09 12:41:18 PM UTC 24
Peak memory 211372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804783657 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.1804783657
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_executable.380368191
Short name T27
Test name
Test status
Simulation time 3612352775 ps
CPU time 159.29 seconds
Started Oct 09 12:23:41 PM UTC 24
Finished Oct 09 12:26:23 PM UTC 24
Peak memory 365544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380368191 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executable.380368191
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_lc_escalation.2678393214
Short name T22
Test name
Test status
Simulation time 29501912290 ps
CPU time 121.65 seconds
Started Oct 09 12:23:11 PM UTC 24
Finished Oct 09 12:25:15 PM UTC 24
Peak memory 211640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678393214 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_escalation.2678393214
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_max_throughput.2464959211
Short name T164
Test name
Test status
Simulation time 706073771 ps
CPU time 22.01 seconds
Started Oct 09 12:22:42 PM UTC 24
Finished Oct 09 12:23:06 PM UTC 24
Peak memory 261108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2464959211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_m
ax_throughput.2464959211
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_partial_access.2569249349
Short name T47
Test name
Test status
Simulation time 2842468241 ps
CPU time 94.8 seconds
Started Oct 09 12:24:04 PM UTC 24
Finished Oct 09 12:25:41 PM UTC 24
Peak memory 228612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569249349 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_mem_partial_access.2569249349
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_mem_walk.2967075645
Short name T46
Test name
Test status
Simulation time 44055972087 ps
CPU time 401.3 seconds
Started Oct 09 12:23:58 PM UTC 24
Finished Oct 09 12:30:44 PM UTC 24
Peak memory 221552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967075645 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_mem_walk.2967075645
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.1092956437
Short name T210
Test name
Test status
Simulation time 22727089593 ps
CPU time 1087.47 seconds
Started Oct 09 12:22:13 PM UTC 24
Finished Oct 09 12:40:32 PM UTC 24
Peak memory 388144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092956437 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multiple_keys.1092956437
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access.1436006205
Short name T165
Test name
Test status
Simulation time 2108722915 ps
CPU time 12.77 seconds
Started Oct 09 12:22:25 PM UTC 24
Finished Oct 09 12:22:39 PM UTC 24
Peak memory 211148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436006205 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_partial_access.1436006205
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_partial_access_b2b.611921754
Short name T109
Test name
Test status
Simulation time 19799078798 ps
CPU time 379.36 seconds
Started Oct 09 12:22:41 PM UTC 24
Finished Oct 09 12:29:05 PM UTC 24
Peak memory 211308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611921754 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_partial_acc
ess_b2b.611921754
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_ram_cfg.1278970316
Short name T128
Test name
Test status
Simulation time 354938472 ps
CPU time 6.2 seconds
Started Oct 09 12:23:56 PM UTC 24
Finished Oct 09 12:24:03 PM UTC 24
Peak memory 211288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278970316 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.1278970316
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_readback_err.3149180485
Short name T129
Test name
Test status
Simulation time 662736941 ps
CPU time 8.84 seconds
Started Oct 09 12:24:20 PM UTC 24
Finished Oct 09 12:24:30 PM UTC 24
Peak memory 211552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149180485 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_readback_err.3149180485
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_regwen.164226603
Short name T131
Test name
Test status
Simulation time 55947788667 ps
CPU time 773.1 seconds
Started Oct 09 12:23:43 PM UTC 24
Finished Oct 09 12:36:46 PM UTC 24
Peak memory 382004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164226603 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.164226603
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_sec_cm.1895000569
Short name T31
Test name
Test status
Simulation time 439616620 ps
CPU time 3.35 seconds
Started Oct 09 12:24:31 PM UTC 24
Finished Oct 09 12:24:36 PM UTC 24
Peak memory 247908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895000569 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_sec_cm.1895000569
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_smoke.2664586508
Short name T56
Test name
Test status
Simulation time 723709069 ps
CPU time 11.73 seconds
Started Oct 09 12:22:12 PM UTC 24
Finished Oct 09 12:22:25 PM UTC 24
Peak memory 211416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664586508 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.2664586508
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all.3200845729
Short name T465
Test name
Test status
Simulation time 269165146058 ps
CPU time 3680.09 seconds
Started Oct 09 12:24:24 PM UTC 24
Finished Oct 09 01:26:23 PM UTC 24
Peak memory 391708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32008457
29 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all.3200845729
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_pipeline.923991621
Short name T110
Test name
Test status
Simulation time 6192072089 ps
CPU time 511.35 seconds
Started Oct 09 12:22:21 PM UTC 24
Finished Oct 09 12:31:00 PM UTC 24
Peak memory 211268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923991621 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_pipeline.923991621
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_throughput_w_partial_write.119361730
Short name T127
Test name
Test status
Simulation time 1517374517 ps
CPU time 45.45 seconds
Started Oct 09 12:23:07 PM UTC 24
Finished Oct 09 12:23:54 PM UTC 24
Peak memory 318456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=119361730 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_t
hroughput_w_partial_write.119361730
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/3.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.1032689004
Short name T614
Test name
Test status
Simulation time 14766503611 ps
CPU time 384.03 seconds
Started Oct 09 01:39:41 PM UTC 24
Finished Oct 09 01:46:10 PM UTC 24
Peak memory 386240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032689004 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_access_duri
ng_key_req.1032689004
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/30.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_alert_test.3459763772
Short name T578
Test name
Test status
Simulation time 15202850 ps
CPU time 0.98 seconds
Started Oct 09 01:41:15 PM UTC 24
Finished Oct 09 01:41:17 PM UTC 24
Peak memory 209432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459763772
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_alert_test.3459763772
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/30.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_bijection.4138488657
Short name T748
Test name
Test status
Simulation time 287529724587 ps
CPU time 1606.18 seconds
Started Oct 09 01:38:58 PM UTC 24
Finished Oct 09 02:06:04 PM UTC 24
Peak memory 211576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138488657 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection.4138488657
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/30.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_executable.1874963991
Short name T678
Test name
Test status
Simulation time 20592310956 ps
CPU time 1027.1 seconds
Started Oct 09 01:39:46 PM UTC 24
Finished Oct 09 01:57:04 PM UTC 24
Peak memory 388168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874963991 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executable.1874963991
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/30.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.1576237881
Short name T584
Test name
Test status
Simulation time 27994239318 ps
CPU time 142.77 seconds
Started Oct 09 01:39:30 PM UTC 24
Finished Oct 09 01:41:56 PM UTC 24
Peak memory 221596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576237881 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_escalation.1576237881
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/30.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.2760517814
Short name T570
Test name
Test status
Simulation time 1797278020 ps
CPU time 32.92 seconds
Started Oct 09 01:39:20 PM UTC 24
Finished Oct 09 01:39:54 PM UTC 24
Peak memory 326832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2760517814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_
max_throughput.2760517814
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/30.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.1356418714
Short name T582
Test name
Test status
Simulation time 2285766381 ps
CPU time 91.6 seconds
Started Oct 09 01:40:15 PM UTC 24
Finished Oct 09 01:41:49 PM UTC 24
Peak memory 221604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356418714 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_mem_partial_access.1356418714
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/30.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.1727709900
Short name T603
Test name
Test status
Simulation time 54476079521 ps
CPU time 261.49 seconds
Started Oct 09 01:40:10 PM UTC 24
Finished Oct 09 01:44:36 PM UTC 24
Peak memory 221604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727709900 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_mem_walk.1727709900
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/30.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.3787384999
Short name T653
Test name
Test status
Simulation time 5925226555 ps
CPU time 756.33 seconds
Started Oct 09 01:38:47 PM UTC 24
Finished Oct 09 01:51:33 PM UTC 24
Peak memory 390252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787384999 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multiple_keys.3787384999
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/30.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access.2183345873
Short name T567
Test name
Test status
Simulation time 1634861400 ps
CPU time 18.48 seconds
Started Oct 09 01:39:10 PM UTC 24
Finished Oct 09 01:39:30 PM UTC 24
Peak memory 244904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183345873 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_partial_access.2183345873
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/30.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.1649188357
Short name T633
Test name
Test status
Simulation time 37563496423 ps
CPU time 581.87 seconds
Started Oct 09 01:39:14 PM UTC 24
Finished Oct 09 01:49:04 PM UTC 24
Peak memory 211516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649188357 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_partial_a
ccess_b2b.1649188357
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/30.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.2855248424
Short name T573
Test name
Test status
Simulation time 2130781148 ps
CPU time 6.22 seconds
Started Oct 09 01:40:07 PM UTC 24
Finished Oct 09 01:40:14 PM UTC 24
Peak memory 211488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855248424 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.2855248424
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/30.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_readback_err.1106446431
Short name T575
Test name
Test status
Simulation time 1324533973 ps
CPU time 10.31 seconds
Started Oct 09 01:40:24 PM UTC 24
Finished Oct 09 01:40:35 PM UTC 24
Peak memory 211556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106446431 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_readback_err.1106446431
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/30.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_regwen.670378953
Short name T729
Test name
Test status
Simulation time 40970596654 ps
CPU time 1393.71 seconds
Started Oct 09 01:39:55 PM UTC 24
Finished Oct 09 02:03:25 PM UTC 24
Peak memory 388320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670378953 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.670378953
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/30.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_smoke.2026118412
Short name T563
Test name
Test status
Simulation time 1353880979 ps
CPU time 25.18 seconds
Started Oct 09 01:38:42 PM UTC 24
Finished Oct 09 01:39:09 PM UTC 24
Peak memory 211508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026118412 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.2026118412
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/30.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_all.3171852109
Short name T710
Test name
Test status
Simulation time 30933774348 ps
CPU time 1197.97 seconds
Started Oct 09 01:40:45 PM UTC 24
Finished Oct 09 02:00:57 PM UTC 24
Peak memory 390140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31718521
09 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_a
ll.3171852109
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/30.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.1124173788
Short name T50
Test name
Test status
Simulation time 3538509093 ps
CPU time 115.81 seconds
Started Oct 09 01:40:36 PM UTC 24
Finished Oct 09 01:42:35 PM UTC 24
Peak memory 294048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124173788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.1124173788
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/30.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.2787915863
Short name T590
Test name
Test status
Simulation time 10920437615 ps
CPU time 251.32 seconds
Started Oct 09 01:39:04 PM UTC 24
Finished Oct 09 01:43:19 PM UTC 24
Peak memory 211360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787915863 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_pipeline.2787915863
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/30.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.1159612410
Short name T568
Test name
Test status
Simulation time 726749562 ps
CPU time 11.4 seconds
Started Oct 09 01:39:27 PM UTC 24
Finished Oct 09 01:39:40 PM UTC 24
Peak memory 227780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1159612410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl
_throughput_w_partial_write.1159612410
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/30.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.996499688
Short name T687
Test name
Test status
Simulation time 54890344884 ps
CPU time 930.77 seconds
Started Oct 09 01:42:36 PM UTC 24
Finished Oct 09 01:58:17 PM UTC 24
Peak memory 386100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996499688 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_access_durin
g_key_req.996499688
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/31.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_alert_test.4274787024
Short name T597
Test name
Test status
Simulation time 21027432 ps
CPU time 1.12 seconds
Started Oct 09 01:44:04 PM UTC 24
Finished Oct 09 01:44:06 PM UTC 24
Peak memory 209432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274787024
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_alert_test.4274787024
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/31.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_bijection.1930881219
Short name T841
Test name
Test status
Simulation time 30079926593 ps
CPU time 2217.21 seconds
Started Oct 09 01:41:26 PM UTC 24
Finished Oct 09 02:18:48 PM UTC 24
Peak memory 212728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930881219 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection.1930881219
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/31.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_executable.1509046141
Short name T671
Test name
Test status
Simulation time 34332379448 ps
CPU time 783.52 seconds
Started Oct 09 01:42:41 PM UTC 24
Finished Oct 09 01:55:54 PM UTC 24
Peak memory 386336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509046141 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executable.1509046141
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/31.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.2525803711
Short name T598
Test name
Test status
Simulation time 81836777541 ps
CPU time 104.69 seconds
Started Oct 09 01:42:29 PM UTC 24
Finished Oct 09 01:44:16 PM UTC 24
Peak memory 221724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525803711 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_escalation.2525803711
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/31.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.583512719
Short name T586
Test name
Test status
Simulation time 2393468405 ps
CPU time 28.88 seconds
Started Oct 09 01:41:57 PM UTC 24
Finished Oct 09 01:42:28 PM UTC 24
Peak memory 300344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
583512719 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_m
ax_throughput.583512719
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/31.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.4232723190
Short name T606
Test name
Test status
Simulation time 1449875936 ps
CPU time 104.5 seconds
Started Oct 09 01:43:28 PM UTC 24
Finished Oct 09 01:45:15 PM UTC 24
Peak memory 228296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232723190 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_mem_partial_access.4232723190
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/31.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.1882858838
Short name T612
Test name
Test status
Simulation time 21512397267 ps
CPU time 158.11 seconds
Started Oct 09 01:43:19 PM UTC 24
Finished Oct 09 01:46:00 PM UTC 24
Peak memory 221864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882858838 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_mem_walk.1882858838
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/31.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.2549350737
Short name T667
Test name
Test status
Simulation time 31185671776 ps
CPU time 809.46 seconds
Started Oct 09 01:41:21 PM UTC 24
Finished Oct 09 01:54:59 PM UTC 24
Peak memory 386160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549350737 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multiple_keys.2549350737
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/31.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access.263067461
Short name T587
Test name
Test status
Simulation time 3417171735 ps
CPU time 48.26 seconds
Started Oct 09 01:41:50 PM UTC 24
Finished Oct 09 01:42:40 PM UTC 24
Peak memory 300052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263067461 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_partial_access.263067461
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/31.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.3548610435
Short name T620
Test name
Test status
Simulation time 11832294035 ps
CPU time 290.8 seconds
Started Oct 09 01:41:54 PM UTC 24
Finished Oct 09 01:46:49 PM UTC 24
Peak memory 211348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548610435 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_partial_a
ccess_b2b.3548610435
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/31.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.376119197
Short name T591
Test name
Test status
Simulation time 1401940417 ps
CPU time 5.99 seconds
Started Oct 09 01:43:19 PM UTC 24
Finished Oct 09 01:43:27 PM UTC 24
Peak memory 211432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376119197 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.376119197
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/31.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_readback_err.1818886353
Short name T593
Test name
Test status
Simulation time 4388480025 ps
CPU time 8.83 seconds
Started Oct 09 01:43:36 PM UTC 24
Finished Oct 09 01:43:46 PM UTC 24
Peak memory 211748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818886353 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_readback_err.1818886353
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/31.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_regwen.805423266
Short name T623
Test name
Test status
Simulation time 7196287160 ps
CPU time 267.27 seconds
Started Oct 09 01:43:07 PM UTC 24
Finished Oct 09 01:47:39 PM UTC 24
Peak memory 382000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805423266 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.805423266
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/31.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_smoke.4109032899
Short name T581
Test name
Test status
Simulation time 6002488112 ps
CPU time 26.93 seconds
Started Oct 09 01:41:18 PM UTC 24
Finished Oct 09 01:41:47 PM UTC 24
Peak memory 211228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109032899 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.4109032899
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/31.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_all.486533654
Short name T726
Test name
Test status
Simulation time 50265978396 ps
CPU time 1155.87 seconds
Started Oct 09 01:43:52 PM UTC 24
Finished Oct 09 02:03:20 PM UTC 24
Peak memory 384124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48653365
4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all.486533654
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/31.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.2172144632
Short name T602
Test name
Test status
Simulation time 1187409086 ps
CPU time 46.94 seconds
Started Oct 09 01:43:47 PM UTC 24
Finished Oct 09 01:44:35 PM UTC 24
Peak memory 223672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172144632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.2172144632
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/31.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.6453350
Short name T619
Test name
Test status
Simulation time 19133969511 ps
CPU time 290.47 seconds
Started Oct 09 01:41:48 PM UTC 24
Finished Oct 09 01:46:42 PM UTC 24
Peak memory 211340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6453350 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_pipeline.6453350
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/31.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.3225016313
Short name T596
Test name
Test status
Simulation time 789867162 ps
CPU time 110.79 seconds
Started Oct 09 01:42:12 PM UTC 24
Finished Oct 09 01:44:06 PM UTC 24
Peak memory 379828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3225016313 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl
_throughput_w_partial_write.3225016313
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/31.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.359204632
Short name T650
Test name
Test status
Simulation time 10267880985 ps
CPU time 366.1 seconds
Started Oct 09 01:45:02 PM UTC 24
Finished Oct 09 01:51:13 PM UTC 24
Peak memory 384228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359204632 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_access_durin
g_key_req.359204632
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/32.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_alert_test.1919777407
Short name T615
Test name
Test status
Simulation time 27417529 ps
CPU time 1.05 seconds
Started Oct 09 01:46:11 PM UTC 24
Finished Oct 09 01:46:13 PM UTC 24
Peak memory 211336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919777407
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_alert_test.1919777407
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/32.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_bijection.2251856187
Short name T730
Test name
Test status
Simulation time 63657837900 ps
CPU time 1133.85 seconds
Started Oct 09 01:44:17 PM UTC 24
Finished Oct 09 02:03:26 PM UTC 24
Peak memory 211384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251856187 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection.2251856187
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/32.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_executable.2933475448
Short name T659
Test name
Test status
Simulation time 3165956156 ps
CPU time 441.57 seconds
Started Oct 09 01:45:16 PM UTC 24
Finished Oct 09 01:52:43 PM UTC 24
Peak memory 386104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933475448 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executable.2933475448
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/32.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.510308700
Short name T617
Test name
Test status
Simulation time 11648922415 ps
CPU time 107.03 seconds
Started Oct 09 01:44:50 PM UTC 24
Finished Oct 09 01:46:40 PM UTC 24
Peak memory 221860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510308700 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_escalation.510308700
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/32.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.1181001247
Short name T605
Test name
Test status
Simulation time 1436989056 ps
CPU time 23.4 seconds
Started Oct 09 01:44:36 PM UTC 24
Finished Oct 09 01:45:01 PM UTC 24
Peak memory 285944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1181001247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_
max_throughput.1181001247
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/32.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.2858422872
Short name T630
Test name
Test status
Simulation time 17594886421 ps
CPU time 156.61 seconds
Started Oct 09 01:45:55 PM UTC 24
Finished Oct 09 01:48:35 PM UTC 24
Peak memory 228560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858422872 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_mem_partial_access.2858422872
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/32.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.2812886522
Short name T632
Test name
Test status
Simulation time 99768783480 ps
CPU time 184.03 seconds
Started Oct 09 01:45:41 PM UTC 24
Finished Oct 09 01:48:48 PM UTC 24
Peak memory 221832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812886522 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_mem_walk.2812886522
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/32.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.3618428493
Short name T689
Test name
Test status
Simulation time 40861019685 ps
CPU time 854.72 seconds
Started Oct 09 01:44:07 PM UTC 24
Finished Oct 09 01:58:32 PM UTC 24
Peak memory 373796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618428493 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multiple_keys.3618428493
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/32.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access.3199055031
Short name T604
Test name
Test status
Simulation time 1110150220 ps
CPU time 27.52 seconds
Started Oct 09 01:44:21 PM UTC 24
Finished Oct 09 01:44:50 PM UTC 24
Peak memory 296104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199055031 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_partial_access.3199055031
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/32.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.2111407354
Short name T637
Test name
Test status
Simulation time 23400543928 ps
CPU time 280.8 seconds
Started Oct 09 01:44:30 PM UTC 24
Finished Oct 09 01:49:15 PM UTC 24
Peak memory 211556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111407354 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_partial_a
ccess_b2b.2111407354
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/32.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.504900350
Short name T609
Test name
Test status
Simulation time 366890876 ps
CPU time 5.86 seconds
Started Oct 09 01:45:33 PM UTC 24
Finished Oct 09 01:45:40 PM UTC 24
Peak memory 211296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504900350 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.504900350
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/32.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_readback_err.3294537884
Short name T613
Test name
Test status
Simulation time 1346821971 ps
CPU time 7.77 seconds
Started Oct 09 01:45:57 PM UTC 24
Finished Oct 09 01:46:06 PM UTC 24
Peak memory 211292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294537884 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_readback_err.3294537884
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/32.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_regwen.3064769420
Short name T701
Test name
Test status
Simulation time 136214892871 ps
CPU time 847.2 seconds
Started Oct 09 01:45:30 PM UTC 24
Finished Oct 09 01:59:47 PM UTC 24
Peak memory 390396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064769420 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.3064769420
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/32.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_smoke.3219890629
Short name T600
Test name
Test status
Simulation time 3077652649 ps
CPU time 12.94 seconds
Started Oct 09 01:44:06 PM UTC 24
Finished Oct 09 01:44:20 PM UTC 24
Peak memory 211228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219890629 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.3219890629
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/32.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all.2219267637
Short name T966
Test name
Test status
Simulation time 106615581861 ps
CPU time 3453.07 seconds
Started Oct 09 01:46:07 PM UTC 24
Finished Oct 09 02:44:17 PM UTC 24
Peak memory 397784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22192676
37 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_a
ll.2219267637
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/32.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.625120993
Short name T616
Test name
Test status
Simulation time 638376065 ps
CPU time 10.84 seconds
Started Oct 09 01:46:02 PM UTC 24
Finished Oct 09 01:46:14 PM UTC 24
Peak memory 221756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625120993 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.625120993
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/32.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.2750013143
Short name T648
Test name
Test status
Simulation time 4753145129 ps
CPU time 396.48 seconds
Started Oct 09 01:44:19 PM UTC 24
Finished Oct 09 01:51:01 PM UTC 24
Peak memory 211448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750013143 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_pipeline.2750013143
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/32.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.1859332764
Short name T608
Test name
Test status
Simulation time 12235378224 ps
CPU time 52.95 seconds
Started Oct 09 01:44:37 PM UTC 24
Finished Oct 09 01:45:32 PM UTC 24
Peak memory 310320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1859332764 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl
_throughput_w_partial_write.1859332764
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/32.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.1758705267
Short name T694
Test name
Test status
Simulation time 23420250008 ps
CPU time 689.34 seconds
Started Oct 09 01:47:40 PM UTC 24
Finished Oct 09 01:59:18 PM UTC 24
Peak memory 386052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758705267 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_access_duri
ng_key_req.1758705267
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/33.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_alert_test.3634997691
Short name T636
Test name
Test status
Simulation time 113927034 ps
CPU time 1 seconds
Started Oct 09 01:49:05 PM UTC 24
Finished Oct 09 01:49:07 PM UTC 24
Peak memory 209432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634997691
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_alert_test.3634997691
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/33.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_bijection.2723485550
Short name T755
Test name
Test status
Simulation time 17060750055 ps
CPU time 1201.91 seconds
Started Oct 09 01:46:41 PM UTC 24
Finished Oct 09 02:06:58 PM UTC 24
Peak memory 211400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723485550 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection.2723485550
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/33.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_executable.3544628169
Short name T644
Test name
Test status
Simulation time 14360977396 ps
CPU time 167.76 seconds
Started Oct 09 01:48:02 PM UTC 24
Finished Oct 09 01:50:52 PM UTC 24
Peak memory 386040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544628169 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executable.3544628169
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/33.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.742142991
Short name T625
Test name
Test status
Simulation time 7943562352 ps
CPU time 19.75 seconds
Started Oct 09 01:47:39 PM UTC 24
Finished Oct 09 01:48:00 PM UTC 24
Peak memory 225788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742142991 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_escalation.742142991
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/33.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.3875902305
Short name T622
Test name
Test status
Simulation time 1815775699 ps
CPU time 7.26 seconds
Started Oct 09 01:47:08 PM UTC 24
Finished Oct 09 01:47:16 PM UTC 24
Peak memory 223408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3875902305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_
max_throughput.3875902305
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/33.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.1361883399
Short name T640
Test name
Test status
Simulation time 4722355805 ps
CPU time 81.28 seconds
Started Oct 09 01:48:14 PM UTC 24
Finished Oct 09 01:49:38 PM UTC 24
Peak memory 221624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361883399 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_mem_partial_access.1361883399
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/33.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.1788483537
Short name T663
Test name
Test status
Simulation time 55279167520 ps
CPU time 371.31 seconds
Started Oct 09 01:48:09 PM UTC 24
Finished Oct 09 01:54:26 PM UTC 24
Peak memory 221536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788483537 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_mem_walk.1788483537
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/33.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.1014905098
Short name T787
Test name
Test status
Simulation time 58962077935 ps
CPU time 1463.65 seconds
Started Oct 09 01:46:15 PM UTC 24
Finished Oct 09 02:10:55 PM UTC 24
Peak memory 390184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014905098 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multiple_keys.1014905098
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/33.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access.2708246254
Short name T624
Test name
Test status
Simulation time 2225495583 ps
CPU time 54.15 seconds
Started Oct 09 01:46:44 PM UTC 24
Finished Oct 09 01:47:39 PM UTC 24
Peak memory 326888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708246254 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_partial_access.2708246254
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/33.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.2856767759
Short name T652
Test name
Test status
Simulation time 13312913601 ps
CPU time 277.84 seconds
Started Oct 09 01:46:50 PM UTC 24
Finished Oct 09 01:51:32 PM UTC 24
Peak memory 211532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856767759 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_partial_a
ccess_b2b.2856767759
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/33.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.2709046033
Short name T629
Test name
Test status
Simulation time 1401600862 ps
CPU time 6.11 seconds
Started Oct 09 01:48:06 PM UTC 24
Finished Oct 09 01:48:13 PM UTC 24
Peak memory 211292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709046033 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.2709046033
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/33.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_readback_err.3236789041
Short name T631
Test name
Test status
Simulation time 1376841542 ps
CPU time 10.2 seconds
Started Oct 09 01:48:35 PM UTC 24
Finished Oct 09 01:48:47 PM UTC 24
Peak memory 211292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236789041 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_readback_err.3236789041
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/33.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_regwen.3880790098
Short name T703
Test name
Test status
Simulation time 25584122609 ps
CPU time 714.55 seconds
Started Oct 09 01:48:03 PM UTC 24
Finished Oct 09 02:00:05 PM UTC 24
Peak memory 388132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880790098 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.3880790098
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/33.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_smoke.3106156186
Short name T626
Test name
Test status
Simulation time 13339767685 ps
CPU time 105.37 seconds
Started Oct 09 01:46:14 PM UTC 24
Finished Oct 09 01:48:02 PM UTC 24
Peak memory 378032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106156186 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.3106156186
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/33.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all.1638348512
Short name T968
Test name
Test status
Simulation time 37737121852 ps
CPU time 3332.15 seconds
Started Oct 09 01:48:49 PM UTC 24
Finished Oct 09 02:45:04 PM UTC 24
Peak memory 389864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16383485
12 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_a
ll.1638348512
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/33.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3589922072
Short name T641
Test name
Test status
Simulation time 1381208923 ps
CPU time 73.48 seconds
Started Oct 09 01:48:48 PM UTC 24
Finished Oct 09 01:50:03 PM UTC 24
Peak memory 223680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589922072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.3589922072
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/33.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.2368947348
Short name T647
Test name
Test status
Simulation time 6230449203 ps
CPU time 252.95 seconds
Started Oct 09 01:46:43 PM UTC 24
Finished Oct 09 01:50:59 PM UTC 24
Peak memory 211312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368947348 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_pipeline.2368947348
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/33.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.1026609293
Short name T627
Test name
Test status
Simulation time 761148409 ps
CPU time 46.11 seconds
Started Oct 09 01:47:17 PM UTC 24
Finished Oct 09 01:48:05 PM UTC 24
Peak memory 340908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1026609293 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl
_throughput_w_partial_write.1026609293
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/33.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.308144309
Short name T754
Test name
Test status
Simulation time 240778321415 ps
CPU time 965.62 seconds
Started Oct 09 01:50:41 PM UTC 24
Finished Oct 09 02:06:58 PM UTC 24
Peak memory 382080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308144309 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_access_durin
g_key_req.308144309
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/34.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_alert_test.3859936220
Short name T654
Test name
Test status
Simulation time 12863597 ps
CPU time 1.07 seconds
Started Oct 09 01:51:31 PM UTC 24
Finished Oct 09 01:51:33 PM UTC 24
Peak memory 209432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859936220
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_alert_test.3859936220
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/34.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_bijection.1326306754
Short name T859
Test name
Test status
Simulation time 72102609152 ps
CPU time 1951.32 seconds
Started Oct 09 01:49:08 PM UTC 24
Finished Oct 09 02:22:02 PM UTC 24
Peak memory 212780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326306754 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection.1326306754
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/34.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_executable.1504120192
Short name T733
Test name
Test status
Simulation time 20510741290 ps
CPU time 776.67 seconds
Started Oct 09 01:50:53 PM UTC 24
Finished Oct 09 02:03:59 PM UTC 24
Peak memory 388476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504120192 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executable.1504120192
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/34.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.73882741
Short name T645
Test name
Test status
Simulation time 3454398921 ps
CPU time 20.58 seconds
Started Oct 09 01:50:36 PM UTC 24
Finished Oct 09 01:50:58 PM UTC 24
Peak memory 221484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73882741 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_escalation.73882741
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/34.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.773025760
Short name T651
Test name
Test status
Simulation time 797651206 ps
CPU time 108.45 seconds
Started Oct 09 01:49:39 PM UTC 24
Finished Oct 09 01:51:30 PM UTC 24
Peak memory 379896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
773025760 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_m
ax_throughput.773025760
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/34.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.4133993904
Short name T660
Test name
Test status
Simulation time 18994729816 ps
CPU time 166.28 seconds
Started Oct 09 01:51:02 PM UTC 24
Finished Oct 09 01:53:51 PM UTC 24
Peak memory 221576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133993904 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_mem_partial_access.4133993904
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/34.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.3790166592
Short name T681
Test name
Test status
Simulation time 149867779613 ps
CPU time 377.78 seconds
Started Oct 09 01:51:00 PM UTC 24
Finished Oct 09 01:57:23 PM UTC 24
Peak memory 221916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790166592 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_mem_walk.3790166592
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/34.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.1009879690
Short name T683
Test name
Test status
Simulation time 6509647023 ps
CPU time 505.03 seconds
Started Oct 09 01:49:08 PM UTC 24
Finished Oct 09 01:57:40 PM UTC 24
Peak memory 338932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009879690 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multiple_keys.1009879690
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/34.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access.3742619662
Short name T639
Test name
Test status
Simulation time 864261239 ps
CPU time 15.86 seconds
Started Oct 09 01:49:19 PM UTC 24
Finished Oct 09 01:49:36 PM UTC 24
Peak memory 240628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742619662 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_partial_access.3742619662
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/34.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.1966978044
Short name T705
Test name
Test status
Simulation time 79118050786 ps
CPU time 640.8 seconds
Started Oct 09 01:49:37 PM UTC 24
Finished Oct 09 02:00:26 PM UTC 24
Peak memory 211556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966978044 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_partial_a
ccess_b2b.1966978044
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/34.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.2863260195
Short name T649
Test name
Test status
Simulation time 694191209 ps
CPU time 5.78 seconds
Started Oct 09 01:51:00 PM UTC 24
Finished Oct 09 01:51:07 PM UTC 24
Peak memory 211288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863260195 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.2863260195
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/34.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_readback_err.2960787907
Short name T35
Test name
Test status
Simulation time 2870833388 ps
CPU time 11.01 seconds
Started Oct 09 01:51:07 PM UTC 24
Finished Oct 09 01:51:20 PM UTC 24
Peak memory 211536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960787907 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_readback_err.2960787907
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/34.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_regwen.4108546863
Short name T696
Test name
Test status
Simulation time 3030655750 ps
CPU time 501.63 seconds
Started Oct 09 01:50:59 PM UTC 24
Finished Oct 09 01:59:26 PM UTC 24
Peak memory 384252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108546863 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.4108546863
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/34.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_smoke.1603591627
Short name T642
Test name
Test status
Simulation time 4683599409 ps
CPU time 88.49 seconds
Started Oct 09 01:49:05 PM UTC 24
Finished Oct 09 01:50:35 PM UTC 24
Peak memory 374132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603591627 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.1603591627
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/34.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all.2890629895
Short name T975
Test name
Test status
Simulation time 104984618083 ps
CPU time 3388.03 seconds
Started Oct 09 01:51:21 PM UTC 24
Finished Oct 09 02:48:28 PM UTC 24
Peak memory 394004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28906298
95 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_a
ll.2890629895
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/34.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3394907761
Short name T656
Test name
Test status
Simulation time 1078042889 ps
CPU time 36.66 seconds
Started Oct 09 01:51:14 PM UTC 24
Finished Oct 09 01:51:52 PM UTC 24
Peak memory 228548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394907761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.3394907761
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/34.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.2528281024
Short name T666
Test name
Test status
Simulation time 4519378670 ps
CPU time 332.65 seconds
Started Oct 09 01:49:15 PM UTC 24
Finished Oct 09 01:54:53 PM UTC 24
Peak memory 211368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528281024 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_pipeline.2528281024
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/34.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.3812969516
Short name T646
Test name
Test status
Simulation time 3177220891 ps
CPU time 53.64 seconds
Started Oct 09 01:50:04 PM UTC 24
Finished Oct 09 01:50:59 PM UTC 24
Peak memory 351480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3812969516 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl
_throughput_w_partial_write.3812969516
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/34.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.1291155896
Short name T695
Test name
Test status
Simulation time 6851382076 ps
CPU time 321.36 seconds
Started Oct 09 01:53:57 PM UTC 24
Finished Oct 09 01:59:23 PM UTC 24
Peak memory 347260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291155896 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_access_duri
ng_key_req.1291155896
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/35.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_alert_test.2598752270
Short name T670
Test name
Test status
Simulation time 29764040 ps
CPU time 0.97 seconds
Started Oct 09 01:55:40 PM UTC 24
Finished Oct 09 01:55:42 PM UTC 24
Peak memory 209432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598752270
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_alert_test.2598752270
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/35.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_bijection.1894218583
Short name T767
Test name
Test status
Simulation time 66818580560 ps
CPU time 1000.79 seconds
Started Oct 09 01:51:34 PM UTC 24
Finished Oct 09 02:08:28 PM UTC 24
Peak memory 211336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894218583 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection.1894218583
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/35.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_executable.3822011691
Short name T784
Test name
Test status
Simulation time 49114550649 ps
CPU time 964.54 seconds
Started Oct 09 01:54:17 PM UTC 24
Finished Oct 09 02:10:33 PM UTC 24
Peak memory 386168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822011691 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executable.3822011691
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/35.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.2415060193
Short name T669
Test name
Test status
Simulation time 48815443451 ps
CPU time 103.61 seconds
Started Oct 09 01:53:53 PM UTC 24
Finished Oct 09 01:55:39 PM UTC 24
Peak memory 221820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415060193 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_escalation.2415060193
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/35.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.1086917488
Short name T662
Test name
Test status
Simulation time 3185118998 ps
CPU time 101.25 seconds
Started Oct 09 01:52:33 PM UTC 24
Finished Oct 09 01:54:16 PM UTC 24
Peak memory 381928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1086917488 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_
max_throughput.1086917488
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/35.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.3708583123
Short name T675
Test name
Test status
Simulation time 2738455568 ps
CPU time 112.04 seconds
Started Oct 09 01:54:42 PM UTC 24
Finished Oct 09 01:56:37 PM UTC 24
Peak memory 221556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708583123 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_mem_partial_access.3708583123
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/35.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.927392654
Short name T713
Test name
Test status
Simulation time 74735919840 ps
CPU time 409.34 seconds
Started Oct 09 01:54:37 PM UTC 24
Finished Oct 09 02:01:32 PM UTC 24
Peak memory 221772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927392654 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_mem_walk.927392654
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/35.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.3093800389
Short name T711
Test name
Test status
Simulation time 27800429819 ps
CPU time 559.31 seconds
Started Oct 09 01:51:34 PM UTC 24
Finished Oct 09 02:01:00 PM UTC 24
Peak memory 380016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093800389 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multiple_keys.3093800389
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/35.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access.1270585575
Short name T658
Test name
Test status
Simulation time 1664086299 ps
CPU time 38.1 seconds
Started Oct 09 01:51:53 PM UTC 24
Finished Oct 09 01:52:32 PM UTC 24
Peak memory 211124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270585575 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_partial_access.1270585575
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/35.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.1980729335
Short name T690
Test name
Test status
Simulation time 7282852397 ps
CPU time 371.71 seconds
Started Oct 09 01:52:32 PM UTC 24
Finished Oct 09 01:58:49 PM UTC 24
Peak memory 211260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980729335 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_partial_a
ccess_b2b.1980729335
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/35.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.1340623268
Short name T665
Test name
Test status
Simulation time 676762456 ps
CPU time 5.04 seconds
Started Oct 09 01:54:35 PM UTC 24
Finished Oct 09 01:54:41 PM UTC 24
Peak memory 211220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340623268 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.1340623268
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/35.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_readback_err.2691508680
Short name T668
Test name
Test status
Simulation time 3295205535 ps
CPU time 11.33 seconds
Started Oct 09 01:54:53 PM UTC 24
Finished Oct 09 01:55:06 PM UTC 24
Peak memory 211348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691508680 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_readback_err.2691508680
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/35.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_regwen.2321340737
Short name T776
Test name
Test status
Simulation time 5556931235 ps
CPU time 912.09 seconds
Started Oct 09 01:54:27 PM UTC 24
Finished Oct 09 02:09:51 PM UTC 24
Peak memory 388416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321340737 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.2321340737
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/35.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_smoke.513261698
Short name T655
Test name
Test status
Simulation time 725186604 ps
CPU time 6.61 seconds
Started Oct 09 01:51:32 PM UTC 24
Finished Oct 09 01:51:40 PM UTC 24
Peak memory 210908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513261698 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.513261698
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/35.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all.1997724144
Short name T955
Test name
Test status
Simulation time 204049943887 ps
CPU time 2487.27 seconds
Started Oct 09 01:55:07 PM UTC 24
Finished Oct 09 02:37:00 PM UTC 24
Peak memory 393756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19977241
44 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_a
ll.1997724144
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/35.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.4279945535
Short name T674
Test name
Test status
Simulation time 3067681543 ps
CPU time 68.29 seconds
Started Oct 09 01:54:59 PM UTC 24
Finished Oct 09 01:56:09 PM UTC 24
Peak memory 221592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279945535 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.4279945535
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/35.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.1297238049
Short name T672
Test name
Test status
Simulation time 4044261121 ps
CPU time 252.87 seconds
Started Oct 09 01:51:41 PM UTC 24
Finished Oct 09 01:55:58 PM UTC 24
Peak memory 211208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297238049 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_pipeline.1297238049
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/35.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.1274088659
Short name T664
Test name
Test status
Simulation time 3308709306 ps
CPU time 107.75 seconds
Started Oct 09 01:52:44 PM UTC 24
Finished Oct 09 01:54:34 PM UTC 24
Peak memory 373884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1274088659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl
_throughput_w_partial_write.1274088659
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/35.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.3185902739
Short name T715
Test name
Test status
Simulation time 25194775958 ps
CPU time 275.15 seconds
Started Oct 09 01:57:21 PM UTC 24
Finished Oct 09 02:02:01 PM UTC 24
Peak memory 382080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185902739 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_access_duri
ng_key_req.3185902739
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/36.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_alert_test.1098620306
Short name T688
Test name
Test status
Simulation time 47762570 ps
CPU time 1.05 seconds
Started Oct 09 01:58:19 PM UTC 24
Finished Oct 09 01:58:21 PM UTC 24
Peak memory 209432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098620306
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_alert_test.1098620306
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/36.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_bijection.633598598
Short name T872
Test name
Test status
Simulation time 22628680499 ps
CPU time 1644.64 seconds
Started Oct 09 01:55:59 PM UTC 24
Finished Oct 09 02:23:43 PM UTC 24
Peak memory 211516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633598598 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection.633598598
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/36.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_executable.279666199
Short name T757
Test name
Test status
Simulation time 54028840807 ps
CPU time 579.36 seconds
Started Oct 09 01:57:22 PM UTC 24
Finished Oct 09 02:07:08 PM UTC 24
Peak memory 388216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279666199 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executable.279666199
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/36.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.244714218
Short name T692
Test name
Test status
Simulation time 42858724520 ps
CPU time 106.58 seconds
Started Oct 09 01:57:05 PM UTC 24
Finished Oct 09 01:58:54 PM UTC 24
Peak memory 225676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244714218 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_escalation.244714218
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/36.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.2048280931
Short name T677
Test name
Test status
Simulation time 9510503660 ps
CPU time 15.79 seconds
Started Oct 09 01:56:47 PM UTC 24
Finished Oct 09 01:57:04 PM UTC 24
Peak memory 221328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2048280931 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_
max_throughput.2048280931
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/36.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.26158387
Short name T697
Test name
Test status
Simulation time 12282321098 ps
CPU time 103.03 seconds
Started Oct 09 01:57:41 PM UTC 24
Finished Oct 09 01:59:26 PM UTC 24
Peak memory 221792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26158387 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_mem_partial_access.26158387
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/36.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.18732595
Short name T724
Test name
Test status
Simulation time 57617174326 ps
CPU time 325.23 seconds
Started Oct 09 01:57:37 PM UTC 24
Finished Oct 09 02:03:07 PM UTC 24
Peak memory 221616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18732595 -assert nopost
proc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_mem_walk.18732595
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/36.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.3271270758
Short name T691
Test name
Test status
Simulation time 4866281540 ps
CPU time 173.14 seconds
Started Oct 09 01:55:55 PM UTC 24
Finished Oct 09 01:58:51 PM UTC 24
Peak memory 388136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271270758 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multiple_keys.3271270758
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/36.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access.858819683
Short name T676
Test name
Test status
Simulation time 3449538843 ps
CPU time 34.19 seconds
Started Oct 09 01:56:11 PM UTC 24
Finished Oct 09 01:56:46 PM UTC 24
Peak memory 293948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858819683 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_partial_access.858819683
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/36.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.2072429904
Short name T716
Test name
Test status
Simulation time 10926340061 ps
CPU time 323.03 seconds
Started Oct 09 01:56:38 PM UTC 24
Finished Oct 09 02:02:06 PM UTC 24
Peak memory 211388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072429904 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_partial_a
ccess_b2b.2072429904
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/36.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.836752219
Short name T684
Test name
Test status
Simulation time 3367894407 ps
CPU time 6.03 seconds
Started Oct 09 01:57:37 PM UTC 24
Finished Oct 09 01:57:44 PM UTC 24
Peak memory 211296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836752219 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.836752219
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/36.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_readback_err.1767516129
Short name T685
Test name
Test status
Simulation time 2749713253 ps
CPU time 10.64 seconds
Started Oct 09 01:57:45 PM UTC 24
Finished Oct 09 01:57:57 PM UTC 24
Peak memory 211424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767516129 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_readback_err.1767516129
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/36.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_regwen.584949212
Short name T781
Test name
Test status
Simulation time 34336172072 ps
CPU time 763.28 seconds
Started Oct 09 01:57:24 PM UTC 24
Finished Oct 09 02:10:17 PM UTC 24
Peak memory 388148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584949212 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.584949212
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/36.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_smoke.1672830535
Short name T673
Test name
Test status
Simulation time 1271405352 ps
CPU time 23.26 seconds
Started Oct 09 01:55:43 PM UTC 24
Finished Oct 09 01:56:07 PM UTC 24
Peak memory 283564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672830535 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.1672830535
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/36.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all.2234875844
Short name T984
Test name
Test status
Simulation time 141992874020 ps
CPU time 4033.17 seconds
Started Oct 09 01:58:13 PM UTC 24
Finished Oct 09 03:06:11 PM UTC 24
Peak memory 389660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22348758
44 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_a
ll.2234875844
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/36.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.2106686869
Short name T686
Test name
Test status
Simulation time 267277355 ps
CPU time 12.3 seconds
Started Oct 09 01:57:58 PM UTC 24
Finished Oct 09 01:58:12 PM UTC 24
Peak memory 228672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106686869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.2106686869
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/36.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.1031219526
Short name T719
Test name
Test status
Simulation time 4910097071 ps
CPU time 358.7 seconds
Started Oct 09 01:56:09 PM UTC 24
Finished Oct 09 02:02:13 PM UTC 24
Peak memory 211332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031219526 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_pipeline.1031219526
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/36.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.812729837
Short name T680
Test name
Test status
Simulation time 2892169344 ps
CPU time 14.29 seconds
Started Oct 09 01:57:05 PM UTC 24
Finished Oct 09 01:57:21 PM UTC 24
Peak memory 250800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=812729837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_
throughput_w_partial_write.812729837
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/36.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.1769960372
Short name T798
Test name
Test status
Simulation time 9682716456 ps
CPU time 733.46 seconds
Started Oct 09 01:59:27 PM UTC 24
Finished Oct 09 02:11:49 PM UTC 24
Peak memory 388144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769960372 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_access_duri
ng_key_req.1769960372
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/37.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_alert_test.2758806602
Short name T707
Test name
Test status
Simulation time 15980493 ps
CPU time 0.94 seconds
Started Oct 09 02:00:27 PM UTC 24
Finished Oct 09 02:00:30 PM UTC 24
Peak memory 211332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758806602
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_alert_test.2758806602
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/37.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_bijection.1171391719
Short name T865
Test name
Test status
Simulation time 21593869093 ps
CPU time 1449.71 seconds
Started Oct 09 01:58:49 PM UTC 24
Finished Oct 09 02:23:16 PM UTC 24
Peak memory 211336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171391719 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection.1171391719
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/37.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_executable.83461853
Short name T791
Test name
Test status
Simulation time 44369603786 ps
CPU time 703.82 seconds
Started Oct 09 01:59:30 PM UTC 24
Finished Oct 09 02:11:23 PM UTC 24
Peak memory 379920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83461853 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executable.83461853
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/37.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.3338659762
Short name T709
Test name
Test status
Simulation time 9855638021 ps
CPU time 80.01 seconds
Started Oct 09 01:59:27 PM UTC 24
Finished Oct 09 02:00:49 PM UTC 24
Peak memory 211224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338659762 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_escalation.3338659762
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/37.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.3167772002
Short name T698
Test name
Test status
Simulation time 2684767743 ps
CPU time 9.54 seconds
Started Oct 09 01:59:19 PM UTC 24
Finished Oct 09 01:59:29 PM UTC 24
Peak memory 227548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3167772002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_
max_throughput.3167772002
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/37.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.293454986
Short name T712
Test name
Test status
Simulation time 5758308862 ps
CPU time 93.9 seconds
Started Oct 09 01:59:50 PM UTC 24
Finished Oct 09 02:01:26 PM UTC 24
Peak memory 228432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293454986 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_mem_partial_access.293454986
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/37.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.336822329
Short name T739
Test name
Test status
Simulation time 3988677334 ps
CPU time 288.69 seconds
Started Oct 09 01:59:48 PM UTC 24
Finished Oct 09 02:04:41 PM UTC 24
Peak memory 221516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336822329 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_mem_walk.336822329
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/37.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.2320106785
Short name T823
Test name
Test status
Simulation time 21972154056 ps
CPU time 1045.06 seconds
Started Oct 09 01:58:33 PM UTC 24
Finished Oct 09 02:16:10 PM UTC 24
Peak memory 388272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320106785 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multiple_keys.2320106785
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/37.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access.2968495385
Short name T699
Test name
Test status
Simulation time 737540316 ps
CPU time 43.2 seconds
Started Oct 09 01:58:56 PM UTC 24
Finished Oct 09 01:59:41 PM UTC 24
Peak memory 306080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968495385 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_partial_access.2968495385
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/37.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.1151542224
Short name T768
Test name
Test status
Simulation time 17720726869 ps
CPU time 576.48 seconds
Started Oct 09 01:58:56 PM UTC 24
Finished Oct 09 02:08:40 PM UTC 24
Peak memory 211500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151542224 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_partial_a
ccess_b2b.1151542224
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/37.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.1040080940
Short name T702
Test name
Test status
Simulation time 376909548 ps
CPU time 4.86 seconds
Started Oct 09 01:59:43 PM UTC 24
Finished Oct 09 01:59:49 PM UTC 24
Peak memory 211552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040080940 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.1040080940
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/37.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_readback_err.2945019264
Short name T704
Test name
Test status
Simulation time 2648203077 ps
CPU time 10.36 seconds
Started Oct 09 02:00:07 PM UTC 24
Finished Oct 09 02:00:19 PM UTC 24
Peak memory 211424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945019264 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_readback_err.2945019264
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/37.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_regwen.2046519518
Short name T854
Test name
Test status
Simulation time 15445534310 ps
CPU time 1286.08 seconds
Started Oct 09 01:59:41 PM UTC 24
Finished Oct 09 02:21:22 PM UTC 24
Peak memory 390280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046519518 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.2046519518
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/37.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_smoke.611984950
Short name T693
Test name
Test status
Simulation time 4930197901 ps
CPU time 31.69 seconds
Started Oct 09 01:58:22 PM UTC 24
Finished Oct 09 01:58:55 PM UTC 24
Peak memory 211596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611984950 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.611984950
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/37.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all.3177317364
Short name T909
Test name
Test status
Simulation time 30605072876 ps
CPU time 1553.75 seconds
Started Oct 09 02:00:26 PM UTC 24
Finished Oct 09 02:26:37 PM UTC 24
Peak memory 388368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31773173
64 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_a
ll.3177317364
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/37.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.471150718
Short name T706
Test name
Test status
Simulation time 1355064855 ps
CPU time 4.67 seconds
Started Oct 09 02:00:20 PM UTC 24
Finished Oct 09 02:00:26 PM UTC 24
Peak memory 221572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=471150718 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.471150718
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/37.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.1520854501
Short name T725
Test name
Test status
Simulation time 13181547500 ps
CPU time 263.22 seconds
Started Oct 09 01:58:52 PM UTC 24
Finished Oct 09 02:03:19 PM UTC 24
Peak memory 211536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520854501 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_pipeline.1520854501
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/37.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.3366686088
Short name T700
Test name
Test status
Simulation time 13338472097 ps
CPU time 17.05 seconds
Started Oct 09 01:59:24 PM UTC 24
Finished Oct 09 01:59:42 PM UTC 24
Peak memory 221596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3366686088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl
_throughput_w_partial_write.3366686088
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/37.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.1847990551
Short name T774
Test name
Test status
Simulation time 14764017894 ps
CPU time 451.29 seconds
Started Oct 09 02:02:07 PM UTC 24
Finished Oct 09 02:09:44 PM UTC 24
Peak memory 367704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847990551 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_access_duri
ng_key_req.1847990551
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/38.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_alert_test.931724001
Short name T728
Test name
Test status
Simulation time 57794452 ps
CPU time 1.06 seconds
Started Oct 09 02:03:20 PM UTC 24
Finished Oct 09 02:03:23 PM UTC 24
Peak memory 211332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931724001 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_alert_test.931724001
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/38.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_bijection.1362477968
Short name T976
Test name
Test status
Simulation time 749228612630 ps
CPU time 2918.46 seconds
Started Oct 09 02:00:50 PM UTC 24
Finished Oct 09 02:50:03 PM UTC 24
Peak memory 212908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362477968 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection.1362477968
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/38.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_executable.1596628130
Short name T814
Test name
Test status
Simulation time 18873465965 ps
CPU time 680.14 seconds
Started Oct 09 02:02:08 PM UTC 24
Finished Oct 09 02:13:36 PM UTC 24
Peak memory 388080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596628130 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executable.1596628130
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/38.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.3671808121
Short name T736
Test name
Test status
Simulation time 48656402629 ps
CPU time 122.39 seconds
Started Oct 09 02:02:02 PM UTC 24
Finished Oct 09 02:04:07 PM UTC 24
Peak memory 221680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671808121 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_escalation.3671808121
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/38.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.1688317337
Short name T717
Test name
Test status
Simulation time 1458681405 ps
CPU time 33.3 seconds
Started Oct 09 02:01:33 PM UTC 24
Finished Oct 09 02:02:08 PM UTC 24
Peak memory 287656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1688317337 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_
max_throughput.1688317337
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/38.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.1005615098
Short name T732
Test name
Test status
Simulation time 4605303435 ps
CPU time 90.1 seconds
Started Oct 09 02:02:20 PM UTC 24
Finished Oct 09 02:03:52 PM UTC 24
Peak memory 221616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005615098 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_mem_partial_access.1005615098
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/38.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.3060277097
Short name T765
Test name
Test status
Simulation time 20711667667 ps
CPU time 346.81 seconds
Started Oct 09 02:02:19 PM UTC 24
Finished Oct 09 02:08:10 PM UTC 24
Peak memory 221532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060277097 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_mem_walk.3060277097
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/38.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.1759111815
Short name T825
Test name
Test status
Simulation time 101476235935 ps
CPU time 935.55 seconds
Started Oct 09 02:00:43 PM UTC 24
Finished Oct 09 02:16:29 PM UTC 24
Peak memory 355412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759111815 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multiple_keys.1759111815
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/38.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access.2816919215
Short name T714
Test name
Test status
Simulation time 3212202586 ps
CPU time 57.51 seconds
Started Oct 09 02:01:01 PM UTC 24
Finished Oct 09 02:02:00 PM UTC 24
Peak memory 336824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816919215 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_partial_access.2816919215
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/38.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.1154541549
Short name T772
Test name
Test status
Simulation time 14948532104 ps
CPU time 454.61 seconds
Started Oct 09 02:01:26 PM UTC 24
Finished Oct 09 02:09:08 PM UTC 24
Peak memory 211536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154541549 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_partial_a
ccess_b2b.1154541549
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/38.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.161646897
Short name T720
Test name
Test status
Simulation time 374704467 ps
CPU time 3.51 seconds
Started Oct 09 02:02:13 PM UTC 24
Finished Oct 09 02:02:18 PM UTC 24
Peak memory 211296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161646897 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.161646897
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/38.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_readback_err.3360472894
Short name T723
Test name
Test status
Simulation time 665255602 ps
CPU time 8.31 seconds
Started Oct 09 02:02:32 PM UTC 24
Finished Oct 09 02:02:41 PM UTC 24
Peak memory 211540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360472894 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_readback_err.3360472894
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/38.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_regwen.1998514653
Short name T762
Test name
Test status
Simulation time 2191363615 ps
CPU time 332.83 seconds
Started Oct 09 02:02:09 PM UTC 24
Finished Oct 09 02:07:47 PM UTC 24
Peak memory 361524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998514653 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.1998514653
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/38.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_smoke.2174295342
Short name T708
Test name
Test status
Simulation time 708033764 ps
CPU time 10.23 seconds
Started Oct 09 02:00:31 PM UTC 24
Finished Oct 09 02:00:42 PM UTC 24
Peak memory 211216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174295342 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.2174295342
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/38.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all.4202718038
Short name T990
Test name
Test status
Simulation time 197678767652 ps
CPU time 7486.4 seconds
Started Oct 09 02:03:08 PM UTC 24
Finished Oct 09 04:09:20 PM UTC 24
Peak memory 389636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42027180
38 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_a
ll.4202718038
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/38.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.1890516616
Short name T731
Test name
Test status
Simulation time 4639304419 ps
CPU time 48.69 seconds
Started Oct 09 02:02:42 PM UTC 24
Finished Oct 09 02:03:32 PM UTC 24
Peak memory 221672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890516616 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.1890516616
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/38.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.684509306
Short name T747
Test name
Test status
Simulation time 5989914676 ps
CPU time 301.4 seconds
Started Oct 09 02:00:58 PM UTC 24
Finished Oct 09 02:06:04 PM UTC 24
Peak memory 211332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684509306 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_pipeline.684509306
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/38.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.997028789
Short name T722
Test name
Test status
Simulation time 2608606706 ps
CPU time 28.04 seconds
Started Oct 09 02:02:02 PM UTC 24
Finished Oct 09 02:02:31 PM UTC 24
Peak memory 298228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=997028789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_
throughput_w_partial_write.997028789
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/38.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.3992426185
Short name T870
Test name
Test status
Simulation time 15575694549 ps
CPU time 1156.59 seconds
Started Oct 09 02:04:02 PM UTC 24
Finished Oct 09 02:23:33 PM UTC 24
Peak memory 384040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992426185 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_access_duri
ng_key_req.3992426185
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/39.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_alert_test.1165699368
Short name T745
Test name
Test status
Simulation time 40996960 ps
CPU time 1.06 seconds
Started Oct 09 02:05:28 PM UTC 24
Finished Oct 09 02:05:30 PM UTC 24
Peak memory 211212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165699368
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_alert_test.1165699368
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/39.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_bijection.3748306087
Short name T855
Test name
Test status
Simulation time 153850403933 ps
CPU time 1067.42 seconds
Started Oct 09 02:03:24 PM UTC 24
Finished Oct 09 02:21:25 PM UTC 24
Peak memory 211360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748306087 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection.3748306087
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/39.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_executable.1504180187
Short name T889
Test name
Test status
Simulation time 46323357717 ps
CPU time 1224.72 seconds
Started Oct 09 02:04:08 PM UTC 24
Finished Oct 09 02:24:47 PM UTC 24
Peak memory 382072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504180187 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executable.1504180187
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/39.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.3516673829
Short name T750
Test name
Test status
Simulation time 14440249963 ps
CPU time 137.11 seconds
Started Oct 09 02:04:02 PM UTC 24
Finished Oct 09 02:06:21 PM UTC 24
Peak memory 211296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516673829 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_escalation.3516673829
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/39.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.1885750491
Short name T743
Test name
Test status
Simulation time 5113443604 ps
CPU time 83.26 seconds
Started Oct 09 02:03:52 PM UTC 24
Finished Oct 09 02:05:18 PM UTC 24
Peak memory 380024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1885750491 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_
max_throughput.1885750491
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/39.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.87725233
Short name T752
Test name
Test status
Simulation time 3077738826 ps
CPU time 107.77 seconds
Started Oct 09 02:04:48 PM UTC 24
Finished Oct 09 02:06:38 PM UTC 24
Peak memory 221468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87725233 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_mem_partial_access.87725233
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/39.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.3240536195
Short name T763
Test name
Test status
Simulation time 10952467198 ps
CPU time 183.14 seconds
Started Oct 09 02:04:43 PM UTC 24
Finished Oct 09 02:07:49 PM UTC 24
Peak memory 211292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240536195 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_mem_walk.3240536195
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/39.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.4209787047
Short name T826
Test name
Test status
Simulation time 19525955530 ps
CPU time 781.42 seconds
Started Oct 09 02:03:22 PM UTC 24
Finished Oct 09 02:16:33 PM UTC 24
Peak memory 388128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209787047 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multiple_keys.4209787047
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/39.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access.2669863107
Short name T735
Test name
Test status
Simulation time 5670468430 ps
CPU time 32.07 seconds
Started Oct 09 02:03:27 PM UTC 24
Finished Oct 09 02:04:01 PM UTC 24
Peak memory 211420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669863107 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_partial_access.2669863107
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/39.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.2269940190
Short name T803
Test name
Test status
Simulation time 84441671566 ps
CPU time 511.06 seconds
Started Oct 09 02:03:33 PM UTC 24
Finished Oct 09 02:12:11 PM UTC 24
Peak memory 211264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269940190 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_partial_a
ccess_b2b.2269940190
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/39.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.2968825605
Short name T740
Test name
Test status
Simulation time 2810950723 ps
CPU time 5.55 seconds
Started Oct 09 02:04:40 PM UTC 24
Finished Oct 09 02:04:47 PM UTC 24
Peak memory 211280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968825605 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.2968825605
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/39.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_readback_err.3407397848
Short name T742
Test name
Test status
Simulation time 3091100453 ps
CPU time 8.19 seconds
Started Oct 09 02:05:05 PM UTC 24
Finished Oct 09 02:05:14 PM UTC 24
Peak memory 211336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407397848 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_readback_err.3407397848
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/39.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_regwen.1207474420
Short name T753
Test name
Test status
Simulation time 14943142945 ps
CPU time 143.83 seconds
Started Oct 09 02:04:25 PM UTC 24
Finished Oct 09 02:06:52 PM UTC 24
Peak memory 332984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207474420 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.1207474420
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/39.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_smoke.1477304931
Short name T734
Test name
Test status
Simulation time 5531526901 ps
CPU time 37.33 seconds
Started Oct 09 02:03:22 PM UTC 24
Finished Oct 09 02:04:01 PM UTC 24
Peak memory 211428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477304931 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.1477304931
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/39.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all.1038200452
Short name T848
Test name
Test status
Simulation time 66338855568 ps
CPU time 897.27 seconds
Started Oct 09 02:05:18 PM UTC 24
Finished Oct 09 02:20:27 PM UTC 24
Peak memory 300048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10382004
52 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_a
ll.1038200452
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/39.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.1917866215
Short name T746
Test name
Test status
Simulation time 1680869455 ps
CPU time 39.44 seconds
Started Oct 09 02:05:15 PM UTC 24
Finished Oct 09 02:05:56 PM UTC 24
Peak memory 221624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917866215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.1917866215
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/39.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.2544911986
Short name T756
Test name
Test status
Simulation time 3062560601 ps
CPU time 213.85 seconds
Started Oct 09 02:03:26 PM UTC 24
Finished Oct 09 02:07:03 PM UTC 24
Peak memory 211236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544911986 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_pipeline.2544911986
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/39.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.1869132638
Short name T738
Test name
Test status
Simulation time 755115079 ps
CPU time 38.14 seconds
Started Oct 09 02:04:00 PM UTC 24
Finished Oct 09 02:04:39 PM UTC 24
Peak memory 289780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1869132638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl
_throughput_w_partial_write.1869132638
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/39.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_access_during_key_req.1151346067
Short name T39
Test name
Test status
Simulation time 4791380903 ps
CPU time 10.76 seconds
Started Oct 09 12:26:24 PM UTC 24
Finished Oct 09 12:26:36 PM UTC 24
Peak memory 224576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151346067 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_access_durin
g_key_req.1151346067
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_alert_test.1836251456
Short name T171
Test name
Test status
Simulation time 58477386 ps
CPU time 0.96 seconds
Started Oct 09 12:28:06 PM UTC 24
Finished Oct 09 12:28:08 PM UTC 24
Peak memory 209432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836251456
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_alert_test.1836251456
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_bijection.4003745428
Short name T194
Test name
Test status
Simulation time 48071350197 ps
CPU time 635.38 seconds
Started Oct 09 12:24:59 PM UTC 24
Finished Oct 09 12:35:43 PM UTC 24
Peak memory 211376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003745428 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection.4003745428
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_executable.915665676
Short name T156
Test name
Test status
Simulation time 55109585997 ps
CPU time 861.68 seconds
Started Oct 09 12:26:34 PM UTC 24
Finished Oct 09 12:41:06 PM UTC 24
Peak memory 388216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915665676 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executable.915665676
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_lc_escalation.3335863876
Short name T147
Test name
Test status
Simulation time 9769813172 ps
CPU time 23.18 seconds
Started Oct 09 12:26:19 PM UTC 24
Finished Oct 09 12:26:44 PM UTC 24
Peak memory 211364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335863876 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_escalation.3335863876
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_max_throughput.3786254585
Short name T166
Test name
Test status
Simulation time 1342018805 ps
CPU time 12.74 seconds
Started Oct 09 12:26:01 PM UTC 24
Finished Oct 09 12:26:15 PM UTC 24
Peak memory 221476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3786254585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_m
ax_throughput.3786254585
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_partial_access.3822974199
Short name T84
Test name
Test status
Simulation time 10156687343 ps
CPU time 108.69 seconds
Started Oct 09 12:27:17 PM UTC 24
Finished Oct 09 12:29:08 PM UTC 24
Peak memory 221636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822974199 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_mem_partial_access.3822974199
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_mem_walk.302342508
Short name T45
Test name
Test status
Simulation time 10440674728 ps
CPU time 172.37 seconds
Started Oct 09 12:26:50 PM UTC 24
Finished Oct 09 12:29:46 PM UTC 24
Peak memory 211624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302342508 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_mem_walk.302342508
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_multiple_keys.2837883117
Short name T192
Test name
Test status
Simulation time 20198579725 ps
CPU time 623.45 seconds
Started Oct 09 12:24:37 PM UTC 24
Finished Oct 09 12:35:08 PM UTC 24
Peak memory 382268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837883117 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multiple_keys.2837883117
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access.157623350
Short name T167
Test name
Test status
Simulation time 3346280135 ps
CPU time 56.95 seconds
Started Oct 09 12:25:19 PM UTC 24
Finished Oct 09 12:26:18 PM UTC 24
Peak memory 336920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157623350 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_partial_access.157623350
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_partial_access_b2b.2065114304
Short name T180
Test name
Test status
Simulation time 6763006718 ps
CPU time 447.41 seconds
Started Oct 09 12:25:41 PM UTC 24
Finished Oct 09 12:33:15 PM UTC 24
Peak memory 211380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065114304 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_partial_ac
cess_b2b.2065114304
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_ram_cfg.2156061733
Short name T168
Test name
Test status
Simulation time 347178361 ps
CPU time 3.54 seconds
Started Oct 09 12:26:45 PM UTC 24
Finished Oct 09 12:26:50 PM UTC 24
Peak memory 211484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156061733 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.2156061733
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_readback_err.3948427321
Short name T170
Test name
Test status
Simulation time 676211132 ps
CPU time 11.39 seconds
Started Oct 09 12:27:21 PM UTC 24
Finished Oct 09 12:27:34 PM UTC 24
Peak memory 211288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948427321 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_readback_err.3948427321
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_regwen.1014979454
Short name T148
Test name
Test status
Simulation time 2891553308 ps
CPU time 437.73 seconds
Started Oct 09 12:26:37 PM UTC 24
Finished Oct 09 12:34:00 PM UTC 24
Peak memory 386056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014979454 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.1014979454
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_sec_cm.1284224795
Short name T7
Test name
Test status
Simulation time 2567318362 ps
CPU time 5.2 seconds
Started Oct 09 12:27:58 PM UTC 24
Finished Oct 09 12:28:05 PM UTC 24
Peak memory 247812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284224795 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_sec_cm.1284224795
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_smoke.2988926859
Short name T163
Test name
Test status
Simulation time 859939052 ps
CPU time 20.76 seconds
Started Oct 09 12:24:36 PM UTC 24
Finished Oct 09 12:24:58 PM UTC 24
Peak memory 250872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988926859 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.2988926859
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all.1205324265
Short name T21
Test name
Test status
Simulation time 15492939533 ps
CPU time 345.11 seconds
Started Oct 09 12:27:49 PM UTC 24
Finished Oct 09 12:33:39 PM UTC 24
Peak memory 359476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12053242
65 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all.1205324265
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.4175815263
Short name T53
Test name
Test status
Simulation time 3474828473 ps
CPU time 32.4 seconds
Started Oct 09 12:27:35 PM UTC 24
Finished Oct 09 12:28:10 PM UTC 24
Peak memory 223640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175815263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.4175815263
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_pipeline.3951949373
Short name T111
Test name
Test status
Simulation time 16560209151 ps
CPU time 359.68 seconds
Started Oct 09 12:25:16 PM UTC 24
Finished Oct 09 12:31:21 PM UTC 24
Peak memory 211320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951949373 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_pipeline.3951949373
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_throughput_w_partial_write.4249650996
Short name T169
Test name
Test status
Simulation time 3226439813 ps
CPU time 58.39 seconds
Started Oct 09 12:26:17 PM UTC 24
Finished Oct 09 12:27:17 PM UTC 24
Peak memory 371824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=4249650996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_
throughput_w_partial_write.4249650996
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/4.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.1019039527
Short name T961
Test name
Test status
Simulation time 98066821015 ps
CPU time 1865.1 seconds
Started Oct 09 02:06:59 PM UTC 24
Finished Oct 09 02:38:28 PM UTC 24
Peak memory 389652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019039527 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_access_duri
ng_key_req.1019039527
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/40.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_alert_test.3872193919
Short name T764
Test name
Test status
Simulation time 13084011 ps
CPU time 0.95 seconds
Started Oct 09 02:07:50 PM UTC 24
Finished Oct 09 02:07:52 PM UTC 24
Peak memory 211212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872193919
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_alert_test.3872193919
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/40.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_bijection.657883982
Short name T980
Test name
Test status
Simulation time 112698257278 ps
CPU time 3027.71 seconds
Started Oct 09 02:06:05 PM UTC 24
Finished Oct 09 02:57:10 PM UTC 24
Peak memory 212884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657883982 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection.657883982
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/40.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_executable.638113460
Short name T868
Test name
Test status
Simulation time 43081335548 ps
CPU time 978.98 seconds
Started Oct 09 02:06:59 PM UTC 24
Finished Oct 09 02:23:29 PM UTC 24
Peak memory 371760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638113460 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executable.638113460
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/40.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.3678679007
Short name T779
Test name
Test status
Simulation time 41506859732 ps
CPU time 180.29 seconds
Started Oct 09 02:06:54 PM UTC 24
Finished Oct 09 02:09:57 PM UTC 24
Peak memory 221512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678679007 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_escalation.3678679007
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/40.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.3804896859
Short name T760
Test name
Test status
Simulation time 775341749 ps
CPU time 53.75 seconds
Started Oct 09 02:06:38 PM UTC 24
Finished Oct 09 02:07:33 PM UTC 24
Peak memory 338928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3804896859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_
max_throughput.3804896859
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/40.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.267676206
Short name T782
Test name
Test status
Simulation time 9752597360 ps
CPU time 179.63 seconds
Started Oct 09 02:07:23 PM UTC 24
Finished Oct 09 02:10:26 PM UTC 24
Peak memory 221872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267676206 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_mem_partial_access.267676206
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/40.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.2834261817
Short name T806
Test name
Test status
Simulation time 10506357607 ps
CPU time 300.58 seconds
Started Oct 09 02:07:18 PM UTC 24
Finished Oct 09 02:12:23 PM UTC 24
Peak memory 221816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834261817 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_mem_walk.2834261817
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/40.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.1056358002
Short name T771
Test name
Test status
Simulation time 2203144750 ps
CPU time 184.69 seconds
Started Oct 09 02:05:57 PM UTC 24
Finished Oct 09 02:09:05 PM UTC 24
Peak memory 377832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056358002 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multiple_keys.1056358002
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/40.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access.2355323237
Short name T751
Test name
Test status
Simulation time 4863027223 ps
CPU time 25.86 seconds
Started Oct 09 02:06:09 PM UTC 24
Finished Oct 09 02:06:37 PM UTC 24
Peak memory 211456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355323237 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_partial_access.2355323237
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/40.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.756910418
Short name T790
Test name
Test status
Simulation time 40502329217 ps
CPU time 285.09 seconds
Started Oct 09 02:06:23 PM UTC 24
Finished Oct 09 02:11:12 PM UTC 24
Peak memory 211476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756910418 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_partial_ac
cess_b2b.756910418
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/40.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.2673528667
Short name T758
Test name
Test status
Simulation time 1210818414 ps
CPU time 5.88 seconds
Started Oct 09 02:07:10 PM UTC 24
Finished Oct 09 02:07:17 PM UTC 24
Peak memory 211488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673528667 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.2673528667
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/40.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_readback_err.87684620
Short name T761
Test name
Test status
Simulation time 2649832211 ps
CPU time 8.21 seconds
Started Oct 09 02:07:35 PM UTC 24
Finished Oct 09 02:07:44 PM UTC 24
Peak memory 211416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87684620 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_readback_err.87684620
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/40.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_regwen.2744287405
Short name T822
Test name
Test status
Simulation time 10898067101 ps
CPU time 524.73 seconds
Started Oct 09 02:07:04 PM UTC 24
Finished Oct 09 02:15:55 PM UTC 24
Peak memory 388212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744287405 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.2744287405
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/40.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_smoke.1695233650
Short name T759
Test name
Test status
Simulation time 3456518494 ps
CPU time 108 seconds
Started Oct 09 02:05:32 PM UTC 24
Finished Oct 09 02:07:22 PM UTC 24
Peak memory 377976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695233650 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.1695233650
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/40.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all.1124685772
Short name T945
Test name
Test status
Simulation time 44603960146 ps
CPU time 1554.24 seconds
Started Oct 09 02:07:48 PM UTC 24
Finished Oct 09 02:34:00 PM UTC 24
Peak memory 392388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11246857
72 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_a
ll.1124685772
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/40.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.79520722
Short name T788
Test name
Test status
Simulation time 1206144850 ps
CPU time 190.46 seconds
Started Oct 09 02:07:46 PM UTC 24
Finished Oct 09 02:11:00 PM UTC 24
Peak memory 386156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79520722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.79520722
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/40.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.113878496
Short name T792
Test name
Test status
Simulation time 19105730778 ps
CPU time 313.71 seconds
Started Oct 09 02:06:05 PM UTC 24
Finished Oct 09 02:11:24 PM UTC 24
Peak memory 211308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113878496 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_pipeline.113878496
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/40.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.3868898655
Short name T769
Test name
Test status
Simulation time 802976000 ps
CPU time 124.69 seconds
Started Oct 09 02:06:39 PM UTC 24
Finished Oct 09 02:08:46 PM UTC 24
Peak memory 379896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3868898655 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl
_throughput_w_partial_write.3868898655
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/40.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.3459856486
Short name T960
Test name
Test status
Simulation time 21810651505 ps
CPU time 1713.51 seconds
Started Oct 09 02:09:32 PM UTC 24
Finished Oct 09 02:38:25 PM UTC 24
Peak memory 386328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459856486 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_access_duri
ng_key_req.3459856486
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/41.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_alert_test.2257307969
Short name T783
Test name
Test status
Simulation time 14521361 ps
CPU time 1.05 seconds
Started Oct 09 02:10:28 PM UTC 24
Finished Oct 09 02:10:31 PM UTC 24
Peak memory 209424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257307969
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_alert_test.2257307969
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/41.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_bijection.1665411784
Short name T982
Test name
Test status
Simulation time 169011613885 ps
CPU time 3278.87 seconds
Started Oct 09 02:08:24 PM UTC 24
Finished Oct 09 03:03:42 PM UTC 24
Peak memory 212872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665411784 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection.1665411784
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/41.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_executable.1599021954
Short name T845
Test name
Test status
Simulation time 30454266700 ps
CPU time 566.81 seconds
Started Oct 09 02:09:45 PM UTC 24
Finished Oct 09 02:19:19 PM UTC 24
Peak memory 377960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599021954 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executable.1599021954
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/41.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.1450432100
Short name T785
Test name
Test status
Simulation time 12674757310 ps
CPU time 85.65 seconds
Started Oct 09 02:09:09 PM UTC 24
Finished Oct 09 02:10:37 PM UTC 24
Peak memory 211508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450432100 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_escalation.1450432100
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/41.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.2138106018
Short name T777
Test name
Test status
Simulation time 2972396627 ps
CPU time 47.64 seconds
Started Oct 09 02:09:04 PM UTC 24
Finished Oct 09 02:09:54 PM UTC 24
Peak memory 341052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2138106018 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_
max_throughput.2138106018
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/41.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.22161991
Short name T795
Test name
Test status
Simulation time 2015665368 ps
CPU time 93.54 seconds
Started Oct 09 02:09:58 PM UTC 24
Finished Oct 09 02:11:34 PM UTC 24
Peak memory 221508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22161991 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_mem_partial_access.22161991
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/41.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.842142590
Short name T812
Test name
Test status
Simulation time 10789767841 ps
CPU time 212.81 seconds
Started Oct 09 02:09:54 PM UTC 24
Finished Oct 09 02:13:31 PM UTC 24
Peak memory 221852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842142590 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_mem_walk.842142590
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/41.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.2567050048
Short name T953
Test name
Test status
Simulation time 26154892882 ps
CPU time 1683.2 seconds
Started Oct 09 02:08:11 PM UTC 24
Finished Oct 09 02:36:32 PM UTC 24
Peak memory 389776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567050048 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multiple_keys.2567050048
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/41.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access.3401807274
Short name T770
Test name
Test status
Simulation time 1000838548 ps
CPU time 20.68 seconds
Started Oct 09 02:08:41 PM UTC 24
Finished Oct 09 02:09:03 PM UTC 24
Peak memory 211092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401807274 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_partial_access.3401807274
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/41.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.2030048996
Short name T829
Test name
Test status
Simulation time 180454279655 ps
CPU time 508.75 seconds
Started Oct 09 02:08:47 PM UTC 24
Finished Oct 09 02:17:23 PM UTC 24
Peak memory 211392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030048996 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_partial_a
ccess_b2b.2030048996
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/41.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.1340456810
Short name T778
Test name
Test status
Simulation time 738126275 ps
CPU time 3.71 seconds
Started Oct 09 02:09:52 PM UTC 24
Finished Oct 09 02:09:57 PM UTC 24
Peak memory 211292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340456810 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.1340456810
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/41.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_readback_err.3405957729
Short name T780
Test name
Test status
Simulation time 691019297 ps
CPU time 10.71 seconds
Started Oct 09 02:09:58 PM UTC 24
Finished Oct 09 02:10:10 PM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405957729 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_readback_err.3405957729
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/41.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_regwen.3379375041
Short name T915
Test name
Test status
Simulation time 13350019411 ps
CPU time 1038.79 seconds
Started Oct 09 02:09:48 PM UTC 24
Finished Oct 09 02:27:18 PM UTC 24
Peak memory 384048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379375041 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.3379375041
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/41.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_smoke.398905608
Short name T766
Test name
Test status
Simulation time 7320797712 ps
CPU time 28.74 seconds
Started Oct 09 02:07:53 PM UTC 24
Finished Oct 09 02:08:23 PM UTC 24
Peak memory 211200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398905608 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.398905608
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/41.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all.3330091172
Short name T988
Test name
Test status
Simulation time 113027153232 ps
CPU time 4783.13 seconds
Started Oct 09 02:10:19 PM UTC 24
Finished Oct 09 03:30:53 PM UTC 24
Peak memory 393716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33300911
72 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_a
ll.3330091172
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/41.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.220430754
Short name T796
Test name
Test status
Simulation time 7805702677 ps
CPU time 82.98 seconds
Started Oct 09 02:10:11 PM UTC 24
Finished Oct 09 02:11:36 PM UTC 24
Peak memory 230476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220430754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.220430754
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/41.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.2786018045
Short name T805
Test name
Test status
Simulation time 4121636527 ps
CPU time 222.26 seconds
Started Oct 09 02:08:30 PM UTC 24
Finished Oct 09 02:12:15 PM UTC 24
Peak memory 211380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786018045 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_pipeline.2786018045
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/41.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.4098151837
Short name T786
Test name
Test status
Simulation time 13054082482 ps
CPU time 104.8 seconds
Started Oct 09 02:09:06 PM UTC 24
Finished Oct 09 02:10:53 PM UTC 24
Peak memory 380024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=4098151837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl
_throughput_w_partial_write.4098151837
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/41.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.1681823671
Short name T863
Test name
Test status
Simulation time 22625975651 ps
CPU time 689.81 seconds
Started Oct 09 02:11:25 PM UTC 24
Finished Oct 09 02:23:03 PM UTC 24
Peak memory 379968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681823671 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_access_duri
ng_key_req.1681823671
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/42.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_alert_test.1835164265
Short name T802
Test name
Test status
Simulation time 11777949 ps
CPU time 0.99 seconds
Started Oct 09 02:12:04 PM UTC 24
Finished Oct 09 02:12:06 PM UTC 24
Peak memory 209424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835164265
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_alert_test.1835164265
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/42.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_bijection.2821985376
Short name T897
Test name
Test status
Simulation time 22574132206 ps
CPU time 874.08 seconds
Started Oct 09 02:10:38 PM UTC 24
Finished Oct 09 02:25:23 PM UTC 24
Peak memory 211472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821985376 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection.2821985376
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/42.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_executable.2993506959
Short name T809
Test name
Test status
Simulation time 2234439647 ps
CPU time 77.24 seconds
Started Oct 09 02:11:31 PM UTC 24
Finished Oct 09 02:12:50 PM UTC 24
Peak memory 345132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993506959 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executable.2993506959
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/42.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.1732126763
Short name T801
Test name
Test status
Simulation time 3569033251 ps
CPU time 35.79 seconds
Started Oct 09 02:11:25 PM UTC 24
Finished Oct 09 02:12:02 PM UTC 24
Peak memory 211452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732126763 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_escalation.1732126763
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/42.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.72736007
Short name T808
Test name
Test status
Simulation time 3061357124 ps
CPU time 88.76 seconds
Started Oct 09 02:11:12 PM UTC 24
Finished Oct 09 02:12:43 PM UTC 24
Peak memory 379896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
72736007 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ma
x_throughput.72736007
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/42.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.756726612
Short name T819
Test name
Test status
Simulation time 15259473599 ps
CPU time 209.28 seconds
Started Oct 09 02:11:41 PM UTC 24
Finished Oct 09 02:15:14 PM UTC 24
Peak memory 221564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756726612 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_mem_partial_access.756726612
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/42.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.1826301210
Short name T828
Test name
Test status
Simulation time 28206426816 ps
CPU time 327.5 seconds
Started Oct 09 02:11:37 PM UTC 24
Finished Oct 09 02:17:10 PM UTC 24
Peak memory 211396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826301210 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_mem_walk.1826301210
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/42.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.3612598883
Short name T880
Test name
Test status
Simulation time 26699350373 ps
CPU time 816.37 seconds
Started Oct 09 02:10:35 PM UTC 24
Finished Oct 09 02:24:20 PM UTC 24
Peak memory 384008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612598883 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multiple_keys.3612598883
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/42.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access.2694724107
Short name T799
Test name
Test status
Simulation time 959008581 ps
CPU time 54.11 seconds
Started Oct 09 02:10:56 PM UTC 24
Finished Oct 09 02:11:51 PM UTC 24
Peak memory 322464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694724107 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_partial_access.2694724107
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/42.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.3806750539
Short name T847
Test name
Test status
Simulation time 271934267665 ps
CPU time 543.79 seconds
Started Oct 09 02:11:01 PM UTC 24
Finished Oct 09 02:20:12 PM UTC 24
Peak memory 211392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806750539 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_partial_a
ccess_b2b.3806750539
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/42.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.3223745577
Short name T797
Test name
Test status
Simulation time 1690878857 ps
CPU time 4.95 seconds
Started Oct 09 02:11:34 PM UTC 24
Finished Oct 09 02:11:40 PM UTC 24
Peak memory 211288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223745577 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.3223745577
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/42.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_readback_err.3209782482
Short name T800
Test name
Test status
Simulation time 707509783 ps
CPU time 10.91 seconds
Started Oct 09 02:11:50 PM UTC 24
Finished Oct 09 02:12:02 PM UTC 24
Peak memory 211272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209782482 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_readback_err.3209782482
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/42.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_regwen.4291718489
Short name T879
Test name
Test status
Simulation time 39744433230 ps
CPU time 749.88 seconds
Started Oct 09 02:11:33 PM UTC 24
Finished Oct 09 02:24:13 PM UTC 24
Peak memory 386424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291718489 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.4291718489
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/42.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_smoke.1403482362
Short name T789
Test name
Test status
Simulation time 1408727036 ps
CPU time 36.24 seconds
Started Oct 09 02:10:33 PM UTC 24
Finished Oct 09 02:11:11 PM UTC 24
Peak memory 211212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403482362 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.1403482362
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/42.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all.156226079
Short name T983
Test name
Test status
Simulation time 32740364244 ps
CPU time 3102.28 seconds
Started Oct 09 02:12:04 PM UTC 24
Finished Oct 09 03:04:17 PM UTC 24
Peak memory 391768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15622607
9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all.156226079
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/42.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.4092870082
Short name T804
Test name
Test status
Simulation time 1771069193 ps
CPU time 17.93 seconds
Started Oct 09 02:11:52 PM UTC 24
Finished Oct 09 02:12:11 PM UTC 24
Peak memory 221816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092870082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.4092870082
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/42.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.2519306418
Short name T816
Test name
Test status
Simulation time 3659701875 ps
CPU time 215.35 seconds
Started Oct 09 02:10:53 PM UTC 24
Finished Oct 09 02:14:32 PM UTC 24
Peak memory 211240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519306418 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_pipeline.2519306418
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/42.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.1621302430
Short name T794
Test name
Test status
Simulation time 1431822184 ps
CPU time 16.19 seconds
Started Oct 09 02:11:14 PM UTC 24
Finished Oct 09 02:11:31 PM UTC 24
Peak memory 238512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1621302430 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl
_throughput_w_partial_write.1621302430
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/42.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.1000771346
Short name T933
Test name
Test status
Simulation time 33462857367 ps
CPU time 1004.94 seconds
Started Oct 09 02:13:01 PM UTC 24
Finished Oct 09 02:29:57 PM UTC 24
Peak memory 388148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000771346 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_access_duri
ng_key_req.1000771346
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/43.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_alert_test.550663054
Short name T821
Test name
Test status
Simulation time 35005897 ps
CPU time 0.93 seconds
Started Oct 09 02:15:40 PM UTC 24
Finished Oct 09 02:15:43 PM UTC 24
Peak memory 209424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550663054 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_alert_test.550663054
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/43.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_bijection.2325978776
Short name T981
Test name
Test status
Simulation time 634362418474 ps
CPU time 2994.71 seconds
Started Oct 09 02:12:12 PM UTC 24
Finished Oct 09 03:02:43 PM UTC 24
Peak memory 212868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325978776 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection.2325978776
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/43.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_executable.1413053780
Short name T919
Test name
Test status
Simulation time 26455548499 ps
CPU time 856.42 seconds
Started Oct 09 02:13:32 PM UTC 24
Finished Oct 09 02:27:59 PM UTC 24
Peak memory 388400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413053780 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executable.1413053780
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/43.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.390652218
Short name T817
Test name
Test status
Simulation time 26347422868 ps
CPU time 114.58 seconds
Started Oct 09 02:12:57 PM UTC 24
Finished Oct 09 02:14:54 PM UTC 24
Peak memory 225884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390652218 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_escalation.390652218
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/43.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.21041106
Short name T813
Test name
Test status
Simulation time 764157095 ps
CPU time 46.12 seconds
Started Oct 09 02:12:44 PM UTC 24
Finished Oct 09 02:13:32 PM UTC 24
Peak memory 300016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
21041106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ma
x_throughput.21041106
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/43.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.545929615
Short name T89
Test name
Test status
Simulation time 10922923678 ps
CPU time 123.03 seconds
Started Oct 09 02:14:33 PM UTC 24
Finished Oct 09 02:16:38 PM UTC 24
Peak memory 228488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545929615 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_mem_partial_access.545929615
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/43.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.3042602366
Short name T831
Test name
Test status
Simulation time 10358174337 ps
CPU time 238 seconds
Started Oct 09 02:13:45 PM UTC 24
Finished Oct 09 02:17:47 PM UTC 24
Peak memory 221604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042602366 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_mem_walk.3042602366
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/43.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.1189456745
Short name T969
Test name
Test status
Simulation time 30632472276 ps
CPU time 1958.05 seconds
Started Oct 09 02:12:12 PM UTC 24
Finished Oct 09 02:45:12 PM UTC 24
Peak memory 388564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189456745 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multiple_keys.1189456745
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/43.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access.683666181
Short name T810
Test name
Test status
Simulation time 1330929467 ps
CPU time 28.86 seconds
Started Oct 09 02:12:25 PM UTC 24
Finished Oct 09 02:12:56 PM UTC 24
Peak memory 211140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683666181 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_partial_access.683666181
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/43.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.3173116738
Short name T838
Test name
Test status
Simulation time 4867501561 ps
CPU time 358.29 seconds
Started Oct 09 02:12:25 PM UTC 24
Finished Oct 09 02:18:29 PM UTC 24
Peak memory 211416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173116738 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_partial_a
ccess_b2b.3173116738
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/43.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.1966118642
Short name T815
Test name
Test status
Simulation time 1404977973 ps
CPU time 5.95 seconds
Started Oct 09 02:13:37 PM UTC 24
Finished Oct 09 02:13:44 PM UTC 24
Peak memory 211356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966118642 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.1966118642
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/43.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_readback_err.2424740751
Short name T818
Test name
Test status
Simulation time 697576937 ps
CPU time 11.16 seconds
Started Oct 09 02:14:55 PM UTC 24
Finished Oct 09 02:15:08 PM UTC 24
Peak memory 211352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424740751 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_readback_err.2424740751
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/43.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_regwen.2188381488
Short name T904
Test name
Test status
Simulation time 7984405920 ps
CPU time 732.49 seconds
Started Oct 09 02:13:34 PM UTC 24
Finished Oct 09 02:25:55 PM UTC 24
Peak memory 388380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188381488 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.2188381488
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/43.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_smoke.1779714247
Short name T807
Test name
Test status
Simulation time 507054010 ps
CPU time 15.87 seconds
Started Oct 09 02:12:07 PM UTC 24
Finished Oct 09 02:12:24 PM UTC 24
Peak memory 211108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779714247 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.1779714247
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/43.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all.660291439
Short name T973
Test name
Test status
Simulation time 16371274705 ps
CPU time 1929.12 seconds
Started Oct 09 02:15:15 PM UTC 24
Finished Oct 09 02:47:47 PM UTC 24
Peak memory 373972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66029143
9 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all.660291439
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/43.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.459642097
Short name T836
Test name
Test status
Simulation time 19616146446 ps
CPU time 358.45 seconds
Started Oct 09 02:12:17 PM UTC 24
Finished Oct 09 02:18:20 PM UTC 24
Peak memory 211340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459642097 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_pipeline.459642097
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/43.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.2346447156
Short name T811
Test name
Test status
Simulation time 1408284106 ps
CPU time 7.34 seconds
Started Oct 09 02:12:52 PM UTC 24
Finished Oct 09 02:13:00 PM UTC 24
Peak memory 227768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2346447156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl
_throughput_w_partial_write.2346447156
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/43.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.4276216722
Short name T861
Test name
Test status
Simulation time 6792182087 ps
CPU time 330.27 seconds
Started Oct 09 02:17:11 PM UTC 24
Finished Oct 09 02:22:46 PM UTC 24
Peak memory 367660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276216722 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_access_duri
ng_key_req.4276216722
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/44.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_alert_test.275633400
Short name T839
Test name
Test status
Simulation time 42057040 ps
CPU time 0.99 seconds
Started Oct 09 02:18:27 PM UTC 24
Finished Oct 09 02:18:30 PM UTC 24
Peak memory 209424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275633400 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_alert_test.275633400
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/44.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_bijection.4104175655
Short name T910
Test name
Test status
Simulation time 30380736375 ps
CPU time 620.65 seconds
Started Oct 09 02:16:11 PM UTC 24
Finished Oct 09 02:26:40 PM UTC 24
Peak memory 211312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104175655 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection.4104175655
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/44.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_executable.807486102
Short name T936
Test name
Test status
Simulation time 16408952017 ps
CPU time 785.03 seconds
Started Oct 09 02:17:24 PM UTC 24
Finished Oct 09 02:30:38 PM UTC 24
Peak memory 386164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807486102 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executable.807486102
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/44.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.3303669103
Short name T840
Test name
Test status
Simulation time 8724481784 ps
CPU time 92.35 seconds
Started Oct 09 02:17:09 PM UTC 24
Finished Oct 09 02:18:43 PM UTC 24
Peak memory 225708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303669103 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_escalation.3303669103
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/44.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.2152922696
Short name T834
Test name
Test status
Simulation time 1549376739 ps
CPU time 95.97 seconds
Started Oct 09 02:16:37 PM UTC 24
Finished Oct 09 02:18:15 PM UTC 24
Peak memory 369648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2152922696 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_
max_throughput.2152922696
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/44.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.668250506
Short name T851
Test name
Test status
Simulation time 7541803179 ps
CPU time 167.91 seconds
Started Oct 09 02:18:10 PM UTC 24
Finished Oct 09 02:21:01 PM UTC 24
Peak memory 228492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668250506 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_mem_partial_access.668250506
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/44.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.720858282
Short name T873
Test name
Test status
Simulation time 86210445611 ps
CPU time 344.4 seconds
Started Oct 09 02:17:55 PM UTC 24
Finished Oct 09 02:23:44 PM UTC 24
Peak memory 211348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720858282 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_mem_walk.720858282
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/44.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.3603611355
Short name T941
Test name
Test status
Simulation time 8362207909 ps
CPU time 923.05 seconds
Started Oct 09 02:15:57 PM UTC 24
Finished Oct 09 02:31:30 PM UTC 24
Peak memory 386092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603611355 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multiple_keys.3603611355
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/44.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access.2456854970
Short name T827
Test name
Test status
Simulation time 1535579090 ps
CPU time 35.5 seconds
Started Oct 09 02:16:31 PM UTC 24
Finished Oct 09 02:17:08 PM UTC 24
Peak memory 211132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456854970 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_partial_access.2456854970
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/44.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.3006336381
Short name T860
Test name
Test status
Simulation time 4109494267 ps
CPU time 353.39 seconds
Started Oct 09 02:16:34 PM UTC 24
Finished Oct 09 02:22:32 PM UTC 24
Peak memory 211260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006336381 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_partial_a
ccess_b2b.3006336381
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/44.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.563190585
Short name T832
Test name
Test status
Simulation time 1471264838 ps
CPU time 4.7 seconds
Started Oct 09 02:17:49 PM UTC 24
Finished Oct 09 02:17:54 PM UTC 24
Peak memory 211292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563190585 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.563190585
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/44.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_readback_err.1230108558
Short name T837
Test name
Test status
Simulation time 1274538399 ps
CPU time 9.12 seconds
Started Oct 09 02:18:16 PM UTC 24
Finished Oct 09 02:18:27 PM UTC 24
Peak memory 211280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230108558 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_readback_err.1230108558
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/44.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_regwen.921093964
Short name T892
Test name
Test status
Simulation time 28090711627 ps
CPU time 438.22 seconds
Started Oct 09 02:17:33 PM UTC 24
Finished Oct 09 02:24:57 PM UTC 24
Peak memory 378236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921093964 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.921093964
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/44.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_smoke.3701548113
Short name T824
Test name
Test status
Simulation time 1011070807 ps
CPU time 37.45 seconds
Started Oct 09 02:15:43 PM UTC 24
Finished Oct 09 02:16:22 PM UTC 24
Peak memory 294140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701548113 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.3701548113
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/44.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all.1859053481
Short name T992
Test name
Test status
Simulation time 1460109771913 ps
CPU time 6878.46 seconds
Started Oct 09 02:18:21 PM UTC 24
Finished Oct 09 04:14:20 PM UTC 24
Peak memory 389644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18590534
81 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_a
ll.1859053481
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/44.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1772613022
Short name T145
Test name
Test status
Simulation time 5522818564 ps
CPU time 123.69 seconds
Started Oct 09 02:18:18 PM UTC 24
Finished Oct 09 02:20:24 PM UTC 24
Peak memory 378008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772613022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.1772613022
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/44.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.1101215908
Short name T843
Test name
Test status
Simulation time 2106558118 ps
CPU time 147.64 seconds
Started Oct 09 02:16:23 PM UTC 24
Finished Oct 09 02:18:54 PM UTC 24
Peak memory 211196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101215908 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_pipeline.1101215908
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/44.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.2018419211
Short name T830
Test name
Test status
Simulation time 14707966303 ps
CPU time 51.58 seconds
Started Oct 09 02:16:39 PM UTC 24
Finished Oct 09 02:17:33 PM UTC 24
Peak memory 310392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2018419211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl
_throughput_w_partial_write.2018419211
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/44.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.931561910
Short name T930
Test name
Test status
Simulation time 52635301223 ps
CPU time 577.77 seconds
Started Oct 09 02:20:04 PM UTC 24
Finished Oct 09 02:29:49 PM UTC 24
Peak memory 367616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931561910 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_access_durin
g_key_req.931561910
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/45.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_alert_test.674624412
Short name T856
Test name
Test status
Simulation time 77204777 ps
CPU time 1.14 seconds
Started Oct 09 02:21:24 PM UTC 24
Finished Oct 09 02:21:26 PM UTC 24
Peak memory 211332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674624412 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_alert_test.674624412
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/45.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_bijection.953387634
Short name T944
Test name
Test status
Simulation time 300584863829 ps
CPU time 863.44 seconds
Started Oct 09 02:18:44 PM UTC 24
Finished Oct 09 02:33:18 PM UTC 24
Peak memory 211372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953387634 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection.953387634
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/45.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_executable.114040590
Short name T882
Test name
Test status
Simulation time 16361505256 ps
CPU time 1006.07 seconds
Started Oct 09 02:20:14 PM UTC 24
Finished Oct 09 02:37:12 PM UTC 24
Peak memory 386164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114040590 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executable.114040590
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/45.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.2999667168
Short name T850
Test name
Test status
Simulation time 8134092339 ps
CPU time 73.57 seconds
Started Oct 09 02:19:27 PM UTC 24
Finished Oct 09 02:20:42 PM UTC 24
Peak memory 211216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999667168 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_escalation.2999667168
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/45.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.3221827465
Short name T846
Test name
Test status
Simulation time 2880073682 ps
CPU time 45.8 seconds
Started Oct 09 02:19:16 PM UTC 24
Finished Oct 09 02:20:03 PM UTC 24
Peak memory 297956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3221827465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_
max_throughput.3221827465
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/45.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.1993157260
Short name T871
Test name
Test status
Simulation time 6101013093 ps
CPU time 168.48 seconds
Started Oct 09 02:20:44 PM UTC 24
Finished Oct 09 02:23:35 PM UTC 24
Peak memory 221644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993157260 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_mem_partial_access.1993157260
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/45.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.523255023
Short name T876
Test name
Test status
Simulation time 43104681707 ps
CPU time 189.78 seconds
Started Oct 09 02:20:36 PM UTC 24
Finished Oct 09 02:23:49 PM UTC 24
Peak memory 221536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523255023 -assert nopos
tproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_mem_walk.523255023
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/45.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.3821577752
Short name T958
Test name
Test status
Simulation time 22987995751 ps
CPU time 1118.78 seconds
Started Oct 09 02:18:31 PM UTC 24
Finished Oct 09 02:37:23 PM UTC 24
Peak memory 377892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821577752 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multiple_keys.3821577752
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/45.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access.45308054
Short name T844
Test name
Test status
Simulation time 2280746805 ps
CPU time 24.15 seconds
Started Oct 09 02:18:49 PM UTC 24
Finished Oct 09 02:19:15 PM UTC 24
Peak memory 211244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45308054 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_partial_access.45308054
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/45.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.22274118
Short name T866
Test name
Test status
Simulation time 14694731623 ps
CPU time 257.86 seconds
Started Oct 09 02:18:55 PM UTC 24
Finished Oct 09 02:23:17 PM UTC 24
Peak memory 211520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22274118 -asse
rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_partial_acc
ess_b2b.22274118
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/45.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.3294312764
Short name T849
Test name
Test status
Simulation time 363528573 ps
CPU time 5.76 seconds
Started Oct 09 02:20:28 PM UTC 24
Finished Oct 09 02:20:35 PM UTC 24
Peak memory 211292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294312764 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.3294312764
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/45.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_readback_err.2312471668
Short name T853
Test name
Test status
Simulation time 691510763 ps
CPU time 8.12 seconds
Started Oct 09 02:21:02 PM UTC 24
Finished Oct 09 02:21:11 PM UTC 24
Peak memory 211272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312471668 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_readback_err.2312471668
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/45.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_regwen.299831337
Short name T901
Test name
Test status
Simulation time 1551551990 ps
CPU time 309.28 seconds
Started Oct 09 02:20:25 PM UTC 24
Finished Oct 09 02:25:38 PM UTC 24
Peak memory 379824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299831337 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.299831337
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/45.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_smoke.606668157
Short name T842
Test name
Test status
Simulation time 517857898 ps
CPU time 15.91 seconds
Started Oct 09 02:18:31 PM UTC 24
Finished Oct 09 02:18:48 PM UTC 24
Peak memory 211124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606668157 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.606668157
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/45.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all.649452088
Short name T991
Test name
Test status
Simulation time 875750000689 ps
CPU time 6621.86 seconds
Started Oct 09 02:21:12 PM UTC 24
Finished Oct 09 04:12:50 PM UTC 24
Peak memory 385628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64945208
8 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all.649452088
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/45.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1707142398
Short name T862
Test name
Test status
Simulation time 2690600051 ps
CPU time 105.79 seconds
Started Oct 09 02:21:06 PM UTC 24
Finished Oct 09 02:22:54 PM UTC 24
Peak memory 257116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707142398 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.1707142398
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/45.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.988894940
Short name T896
Test name
Test status
Simulation time 61699978587 ps
CPU time 384.23 seconds
Started Oct 09 02:18:49 PM UTC 24
Finished Oct 09 02:25:19 PM UTC 24
Peak memory 211504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988894940 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_pipeline.988894940
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/45.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.583568654
Short name T852
Test name
Test status
Simulation time 2872393572 ps
CPU time 101.52 seconds
Started Oct 09 02:19:21 PM UTC 24
Finished Oct 09 02:21:05 PM UTC 24
Peak memory 369720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=583568654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_
throughput_w_partial_write.583568654
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/45.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.3980954369
Short name T971
Test name
Test status
Simulation time 19662050623 ps
CPU time 1362.24 seconds
Started Oct 09 02:23:08 PM UTC 24
Finished Oct 09 02:46:05 PM UTC 24
Peak memory 386160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980954369 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_access_duri
ng_key_req.3980954369
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/46.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_alert_test.131015969
Short name T875
Test name
Test status
Simulation time 26218049 ps
CPU time 1.03 seconds
Started Oct 09 02:23:46 PM UTC 24
Finished Oct 09 02:23:48 PM UTC 24
Peak memory 211332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131015969 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_alert_test.131015969
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/46.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_bijection.2348405927
Short name T939
Test name
Test status
Simulation time 37291693598 ps
CPU time 567.86 seconds
Started Oct 09 02:21:50 PM UTC 24
Finished Oct 09 02:31:25 PM UTC 24
Peak memory 211276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348405927 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection.2348405927
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/46.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_executable.991090448
Short name T903
Test name
Test status
Simulation time 6100747804 ps
CPU time 149.87 seconds
Started Oct 09 02:23:17 PM UTC 24
Finished Oct 09 02:25:49 PM UTC 24
Peak memory 384116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991090448 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executable.991090448
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/46.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.2283033110
Short name T884
Test name
Test status
Simulation time 120019886405 ps
CPU time 83.47 seconds
Started Oct 09 02:23:04 PM UTC 24
Finished Oct 09 02:24:30 PM UTC 24
Peak memory 211356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283033110 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_escalation.2283033110
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/46.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.1324476968
Short name T881
Test name
Test status
Simulation time 766314591 ps
CPU time 94.13 seconds
Started Oct 09 02:22:47 PM UTC 24
Finished Oct 09 02:24:23 PM UTC 24
Peak memory 375724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1324476968 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_
max_throughput.1324476968
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/46.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.2306944629
Short name T891
Test name
Test status
Simulation time 1463957873 ps
CPU time 78.25 seconds
Started Oct 09 02:23:31 PM UTC 24
Finished Oct 09 02:24:51 PM UTC 24
Peak memory 228308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306944629 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_mem_partial_access.2306944629
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/46.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.2595039977
Short name T921
Test name
Test status
Simulation time 18760360744 ps
CPU time 306.04 seconds
Started Oct 09 02:23:30 PM UTC 24
Finished Oct 09 02:28:40 PM UTC 24
Peak memory 221564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595039977 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_mem_walk.2595039977
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/46.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.1890043045
Short name T956
Test name
Test status
Simulation time 8062393853 ps
CPU time 927 seconds
Started Oct 09 02:21:27 PM UTC 24
Finished Oct 09 02:37:07 PM UTC 24
Peak memory 384032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890043045 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multiple_keys.1890043045
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/46.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access.869208474
Short name T864
Test name
Test status
Simulation time 1504154695 ps
CPU time 62.04 seconds
Started Oct 09 02:22:03 PM UTC 24
Finished Oct 09 02:23:07 PM UTC 24
Peak memory 330932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869208474 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_partial_access.869208474
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/46.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.3053592033
Short name T898
Test name
Test status
Simulation time 2827694239 ps
CPU time 174.48 seconds
Started Oct 09 02:22:34 PM UTC 24
Finished Oct 09 02:25:31 PM UTC 24
Peak memory 211280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053592033 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_partial_a
ccess_b2b.3053592033
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/46.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.4142994899
Short name T869
Test name
Test status
Simulation time 347392888 ps
CPU time 4.84 seconds
Started Oct 09 02:23:24 PM UTC 24
Finished Oct 09 02:23:30 PM UTC 24
Peak memory 211216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142994899 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.4142994899
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/46.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_readback_err.1269560227
Short name T874
Test name
Test status
Simulation time 3008760346 ps
CPU time 11.66 seconds
Started Oct 09 02:23:34 PM UTC 24
Finished Oct 09 02:23:47 PM UTC 24
Peak memory 211416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269560227 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_readback_err.1269560227
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/46.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_regwen.2947355729
Short name T948
Test name
Test status
Simulation time 8611715984 ps
CPU time 652.64 seconds
Started Oct 09 02:23:18 PM UTC 24
Finished Oct 09 02:34:20 PM UTC 24
Peak memory 379896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947355729 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.2947355729
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/46.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_smoke.754871598
Short name T858
Test name
Test status
Simulation time 1472957802 ps
CPU time 24.46 seconds
Started Oct 09 02:21:26 PM UTC 24
Finished Oct 09 02:21:52 PM UTC 24
Peak memory 277560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754871598 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.754871598
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/46.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all.1856152264
Short name T987
Test name
Test status
Simulation time 89757956114 ps
CPU time 3245.04 seconds
Started Oct 09 02:23:45 PM UTC 24
Finished Oct 09 03:18:32 PM UTC 24
Peak memory 389888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18561522
64 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_a
ll.1856152264
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/46.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2886516511
Short name T887
Test name
Test status
Simulation time 5392049798 ps
CPU time 66.15 seconds
Started Oct 09 02:23:35 PM UTC 24
Finished Oct 09 02:24:43 PM UTC 24
Peak memory 308528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886516511 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.2886516511
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/46.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.499101992
Short name T885
Test name
Test status
Simulation time 2626833426 ps
CPU time 154.52 seconds
Started Oct 09 02:21:53 PM UTC 24
Finished Oct 09 02:24:30 PM UTC 24
Peak memory 211468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499101992 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_pipeline.499101992
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/46.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.1776081459
Short name T867
Test name
Test status
Simulation time 758565906 ps
CPU time 26.41 seconds
Started Oct 09 02:22:55 PM UTC 24
Finished Oct 09 02:23:23 PM UTC 24
Peak memory 285688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1776081459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl
_throughput_w_partial_write.1776081459
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/46.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.361109548
Short name T927
Test name
Test status
Simulation time 10252961854 ps
CPU time 292.73 seconds
Started Oct 09 02:24:31 PM UTC 24
Finished Oct 09 02:29:28 PM UTC 24
Peak memory 369716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361109548 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_access_durin
g_key_req.361109548
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/47.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_alert_test.3428617692
Short name T894
Test name
Test status
Simulation time 29641848 ps
CPU time 0.87 seconds
Started Oct 09 02:25:05 PM UTC 24
Finished Oct 09 02:25:06 PM UTC 24
Peak memory 209424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428617692
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_alert_test.3428617692
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/47.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_bijection.70100184
Short name T978
Test name
Test status
Simulation time 102813448861 ps
CPU time 1656.47 seconds
Started Oct 09 02:23:51 PM UTC 24
Finished Oct 09 02:51:47 PM UTC 24
Peak memory 211376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70100184 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection.70100184
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/47.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_executable.4183119982
Short name T959
Test name
Test status
Simulation time 55071327174 ps
CPU time 816.97 seconds
Started Oct 09 02:24:32 PM UTC 24
Finished Oct 09 02:38:19 PM UTC 24
Peak memory 382192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183119982 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executable.4183119982
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/47.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.3723766400
Short name T905
Test name
Test status
Simulation time 38395760545 ps
CPU time 89.39 seconds
Started Oct 09 02:24:28 PM UTC 24
Finished Oct 09 02:26:00 PM UTC 24
Peak memory 211516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723766400 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_escalation.3723766400
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/47.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.2734508985
Short name T886
Test name
Test status
Simulation time 2806620655 ps
CPU time 9.35 seconds
Started Oct 09 02:24:22 PM UTC 24
Finished Oct 09 02:24:32 PM UTC 24
Peak memory 227868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2734508985 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_
max_throughput.2734508985
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/47.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.1234192158
Short name T908
Test name
Test status
Simulation time 4026117513 ps
CPU time 88.69 seconds
Started Oct 09 02:24:48 PM UTC 24
Finished Oct 09 02:26:18 PM UTC 24
Peak memory 228316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234192158 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_mem_partial_access.1234192158
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/47.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.3543298604
Short name T928
Test name
Test status
Simulation time 16416225968 ps
CPU time 288.91 seconds
Started Oct 09 02:24:45 PM UTC 24
Finished Oct 09 02:29:39 PM UTC 24
Peak memory 221820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543298604 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_mem_walk.3543298604
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/47.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access.654865849
Short name T883
Test name
Test status
Simulation time 3266125014 ps
CPU time 20.93 seconds
Started Oct 09 02:24:05 PM UTC 24
Finished Oct 09 02:24:27 PM UTC 24
Peak memory 211272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654865849 -ass
ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_partial_access.654865849
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/47.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.3841419819
Short name T940
Test name
Test status
Simulation time 13293740630 ps
CPU time 426.44 seconds
Started Oct 09 02:24:14 PM UTC 24
Finished Oct 09 02:31:26 PM UTC 24
Peak memory 211288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841419819 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_partial_a
ccess_b2b.3841419819
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/47.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.995696338
Short name T890
Test name
Test status
Simulation time 2413995256 ps
CPU time 5.34 seconds
Started Oct 09 02:24:44 PM UTC 24
Finished Oct 09 02:24:50 PM UTC 24
Peak memory 211560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995696338 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.995696338
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/47.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_readback_err.4090979619
Short name T893
Test name
Test status
Simulation time 3684067923 ps
CPU time 10.6 seconds
Started Oct 09 02:24:52 PM UTC 24
Finished Oct 09 02:25:04 PM UTC 24
Peak memory 211544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090979619 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_readback_err.4090979619
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/47.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_regwen.943508996
Short name T947
Test name
Test status
Simulation time 11486991889 ps
CPU time 571.25 seconds
Started Oct 09 02:24:34 PM UTC 24
Finished Oct 09 02:34:13 PM UTC 24
Peak memory 363876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943508996 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.943508996
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/47.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_smoke.2382765651
Short name T877
Test name
Test status
Simulation time 1668668854 ps
CPU time 12.52 seconds
Started Oct 09 02:23:48 PM UTC 24
Finished Oct 09 02:24:02 PM UTC 24
Peak memory 234488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382765651 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.2382765651
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/47.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all.3886708632
Short name T989
Test name
Test status
Simulation time 700360470816 ps
CPU time 4627.72 seconds
Started Oct 09 02:24:58 PM UTC 24
Finished Oct 09 03:42:58 PM UTC 24
Peak memory 389636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38867086
32 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_a
ll.3886708632
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/47.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1030232110
Short name T899
Test name
Test status
Simulation time 5507376212 ps
CPU time 41.46 seconds
Started Oct 09 02:24:52 PM UTC 24
Finished Oct 09 02:25:35 PM UTC 24
Peak memory 221752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030232110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.1030232110
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/47.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.2419862614
Short name T916
Test name
Test status
Simulation time 2637939153 ps
CPU time 204.37 seconds
Started Oct 09 02:24:03 PM UTC 24
Finished Oct 09 02:27:31 PM UTC 24
Peak memory 211236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419862614 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_pipeline.2419862614
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/47.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.714589178
Short name T888
Test name
Test status
Simulation time 1412796519 ps
CPU time 19.01 seconds
Started Oct 09 02:24:24 PM UTC 24
Finished Oct 09 02:24:44 PM UTC 24
Peak memory 265204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=714589178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_
throughput_w_partial_write.714589178
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/47.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.1794036002
Short name T965
Test name
Test status
Simulation time 236877778672 ps
CPU time 1090.88 seconds
Started Oct 09 02:25:50 PM UTC 24
Finished Oct 09 02:44:14 PM UTC 24
Peak memory 388212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794036002 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_access_duri
ng_key_req.1794036002
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/48.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_alert_test.1490105829
Short name T913
Test name
Test status
Simulation time 22420415 ps
CPU time 0.89 seconds
Started Oct 09 02:26:57 PM UTC 24
Finished Oct 09 02:26:59 PM UTC 24
Peak memory 209424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490105829
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_alert_test.1490105829
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/48.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_bijection.3778103061
Short name T950
Test name
Test status
Simulation time 39084157357 ps
CPU time 595.63 seconds
Started Oct 09 02:25:20 PM UTC 24
Finished Oct 09 02:35:25 PM UTC 24
Peak memory 211332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778103061 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection.3778103061
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/48.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_executable.1876107218
Short name T967
Test name
Test status
Simulation time 45339728411 ps
CPU time 1135.01 seconds
Started Oct 09 02:25:56 PM UTC 24
Finished Oct 09 02:45:04 PM UTC 24
Peak memory 388184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876107218 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executable.1876107218
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/48.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.2390780657
Short name T912
Test name
Test status
Simulation time 18031217113 ps
CPU time 70.39 seconds
Started Oct 09 02:25:44 PM UTC 24
Finished Oct 09 02:26:56 PM UTC 24
Peak memory 211516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390780657 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_escalation.2390780657
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/48.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.4093647971
Short name T906
Test name
Test status
Simulation time 2817621805 ps
CPU time 27.26 seconds
Started Oct 09 02:25:36 PM UTC 24
Finished Oct 09 02:26:06 PM UTC 24
Peak memory 279440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
4093647971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_
max_throughput.4093647971
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/48.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.1480880893
Short name T929
Test name
Test status
Simulation time 26967006002 ps
CPU time 197.77 seconds
Started Oct 09 02:26:20 PM UTC 24
Finished Oct 09 02:29:41 PM UTC 24
Peak memory 221644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1480880893 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_mem_partial_access.1480880893
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/48.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.2426932930
Short name T946
Test name
Test status
Simulation time 42274766080 ps
CPU time 460.33 seconds
Started Oct 09 02:26:14 PM UTC 24
Finished Oct 09 02:34:01 PM UTC 24
Peak memory 221668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426932930 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_mem_walk.2426932930
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/48.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.3824773961
Short name T963
Test name
Test status
Simulation time 50564637867 ps
CPU time 923.22 seconds
Started Oct 09 02:25:16 PM UTC 24
Finished Oct 09 02:40:49 PM UTC 24
Peak memory 388128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824773961 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multiple_keys.3824773961
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/48.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access.1161802502
Short name T902
Test name
Test status
Simulation time 687229612 ps
CPU time 9.83 seconds
Started Oct 09 02:25:32 PM UTC 24
Finished Oct 09 02:25:43 PM UTC 24
Peak memory 222120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161802502 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_partial_access.1161802502
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/48.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.1102442136
Short name T934
Test name
Test status
Simulation time 4885663208 ps
CPU time 289.9 seconds
Started Oct 09 02:25:36 PM UTC 24
Finished Oct 09 02:30:32 PM UTC 24
Peak memory 211308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102442136 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_partial_a
ccess_b2b.1102442136
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/48.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.628607210
Short name T907
Test name
Test status
Simulation time 353440474 ps
CPU time 5.3 seconds
Started Oct 09 02:26:06 PM UTC 24
Finished Oct 09 02:26:13 PM UTC 24
Peak memory 211492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628607210 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.628607210
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/48.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_readback_err.3874056540
Short name T911
Test name
Test status
Simulation time 694366868 ps
CPU time 11.31 seconds
Started Oct 09 02:26:39 PM UTC 24
Finished Oct 09 02:26:51 PM UTC 24
Peak memory 211272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874056540 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_readback_err.3874056540
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/48.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_regwen.1095189445
Short name T972
Test name
Test status
Simulation time 14845532102 ps
CPU time 1287.8 seconds
Started Oct 09 02:26:01 PM UTC 24
Finished Oct 09 02:47:45 PM UTC 24
Peak memory 390268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095189445 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.1095189445
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/48.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_smoke.3127873941
Short name T900
Test name
Test status
Simulation time 609359734 ps
CPU time 26.09 seconds
Started Oct 09 02:25:08 PM UTC 24
Finished Oct 09 02:25:35 PM UTC 24
Peak memory 269144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127873941 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.3127873941
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/48.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all.3413685763
Short name T979
Test name
Test status
Simulation time 342529347081 ps
CPU time 1623.28 seconds
Started Oct 09 02:26:52 PM UTC 24
Finished Oct 09 02:54:14 PM UTC 24
Peak memory 398444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34136857
63 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_a
ll.3413685763
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/48.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1500634533
Short name T146
Test name
Test status
Simulation time 3155020174 ps
CPU time 181.52 seconds
Started Oct 09 02:26:41 PM UTC 24
Finished Oct 09 02:29:46 PM UTC 24
Peak memory 343224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500634533 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.1500634533
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/48.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.3228700974
Short name T920
Test name
Test status
Simulation time 2347234306 ps
CPU time 154.94 seconds
Started Oct 09 02:25:25 PM UTC 24
Finished Oct 09 02:28:03 PM UTC 24
Peak memory 211572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228700974 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_pipeline.3228700974
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/48.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.2209247486
Short name T917
Test name
Test status
Simulation time 3412673053 ps
CPU time 115.64 seconds
Started Oct 09 02:25:40 PM UTC 24
Finished Oct 09 02:27:38 PM UTC 24
Peak memory 381888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2209247486 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl
_throughput_w_partial_write.2209247486
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/48.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.1965953983
Short name T974
Test name
Test status
Simulation time 48269705500 ps
CPU time 1149.32 seconds
Started Oct 09 02:28:53 PM UTC 24
Finished Oct 09 02:48:18 PM UTC 24
Peak memory 388208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965953983 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_access_duri
ng_key_req.1965953983
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/49.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_alert_test.2788024379
Short name T931
Test name
Test status
Simulation time 17936250 ps
CPU time 1.06 seconds
Started Oct 09 02:29:50 PM UTC 24
Finished Oct 09 02:29:52 PM UTC 24
Peak memory 209424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788024379
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_alert_test.2788024379
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/49.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_bijection.13875915
Short name T985
Test name
Test status
Simulation time 261779710061 ps
CPU time 2694.18 seconds
Started Oct 09 02:27:20 PM UTC 24
Finished Oct 09 03:12:48 PM UTC 24
Peak memory 212840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13875915 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection.13875915
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/49.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_executable.1891860200
Short name T962
Test name
Test status
Simulation time 26432413084 ps
CPU time 655.12 seconds
Started Oct 09 02:29:05 PM UTC 24
Finished Oct 09 02:40:08 PM UTC 24
Peak memory 384048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891860200 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executable.1891860200
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/49.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.751329908
Short name T938
Test name
Test status
Simulation time 19464031113 ps
CPU time 139.54 seconds
Started Oct 09 02:28:41 PM UTC 24
Finished Oct 09 02:31:03 PM UTC 24
Peak memory 221616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751329908 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_escalation.751329908
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/49.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.1921043832
Short name T923
Test name
Test status
Simulation time 2724489535 ps
CPU time 62.47 seconds
Started Oct 09 02:27:59 PM UTC 24
Finished Oct 09 02:29:04 PM UTC 24
Peak memory 328688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1921043832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_
max_throughput.1921043832
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/49.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.2248060238
Short name T937
Test name
Test status
Simulation time 2496800871 ps
CPU time 89.32 seconds
Started Oct 09 02:29:30 PM UTC 24
Finished Oct 09 02:31:01 PM UTC 24
Peak memory 221608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248060238 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_mem_partial_access.2248060238
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/49.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.3616892283
Short name T951
Test name
Test status
Simulation time 18685763251 ps
CPU time 358.8 seconds
Started Oct 09 02:29:30 PM UTC 24
Finished Oct 09 02:35:34 PM UTC 24
Peak memory 221700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616892283 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_mem_walk.3616892283
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/49.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.3915451418
Short name T952
Test name
Test status
Simulation time 20588810739 ps
CPU time 514.4 seconds
Started Oct 09 02:27:19 PM UTC 24
Finished Oct 09 02:36:00 PM UTC 24
Peak memory 384112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915451418 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multiple_keys.3915451418
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/49.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access.2824511584
Short name T918
Test name
Test status
Simulation time 700117016 ps
CPU time 8.57 seconds
Started Oct 09 02:27:39 PM UTC 24
Finished Oct 09 02:27:49 PM UTC 24
Peak memory 210876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824511584 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_partial_access.2824511584
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/49.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.3714813981
Short name T949
Test name
Test status
Simulation time 15913309571 ps
CPU time 388.01 seconds
Started Oct 09 02:27:49 PM UTC 24
Finished Oct 09 02:34:23 PM UTC 24
Peak memory 211648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714813981 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_partial_a
ccess_b2b.3714813981
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/49.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.3549328961
Short name T926
Test name
Test status
Simulation time 362830995 ps
CPU time 5.83 seconds
Started Oct 09 02:29:21 PM UTC 24
Finished Oct 09 02:29:28 PM UTC 24
Peak memory 211292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549328961 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.3549328961
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/49.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_readback_err.2959382033
Short name T932
Test name
Test status
Simulation time 1327527463 ps
CPU time 10.7 seconds
Started Oct 09 02:29:40 PM UTC 24
Finished Oct 09 02:29:52 PM UTC 24
Peak memory 211728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959382033 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_readback_err.2959382033
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/49.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_regwen.526142273
Short name T970
Test name
Test status
Simulation time 11305943686 ps
CPU time 967.95 seconds
Started Oct 09 02:29:19 PM UTC 24
Finished Oct 09 02:45:38 PM UTC 24
Peak memory 386096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526142273 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.526142273
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/49.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_smoke.2240432899
Short name T914
Test name
Test status
Simulation time 753801648 ps
CPU time 16.12 seconds
Started Oct 09 02:27:01 PM UTC 24
Finished Oct 09 02:27:18 PM UTC 24
Peak memory 211212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240432899 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.2240432899
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/49.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all.2194267747
Short name T986
Test name
Test status
Simulation time 49558286919 ps
CPU time 2771.55 seconds
Started Oct 09 02:29:47 PM UTC 24
Finished Oct 09 03:16:30 PM UTC 24
Peak memory 389644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21942677
47 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_a
ll.2194267747
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/49.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.2079361131
Short name T935
Test name
Test status
Simulation time 1777414649 ps
CPU time 48.78 seconds
Started Oct 09 02:29:42 PM UTC 24
Finished Oct 09 02:30:33 PM UTC 24
Peak memory 221600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079361131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.2079361131
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/49.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.2092355519
Short name T942
Test name
Test status
Simulation time 4964496295 ps
CPU time 283.74 seconds
Started Oct 09 02:27:31 PM UTC 24
Finished Oct 09 02:32:20 PM UTC 24
Peak memory 211324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092355519 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_pipeline.2092355519
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/49.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.1782967975
Short name T924
Test name
Test status
Simulation time 774148421 ps
CPU time 71.87 seconds
Started Oct 09 02:28:04 PM UTC 24
Finished Oct 09 02:29:18 PM UTC 24
Peak memory 332792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1782967975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl
_throughput_w_partial_write.1782967975
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/49.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_access_during_key_req.2961102422
Short name T262
Test name
Test status
Simulation time 46165765165 ps
CPU time 1354.26 seconds
Started Oct 09 12:30:42 PM UTC 24
Finished Oct 09 12:53:32 PM UTC 24
Peak memory 388296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961102422 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_access_durin
g_key_req.2961102422
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_alert_test.3724837730
Short name T177
Test name
Test status
Simulation time 21925754 ps
CPU time 1.07 seconds
Started Oct 09 12:32:03 PM UTC 24
Finished Oct 09 12:32:05 PM UTC 24
Peak memory 209432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724837730
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_alert_test.3724837730
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_bijection.4105989371
Short name T215
Test name
Test status
Simulation time 12547982765 ps
CPU time 742.19 seconds
Started Oct 09 12:28:46 PM UTC 24
Finished Oct 09 12:41:18 PM UTC 24
Peak memory 211252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105989371 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.4105989371
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_executable.3326966853
Short name T247
Test name
Test status
Simulation time 17905887479 ps
CPU time 1184.76 seconds
Started Oct 09 12:30:46 PM UTC 24
Finished Oct 09 12:50:44 PM UTC 24
Peak memory 386096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326966853 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executable.3326966853
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_lc_escalation.973228267
Short name T160
Test name
Test status
Simulation time 11774221752 ps
CPU time 110.48 seconds
Started Oct 09 12:29:51 PM UTC 24
Finished Oct 09 12:31:44 PM UTC 24
Peak memory 211232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973228267 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_escalation.973228267
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_max_throughput.55431582
Short name T174
Test name
Test status
Simulation time 695579924 ps
CPU time 13.84 seconds
Started Oct 09 12:29:35 PM UTC 24
Finished Oct 09 12:29:50 PM UTC 24
Peak memory 234420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
55431582 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_max
_throughput.55431582
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_partial_access.1365564677
Short name T95
Test name
Test status
Simulation time 5106590740 ps
CPU time 177.67 seconds
Started Oct 09 12:31:22 PM UTC 24
Finished Oct 09 12:34:23 PM UTC 24
Peak memory 221644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365564677 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_mem_partial_access.1365564677
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_mem_walk.1804362828
Short name T186
Test name
Test status
Simulation time 7195665555 ps
CPU time 191.59 seconds
Started Oct 09 12:31:21 PM UTC 24
Finished Oct 09 12:34:36 PM UTC 24
Peak memory 211412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804362828 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_mem_walk.1804362828
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.813284771
Short name T217
Test name
Test status
Simulation time 125165754826 ps
CPU time 799.38 seconds
Started Oct 09 12:28:11 PM UTC 24
Finished Oct 09 12:41:41 PM UTC 24
Peak memory 388220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813284771 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multiple_keys.813284771
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access.2415141703
Short name T173
Test name
Test status
Simulation time 1090463814 ps
CPU time 24.74 seconds
Started Oct 09 12:29:08 PM UTC 24
Finished Oct 09 12:29:34 PM UTC 24
Peak memory 211396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415141703 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_partial_access.2415141703
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_partial_access_b2b.1402369150
Short name T158
Test name
Test status
Simulation time 23382315244 ps
CPU time 555.76 seconds
Started Oct 09 12:29:10 PM UTC 24
Finished Oct 09 12:38:33 PM UTC 24
Peak memory 211284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402369150 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_partial_ac
cess_b2b.1402369150
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_ram_cfg.2098904662
Short name T176
Test name
Test status
Simulation time 693392501 ps
CPU time 5.79 seconds
Started Oct 09 12:31:13 PM UTC 24
Finished Oct 09 12:31:20 PM UTC 24
Peak memory 211212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098904662 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.2098904662
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_readback_err.1941498384
Short name T162
Test name
Test status
Simulation time 691842221 ps
CPU time 10.88 seconds
Started Oct 09 12:31:42 PM UTC 24
Finished Oct 09 12:31:55 PM UTC 24
Peak memory 211288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941498384 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_readback_err.1941498384
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_regwen.2860762191
Short name T116
Test name
Test status
Simulation time 757596863 ps
CPU time 108.59 seconds
Started Oct 09 12:31:02 PM UTC 24
Finished Oct 09 12:32:52 PM UTC 24
Peak memory 359420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860762191 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.2860762191
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_smoke.3177778456
Short name T172
Test name
Test status
Simulation time 5684793157 ps
CPU time 55.68 seconds
Started Oct 09 12:28:09 PM UTC 24
Finished Oct 09 12:29:06 PM UTC 24
Peak memory 322876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177778456 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.3177778456
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all.269686024
Short name T682
Test name
Test status
Simulation time 787213877930 ps
CPU time 5079.84 seconds
Started Oct 09 12:31:55 PM UTC 24
Finished Oct 09 01:57:36 PM UTC 24
Peak memory 365072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26968602
4 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all.269686024
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.4231165320
Short name T64
Test name
Test status
Simulation time 1092816881 ps
CPU time 14.72 seconds
Started Oct 09 12:31:45 PM UTC 24
Finished Oct 09 12:32:01 PM UTC 24
Peak memory 221724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231165320 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.4231165320
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_pipeline.3184968903
Short name T183
Test name
Test status
Simulation time 8504304755 ps
CPU time 283.04 seconds
Started Oct 09 12:29:06 PM UTC 24
Finished Oct 09 12:33:53 PM UTC 24
Peak memory 211536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184968903 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_pipeline.3184968903
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_throughput_w_partial_write.4214074628
Short name T175
Test name
Test status
Simulation time 3223158264 ps
CPU time 53.26 seconds
Started Oct 09 12:29:46 PM UTC 24
Finished Oct 09 12:30:41 PM UTC 24
Peak memory 314296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=4214074628 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_
throughput_w_partial_write.4214074628
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/5.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_access_during_key_req.2866813901
Short name T204
Test name
Test status
Simulation time 4566637923 ps
CPU time 234.77 seconds
Started Oct 09 12:33:41 PM UTC 24
Finished Oct 09 12:37:39 PM UTC 24
Peak memory 386056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866813901 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_access_durin
g_key_req.2866813901
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_alert_test.1004753402
Short name T187
Test name
Test status
Simulation time 13544567 ps
CPU time 1.04 seconds
Started Oct 09 12:34:37 PM UTC 24
Finished Oct 09 12:34:39 PM UTC 24
Peak memory 211336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004753402
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_alert_test.1004753402
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_bijection.938362602
Short name T363
Test name
Test status
Simulation time 33236099217 ps
CPU time 2293.58 seconds
Started Oct 09 12:32:27 PM UTC 24
Finished Oct 09 01:11:08 PM UTC 24
Peak memory 211460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938362602 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.938362602
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_executable.3831728335
Short name T155
Test name
Test status
Simulation time 17867360936 ps
CPU time 674.98 seconds
Started Oct 09 12:33:42 PM UTC 24
Finished Oct 09 12:45:05 PM UTC 24
Peak memory 388220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831728335 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executable.3831728335
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_lc_escalation.3209093615
Short name T188
Test name
Test status
Simulation time 38667472823 ps
CPU time 73 seconds
Started Oct 09 12:33:40 PM UTC 24
Finished Oct 09 12:34:55 PM UTC 24
Peak memory 211312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209093615 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_escalation.3209093615
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_max_throughput.1422697318
Short name T190
Test name
Test status
Simulation time 781749687 ps
CPU time 103.54 seconds
Started Oct 09 12:33:21 PM UTC 24
Finished Oct 09 12:35:07 PM UTC 24
Peak memory 361652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1422697318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_m
ax_throughput.1422697318
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_partial_access.2109003361
Short name T96
Test name
Test status
Simulation time 4911356263 ps
CPU time 77.62 seconds
Started Oct 09 12:34:02 PM UTC 24
Finished Oct 09 12:35:22 PM UTC 24
Peak memory 221884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109003361 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_mem_partial_access.2109003361
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_mem_walk.2525218107
Short name T207
Test name
Test status
Simulation time 4109754184 ps
CPU time 253.67 seconds
Started Oct 09 12:34:01 PM UTC 24
Finished Oct 09 12:38:19 PM UTC 24
Peak memory 221652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525218107 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_mem_walk.2525218107
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_multiple_keys.3798247600
Short name T241
Test name
Test status
Simulation time 78753918005 ps
CPU time 1056.49 seconds
Started Oct 09 12:32:20 PM UTC 24
Finished Oct 09 12:50:09 PM UTC 24
Peak memory 386300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798247600 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multiple_keys.3798247600
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access.1573591543
Short name T182
Test name
Test status
Simulation time 5030542924 ps
CPU time 54.69 seconds
Started Oct 09 12:32:53 PM UTC 24
Finished Oct 09 12:33:50 PM UTC 24
Peak memory 337244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573591543 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_partial_access.1573591543
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_partial_access_b2b.2223397544
Short name T159
Test name
Test status
Simulation time 45415611994 ps
CPU time 416.53 seconds
Started Oct 09 12:33:15 PM UTC 24
Finished Oct 09 12:40:18 PM UTC 24
Peak memory 211584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223397544 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_partial_ac
cess_b2b.2223397544
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_ram_cfg.50887118
Short name T184
Test name
Test status
Simulation time 354251740 ps
CPU time 5.92 seconds
Started Oct 09 12:33:54 PM UTC 24
Finished Oct 09 12:34:02 PM UTC 24
Peak memory 211216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50887118 -assert nopostproc +UVM_TEST
NAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.50887118
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_readback_err.3201485217
Short name T185
Test name
Test status
Simulation time 2554178008 ps
CPU time 10.64 seconds
Started Oct 09 12:34:04 PM UTC 24
Finished Oct 09 12:34:16 PM UTC 24
Peak memory 211620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201485217 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_readback_err.3201485217
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_regwen.1517123580
Short name T244
Test name
Test status
Simulation time 54409297289 ps
CPU time 988.76 seconds
Started Oct 09 12:33:50 PM UTC 24
Finished Oct 09 12:50:31 PM UTC 24
Peak memory 390196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517123580 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.1517123580
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_smoke.1566626219
Short name T179
Test name
Test status
Simulation time 745103650 ps
CPU time 37.43 seconds
Started Oct 09 12:32:06 PM UTC 24
Finished Oct 09 12:32:45 PM UTC 24
Peak memory 292028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566626219 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.1566626219
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all.298665005
Short name T471
Test name
Test status
Simulation time 51697481893 ps
CPU time 3109.4 seconds
Started Oct 09 12:34:24 PM UTC 24
Finished Oct 09 01:26:51 PM UTC 24
Peak memory 391696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29866500
5 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all.298665005
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.626491335
Short name T48
Test name
Test status
Simulation time 1639622996 ps
CPU time 115.33 seconds
Started Oct 09 12:34:17 PM UTC 24
Finished Oct 09 12:36:14 PM UTC 24
Peak memory 359724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626491335 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.626491335
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_stress_pipeline.224349654
Short name T199
Test name
Test status
Simulation time 3633023358 ps
CPU time 203.89 seconds
Started Oct 09 12:32:46 PM UTC 24
Finished Oct 09 12:36:13 PM UTC 24
Peak memory 211148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224349654 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_pipeline.224349654
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_throughput_w_partial_write.1952137761
Short name T191
Test name
Test status
Simulation time 828627925 ps
CPU time 94.03 seconds
Started Oct 09 12:33:32 PM UTC 24
Finished Oct 09 12:35:08 PM UTC 24
Peak memory 378100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1952137761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_
throughput_w_partial_write.1952137761
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/6.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_access_during_key_req.3004734564
Short name T243
Test name
Test status
Simulation time 59421643210 ps
CPU time 848 seconds
Started Oct 09 12:35:55 PM UTC 24
Finished Oct 09 12:50:14 PM UTC 24
Peak memory 382280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004734564 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_access_durin
g_key_req.3004734564
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_alert_test.718499139
Short name T202
Test name
Test status
Simulation time 13214996 ps
CPU time 0.99 seconds
Started Oct 09 12:36:51 PM UTC 24
Finished Oct 09 12:36:53 PM UTC 24
Peak memory 209432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718499139 -
assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_alert_test.718499139
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_bijection.203248631
Short name T355
Test name
Test status
Simulation time 37996187174 ps
CPU time 2039.44 seconds
Started Oct 09 12:35:07 PM UTC 24
Finished Oct 09 01:09:29 PM UTC 24
Peak memory 211300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203248631 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.203248631
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_executable.3603311040
Short name T292
Test name
Test status
Simulation time 20784071047 ps
CPU time 1396.21 seconds
Started Oct 09 12:35:55 PM UTC 24
Finished Oct 09 12:59:27 PM UTC 24
Peak memory 388256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603311040 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executable.3603311040
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_lc_escalation.3876987801
Short name T196
Test name
Test status
Simulation time 1461516875 ps
CPU time 8.86 seconds
Started Oct 09 12:35:44 PM UTC 24
Finished Oct 09 12:35:55 PM UTC 24
Peak memory 211180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876987801 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_escalation.3876987801
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_max_throughput.3578489964
Short name T198
Test name
Test status
Simulation time 2615512342 ps
CPU time 41.01 seconds
Started Oct 09 12:35:23 PM UTC 24
Finished Oct 09 12:36:05 PM UTC 24
Peak memory 322808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3578489964 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_m
ax_throughput.3578489964
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_partial_access.248428525
Short name T57
Test name
Test status
Simulation time 10475458012 ps
CPU time 98.27 seconds
Started Oct 09 12:36:16 PM UTC 24
Finished Oct 09 12:37:56 PM UTC 24
Peak memory 221704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248428525 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_mem_partial_access.248428525
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_mem_walk.3199652138
Short name T218
Test name
Test status
Simulation time 27671791705 ps
CPU time 323.84 seconds
Started Oct 09 12:36:14 PM UTC 24
Finished Oct 09 12:41:43 PM UTC 24
Peak memory 221620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199652138 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_mem_walk.3199652138
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_multiple_keys.3798146143
Short name T328
Test name
Test status
Simulation time 47669039355 ps
CPU time 1736.78 seconds
Started Oct 09 12:34:56 PM UTC 24
Finished Oct 09 01:04:12 PM UTC 24
Peak memory 388152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798146143 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multiple_keys.3798146143
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access.1582504142
Short name T193
Test name
Test status
Simulation time 1246099634 ps
CPU time 19.9 seconds
Started Oct 09 12:35:08 PM UTC 24
Finished Oct 09 12:35:30 PM UTC 24
Peak memory 211256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582504142 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_partial_access.1582504142
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_partial_access_b2b.1263139711
Short name T229
Test name
Test status
Simulation time 19951125201 ps
CPU time 617.05 seconds
Started Oct 09 12:35:09 PM UTC 24
Finished Oct 09 12:45:34 PM UTC 24
Peak memory 211384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263139711 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_partial_ac
cess_b2b.1263139711
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_ram_cfg.1159052433
Short name T200
Test name
Test status
Simulation time 1031093526 ps
CPU time 6.53 seconds
Started Oct 09 12:36:06 PM UTC 24
Finished Oct 09 12:36:14 PM UTC 24
Peak memory 211484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159052433 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.1159052433
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_readback_err.1149758786
Short name T201
Test name
Test status
Simulation time 8248457369 ps
CPU time 12.79 seconds
Started Oct 09 12:36:16 PM UTC 24
Finished Oct 09 12:36:30 PM UTC 24
Peak memory 211680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149758786 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_readback_err.1149758786
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_smoke.3415686705
Short name T189
Test name
Test status
Simulation time 1648632022 ps
CPU time 24.57 seconds
Started Oct 09 12:34:40 PM UTC 24
Finished Oct 09 12:35:06 PM UTC 24
Peak memory 211300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415686705 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.3415686705
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_stress_pipeline.638499784
Short name T211
Test name
Test status
Simulation time 16353009212 ps
CPU time 353.08 seconds
Started Oct 09 12:35:07 PM UTC 24
Finished Oct 09 12:41:06 PM UTC 24
Peak memory 211336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638499784 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_pipeline.638499784
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_throughput_w_partial_write.1761903578
Short name T197
Test name
Test status
Simulation time 1072743365 ps
CPU time 26.56 seconds
Started Oct 09 12:35:31 PM UTC 24
Finished Oct 09 12:35:59 PM UTC 24
Peak memory 263348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1761903578 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_
throughput_w_partial_write.1761903578
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/7.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_access_during_key_req.1782205678
Short name T212
Test name
Test status
Simulation time 10402785531 ps
CPU time 155.13 seconds
Started Oct 09 12:38:33 PM UTC 24
Finished Oct 09 12:41:11 PM UTC 24
Peak memory 306232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782205678 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_access_durin
g_key_req.1782205678
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_alert_test.4102738045
Short name T216
Test name
Test status
Simulation time 24074778 ps
CPU time 1.03 seconds
Started Oct 09 12:41:18 PM UTC 24
Finished Oct 09 12:41:20 PM UTC 24
Peak memory 211336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102738045
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_alert_test.4102738045
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_bijection.3739291750
Short name T317
Test name
Test status
Simulation time 66741107148 ps
CPU time 1474.53 seconds
Started Oct 09 12:37:35 PM UTC 24
Finished Oct 09 01:02:26 PM UTC 24
Peak memory 211392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739291750 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection.3739291750
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_executable.1108290130
Short name T153
Test name
Test status
Simulation time 18574662861 ps
CPU time 705.19 seconds
Started Oct 09 12:38:35 PM UTC 24
Finished Oct 09 12:50:29 PM UTC 24
Peak memory 363640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108290130 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executable.1108290130
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_executable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_lc_escalation.956624679
Short name T161
Test name
Test status
Simulation time 27012017202 ps
CPU time 56.58 seconds
Started Oct 09 12:38:20 PM UTC 24
Finished Oct 09 12:39:18 PM UTC 24
Peak memory 221736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956624679 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_escalation.956624679
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_max_throughput.3788334981
Short name T206
Test name
Test status
Simulation time 2241555206 ps
CPU time 9.3 seconds
Started Oct 09 12:37:58 PM UTC 24
Finished Oct 09 12:38:08 PM UTC 24
Peak memory 221404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3788334981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_m
ax_throughput.3788334981
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_partial_access.908649972
Short name T223
Test name
Test status
Simulation time 4994152017 ps
CPU time 171.44 seconds
Started Oct 09 12:40:33 PM UTC 24
Finished Oct 09 12:43:29 PM UTC 24
Peak memory 221580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908649972 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_mem_partial_access.908649972
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_mem_walk.1387045645
Short name T232
Test name
Test status
Simulation time 86164391150 ps
CPU time 348.67 seconds
Started Oct 09 12:40:27 PM UTC 24
Finished Oct 09 12:46:21 PM UTC 24
Peak memory 211408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387045645 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_mem_walk.1387045645
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_multiple_keys.3729148986
Short name T290
Test name
Test status
Simulation time 11995786784 ps
CPU time 1262.15 seconds
Started Oct 09 12:37:24 PM UTC 24
Finished Oct 09 12:58:41 PM UTC 24
Peak memory 386360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729148986 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multiple_keys.3729148986
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access.3388787233
Short name T205
Test name
Test status
Simulation time 712913801 ps
CPU time 10.96 seconds
Started Oct 09 12:37:45 PM UTC 24
Finished Oct 09 12:37:57 PM UTC 24
Peak memory 210884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388787233 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_partial_access.3388787233
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_partial_access_b2b.4234339299
Short name T227
Test name
Test status
Simulation time 28827608183 ps
CPU time 353.18 seconds
Started Oct 09 12:37:57 PM UTC 24
Finished Oct 09 12:43:55 PM UTC 24
Peak memory 211360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234339299 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_partial_ac
cess_b2b.4234339299
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_ram_cfg.3688918730
Short name T209
Test name
Test status
Simulation time 360116096 ps
CPU time 5.92 seconds
Started Oct 09 12:40:19 PM UTC 24
Finished Oct 09 12:40:26 PM UTC 24
Peak memory 211292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688918730 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.3688918730
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_readback_err.1161397954
Short name T213
Test name
Test status
Simulation time 2742388075 ps
CPU time 9.67 seconds
Started Oct 09 12:41:07 PM UTC 24
Finished Oct 09 12:41:18 PM UTC 24
Peak memory 211348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161397954 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_readback_err.1161397954
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_readback_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_regwen.595168857
Short name T132
Test name
Test status
Simulation time 16348207382 ps
CPU time 255.2 seconds
Started Oct 09 12:39:20 PM UTC 24
Finished Oct 09 12:43:38 PM UTC 24
Peak memory 386240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595168857 -assert nopostproc +UVM_TES
TNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.595168857
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_smoke.4061901889
Short name T203
Test name
Test status
Simulation time 556865316 ps
CPU time 27.37 seconds
Started Oct 09 12:36:54 PM UTC 24
Finished Oct 09 12:37:23 PM UTC 24
Peak memory 211204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061901889 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.4061901889
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all.1857385962
Short name T542
Test name
Test status
Simulation time 102196379827 ps
CPU time 3283.2 seconds
Started Oct 09 12:41:12 PM UTC 24
Finished Oct 09 01:36:31 PM UTC 24
Peak memory 399896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18573859
62 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all.1857385962
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1291823145
Short name T65
Test name
Test status
Simulation time 2569312496 ps
CPU time 46.05 seconds
Started Oct 09 12:41:07 PM UTC 24
Finished Oct 09 12:41:54 PM UTC 24
Peak memory 223660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291823145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.1291823145
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_stress_pipeline.644684306
Short name T224
Test name
Test status
Simulation time 4396041688 ps
CPU time 353.33 seconds
Started Oct 09 12:37:40 PM UTC 24
Finished Oct 09 12:43:38 PM UTC 24
Peak memory 211232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644684306 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_pipeline.644684306
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_throughput_w_partial_write.1008002943
Short name T208
Test name
Test status
Simulation time 733569130 ps
CPU time 23.83 seconds
Started Oct 09 12:38:09 PM UTC 24
Finished Oct 09 12:38:34 PM UTC 24
Peak memory 261296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1008002943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_
throughput_w_partial_write.1008002943
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/8.sram_ctrl_throughput_w_partial_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_access_during_key_req.1195559760
Short name T266
Test name
Test status
Simulation time 17498294944 ps
CPU time 638.95 seconds
Started Oct 09 12:42:59 PM UTC 24
Finished Oct 09 12:53:47 PM UTC 24
Peak memory 386104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195559760 -assert nop
ostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_access_durin
g_key_req.1195559760
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_access_during_key_req/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_alert_test.1711588505
Short name T228
Test name
Test status
Simulation time 14474018 ps
CPU time 1 seconds
Started Oct 09 12:45:06 PM UTC 24
Finished Oct 09 12:45:08 PM UTC 24
Peak memory 209432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711588505
-assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_alert_test.1711588505
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_bijection.1680074195
Short name T268
Test name
Test status
Simulation time 164008125593 ps
CPU time 760.1 seconds
Started Oct 09 12:41:21 PM UTC 24
Finished Oct 09 12:54:11 PM UTC 24
Peak memory 211272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680074195 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.1680074195
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_bijection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_lc_escalation.2752637883
Short name T226
Test name
Test status
Simulation time 9689212744 ps
CPU time 66.82 seconds
Started Oct 09 12:42:45 PM UTC 24
Finished Oct 09 12:43:54 PM UTC 24
Peak memory 221480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752637883 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_escalation.2752637883
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_max_throughput.1126153787
Short name T222
Test name
Test status
Simulation time 5207586384 ps
CPU time 60.59 seconds
Started Oct 09 12:41:56 PM UTC 24
Finished Oct 09 12:42:58 PM UTC 24
Peak memory 318584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1126153787 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_m
ax_throughput.1126153787
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_max_throughput/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_partial_access.1259410546
Short name T58
Test name
Test status
Simulation time 1451157501 ps
CPU time 100.85 seconds
Started Oct 09 12:43:55 PM UTC 24
Finished Oct 09 12:45:38 PM UTC 24
Peak memory 228300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259410546 -a
ssert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_mem_partial_access.1259410546
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_mem_walk.3643126785
Short name T235
Test name
Test status
Simulation time 28899117704 ps
CPU time 234.74 seconds
Started Oct 09 12:43:46 PM UTC 24
Finished Oct 09 12:47:44 PM UTC 24
Peak memory 221620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643126785 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_mem_walk.3643126785
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_multiple_keys.3768267969
Short name T239
Test name
Test status
Simulation time 10869846685 ps
CPU time 433.9 seconds
Started Oct 09 12:41:19 PM UTC 24
Finished Oct 09 12:48:38 PM UTC 24
Peak memory 384044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768267969 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multiple_keys.3768267969
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_multiple_keys/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access.1382039825
Short name T219
Test name
Test status
Simulation time 1479989057 ps
CPU time 9.66 seconds
Started Oct 09 12:41:44 PM UTC 24
Finished Oct 09 12:41:54 PM UTC 24
Peak memory 211340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382039825 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_partial_access.1382039825
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_partial_access_b2b.1222136330
Short name T258
Test name
Test status
Simulation time 35251631874 ps
CPU time 607.51 seconds
Started Oct 09 12:41:56 PM UTC 24
Finished Oct 09 12:52:11 PM UTC 24
Peak memory 211528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222136330 -as
sert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_partial_ac
cess_b2b.1222136330
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_partial_access_b2b/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_ram_cfg.3488715569
Short name T225
Test name
Test status
Simulation time 5590504463 ps
CPU time 3.96 seconds
Started Oct 09 12:43:40 PM UTC 24
Finished Oct 09 12:43:45 PM UTC 24
Peak memory 211420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488715569 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.3488715569
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_ram_cfg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_regwen.2446269650
Short name T154
Test name
Test status
Simulation time 2784668883 ps
CPU time 731.88 seconds
Started Oct 09 12:43:39 PM UTC 24
Finished Oct 09 12:56:01 PM UTC 24
Peak memory 382148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446269650 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.2446269650
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_smoke.4134330935
Short name T220
Test name
Test status
Simulation time 3081615368 ps
CPU time 67.47 seconds
Started Oct 09 12:41:19 PM UTC 24
Finished Oct 09 12:42:28 PM UTC 24
Peak memory 369724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134330935 -assert nopostproc +UVM_TE
STNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.4134330935
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all.3144713485
Short name T537
Test name
Test status
Simulation time 122678633695 ps
CPU time 3057.69 seconds
Started Oct 09 12:44:13 PM UTC 24
Finished Oct 09 01:35:42 PM UTC 24
Peak memory 397928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31447134
85 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all.3144713485
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.794618529
Short name T66
Test name
Test status
Simulation time 7381520160 ps
CPU time 58 seconds
Started Oct 09 12:44:08 PM UTC 24
Finished Oct 09 12:45:08 PM UTC 24
Peak memory 227976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +st
ress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794618529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.794618529
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_pipeline.191326471
Short name T236
Test name
Test status
Simulation time 4854948990 ps
CPU time 361.77 seconds
Started Oct 09 12:41:41 PM UTC 24
Finished Oct 09 12:47:48 PM UTC 24
Peak memory 211468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191326471 -assert nopo
stproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_pipeline.191326471
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_stress_pipeline/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_throughput_w_partial_write.3427789958
Short name T221
Test name
Test status
Simulation time 4166448437 ps
CPU time 13.89 seconds
Started Oct 09 12:42:29 PM UTC 24
Finished Oct 09 12:42:44 PM UTC 24
Peak memory 221696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=100000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3427789958 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_
throughput_w_partial_write.3427789958
Directory /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/9.sram_ctrl_throughput_w_partial_write/latest
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