| T799 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access.2694724107 |
|
|
Oct 09 02:10:56 PM UTC 24 |
Oct 09 02:11:51 PM UTC 24 |
959008581 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_readback_err.3209782482 |
|
|
Oct 09 02:11:50 PM UTC 24 |
Oct 09 02:12:02 PM UTC 24 |
707509783 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_lc_escalation.1732126763 |
|
|
Oct 09 02:11:25 PM UTC 24 |
Oct 09 02:12:02 PM UTC 24 |
3569033251 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_alert_test.1835164265 |
|
|
Oct 09 02:12:04 PM UTC 24 |
Oct 09 02:12:06 PM UTC 24 |
11777949 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access_b2b.2269940190 |
|
|
Oct 09 02:03:33 PM UTC 24 |
Oct 09 02:12:11 PM UTC 24 |
84441671566 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.4092870082 |
|
|
Oct 09 02:11:52 PM UTC 24 |
Oct 09 02:12:11 PM UTC 24 |
1771069193 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_pipeline.2786018045 |
|
|
Oct 09 02:08:30 PM UTC 24 |
Oct 09 02:12:15 PM UTC 24 |
4121636527 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_walk.2834261817 |
|
|
Oct 09 02:07:18 PM UTC 24 |
Oct 09 02:12:23 PM UTC 24 |
10506357607 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_smoke.1779714247 |
|
|
Oct 09 02:12:07 PM UTC 24 |
Oct 09 02:12:24 PM UTC 24 |
507054010 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_max_throughput.72736007 |
|
|
Oct 09 02:11:12 PM UTC 24 |
Oct 09 02:12:43 PM UTC 24 |
3061357124 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_executable.2993506959 |
|
|
Oct 09 02:11:31 PM UTC 24 |
Oct 09 02:12:50 PM UTC 24 |
2234439647 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access.683666181 |
|
|
Oct 09 02:12:25 PM UTC 24 |
Oct 09 02:12:56 PM UTC 24 |
1330929467 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_throughput_w_partial_write.2346447156 |
|
|
Oct 09 02:12:52 PM UTC 24 |
Oct 09 02:13:00 PM UTC 24 |
1408284106 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_walk.842142590 |
|
|
Oct 09 02:09:54 PM UTC 24 |
Oct 09 02:13:31 PM UTC 24 |
10789767841 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_max_throughput.21041106 |
|
|
Oct 09 02:12:44 PM UTC 24 |
Oct 09 02:13:32 PM UTC 24 |
764157095 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_executable.1596628130 |
|
|
Oct 09 02:02:08 PM UTC 24 |
Oct 09 02:13:36 PM UTC 24 |
18873465965 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_ram_cfg.1966118642 |
|
|
Oct 09 02:13:37 PM UTC 24 |
Oct 09 02:13:44 PM UTC 24 |
1404977973 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_pipeline.2519306418 |
|
|
Oct 09 02:10:53 PM UTC 24 |
Oct 09 02:14:32 PM UTC 24 |
3659701875 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_lc_escalation.390652218 |
|
|
Oct 09 02:12:57 PM UTC 24 |
Oct 09 02:14:54 PM UTC 24 |
26347422868 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_readback_err.2424740751 |
|
|
Oct 09 02:14:55 PM UTC 24 |
Oct 09 02:15:08 PM UTC 24 |
697576937 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_partial_access.756726612 |
|
|
Oct 09 02:11:41 PM UTC 24 |
Oct 09 02:15:14 PM UTC 24 |
15259473599 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all.1468538528 |
|
|
Oct 09 01:21:15 PM UTC 24 |
Oct 09 02:15:39 PM UTC 24 |
45063609450 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_alert_test.550663054 |
|
|
Oct 09 02:15:40 PM UTC 24 |
Oct 09 02:15:43 PM UTC 24 |
35005897 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_regwen.2744287405 |
|
|
Oct 09 02:07:04 PM UTC 24 |
Oct 09 02:15:55 PM UTC 24 |
10898067101 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_multiple_keys.2320106785 |
|
|
Oct 09 01:58:33 PM UTC 24 |
Oct 09 02:16:10 PM UTC 24 |
21972154056 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_smoke.3701548113 |
|
|
Oct 09 02:15:43 PM UTC 24 |
Oct 09 02:16:22 PM UTC 24 |
1011070807 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_multiple_keys.1759111815 |
|
|
Oct 09 02:00:43 PM UTC 24 |
Oct 09 02:16:29 PM UTC 24 |
101476235935 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_multiple_keys.4209787047 |
|
|
Oct 09 02:03:22 PM UTC 24 |
Oct 09 02:16:33 PM UTC 24 |
19525955530 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.125574064 |
|
|
Oct 09 02:15:08 PM UTC 24 |
Oct 09 02:16:36 PM UTC 24 |
5377981543 ps |
| T89 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_partial_access.545929615 |
|
|
Oct 09 02:14:33 PM UTC 24 |
Oct 09 02:16:38 PM UTC 24 |
10922923678 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access.2456854970 |
|
|
Oct 09 02:16:31 PM UTC 24 |
Oct 09 02:17:08 PM UTC 24 |
1535579090 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_mem_walk.1826301210 |
|
|
Oct 09 02:11:37 PM UTC 24 |
Oct 09 02:17:10 PM UTC 24 |
28206426816 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access_b2b.2030048996 |
|
|
Oct 09 02:08:47 PM UTC 24 |
Oct 09 02:17:23 PM UTC 24 |
180454279655 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_throughput_w_partial_write.2018419211 |
|
|
Oct 09 02:16:39 PM UTC 24 |
Oct 09 02:17:33 PM UTC 24 |
14707966303 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_mem_walk.3042602366 |
|
|
Oct 09 02:13:45 PM UTC 24 |
Oct 09 02:17:47 PM UTC 24 |
10358174337 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_ram_cfg.563190585 |
|
|
Oct 09 02:17:49 PM UTC 24 |
Oct 09 02:17:54 PM UTC 24 |
1471264838 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all.1156649936 |
|
|
Oct 09 01:02:50 PM UTC 24 |
Oct 09 02:18:09 PM UTC 24 |
960989284867 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_max_throughput.2152922696 |
|
|
Oct 09 02:16:37 PM UTC 24 |
Oct 09 02:18:15 PM UTC 24 |
1549376739 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all.3312934865 |
|
|
Oct 09 01:12:24 PM UTC 24 |
Oct 09 02:18:17 PM UTC 24 |
243963711868 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_pipeline.459642097 |
|
|
Oct 09 02:12:17 PM UTC 24 |
Oct 09 02:18:20 PM UTC 24 |
19616146446 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_readback_err.1230108558 |
|
|
Oct 09 02:18:16 PM UTC 24 |
Oct 09 02:18:27 PM UTC 24 |
1274538399 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_partial_access_b2b.3173116738 |
|
|
Oct 09 02:12:25 PM UTC 24 |
Oct 09 02:18:29 PM UTC 24 |
4867501561 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_alert_test.275633400 |
|
|
Oct 09 02:18:27 PM UTC 24 |
Oct 09 02:18:30 PM UTC 24 |
42057040 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_lc_escalation.3303669103 |
|
|
Oct 09 02:17:09 PM UTC 24 |
Oct 09 02:18:43 PM UTC 24 |
8724481784 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_bijection.1930881219 |
|
|
Oct 09 01:41:26 PM UTC 24 |
Oct 09 02:18:48 PM UTC 24 |
30079926593 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_smoke.606668157 |
|
|
Oct 09 02:18:31 PM UTC 24 |
Oct 09 02:18:48 PM UTC 24 |
517857898 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_pipeline.1101215908 |
|
|
Oct 09 02:16:23 PM UTC 24 |
Oct 09 02:18:54 PM UTC 24 |
2106558118 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access.45308054 |
|
|
Oct 09 02:18:49 PM UTC 24 |
Oct 09 02:19:15 PM UTC 24 |
2280746805 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_executable.1599021954 |
|
|
Oct 09 02:09:45 PM UTC 24 |
Oct 09 02:19:19 PM UTC 24 |
30454266700 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_max_throughput.3221827465 |
|
|
Oct 09 02:19:16 PM UTC 24 |
Oct 09 02:20:03 PM UTC 24 |
2880073682 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_partial_access_b2b.3806750539 |
|
|
Oct 09 02:11:01 PM UTC 24 |
Oct 09 02:20:12 PM UTC 24 |
271934267665 ps |
| T145 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1772613022 |
|
|
Oct 09 02:18:18 PM UTC 24 |
Oct 09 02:20:24 PM UTC 24 |
5522818564 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all.1038200452 |
|
|
Oct 09 02:05:18 PM UTC 24 |
Oct 09 02:20:27 PM UTC 24 |
66338855568 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_ram_cfg.3294312764 |
|
|
Oct 09 02:20:28 PM UTC 24 |
Oct 09 02:20:35 PM UTC 24 |
363528573 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_lc_escalation.2999667168 |
|
|
Oct 09 02:19:27 PM UTC 24 |
Oct 09 02:20:42 PM UTC 24 |
8134092339 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_partial_access.668250506 |
|
|
Oct 09 02:18:10 PM UTC 24 |
Oct 09 02:21:01 PM UTC 24 |
7541803179 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_throughput_w_partial_write.583568654 |
|
|
Oct 09 02:19:21 PM UTC 24 |
Oct 09 02:21:05 PM UTC 24 |
2872393572 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_readback_err.2312471668 |
|
|
Oct 09 02:21:02 PM UTC 24 |
Oct 09 02:21:11 PM UTC 24 |
691510763 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_regwen.2046519518 |
|
|
Oct 09 01:59:41 PM UTC 24 |
Oct 09 02:21:22 PM UTC 24 |
15445534310 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_bijection.3748306087 |
|
|
Oct 09 02:03:24 PM UTC 24 |
Oct 09 02:21:25 PM UTC 24 |
153850403933 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_alert_test.674624412 |
|
|
Oct 09 02:21:24 PM UTC 24 |
Oct 09 02:21:26 PM UTC 24 |
77204777 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all.688772852 |
|
|
Oct 09 01:34:21 PM UTC 24 |
Oct 09 02:21:49 PM UTC 24 |
42009307874 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_smoke.754871598 |
|
|
Oct 09 02:21:26 PM UTC 24 |
Oct 09 02:21:52 PM UTC 24 |
1472957802 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_bijection.1326306754 |
|
|
Oct 09 01:49:08 PM UTC 24 |
Oct 09 02:22:02 PM UTC 24 |
72102609152 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_partial_access_b2b.3006336381 |
|
|
Oct 09 02:16:34 PM UTC 24 |
Oct 09 02:22:32 PM UTC 24 |
4109494267 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_access_during_key_req.4276216722 |
|
|
Oct 09 02:17:11 PM UTC 24 |
Oct 09 02:22:46 PM UTC 24 |
6792182087 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1707142398 |
|
|
Oct 09 02:21:06 PM UTC 24 |
Oct 09 02:22:54 PM UTC 24 |
2690600051 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_access_during_key_req.1681823671 |
|
|
Oct 09 02:11:25 PM UTC 24 |
Oct 09 02:23:03 PM UTC 24 |
22625975651 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access.869208474 |
|
|
Oct 09 02:22:03 PM UTC 24 |
Oct 09 02:23:07 PM UTC 24 |
1504154695 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_bijection.1171391719 |
|
|
Oct 09 01:58:49 PM UTC 24 |
Oct 09 02:23:16 PM UTC 24 |
21593869093 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_partial_access_b2b.22274118 |
|
|
Oct 09 02:18:55 PM UTC 24 |
Oct 09 02:23:17 PM UTC 24 |
14694731623 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_throughput_w_partial_write.1776081459 |
|
|
Oct 09 02:22:55 PM UTC 24 |
Oct 09 02:23:23 PM UTC 24 |
758565906 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_executable.638113460 |
|
|
Oct 09 02:06:59 PM UTC 24 |
Oct 09 02:23:29 PM UTC 24 |
43081335548 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_ram_cfg.4142994899 |
|
|
Oct 09 02:23:24 PM UTC 24 |
Oct 09 02:23:30 PM UTC 24 |
347392888 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_access_during_key_req.3992426185 |
|
|
Oct 09 02:04:02 PM UTC 24 |
Oct 09 02:23:33 PM UTC 24 |
15575694549 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_partial_access.1993157260 |
|
|
Oct 09 02:20:44 PM UTC 24 |
Oct 09 02:23:35 PM UTC 24 |
6101013093 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_bijection.633598598 |
|
|
Oct 09 01:55:59 PM UTC 24 |
Oct 09 02:23:43 PM UTC 24 |
22628680499 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_mem_walk.720858282 |
|
|
Oct 09 02:17:55 PM UTC 24 |
Oct 09 02:23:44 PM UTC 24 |
86210445611 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_readback_err.1269560227 |
|
|
Oct 09 02:23:34 PM UTC 24 |
Oct 09 02:23:47 PM UTC 24 |
3008760346 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_alert_test.131015969 |
|
|
Oct 09 02:23:46 PM UTC 24 |
Oct 09 02:23:48 PM UTC 24 |
26218049 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_mem_walk.523255023 |
|
|
Oct 09 02:20:36 PM UTC 24 |
Oct 09 02:23:49 PM UTC 24 |
43104681707 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_smoke.2382765651 |
|
|
Oct 09 02:23:48 PM UTC 24 |
Oct 09 02:24:02 PM UTC 24 |
1668668854 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all.216907803 |
|
|
Oct 09 12:49:27 PM UTC 24 |
Oct 09 02:24:03 PM UTC 24 |
1482878266945 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_regwen.4291718489 |
|
|
Oct 09 02:11:33 PM UTC 24 |
Oct 09 02:24:13 PM UTC 24 |
39744433230 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_multiple_keys.3612598883 |
|
|
Oct 09 02:10:35 PM UTC 24 |
Oct 09 02:24:20 PM UTC 24 |
26699350373 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_max_throughput.1324476968 |
|
|
Oct 09 02:22:47 PM UTC 24 |
Oct 09 02:24:23 PM UTC 24 |
766314591 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_executable.114040590 |
|
|
Oct 09 02:20:14 PM UTC 24 |
Oct 09 02:37:12 PM UTC 24 |
16361505256 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access.654865849 |
|
|
Oct 09 02:24:05 PM UTC 24 |
Oct 09 02:24:27 PM UTC 24 |
3266125014 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_lc_escalation.2283033110 |
|
|
Oct 09 02:23:04 PM UTC 24 |
Oct 09 02:24:30 PM UTC 24 |
120019886405 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_pipeline.499101992 |
|
|
Oct 09 02:21:53 PM UTC 24 |
Oct 09 02:24:30 PM UTC 24 |
2626833426 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_max_throughput.2734508985 |
|
|
Oct 09 02:24:22 PM UTC 24 |
Oct 09 02:24:32 PM UTC 24 |
2806620655 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2886516511 |
|
|
Oct 09 02:23:35 PM UTC 24 |
Oct 09 02:24:43 PM UTC 24 |
5392049798 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_throughput_w_partial_write.714589178 |
|
|
Oct 09 02:24:24 PM UTC 24 |
Oct 09 02:24:44 PM UTC 24 |
1412796519 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_executable.1504180187 |
|
|
Oct 09 02:04:08 PM UTC 24 |
Oct 09 02:24:47 PM UTC 24 |
46323357717 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_ram_cfg.995696338 |
|
|
Oct 09 02:24:44 PM UTC 24 |
Oct 09 02:24:50 PM UTC 24 |
2413995256 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_partial_access.2306944629 |
|
|
Oct 09 02:23:31 PM UTC 24 |
Oct 09 02:24:51 PM UTC 24 |
1463957873 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_regwen.921093964 |
|
|
Oct 09 02:17:33 PM UTC 24 |
Oct 09 02:24:57 PM UTC 24 |
28090711627 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_readback_err.4090979619 |
|
|
Oct 09 02:24:52 PM UTC 24 |
Oct 09 02:25:04 PM UTC 24 |
3684067923 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_alert_test.3428617692 |
|
|
Oct 09 02:25:05 PM UTC 24 |
Oct 09 02:25:06 PM UTC 24 |
29641848 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all.3403217157 |
|
|
Oct 09 01:35:57 PM UTC 24 |
Oct 09 02:25:15 PM UTC 24 |
352890408811 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_pipeline.988894940 |
|
|
Oct 09 02:18:49 PM UTC 24 |
Oct 09 02:25:19 PM UTC 24 |
61699978587 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_bijection.2821985376 |
|
|
Oct 09 02:10:38 PM UTC 24 |
Oct 09 02:25:23 PM UTC 24 |
22574132206 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_partial_access_b2b.3053592033 |
|
|
Oct 09 02:22:34 PM UTC 24 |
Oct 09 02:25:31 PM UTC 24 |
2827694239 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1030232110 |
|
|
Oct 09 02:24:52 PM UTC 24 |
Oct 09 02:25:35 PM UTC 24 |
5507376212 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_smoke.3127873941 |
|
|
Oct 09 02:25:08 PM UTC 24 |
Oct 09 02:25:35 PM UTC 24 |
609359734 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_regwen.299831337 |
|
|
Oct 09 02:20:25 PM UTC 24 |
Oct 09 02:25:38 PM UTC 24 |
1551551990 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access.1161802502 |
|
|
Oct 09 02:25:32 PM UTC 24 |
Oct 09 02:25:43 PM UTC 24 |
687229612 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_executable.991090448 |
|
|
Oct 09 02:23:17 PM UTC 24 |
Oct 09 02:25:49 PM UTC 24 |
6100747804 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_regwen.2188381488 |
|
|
Oct 09 02:13:34 PM UTC 24 |
Oct 09 02:25:55 PM UTC 24 |
7984405920 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_lc_escalation.3723766400 |
|
|
Oct 09 02:24:28 PM UTC 24 |
Oct 09 02:26:00 PM UTC 24 |
38395760545 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_max_throughput.4093647971 |
|
|
Oct 09 02:25:36 PM UTC 24 |
Oct 09 02:26:06 PM UTC 24 |
2817621805 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_ram_cfg.628607210 |
|
|
Oct 09 02:26:06 PM UTC 24 |
Oct 09 02:26:13 PM UTC 24 |
353440474 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_partial_access.1234192158 |
|
|
Oct 09 02:24:48 PM UTC 24 |
Oct 09 02:26:18 PM UTC 24 |
4026117513 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all.3177317364 |
|
|
Oct 09 02:00:26 PM UTC 24 |
Oct 09 02:26:37 PM UTC 24 |
30605072876 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_bijection.4104175655 |
|
|
Oct 09 02:16:11 PM UTC 24 |
Oct 09 02:26:40 PM UTC 24 |
30380736375 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_readback_err.3874056540 |
|
|
Oct 09 02:26:39 PM UTC 24 |
Oct 09 02:26:51 PM UTC 24 |
694366868 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_lc_escalation.2390780657 |
|
|
Oct 09 02:25:44 PM UTC 24 |
Oct 09 02:26:56 PM UTC 24 |
18031217113 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_alert_test.1490105829 |
|
|
Oct 09 02:26:57 PM UTC 24 |
Oct 09 02:26:59 PM UTC 24 |
22420415 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_smoke.2240432899 |
|
|
Oct 09 02:27:01 PM UTC 24 |
Oct 09 02:27:18 PM UTC 24 |
753801648 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_regwen.3379375041 |
|
|
Oct 09 02:09:48 PM UTC 24 |
Oct 09 02:27:18 PM UTC 24 |
13350019411 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_pipeline.2419862614 |
|
|
Oct 09 02:24:03 PM UTC 24 |
Oct 09 02:27:31 PM UTC 24 |
2637939153 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_throughput_w_partial_write.2209247486 |
|
|
Oct 09 02:25:40 PM UTC 24 |
Oct 09 02:27:38 PM UTC 24 |
3412673053 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access.2824511584 |
|
|
Oct 09 02:27:39 PM UTC 24 |
Oct 09 02:27:49 PM UTC 24 |
700117016 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_executable.1413053780 |
|
|
Oct 09 02:13:32 PM UTC 24 |
Oct 09 02:27:59 PM UTC 24 |
26455548499 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_pipeline.3228700974 |
|
|
Oct 09 02:25:25 PM UTC 24 |
Oct 09 02:28:03 PM UTC 24 |
2347234306 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_mem_walk.2595039977 |
|
|
Oct 09 02:23:30 PM UTC 24 |
Oct 09 02:28:40 PM UTC 24 |
18760360744 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all.20415957 |
|
|
Oct 09 12:56:01 PM UTC 24 |
Oct 09 02:28:52 PM UTC 24 |
523938683516 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_max_throughput.1921043832 |
|
|
Oct 09 02:27:59 PM UTC 24 |
Oct 09 02:29:04 PM UTC 24 |
2724489535 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_throughput_w_partial_write.1782967975 |
|
|
Oct 09 02:28:04 PM UTC 24 |
Oct 09 02:29:18 PM UTC 24 |
774148421 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all.1202577977 |
|
|
Oct 09 01:28:35 PM UTC 24 |
Oct 09 02:29:20 PM UTC 24 |
236012077435 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_ram_cfg.3549328961 |
|
|
Oct 09 02:29:21 PM UTC 24 |
Oct 09 02:29:28 PM UTC 24 |
362830995 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_access_during_key_req.361109548 |
|
|
Oct 09 02:24:31 PM UTC 24 |
Oct 09 02:29:28 PM UTC 24 |
10252961854 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_mem_walk.3543298604 |
|
|
Oct 09 02:24:45 PM UTC 24 |
Oct 09 02:29:39 PM UTC 24 |
16416225968 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_partial_access.1480880893 |
|
|
Oct 09 02:26:20 PM UTC 24 |
Oct 09 02:29:41 PM UTC 24 |
26967006002 ps |
| T146 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1500634533 |
|
|
Oct 09 02:26:41 PM UTC 24 |
Oct 09 02:29:46 PM UTC 24 |
3155020174 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_access_during_key_req.931561910 |
|
|
Oct 09 02:20:04 PM UTC 24 |
Oct 09 02:29:49 PM UTC 24 |
52635301223 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_alert_test.2788024379 |
|
|
Oct 09 02:29:50 PM UTC 24 |
Oct 09 02:29:52 PM UTC 24 |
17936250 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_readback_err.2959382033 |
|
|
Oct 09 02:29:40 PM UTC 24 |
Oct 09 02:29:52 PM UTC 24 |
1327527463 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_access_during_key_req.1000771346 |
|
|
Oct 09 02:13:01 PM UTC 24 |
Oct 09 02:29:57 PM UTC 24 |
33462857367 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_partial_access_b2b.1102442136 |
|
|
Oct 09 02:25:36 PM UTC 24 |
Oct 09 02:30:32 PM UTC 24 |
4885663208 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.2079361131 |
|
|
Oct 09 02:29:42 PM UTC 24 |
Oct 09 02:30:33 PM UTC 24 |
1777414649 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_executable.807486102 |
|
|
Oct 09 02:17:24 PM UTC 24 |
Oct 09 02:30:38 PM UTC 24 |
16408952017 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_partial_access.2248060238 |
|
|
Oct 09 02:29:30 PM UTC 24 |
Oct 09 02:31:01 PM UTC 24 |
2496800871 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_lc_escalation.751329908 |
|
|
Oct 09 02:28:41 PM UTC 24 |
Oct 09 02:31:03 PM UTC 24 |
19464031113 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_bijection.2348405927 |
|
|
Oct 09 02:21:50 PM UTC 24 |
Oct 09 02:31:25 PM UTC 24 |
37291693598 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_partial_access_b2b.3841419819 |
|
|
Oct 09 02:24:14 PM UTC 24 |
Oct 09 02:31:26 PM UTC 24 |
13293740630 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_multiple_keys.3603611355 |
|
|
Oct 09 02:15:57 PM UTC 24 |
Oct 09 02:31:30 PM UTC 24 |
8362207909 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_pipeline.2092355519 |
|
|
Oct 09 02:27:31 PM UTC 24 |
Oct 09 02:32:20 PM UTC 24 |
4964496295 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all.189808237 |
|
|
Oct 09 01:19:41 PM UTC 24 |
Oct 09 02:32:56 PM UTC 24 |
786781058669 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_bijection.953387634 |
|
|
Oct 09 02:18:44 PM UTC 24 |
Oct 09 02:33:18 PM UTC 24 |
300584863829 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all.1124685772 |
|
|
Oct 09 02:07:48 PM UTC 24 |
Oct 09 02:34:00 PM UTC 24 |
44603960146 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_mem_walk.2426932930 |
|
|
Oct 09 02:26:14 PM UTC 24 |
Oct 09 02:34:01 PM UTC 24 |
42274766080 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_regwen.943508996 |
|
|
Oct 09 02:24:34 PM UTC 24 |
Oct 09 02:34:13 PM UTC 24 |
11486991889 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_regwen.2947355729 |
|
|
Oct 09 02:23:18 PM UTC 24 |
Oct 09 02:34:20 PM UTC 24 |
8611715984 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_partial_access_b2b.3714813981 |
|
|
Oct 09 02:27:49 PM UTC 24 |
Oct 09 02:34:23 PM UTC 24 |
15913309571 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_bijection.3778103061 |
|
|
Oct 09 02:25:20 PM UTC 24 |
Oct 09 02:35:25 PM UTC 24 |
39084157357 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_mem_walk.3616892283 |
|
|
Oct 09 02:29:30 PM UTC 24 |
Oct 09 02:35:34 PM UTC 24 |
18685763251 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_multiple_keys.3915451418 |
|
|
Oct 09 02:27:19 PM UTC 24 |
Oct 09 02:36:00 PM UTC 24 |
20588810739 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_multiple_keys.2567050048 |
|
|
Oct 09 02:08:11 PM UTC 24 |
Oct 09 02:36:32 PM UTC 24 |
26154892882 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all.67228823 |
|
|
Oct 09 01:23:48 PM UTC 24 |
Oct 09 02:36:50 PM UTC 24 |
41426963175 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all.1997724144 |
|
|
Oct 09 01:55:07 PM UTC 24 |
Oct 09 02:37:00 PM UTC 24 |
204049943887 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_multiple_keys.1890043045 |
|
|
Oct 09 02:21:27 PM UTC 24 |
Oct 09 02:37:07 PM UTC 24 |
8062393853 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all.1416675056 |
|
|
Oct 09 12:52:08 PM UTC 24 |
Oct 09 02:37:09 PM UTC 24 |
245802519281 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_multiple_keys.3821577752 |
|
|
Oct 09 02:18:31 PM UTC 24 |
Oct 09 02:37:23 PM UTC 24 |
22987995751 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_executable.4183119982 |
|
|
Oct 09 02:24:32 PM UTC 24 |
Oct 09 02:38:19 PM UTC 24 |
55071327174 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_access_during_key_req.3459856486 |
|
|
Oct 09 02:09:32 PM UTC 24 |
Oct 09 02:38:25 PM UTC 24 |
21810651505 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_access_during_key_req.1019039527 |
|
|
Oct 09 02:06:59 PM UTC 24 |
Oct 09 02:38:28 PM UTC 24 |
98066821015 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_executable.1891860200 |
|
|
Oct 09 02:29:05 PM UTC 24 |
Oct 09 02:40:08 PM UTC 24 |
26432413084 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_multiple_keys.3824773961 |
|
|
Oct 09 02:25:16 PM UTC 24 |
Oct 09 02:40:49 PM UTC 24 |
50564637867 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all.4009889708 |
|
|
Oct 09 01:26:15 PM UTC 24 |
Oct 09 02:42:33 PM UTC 24 |
499519251263 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_access_during_key_req.1794036002 |
|
|
Oct 09 02:25:50 PM UTC 24 |
Oct 09 02:44:14 PM UTC 24 |
236877778672 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all.2219267637 |
|
|
Oct 09 01:46:07 PM UTC 24 |
Oct 09 02:44:17 PM UTC 24 |
106615581861 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_executable.1876107218 |
|
|
Oct 09 02:25:56 PM UTC 24 |
Oct 09 02:45:04 PM UTC 24 |
45339728411 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all.1638348512 |
|
|
Oct 09 01:48:49 PM UTC 24 |
Oct 09 02:45:04 PM UTC 24 |
37737121852 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_multiple_keys.1189456745 |
|
|
Oct 09 02:12:12 PM UTC 24 |
Oct 09 02:45:12 PM UTC 24 |
30632472276 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_regwen.526142273 |
|
|
Oct 09 02:29:19 PM UTC 24 |
Oct 09 02:45:38 PM UTC 24 |
11305943686 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_access_during_key_req.3980954369 |
|
|
Oct 09 02:23:08 PM UTC 24 |
Oct 09 02:46:05 PM UTC 24 |
19662050623 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_regwen.1095189445 |
|
|
Oct 09 02:26:01 PM UTC 24 |
Oct 09 02:47:45 PM UTC 24 |
14845532102 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_stress_all.660291439 |
|
|
Oct 09 02:15:15 PM UTC 24 |
Oct 09 02:47:47 PM UTC 24 |
16371274705 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_access_during_key_req.1965953983 |
|
|
Oct 09 02:28:53 PM UTC 24 |
Oct 09 02:48:18 PM UTC 24 |
48269705500 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all.2890629895 |
|
|
Oct 09 01:51:21 PM UTC 24 |
Oct 09 02:48:28 PM UTC 24 |
104984618083 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_bijection.1362477968 |
|
|
Oct 09 02:00:50 PM UTC 24 |
Oct 09 02:50:03 PM UTC 24 |
749228612630 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all.1251042025 |
|
|
Oct 09 01:38:17 PM UTC 24 |
Oct 09 02:50:03 PM UTC 24 |
1293753676435 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_bijection.70100184 |
|
|
Oct 09 02:23:51 PM UTC 24 |
Oct 09 02:51:47 PM UTC 24 |
102813448861 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/48.sram_ctrl_stress_all.3413685763 |
|
|
Oct 09 02:26:52 PM UTC 24 |
Oct 09 02:54:14 PM UTC 24 |
342529347081 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_bijection.657883982 |
|
|
Oct 09 02:06:05 PM UTC 24 |
Oct 09 02:57:10 PM UTC 24 |
112698257278 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/43.sram_ctrl_bijection.2325978776 |
|
|
Oct 09 02:12:12 PM UTC 24 |
Oct 09 03:02:43 PM UTC 24 |
634362418474 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_bijection.1665411784 |
|
|
Oct 09 02:08:24 PM UTC 24 |
Oct 09 03:03:42 PM UTC 24 |
169011613885 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_stress_all.156226079 |
|
|
Oct 09 02:12:04 PM UTC 24 |
Oct 09 03:04:17 PM UTC 24 |
32740364244 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all.2234875844 |
|
|
Oct 09 01:58:13 PM UTC 24 |
Oct 09 03:06:11 PM UTC 24 |
141992874020 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_bijection.13875915 |
|
|
Oct 09 02:27:20 PM UTC 24 |
Oct 09 03:12:48 PM UTC 24 |
261779710061 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/49.sram_ctrl_stress_all.2194267747 |
|
|
Oct 09 02:29:47 PM UTC 24 |
Oct 09 03:16:30 PM UTC 24 |
49558286919 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/46.sram_ctrl_stress_all.1856152264 |
|
|
Oct 09 02:23:45 PM UTC 24 |
Oct 09 03:18:32 PM UTC 24 |
89757956114 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all.3330091172 |
|
|
Oct 09 02:10:19 PM UTC 24 |
Oct 09 03:30:53 PM UTC 24 |
113027153232 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/47.sram_ctrl_stress_all.3886708632 |
|
|
Oct 09 02:24:58 PM UTC 24 |
Oct 09 03:42:58 PM UTC 24 |
700360470816 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all.4202718038 |
|
|
Oct 09 02:03:08 PM UTC 24 |
Oct 09 04:09:20 PM UTC 24 |
197678767652 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/45.sram_ctrl_stress_all.649452088 |
|
|
Oct 09 02:21:12 PM UTC 24 |
Oct 09 04:12:50 PM UTC 24 |
875750000689 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/44.sram_ctrl_stress_all.1859053481 |
|
|
Oct 09 02:18:21 PM UTC 24 |
Oct 09 04:14:20 PM UTC 24 |
1460109771913 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2342138767 |
|
|
Oct 09 10:09:31 AM UTC 24 |
Oct 09 10:09:33 AM UTC 24 |
42308774 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2034153356 |
|
|
Oct 09 10:09:31 AM UTC 24 |
Oct 09 10:09:33 AM UTC 24 |
22456451 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.444408866 |
|
|
Oct 09 10:09:31 AM UTC 24 |
Oct 09 10:09:34 AM UTC 24 |
210103162 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1520453853 |
|
|
Oct 09 10:09:32 AM UTC 24 |
Oct 09 10:09:34 AM UTC 24 |
22874560 ps |
| T97 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3490424267 |
|
|
Oct 09 10:09:32 AM UTC 24 |
Oct 09 10:09:34 AM UTC 24 |
19206255 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.890781814 |
|
|
Oct 09 10:09:31 AM UTC 24 |
Oct 09 10:09:35 AM UTC 24 |
621683634 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_tl_errors.185598413 |
|
|
Oct 09 10:09:29 AM UTC 24 |
Oct 09 10:09:36 AM UTC 24 |
92499610 ps |
| T98 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_rw.633697829 |
|
|
Oct 09 10:09:35 AM UTC 24 |
Oct 09 10:09:37 AM UTC 24 |
11736559 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1436522902 |
|
|
Oct 09 10:09:35 AM UTC 24 |
Oct 09 10:09:37 AM UTC 24 |
51024826 ps |
| T99 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.346917829 |
|
|
Oct 09 10:09:35 AM UTC 24 |
Oct 09 10:09:37 AM UTC 24 |
20269248 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1444967382 |
|
|
Oct 09 10:09:35 AM UTC 24 |
Oct 09 10:09:37 AM UTC 24 |
22763698 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2612045579 |
|
|
Oct 09 10:09:33 AM UTC 24 |
Oct 09 10:09:38 AM UTC 24 |
1256588679 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2945805891 |
|
|
Oct 09 10:09:35 AM UTC 24 |
Oct 09 10:09:38 AM UTC 24 |
374372374 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.66505225 |
|
|
Oct 09 10:09:32 AM UTC 24 |
Oct 09 10:09:39 AM UTC 24 |
352018905 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2522519105 |
|
|
Oct 09 10:09:33 AM UTC 24 |
Oct 09 10:09:40 AM UTC 24 |
107836082 ps |
| T72 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_rw.485777188 |
|
|
Oct 09 10:09:38 AM UTC 24 |
Oct 09 10:09:40 AM UTC 24 |
46060737 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2967025671 |
|
|
Oct 09 10:09:38 AM UTC 24 |
Oct 09 10:09:40 AM UTC 24 |
21507068 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2387003505 |
|
|
Oct 09 10:09:39 AM UTC 24 |
Oct 09 10:09:41 AM UTC 24 |
45620029 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_errors.794717033 |
|
|
Oct 09 10:09:37 AM UTC 24 |
Oct 09 10:09:41 AM UTC 24 |
123376188 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1725555156 |
|
|
Oct 09 10:09:36 AM UTC 24 |
Oct 09 10:09:41 AM UTC 24 |
363835139 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3856646672 |
|
|
Oct 09 10:09:39 AM UTC 24 |
Oct 09 10:09:42 AM UTC 24 |
45938961 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.4012557481 |
|
|
Oct 09 10:09:37 AM UTC 24 |
Oct 09 10:09:42 AM UTC 24 |
195674919 ps |
| T100 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.936308777 |
|
|
Oct 09 10:09:40 AM UTC 24 |
Oct 09 10:09:42 AM UTC 24 |
22116280 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3405468819 |
|
|
Oct 09 10:09:41 AM UTC 24 |
Oct 09 10:09:46 AM UTC 24 |
15570406 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.506167649 |
|
|
Oct 09 10:09:40 AM UTC 24 |
Oct 09 10:09:46 AM UTC 24 |
724886403 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2364689593 |
|
|
Oct 09 10:09:42 AM UTC 24 |
Oct 09 10:09:48 AM UTC 24 |
49051947 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1876484718 |
|
|
Oct 09 10:09:43 AM UTC 24 |
Oct 09 10:09:48 AM UTC 24 |
22805008 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.98120302 |
|
|
Oct 09 10:09:43 AM UTC 24 |
Oct 09 10:09:48 AM UTC 24 |
42954926 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.653830701 |
|
|
Oct 09 10:09:41 AM UTC 24 |
Oct 09 10:09:48 AM UTC 24 |
1472774562 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1966248864 |
|
|
Oct 09 10:09:42 AM UTC 24 |
Oct 09 10:09:49 AM UTC 24 |
411088620 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_tl_errors.33748730 |
|
|
Oct 09 10:09:41 AM UTC 24 |
Oct 09 10:09:52 AM UTC 24 |
147823810 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.301428978 |
|
|
Oct 09 10:10:16 AM UTC 24 |
Oct 09 10:10:20 AM UTC 24 |
379775387 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3900259730 |
|
|
Oct 09 10:09:50 AM UTC 24 |
Oct 09 10:09:54 AM UTC 24 |
14103940 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.799292030 |
|
|
Oct 09 10:09:50 AM UTC 24 |
Oct 09 10:09:54 AM UTC 24 |
39779734 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1528791809 |
|
|
Oct 09 10:09:50 AM UTC 24 |
Oct 09 10:09:54 AM UTC 24 |
17865416 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3799817957 |
|
|
Oct 09 10:09:43 AM UTC 24 |
Oct 09 10:09:54 AM UTC 24 |
1814372003 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.4140165279 |
|
|
Oct 09 10:09:50 AM UTC 24 |
Oct 09 10:09:54 AM UTC 24 |
56892773 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2818885844 |
|
|
Oct 09 10:09:48 AM UTC 24 |
Oct 09 10:09:55 AM UTC 24 |
79056407 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3127319775 |
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|
Oct 09 10:09:48 AM UTC 24 |
Oct 09 10:09:56 AM UTC 24 |
776141253 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3454854929 |
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|
Oct 09 10:09:50 AM UTC 24 |
Oct 09 10:09:56 AM UTC 24 |
679891566 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_rw.4077131044 |
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|
Oct 09 10:09:55 AM UTC 24 |
Oct 09 10:09:57 AM UTC 24 |
28731178 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.9365998 |
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|
Oct 09 10:09:55 AM UTC 24 |
Oct 09 10:09:57 AM UTC 24 |
35536937 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1342321632 |
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|
Oct 09 10:09:55 AM UTC 24 |
Oct 09 10:09:58 AM UTC 24 |
96970661 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3031886717 |
|
|
Oct 09 10:09:58 AM UTC 24 |
Oct 09 10:10:00 AM UTC 24 |
62216735 ps |
| T104 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1960157127 |
|
|
Oct 09 10:09:58 AM UTC 24 |
Oct 09 10:10:00 AM UTC 24 |
15764146 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3487167937 |
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|
Oct 09 10:09:57 AM UTC 24 |
Oct 09 10:10:01 AM UTC 24 |
705841140 ps |
| T1011 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3560467562 |
|
|
Oct 09 10:09:52 AM UTC 24 |
Oct 09 10:10:01 AM UTC 24 |
1360936859 ps |
| T1012 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_tl_errors.4214918514 |
|
|
Oct 09 10:09:56 AM UTC 24 |
Oct 09 10:10:01 AM UTC 24 |
52796006 ps |
| T1013 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3013479674 |
|
|
Oct 09 10:09:55 AM UTC 24 |
Oct 09 10:10:02 AM UTC 24 |
273628437 ps |
| T1014 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3177565683 |
|
|
Oct 09 10:09:55 AM UTC 24 |
Oct 09 10:10:02 AM UTC 24 |
1507022523 ps |
| T1015 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2350843688 |
|
|
Oct 09 10:10:00 AM UTC 24 |
Oct 09 10:10:04 AM UTC 24 |
380071209 ps |
| T1016 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2539730377 |
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|
Oct 09 10:10:02 AM UTC 24 |
Oct 09 10:10:04 AM UTC 24 |
29672902 ps |