| T551 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_regwen.3330673475 |
|
|
Oct 09 01:22:44 PM UTC 24 |
Oct 09 01:37:24 PM UTC 24 |
12582549562 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.3463013974 |
|
|
Oct 09 01:36:54 PM UTC 24 |
Oct 09 01:37:24 PM UTC 24 |
2287337916 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.278106351 |
|
|
Oct 09 01:37:25 PM UTC 24 |
Oct 09 01:37:34 PM UTC 24 |
5611456309 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.1112682861 |
|
|
Oct 09 01:37:10 PM UTC 24 |
Oct 09 01:37:43 PM UTC 24 |
3559477188 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_regwen.116183509 |
|
|
Oct 09 01:25:12 PM UTC 24 |
Oct 09 01:37:48 PM UTC 24 |
31947610534 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_readback_err.1936897087 |
|
|
Oct 09 01:37:50 PM UTC 24 |
Oct 09 01:38:02 PM UTC 24 |
2352309204 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1585971131 |
|
|
Oct 09 01:38:03 PM UTC 24 |
Oct 09 01:38:16 PM UTC 24 |
1196209603 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.64999906 |
|
|
Oct 09 01:37:01 PM UTC 24 |
Oct 09 01:38:38 PM UTC 24 |
3268450050 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_alert_test.250880083 |
|
|
Oct 09 01:38:39 PM UTC 24 |
Oct 09 01:38:41 PM UTC 24 |
36977636 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_executable.2870036264 |
|
|
Oct 09 01:18:08 PM UTC 24 |
Oct 09 01:38:47 PM UTC 24 |
18440977926 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.733572929 |
|
|
Oct 09 01:34:52 PM UTC 24 |
Oct 09 01:38:57 PM UTC 24 |
10387950164 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access_b2b.3652306790 |
|
|
Oct 09 01:33:03 PM UTC 24 |
Oct 09 01:39:03 PM UTC 24 |
18894437635 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_smoke.2026118412 |
|
|
Oct 09 01:38:42 PM UTC 24 |
Oct 09 01:39:09 PM UTC 24 |
1353880979 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_partial_access.2727192136 |
|
|
Oct 09 01:37:44 PM UTC 24 |
Oct 09 01:39:13 PM UTC 24 |
972440925 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_multiple_keys.4100829727 |
|
|
Oct 09 01:21:23 PM UTC 24 |
Oct 09 01:39:20 PM UTC 24 |
51060970471 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.2565815203 |
|
|
Oct 09 01:37:21 PM UTC 24 |
Oct 09 01:39:26 PM UTC 24 |
2256371307 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access.2183345873 |
|
|
Oct 09 01:39:10 PM UTC 24 |
Oct 09 01:39:30 PM UTC 24 |
1634861400 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_throughput_w_partial_write.1159612410 |
|
|
Oct 09 01:39:27 PM UTC 24 |
Oct 09 01:39:40 PM UTC 24 |
726749562 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_executable.2311530262 |
|
|
Oct 09 01:33:50 PM UTC 24 |
Oct 09 01:39:45 PM UTC 24 |
5122442732 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_max_throughput.2760517814 |
|
|
Oct 09 01:39:20 PM UTC 24 |
Oct 09 01:39:54 PM UTC 24 |
1797278020 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access_b2b.3403550498 |
|
|
Oct 09 01:35:09 PM UTC 24 |
Oct 09 01:40:06 PM UTC 24 |
17177318275 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.632432560 |
|
|
Oct 09 01:32:22 PM UTC 24 |
Oct 09 01:40:10 PM UTC 24 |
37488584349 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_ram_cfg.2855248424 |
|
|
Oct 09 01:40:07 PM UTC 24 |
Oct 09 01:40:14 PM UTC 24 |
2130781148 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_mem_walk.198687817 |
|
|
Oct 09 01:37:35 PM UTC 24 |
Oct 09 01:40:23 PM UTC 24 |
1981201138 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_readback_err.1106446431 |
|
|
Oct 09 01:40:24 PM UTC 24 |
Oct 09 01:40:35 PM UTC 24 |
1324533973 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.3560623231 |
|
|
Oct 09 01:34:02 PM UTC 24 |
Oct 09 01:40:44 PM UTC 24 |
20694441849 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_regwen.848570896 |
|
|
Oct 09 01:18:09 PM UTC 24 |
Oct 09 01:41:14 PM UTC 24 |
43928346111 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_alert_test.3459763772 |
|
|
Oct 09 01:41:15 PM UTC 24 |
Oct 09 01:41:17 PM UTC 24 |
15202850 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.3848007094 |
|
|
Oct 09 01:35:43 PM UTC 24 |
Oct 09 01:41:19 PM UTC 24 |
65627586980 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_executable.1200654183 |
|
|
Oct 09 01:20:36 PM UTC 24 |
Oct 09 01:41:24 PM UTC 24 |
37351860085 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_smoke.4109032899 |
|
|
Oct 09 01:41:18 PM UTC 24 |
Oct 09 01:41:47 PM UTC 24 |
6002488112 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_partial_access.1356418714 |
|
|
Oct 09 01:40:15 PM UTC 24 |
Oct 09 01:41:49 PM UTC 24 |
2285766381 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_executable.3188903474 |
|
|
Oct 09 01:37:22 PM UTC 24 |
Oct 09 01:41:53 PM UTC 24 |
15900977223 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_lc_escalation.1576237881 |
|
|
Oct 09 01:39:30 PM UTC 24 |
Oct 09 01:41:56 PM UTC 24 |
27994239318 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_multiple_keys.286707692 |
|
|
Oct 09 01:26:29 PM UTC 24 |
Oct 09 01:42:11 PM UTC 24 |
44039664913 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_max_throughput.583512719 |
|
|
Oct 09 01:41:57 PM UTC 24 |
Oct 09 01:42:28 PM UTC 24 |
2393468405 ps |
| T50 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.1124173788 |
|
|
Oct 09 01:40:36 PM UTC 24 |
Oct 09 01:42:35 PM UTC 24 |
3538509093 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access.263067461 |
|
|
Oct 09 01:41:50 PM UTC 24 |
Oct 09 01:42:40 PM UTC 24 |
3417171735 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access_b2b.1373814127 |
|
|
Oct 09 01:36:45 PM UTC 24 |
Oct 09 01:43:06 PM UTC 24 |
6497445887 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_executable.2776395206 |
|
|
Oct 09 01:22:39 PM UTC 24 |
Oct 09 01:43:18 PM UTC 24 |
38379068573 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_pipeline.2787915863 |
|
|
Oct 09 01:39:04 PM UTC 24 |
Oct 09 01:43:19 PM UTC 24 |
10920437615 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_ram_cfg.376119197 |
|
|
Oct 09 01:43:19 PM UTC 24 |
Oct 09 01:43:27 PM UTC 24 |
1401940417 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.1182688524 |
|
|
Oct 09 01:30:32 PM UTC 24 |
Oct 09 01:43:35 PM UTC 24 |
26985498481 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_readback_err.1818886353 |
|
|
Oct 09 01:43:36 PM UTC 24 |
Oct 09 01:43:46 PM UTC 24 |
4388480025 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_regwen.2902922737 |
|
|
Oct 09 01:30:54 PM UTC 24 |
Oct 09 01:43:51 PM UTC 24 |
57595693168 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_stress_pipeline.1037886974 |
|
|
Oct 09 01:36:35 PM UTC 24 |
Oct 09 01:44:03 PM UTC 24 |
12857154390 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_throughput_w_partial_write.3225016313 |
|
|
Oct 09 01:42:12 PM UTC 24 |
Oct 09 01:44:06 PM UTC 24 |
789867162 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_alert_test.4274787024 |
|
|
Oct 09 01:44:04 PM UTC 24 |
Oct 09 01:44:06 PM UTC 24 |
21027432 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_lc_escalation.2525803711 |
|
|
Oct 09 01:42:29 PM UTC 24 |
Oct 09 01:44:16 PM UTC 24 |
81836777541 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.1058082911 |
|
|
Oct 09 01:25:08 PM UTC 24 |
Oct 09 01:44:17 PM UTC 24 |
15411446518 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_smoke.3219890629 |
|
|
Oct 09 01:44:06 PM UTC 24 |
Oct 09 01:44:20 PM UTC 24 |
3077652649 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_executable.342284185 |
|
|
Oct 09 01:27:42 PM UTC 24 |
Oct 09 01:44:29 PM UTC 24 |
20079230268 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.2172144632 |
|
|
Oct 09 01:43:47 PM UTC 24 |
Oct 09 01:44:35 PM UTC 24 |
1187409086 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_mem_walk.1727709900 |
|
|
Oct 09 01:40:10 PM UTC 24 |
Oct 09 01:44:36 PM UTC 24 |
54476079521 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access.3199055031 |
|
|
Oct 09 01:44:21 PM UTC 24 |
Oct 09 01:44:50 PM UTC 24 |
1110150220 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_max_throughput.1181001247 |
|
|
Oct 09 01:44:36 PM UTC 24 |
Oct 09 01:45:01 PM UTC 24 |
1436989056 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_partial_access.4232723190 |
|
|
Oct 09 01:43:28 PM UTC 24 |
Oct 09 01:45:15 PM UTC 24 |
1449875936 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_bijection.1211367215 |
|
|
Oct 09 01:07:05 PM UTC 24 |
Oct 09 01:45:29 PM UTC 24 |
100607060223 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_throughput_w_partial_write.1859332764 |
|
|
Oct 09 01:44:37 PM UTC 24 |
Oct 09 01:45:32 PM UTC 24 |
12235378224 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_ram_cfg.504900350 |
|
|
Oct 09 01:45:33 PM UTC 24 |
Oct 09 01:45:40 PM UTC 24 |
366890876 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.2278033193 |
|
|
Oct 09 01:36:19 PM UTC 24 |
Oct 09 01:45:55 PM UTC 24 |
8779494187 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_stress_all.1506643624 |
|
|
Oct 09 01:00:45 PM UTC 24 |
Oct 09 01:45:56 PM UTC 24 |
157764004107 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_mem_walk.1882858838 |
|
|
Oct 09 01:43:19 PM UTC 24 |
Oct 09 01:46:00 PM UTC 24 |
21512397267 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_readback_err.3294537884 |
|
|
Oct 09 01:45:57 PM UTC 24 |
Oct 09 01:46:06 PM UTC 24 |
1346821971 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_access_during_key_req.1032689004 |
|
|
Oct 09 01:39:41 PM UTC 24 |
Oct 09 01:46:10 PM UTC 24 |
14766503611 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_alert_test.1919777407 |
|
|
Oct 09 01:46:11 PM UTC 24 |
Oct 09 01:46:13 PM UTC 24 |
27417529 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.625120993 |
|
|
Oct 09 01:46:02 PM UTC 24 |
Oct 09 01:46:14 PM UTC 24 |
638376065 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_lc_escalation.510308700 |
|
|
Oct 09 01:44:50 PM UTC 24 |
Oct 09 01:46:40 PM UTC 24 |
11648922415 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.4152416493 |
|
|
Oct 09 01:16:16 PM UTC 24 |
Oct 09 01:46:42 PM UTC 24 |
117751973633 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_pipeline.6453350 |
|
|
Oct 09 01:41:48 PM UTC 24 |
Oct 09 01:46:42 PM UTC 24 |
19133969511 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_partial_access_b2b.3548610435 |
|
|
Oct 09 01:41:54 PM UTC 24 |
Oct 09 01:46:49 PM UTC 24 |
11832294035 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_bijection.2058770356 |
|
|
Oct 09 01:29:27 PM UTC 24 |
Oct 09 01:47:07 PM UTC 24 |
55380400763 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_max_throughput.3875902305 |
|
|
Oct 09 01:47:08 PM UTC 24 |
Oct 09 01:47:16 PM UTC 24 |
1815775699 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_regwen.805423266 |
|
|
Oct 09 01:43:07 PM UTC 24 |
Oct 09 01:47:39 PM UTC 24 |
7196287160 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access.2708246254 |
|
|
Oct 09 01:46:44 PM UTC 24 |
Oct 09 01:47:39 PM UTC 24 |
2225495583 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_lc_escalation.742142991 |
|
|
Oct 09 01:47:39 PM UTC 24 |
Oct 09 01:48:00 PM UTC 24 |
7943562352 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_smoke.3106156186 |
|
|
Oct 09 01:46:14 PM UTC 24 |
Oct 09 01:48:02 PM UTC 24 |
13339767685 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_throughput_w_partial_write.1026609293 |
|
|
Oct 09 01:47:17 PM UTC 24 |
Oct 09 01:48:05 PM UTC 24 |
761148409 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_executable.3955913221 |
|
|
Oct 09 01:35:27 PM UTC 24 |
Oct 09 01:48:08 PM UTC 24 |
92668143596 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_ram_cfg.2709046033 |
|
|
Oct 09 01:48:06 PM UTC 24 |
Oct 09 01:48:13 PM UTC 24 |
1401600862 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_partial_access.2858422872 |
|
|
Oct 09 01:45:55 PM UTC 24 |
Oct 09 01:48:35 PM UTC 24 |
17594886421 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_readback_err.3236789041 |
|
|
Oct 09 01:48:35 PM UTC 24 |
Oct 09 01:48:47 PM UTC 24 |
1376841542 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_mem_walk.2812886522 |
|
|
Oct 09 01:45:41 PM UTC 24 |
Oct 09 01:48:48 PM UTC 24 |
99768783480 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_partial_access_b2b.1649188357 |
|
|
Oct 09 01:39:14 PM UTC 24 |
Oct 09 01:49:04 PM UTC 24 |
37563496423 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_regwen.1823971521 |
|
|
Oct 09 01:33:57 PM UTC 24 |
Oct 09 01:49:04 PM UTC 24 |
9310233303 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_regwen.536458107 |
|
|
Oct 09 01:35:33 PM UTC 24 |
Oct 09 01:49:07 PM UTC 24 |
39925618107 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_alert_test.3634997691 |
|
|
Oct 09 01:49:05 PM UTC 24 |
Oct 09 01:49:07 PM UTC 24 |
113927034 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_partial_access_b2b.2111407354 |
|
|
Oct 09 01:44:30 PM UTC 24 |
Oct 09 01:49:15 PM UTC 24 |
23400543928 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_bijection.151511993 |
|
|
Oct 09 01:19:48 PM UTC 24 |
Oct 09 01:49:18 PM UTC 24 |
69277704187 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access.3742619662 |
|
|
Oct 09 01:49:19 PM UTC 24 |
Oct 09 01:49:36 PM UTC 24 |
864261239 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_partial_access.1361883399 |
|
|
Oct 09 01:48:14 PM UTC 24 |
Oct 09 01:49:38 PM UTC 24 |
4722355805 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3589922072 |
|
|
Oct 09 01:48:48 PM UTC 24 |
Oct 09 01:50:03 PM UTC 24 |
1381208923 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_smoke.1603591627 |
|
|
Oct 09 01:49:05 PM UTC 24 |
Oct 09 01:50:35 PM UTC 24 |
4683599409 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.578677668 |
|
|
Oct 09 01:33:42 PM UTC 24 |
Oct 09 01:50:41 PM UTC 24 |
13376792570 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_executable.3544628169 |
|
|
Oct 09 01:48:02 PM UTC 24 |
Oct 09 01:50:52 PM UTC 24 |
14360977396 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_lc_escalation.73882741 |
|
|
Oct 09 01:50:36 PM UTC 24 |
Oct 09 01:50:58 PM UTC 24 |
3454398921 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_throughput_w_partial_write.3812969516 |
|
|
Oct 09 01:50:04 PM UTC 24 |
Oct 09 01:50:59 PM UTC 24 |
3177220891 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_stress_pipeline.2368947348 |
|
|
Oct 09 01:46:43 PM UTC 24 |
Oct 09 01:50:59 PM UTC 24 |
6230449203 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_stress_pipeline.2750013143 |
|
|
Oct 09 01:44:19 PM UTC 24 |
Oct 09 01:51:01 PM UTC 24 |
4753145129 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_ram_cfg.2863260195 |
|
|
Oct 09 01:51:00 PM UTC 24 |
Oct 09 01:51:07 PM UTC 24 |
694191209 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_access_during_key_req.359204632 |
|
|
Oct 09 01:45:02 PM UTC 24 |
Oct 09 01:51:13 PM UTC 24 |
10267880985 ps |
| T35 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_readback_err.2960787907 |
|
|
Oct 09 01:51:07 PM UTC 24 |
Oct 09 01:51:20 PM UTC 24 |
2870833388 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_max_throughput.773025760 |
|
|
Oct 09 01:49:39 PM UTC 24 |
Oct 09 01:51:30 PM UTC 24 |
797651206 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_partial_access_b2b.2856767759 |
|
|
Oct 09 01:46:50 PM UTC 24 |
Oct 09 01:51:32 PM UTC 24 |
13312913601 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_multiple_keys.3787384999 |
|
|
Oct 09 01:38:47 PM UTC 24 |
Oct 09 01:51:33 PM UTC 24 |
5925226555 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_alert_test.3859936220 |
|
|
Oct 09 01:51:31 PM UTC 24 |
Oct 09 01:51:33 PM UTC 24 |
12863597 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_smoke.513261698 |
|
|
Oct 09 01:51:32 PM UTC 24 |
Oct 09 01:51:40 PM UTC 24 |
725186604 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3394907761 |
|
|
Oct 09 01:51:14 PM UTC 24 |
Oct 09 01:51:52 PM UTC 24 |
1078042889 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_regwen.770043066 |
|
|
Oct 09 01:37:25 PM UTC 24 |
Oct 09 01:52:31 PM UTC 24 |
12772778769 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access.1270585575 |
|
|
Oct 09 01:51:53 PM UTC 24 |
Oct 09 01:52:32 PM UTC 24 |
1664086299 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_executable.2933475448 |
|
|
Oct 09 01:45:16 PM UTC 24 |
Oct 09 01:52:43 PM UTC 24 |
3165956156 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_partial_access.4133993904 |
|
|
Oct 09 01:51:02 PM UTC 24 |
Oct 09 01:53:51 PM UTC 24 |
18994729816 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.2021533337 |
|
|
Oct 09 01:34:45 PM UTC 24 |
Oct 09 01:53:56 PM UTC 24 |
126971855495 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_max_throughput.1086917488 |
|
|
Oct 09 01:52:33 PM UTC 24 |
Oct 09 01:54:16 PM UTC 24 |
3185118998 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_mem_walk.1788483537 |
|
|
Oct 09 01:48:09 PM UTC 24 |
Oct 09 01:54:26 PM UTC 24 |
55279167520 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_throughput_w_partial_write.1274088659 |
|
|
Oct 09 01:52:44 PM UTC 24 |
Oct 09 01:54:34 PM UTC 24 |
3308709306 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_ram_cfg.1340623268 |
|
|
Oct 09 01:54:35 PM UTC 24 |
Oct 09 01:54:41 PM UTC 24 |
676762456 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_stress_pipeline.2528281024 |
|
|
Oct 09 01:49:15 PM UTC 24 |
Oct 09 01:54:53 PM UTC 24 |
4519378670 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_multiple_keys.2549350737 |
|
|
Oct 09 01:41:21 PM UTC 24 |
Oct 09 01:54:59 PM UTC 24 |
31185671776 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_readback_err.2691508680 |
|
|
Oct 09 01:54:53 PM UTC 24 |
Oct 09 01:55:06 PM UTC 24 |
3295205535 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_lc_escalation.2415060193 |
|
|
Oct 09 01:53:53 PM UTC 24 |
Oct 09 01:55:39 PM UTC 24 |
48815443451 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_alert_test.2598752270 |
|
|
Oct 09 01:55:40 PM UTC 24 |
Oct 09 01:55:42 PM UTC 24 |
29764040 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_executable.1509046141 |
|
|
Oct 09 01:42:41 PM UTC 24 |
Oct 09 01:55:54 PM UTC 24 |
34332379448 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_pipeline.1297238049 |
|
|
Oct 09 01:51:41 PM UTC 24 |
Oct 09 01:55:58 PM UTC 24 |
4044261121 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_smoke.1672830535 |
|
|
Oct 09 01:55:43 PM UTC 24 |
Oct 09 01:56:07 PM UTC 24 |
1271405352 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.4279945535 |
|
|
Oct 09 01:54:59 PM UTC 24 |
Oct 09 01:56:09 PM UTC 24 |
3067681543 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_partial_access.3708583123 |
|
|
Oct 09 01:54:42 PM UTC 24 |
Oct 09 01:56:37 PM UTC 24 |
2738455568 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access.858819683 |
|
|
Oct 09 01:56:11 PM UTC 24 |
Oct 09 01:56:46 PM UTC 24 |
3449538843 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_max_throughput.2048280931 |
|
|
Oct 09 01:56:47 PM UTC 24 |
Oct 09 01:57:04 PM UTC 24 |
9510503660 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_executable.1874963991 |
|
|
Oct 09 01:39:46 PM UTC 24 |
Oct 09 01:57:04 PM UTC 24 |
20592310956 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.897334263 |
|
|
Oct 09 01:35:20 PM UTC 24 |
Oct 09 01:57:21 PM UTC 24 |
20311078654 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_throughput_w_partial_write.812729837 |
|
|
Oct 09 01:57:05 PM UTC 24 |
Oct 09 01:57:21 PM UTC 24 |
2892169344 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_mem_walk.3790166592 |
|
|
Oct 09 01:51:00 PM UTC 24 |
Oct 09 01:57:23 PM UTC 24 |
149867779613 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_stress_all.269686024 |
|
|
Oct 09 12:31:55 PM UTC 24 |
Oct 09 01:57:36 PM UTC 24 |
787213877930 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_multiple_keys.1009879690 |
|
|
Oct 09 01:49:08 PM UTC 24 |
Oct 09 01:57:40 PM UTC 24 |
6509647023 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_ram_cfg.836752219 |
|
|
Oct 09 01:57:37 PM UTC 24 |
Oct 09 01:57:44 PM UTC 24 |
3367894407 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_readback_err.1767516129 |
|
|
Oct 09 01:57:45 PM UTC 24 |
Oct 09 01:57:57 PM UTC 24 |
2749713253 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.2106686869 |
|
|
Oct 09 01:57:58 PM UTC 24 |
Oct 09 01:58:12 PM UTC 24 |
267277355 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_access_during_key_req.996499688 |
|
|
Oct 09 01:42:36 PM UTC 24 |
Oct 09 01:58:17 PM UTC 24 |
54890344884 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_alert_test.1098620306 |
|
|
Oct 09 01:58:19 PM UTC 24 |
Oct 09 01:58:21 PM UTC 24 |
47762570 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_multiple_keys.3618428493 |
|
|
Oct 09 01:44:07 PM UTC 24 |
Oct 09 01:58:32 PM UTC 24 |
40861019685 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_partial_access_b2b.1980729335 |
|
|
Oct 09 01:52:32 PM UTC 24 |
Oct 09 01:58:49 PM UTC 24 |
7282852397 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_multiple_keys.3271270758 |
|
|
Oct 09 01:55:55 PM UTC 24 |
Oct 09 01:58:51 PM UTC 24 |
4866281540 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_lc_escalation.244714218 |
|
|
Oct 09 01:57:05 PM UTC 24 |
Oct 09 01:58:54 PM UTC 24 |
42858724520 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_smoke.611984950 |
|
|
Oct 09 01:58:22 PM UTC 24 |
Oct 09 01:58:55 PM UTC 24 |
4930197901 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_access_during_key_req.1758705267 |
|
|
Oct 09 01:47:40 PM UTC 24 |
Oct 09 01:59:18 PM UTC 24 |
23420250008 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_access_during_key_req.1291155896 |
|
|
Oct 09 01:53:57 PM UTC 24 |
Oct 09 01:59:23 PM UTC 24 |
6851382076 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_regwen.4108546863 |
|
|
Oct 09 01:50:59 PM UTC 24 |
Oct 09 01:59:26 PM UTC 24 |
3030655750 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_partial_access.26158387 |
|
|
Oct 09 01:57:41 PM UTC 24 |
Oct 09 01:59:26 PM UTC 24 |
12282321098 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_max_throughput.3167772002 |
|
|
Oct 09 01:59:19 PM UTC 24 |
Oct 09 01:59:29 PM UTC 24 |
2684767743 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access.2968495385 |
|
|
Oct 09 01:58:56 PM UTC 24 |
Oct 09 01:59:41 PM UTC 24 |
737540316 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_throughput_w_partial_write.3366686088 |
|
|
Oct 09 01:59:24 PM UTC 24 |
Oct 09 01:59:42 PM UTC 24 |
13338472097 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_regwen.3064769420 |
|
|
Oct 09 01:45:30 PM UTC 24 |
Oct 09 01:59:47 PM UTC 24 |
136214892871 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_ram_cfg.1040080940 |
|
|
Oct 09 01:59:43 PM UTC 24 |
Oct 09 01:59:49 PM UTC 24 |
376909548 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_regwen.3880790098 |
|
|
Oct 09 01:48:03 PM UTC 24 |
Oct 09 02:00:05 PM UTC 24 |
25584122609 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_readback_err.2945019264 |
|
|
Oct 09 02:00:07 PM UTC 24 |
Oct 09 02:00:19 PM UTC 24 |
2648203077 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_partial_access_b2b.1966978044 |
|
|
Oct 09 01:49:37 PM UTC 24 |
Oct 09 02:00:26 PM UTC 24 |
79118050786 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.471150718 |
|
|
Oct 09 02:00:20 PM UTC 24 |
Oct 09 02:00:26 PM UTC 24 |
1355064855 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_alert_test.2758806602 |
|
|
Oct 09 02:00:27 PM UTC 24 |
Oct 09 02:00:30 PM UTC 24 |
15980493 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_smoke.2174295342 |
|
|
Oct 09 02:00:31 PM UTC 24 |
Oct 09 02:00:42 PM UTC 24 |
708033764 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_lc_escalation.3338659762 |
|
|
Oct 09 01:59:27 PM UTC 24 |
Oct 09 02:00:49 PM UTC 24 |
9855638021 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_stress_all.3171852109 |
|
|
Oct 09 01:40:45 PM UTC 24 |
Oct 09 02:00:57 PM UTC 24 |
30933774348 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_multiple_keys.3093800389 |
|
|
Oct 09 01:51:34 PM UTC 24 |
Oct 09 02:01:00 PM UTC 24 |
27800429819 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_partial_access.293454986 |
|
|
Oct 09 01:59:50 PM UTC 24 |
Oct 09 02:01:26 PM UTC 24 |
5758308862 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_mem_walk.927392654 |
|
|
Oct 09 01:54:37 PM UTC 24 |
Oct 09 02:01:32 PM UTC 24 |
74735919840 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access.2816919215 |
|
|
Oct 09 02:01:01 PM UTC 24 |
Oct 09 02:02:00 PM UTC 24 |
3212202586 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_access_during_key_req.3185902739 |
|
|
Oct 09 01:57:21 PM UTC 24 |
Oct 09 02:02:01 PM UTC 24 |
25194775958 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_partial_access_b2b.2072429904 |
|
|
Oct 09 01:56:38 PM UTC 24 |
Oct 09 02:02:06 PM UTC 24 |
10926340061 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_max_throughput.1688317337 |
|
|
Oct 09 02:01:33 PM UTC 24 |
Oct 09 02:02:08 PM UTC 24 |
1458681405 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_bijection.3398764863 |
|
|
Oct 09 01:16:25 PM UTC 24 |
Oct 09 02:02:08 PM UTC 24 |
129445183581 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_stress_pipeline.1031219526 |
|
|
Oct 09 01:56:09 PM UTC 24 |
Oct 09 02:02:13 PM UTC 24 |
4910097071 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_ram_cfg.161646897 |
|
|
Oct 09 02:02:13 PM UTC 24 |
Oct 09 02:02:18 PM UTC 24 |
374704467 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all.4246513808 |
|
|
Oct 09 01:18:30 PM UTC 24 |
Oct 09 02:02:19 PM UTC 24 |
307652160301 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_throughput_w_partial_write.997028789 |
|
|
Oct 09 02:02:02 PM UTC 24 |
Oct 09 02:02:31 PM UTC 24 |
2608606706 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_readback_err.3360472894 |
|
|
Oct 09 02:02:32 PM UTC 24 |
Oct 09 02:02:41 PM UTC 24 |
665255602 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_mem_walk.18732595 |
|
|
Oct 09 01:57:37 PM UTC 24 |
Oct 09 02:03:07 PM UTC 24 |
57617174326 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_stress_pipeline.1520854501 |
|
|
Oct 09 01:58:52 PM UTC 24 |
Oct 09 02:03:19 PM UTC 24 |
13181547500 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/31.sram_ctrl_stress_all.486533654 |
|
|
Oct 09 01:43:52 PM UTC 24 |
Oct 09 02:03:20 PM UTC 24 |
50265978396 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_bijection.2711303968 |
|
|
Oct 09 01:09:43 PM UTC 24 |
Oct 09 02:03:21 PM UTC 24 |
119845515172 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_alert_test.931724001 |
|
|
Oct 09 02:03:20 PM UTC 24 |
Oct 09 02:03:23 PM UTC 24 |
57794452 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_regwen.670378953 |
|
|
Oct 09 01:39:55 PM UTC 24 |
Oct 09 02:03:25 PM UTC 24 |
40970596654 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/32.sram_ctrl_bijection.2251856187 |
|
|
Oct 09 01:44:17 PM UTC 24 |
Oct 09 02:03:26 PM UTC 24 |
63657837900 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.1890516616 |
|
|
Oct 09 02:02:42 PM UTC 24 |
Oct 09 02:03:32 PM UTC 24 |
4639304419 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_partial_access.1005615098 |
|
|
Oct 09 02:02:20 PM UTC 24 |
Oct 09 02:03:52 PM UTC 24 |
4605303435 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_executable.1504120192 |
|
|
Oct 09 01:50:53 PM UTC 24 |
Oct 09 02:03:59 PM UTC 24 |
20510741290 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_smoke.1477304931 |
|
|
Oct 09 02:03:22 PM UTC 24 |
Oct 09 02:04:01 PM UTC 24 |
5531526901 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_partial_access.2669863107 |
|
|
Oct 09 02:03:27 PM UTC 24 |
Oct 09 02:04:01 PM UTC 24 |
5670468430 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_lc_escalation.3671808121 |
|
|
Oct 09 02:02:02 PM UTC 24 |
Oct 09 02:04:07 PM UTC 24 |
48656402629 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_bijection.2188205498 |
|
|
Oct 09 01:32:28 PM UTC 24 |
Oct 09 02:04:24 PM UTC 24 |
107919643907 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_throughput_w_partial_write.1869132638 |
|
|
Oct 09 02:04:00 PM UTC 24 |
Oct 09 02:04:39 PM UTC 24 |
755115079 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_mem_walk.336822329 |
|
|
Oct 09 01:59:48 PM UTC 24 |
Oct 09 02:04:41 PM UTC 24 |
3988677334 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_ram_cfg.2968825605 |
|
|
Oct 09 02:04:40 PM UTC 24 |
Oct 09 02:04:47 PM UTC 24 |
2810950723 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all.4234508975 |
|
|
Oct 09 01:15:21 PM UTC 24 |
Oct 09 02:05:04 PM UTC 24 |
219626760039 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_readback_err.3407397848 |
|
|
Oct 09 02:05:05 PM UTC 24 |
Oct 09 02:05:14 PM UTC 24 |
3091100453 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_max_throughput.1885750491 |
|
|
Oct 09 02:03:52 PM UTC 24 |
Oct 09 02:05:18 PM UTC 24 |
5113443604 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_stress_all.1326716023 |
|
|
Oct 09 12:19:45 PM UTC 24 |
Oct 09 02:05:27 PM UTC 24 |
180532967524 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_alert_test.1165699368 |
|
|
Oct 09 02:05:28 PM UTC 24 |
Oct 09 02:05:30 PM UTC 24 |
40996960 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.1917866215 |
|
|
Oct 09 02:05:15 PM UTC 24 |
Oct 09 02:05:56 PM UTC 24 |
1680869455 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_stress_pipeline.684509306 |
|
|
Oct 09 02:00:58 PM UTC 24 |
Oct 09 02:06:04 PM UTC 24 |
5989914676 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_bijection.4138488657 |
|
|
Oct 09 01:38:58 PM UTC 24 |
Oct 09 02:06:04 PM UTC 24 |
287529724587 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all.2710724899 |
|
|
Oct 09 01:31:30 PM UTC 24 |
Oct 09 02:06:07 PM UTC 24 |
150432995416 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_lc_escalation.3516673829 |
|
|
Oct 09 02:04:02 PM UTC 24 |
Oct 09 02:06:21 PM UTC 24 |
14440249963 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access.2355323237 |
|
|
Oct 09 02:06:09 PM UTC 24 |
Oct 09 02:06:37 PM UTC 24 |
4863027223 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_partial_access.87725233 |
|
|
Oct 09 02:04:48 PM UTC 24 |
Oct 09 02:06:38 PM UTC 24 |
3077738826 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_regwen.1207474420 |
|
|
Oct 09 02:04:25 PM UTC 24 |
Oct 09 02:06:52 PM UTC 24 |
14943142945 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/34.sram_ctrl_access_during_key_req.308144309 |
|
|
Oct 09 01:50:41 PM UTC 24 |
Oct 09 02:06:58 PM UTC 24 |
240778321415 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_bijection.2723485550 |
|
|
Oct 09 01:46:41 PM UTC 24 |
Oct 09 02:06:58 PM UTC 24 |
17060750055 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_stress_pipeline.2544911986 |
|
|
Oct 09 02:03:26 PM UTC 24 |
Oct 09 02:07:03 PM UTC 24 |
3062560601 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_executable.279666199 |
|
|
Oct 09 01:57:22 PM UTC 24 |
Oct 09 02:07:08 PM UTC 24 |
54028840807 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_ram_cfg.2673528667 |
|
|
Oct 09 02:07:10 PM UTC 24 |
Oct 09 02:07:17 PM UTC 24 |
1210818414 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_smoke.1695233650 |
|
|
Oct 09 02:05:32 PM UTC 24 |
Oct 09 02:07:22 PM UTC 24 |
3456518494 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_max_throughput.3804896859 |
|
|
Oct 09 02:06:38 PM UTC 24 |
Oct 09 02:07:33 PM UTC 24 |
775341749 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_readback_err.87684620 |
|
|
Oct 09 02:07:35 PM UTC 24 |
Oct 09 02:07:44 PM UTC 24 |
2649832211 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_regwen.1998514653 |
|
|
Oct 09 02:02:09 PM UTC 24 |
Oct 09 02:07:47 PM UTC 24 |
2191363615 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/39.sram_ctrl_mem_walk.3240536195 |
|
|
Oct 09 02:04:43 PM UTC 24 |
Oct 09 02:07:49 PM UTC 24 |
10952467198 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_alert_test.3872193919 |
|
|
Oct 09 02:07:50 PM UTC 24 |
Oct 09 02:07:52 PM UTC 24 |
13084011 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_mem_walk.3060277097 |
|
|
Oct 09 02:02:19 PM UTC 24 |
Oct 09 02:08:10 PM UTC 24 |
20711667667 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_smoke.398905608 |
|
|
Oct 09 02:07:53 PM UTC 24 |
Oct 09 02:08:23 PM UTC 24 |
7320797712 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_bijection.1894218583 |
|
|
Oct 09 01:51:34 PM UTC 24 |
Oct 09 02:08:28 PM UTC 24 |
66818580560 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_partial_access_b2b.1151542224 |
|
|
Oct 09 01:58:56 PM UTC 24 |
Oct 09 02:08:40 PM UTC 24 |
17720726869 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_throughput_w_partial_write.3868898655 |
|
|
Oct 09 02:06:39 PM UTC 24 |
Oct 09 02:08:46 PM UTC 24 |
802976000 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_partial_access.3401807274 |
|
|
Oct 09 02:08:41 PM UTC 24 |
Oct 09 02:09:03 PM UTC 24 |
1000838548 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_multiple_keys.1056358002 |
|
|
Oct 09 02:05:57 PM UTC 24 |
Oct 09 02:09:05 PM UTC 24 |
2203144750 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_partial_access_b2b.1154541549 |
|
|
Oct 09 02:01:26 PM UTC 24 |
Oct 09 02:09:08 PM UTC 24 |
14948532104 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_bijection.3622667754 |
|
|
Oct 09 01:24:04 PM UTC 24 |
Oct 09 02:09:32 PM UTC 24 |
275892089698 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/38.sram_ctrl_access_during_key_req.1847990551 |
|
|
Oct 09 02:02:07 PM UTC 24 |
Oct 09 02:09:44 PM UTC 24 |
14764017894 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all.3997742629 |
|
|
Oct 09 01:09:32 PM UTC 24 |
Oct 09 02:09:46 PM UTC 24 |
35556652417 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_regwen.2321340737 |
|
|
Oct 09 01:54:27 PM UTC 24 |
Oct 09 02:09:51 PM UTC 24 |
5556931235 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_max_throughput.2138106018 |
|
|
Oct 09 02:09:04 PM UTC 24 |
Oct 09 02:09:54 PM UTC 24 |
2972396627 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_ram_cfg.1340456810 |
|
|
Oct 09 02:09:52 PM UTC 24 |
Oct 09 02:09:57 PM UTC 24 |
738126275 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_lc_escalation.3678679007 |
|
|
Oct 09 02:06:54 PM UTC 24 |
Oct 09 02:09:57 PM UTC 24 |
41506859732 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_readback_err.3405957729 |
|
|
Oct 09 02:09:58 PM UTC 24 |
Oct 09 02:10:10 PM UTC 24 |
691019297 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/36.sram_ctrl_regwen.584949212 |
|
|
Oct 09 01:57:24 PM UTC 24 |
Oct 09 02:10:17 PM UTC 24 |
34336172072 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_mem_partial_access.267676206 |
|
|
Oct 09 02:07:23 PM UTC 24 |
Oct 09 02:10:26 PM UTC 24 |
9752597360 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_alert_test.2257307969 |
|
|
Oct 09 02:10:28 PM UTC 24 |
Oct 09 02:10:31 PM UTC 24 |
14521361 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/35.sram_ctrl_executable.3822011691 |
|
|
Oct 09 01:54:17 PM UTC 24 |
Oct 09 02:10:33 PM UTC 24 |
49114550649 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_lc_escalation.1450432100 |
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Oct 09 02:09:09 PM UTC 24 |
Oct 09 02:10:37 PM UTC 24 |
12674757310 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_throughput_w_partial_write.4098151837 |
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Oct 09 02:09:06 PM UTC 24 |
Oct 09 02:10:53 PM UTC 24 |
13054082482 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/33.sram_ctrl_multiple_keys.1014905098 |
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Oct 09 01:46:15 PM UTC 24 |
Oct 09 02:10:55 PM UTC 24 |
58962077935 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.79520722 |
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Oct 09 02:07:46 PM UTC 24 |
Oct 09 02:11:00 PM UTC 24 |
1206144850 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_smoke.1403482362 |
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Oct 09 02:10:33 PM UTC 24 |
Oct 09 02:11:11 PM UTC 24 |
1408727036 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_partial_access_b2b.756910418 |
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Oct 09 02:06:23 PM UTC 24 |
Oct 09 02:11:12 PM UTC 24 |
40502329217 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_executable.83461853 |
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Oct 09 01:59:30 PM UTC 24 |
Oct 09 02:11:23 PM UTC 24 |
44369603786 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/40.sram_ctrl_stress_pipeline.113878496 |
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Oct 09 02:06:05 PM UTC 24 |
Oct 09 02:11:24 PM UTC 24 |
19105730778 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all.2721987334 |
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Oct 09 12:58:07 PM UTC 24 |
Oct 09 02:11:31 PM UTC 24 |
395170832421 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_throughput_w_partial_write.1621302430 |
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Oct 09 02:11:14 PM UTC 24 |
Oct 09 02:11:31 PM UTC 24 |
1431822184 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_mem_partial_access.22161991 |
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Oct 09 02:09:58 PM UTC 24 |
Oct 09 02:11:34 PM UTC 24 |
2015665368 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.220430754 |
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Oct 09 02:10:11 PM UTC 24 |
Oct 09 02:11:36 PM UTC 24 |
7805702677 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/42.sram_ctrl_ram_cfg.3223745577 |
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Oct 09 02:11:34 PM UTC 24 |
Oct 09 02:11:40 PM UTC 24 |
1690878857 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_main-sim-vcs/coverage/default/37.sram_ctrl_access_during_key_req.1769960372 |
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Oct 09 01:59:27 PM UTC 24 |
Oct 09 02:11:49 PM UTC 24 |
9682716456 ps |