| T314 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_multiple_keys.2379963486 |
|
|
Oct 15 01:12:05 AM UTC 24 |
Oct 15 01:35:23 AM UTC 24 |
110217423413 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access.2893405684 |
|
|
Oct 15 01:35:12 AM UTC 24 |
Oct 15 01:35:31 AM UTC 24 |
1180937358 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.1845755699 |
|
|
Oct 15 01:34:02 AM UTC 24 |
Oct 15 01:35:35 AM UTC 24 |
4164873737 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.3439062066 |
|
|
Oct 15 01:35:32 AM UTC 24 |
Oct 15 01:35:42 AM UTC 24 |
712506782 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_access_during_key_req.3026319957 |
|
|
Oct 15 01:24:36 AM UTC 24 |
Oct 15 01:35:51 AM UTC 24 |
25985782316 ps |
| T165 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_executable.1042015136 |
|
|
Oct 15 01:21:18 AM UTC 24 |
Oct 15 01:36:11 AM UTC 24 |
15725301887 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_smoke.3813287956 |
|
|
Oct 15 01:34:34 AM UTC 24 |
Oct 15 01:36:13 AM UTC 24 |
1543923572 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.1572072658 |
|
|
Oct 15 01:36:14 AM UTC 24 |
Oct 15 01:36:21 AM UTC 24 |
1359044858 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.857272117 |
|
|
Oct 15 01:35:24 AM UTC 24 |
Oct 15 01:36:26 AM UTC 24 |
1510790891 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.2889635811 |
|
|
Oct 15 01:35:36 AM UTC 24 |
Oct 15 01:36:26 AM UTC 24 |
9151531459 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_readback_err.563205423 |
|
|
Oct 15 01:36:27 AM UTC 24 |
Oct 15 01:36:35 AM UTC 24 |
2637280528 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.75951746 |
|
|
Oct 15 01:31:20 AM UTC 24 |
Oct 15 01:36:36 AM UTC 24 |
22822634446 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.3729693704 |
|
|
Oct 15 01:29:19 AM UTC 24 |
Oct 15 01:37:14 AM UTC 24 |
5201427664 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_alert_test.3949479923 |
|
|
Oct 15 01:37:15 AM UTC 24 |
Oct 15 01:37:17 AM UTC 24 |
39647463 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.1481770640 |
|
|
Oct 15 01:36:36 AM UTC 24 |
Oct 15 01:37:28 AM UTC 24 |
938524127 ps |
| T166 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_regwen.59656923 |
|
|
Oct 15 01:24:54 AM UTC 24 |
Oct 15 01:37:32 AM UTC 24 |
8441136348 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_bijection.1518034915 |
|
|
Oct 15 01:17:00 AM UTC 24 |
Oct 15 01:37:39 AM UTC 24 |
64891005004 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_regwen.781971283 |
|
|
Oct 15 01:28:32 AM UTC 24 |
Oct 15 01:37:42 AM UTC 24 |
61759833486 ps |
| T167 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_executable.2874971941 |
|
|
Oct 15 01:24:45 AM UTC 24 |
Oct 15 01:37:43 AM UTC 24 |
39376283486 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_smoke.1819098182 |
|
|
Oct 15 01:37:18 AM UTC 24 |
Oct 15 01:37:45 AM UTC 24 |
2021154144 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.357159942 |
|
|
Oct 15 01:32:11 AM UTC 24 |
Oct 15 01:37:45 AM UTC 24 |
5425122995 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_multiple_keys.2040966401 |
|
|
Oct 15 01:22:40 AM UTC 24 |
Oct 15 01:37:49 AM UTC 24 |
11892011036 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.4132723100 |
|
|
Oct 15 01:37:46 AM UTC 24 |
Oct 15 01:38:06 AM UTC 24 |
7651538994 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.1192042017 |
|
|
Oct 15 01:33:59 AM UTC 24 |
Oct 15 01:38:11 AM UTC 24 |
149485621658 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_executable.2486208545 |
|
|
Oct 15 01:28:12 AM UTC 24 |
Oct 15 01:38:14 AM UTC 24 |
11917461925 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access.1605312581 |
|
|
Oct 15 01:37:43 AM UTC 24 |
Oct 15 01:38:18 AM UTC 24 |
1526310174 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.3124195800 |
|
|
Oct 15 01:38:19 AM UTC 24 |
Oct 15 01:38:26 AM UTC 24 |
1355921667 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/7.sram_ctrl_executable.888314175 |
|
|
Oct 15 01:17:39 AM UTC 24 |
Oct 15 01:38:42 AM UTC 24 |
19068928445 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.441368905 |
|
|
Oct 15 01:37:46 AM UTC 24 |
Oct 15 01:38:48 AM UTC 24 |
758192051 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.2331952492 |
|
|
Oct 15 01:37:50 AM UTC 24 |
Oct 15 01:38:52 AM UTC 24 |
5601599747 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.2405607376 |
|
|
Oct 15 01:37:29 AM UTC 24 |
Oct 15 01:39:01 AM UTC 24 |
5622559741 ps |
| T38 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_readback_err.3612040358 |
|
|
Oct 15 01:38:49 AM UTC 24 |
Oct 15 01:39:01 AM UTC 24 |
702783885 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_alert_test.1747612625 |
|
|
Oct 15 01:39:02 AM UTC 24 |
Oct 15 01:39:04 AM UTC 24 |
62309478 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_access_during_key_req.2524264472 |
|
|
Oct 15 01:23:13 AM UTC 24 |
Oct 15 01:39:24 AM UTC 24 |
61945112765 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_smoke.3228550835 |
|
|
Oct 15 01:39:05 AM UTC 24 |
Oct 15 01:39:25 AM UTC 24 |
907348078 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.139963316 |
|
|
Oct 15 01:33:06 AM UTC 24 |
Oct 15 01:39:25 AM UTC 24 |
59856872164 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.194253084 |
|
|
Oct 15 01:38:52 AM UTC 24 |
Oct 15 01:39:27 AM UTC 24 |
608285918 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/5.sram_ctrl_multiple_keys.329442044 |
|
|
Oct 15 01:13:14 AM UTC 24 |
Oct 15 01:39:34 AM UTC 24 |
254907506709 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.20152743 |
|
|
Oct 15 01:36:27 AM UTC 24 |
Oct 15 01:39:46 AM UTC 24 |
10053069583 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access.80867725 |
|
|
Oct 15 01:39:28 AM UTC 24 |
Oct 15 01:39:57 AM UTC 24 |
1116745286 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.3758432182 |
|
|
Oct 15 01:39:46 AM UTC 24 |
Oct 15 01:40:15 AM UTC 24 |
2937921840 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_regwen.3460828479 |
|
|
Oct 15 01:33:41 AM UTC 24 |
Oct 15 01:40:16 AM UTC 24 |
7138486153 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.3811648055 |
|
|
Oct 15 01:39:58 AM UTC 24 |
Oct 15 01:40:18 AM UTC 24 |
2801525237 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.3469754374 |
|
|
Oct 15 01:38:43 AM UTC 24 |
Oct 15 01:40:23 AM UTC 24 |
2946921731 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_regwen.1978321539 |
|
|
Oct 15 01:15:58 AM UTC 24 |
Oct 15 01:40:28 AM UTC 24 |
235455460709 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.629361354 |
|
|
Oct 15 01:40:29 AM UTC 24 |
Oct 15 01:40:37 AM UTC 24 |
1342278728 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.1055705323 |
|
|
Oct 15 01:35:18 AM UTC 24 |
Oct 15 01:40:40 AM UTC 24 |
5810853302 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.1705826516 |
|
|
Oct 15 01:32:11 AM UTC 24 |
Oct 15 01:40:47 AM UTC 24 |
6711339804 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.1735274840 |
|
|
Oct 15 01:34:58 AM UTC 24 |
Oct 15 01:40:50 AM UTC 24 |
4727533398 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_executable.2453289353 |
|
|
Oct 15 01:23:16 AM UTC 24 |
Oct 15 01:40:57 AM UTC 24 |
32782498893 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_readback_err.2476651315 |
|
|
Oct 15 01:40:47 AM UTC 24 |
Oct 15 01:40:59 AM UTC 24 |
1074138592 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_alert_test.2729441166 |
|
|
Oct 15 01:41:00 AM UTC 24 |
Oct 15 01:41:02 AM UTC 24 |
36491591 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.4075372821 |
|
|
Oct 15 01:32:01 AM UTC 24 |
Oct 15 01:41:11 AM UTC 24 |
43418293454 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.3249277790 |
|
|
Oct 15 01:37:40 AM UTC 24 |
Oct 15 01:41:12 AM UTC 24 |
2641792857 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.1423315811 |
|
|
Oct 15 01:38:27 AM UTC 24 |
Oct 15 01:41:12 AM UTC 24 |
24682931746 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_smoke.897428481 |
|
|
Oct 15 01:52:02 AM UTC 24 |
Oct 15 01:52:15 AM UTC 24 |
842849274 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.1933920742 |
|
|
Oct 15 01:40:50 AM UTC 24 |
Oct 15 01:41:23 AM UTC 24 |
1353597378 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_smoke.3935900938 |
|
|
Oct 15 01:41:03 AM UTC 24 |
Oct 15 01:41:28 AM UTC 24 |
4672154774 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.2911766268 |
|
|
Oct 15 01:36:23 AM UTC 24 |
Oct 15 01:41:50 AM UTC 24 |
20998792314 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.3542282621 |
|
|
Oct 15 01:41:51 AM UTC 24 |
Oct 15 01:42:10 AM UTC 24 |
731432169 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.1146158841 |
|
|
Oct 15 01:26:55 AM UTC 24 |
Oct 15 01:42:14 AM UTC 24 |
8543235848 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.1492306669 |
|
|
Oct 15 01:40:41 AM UTC 24 |
Oct 15 01:42:17 AM UTC 24 |
4377641003 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access.4189155663 |
|
|
Oct 15 01:41:24 AM UTC 24 |
Oct 15 01:42:21 AM UTC 24 |
6172446469 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.1281675051 |
|
|
Oct 15 01:42:12 AM UTC 24 |
Oct 15 01:42:27 AM UTC 24 |
728735048 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_bijection.4282568080 |
|
|
Oct 15 01:12:25 AM UTC 24 |
Oct 15 01:42:39 AM UTC 24 |
53698501551 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.3072774743 |
|
|
Oct 15 01:35:42 AM UTC 24 |
Oct 15 01:42:42 AM UTC 24 |
13280590037 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.130732588 |
|
|
Oct 15 01:42:39 AM UTC 24 |
Oct 15 01:42:46 AM UTC 24 |
701442804 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.300317507 |
|
|
Oct 15 01:42:15 AM UTC 24 |
Oct 15 01:42:49 AM UTC 24 |
3373445826 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_readback_err.457799053 |
|
|
Oct 15 01:42:50 AM UTC 24 |
Oct 15 01:43:01 AM UTC 24 |
2659049303 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_access_during_key_req.3729748325 |
|
|
Oct 15 01:26:14 AM UTC 24 |
Oct 15 01:43:21 AM UTC 24 |
15632222700 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_executable.1348743337 |
|
|
Oct 15 01:35:51 AM UTC 24 |
Oct 15 01:43:22 AM UTC 24 |
17861242876 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_alert_test.1541060634 |
|
|
Oct 15 01:43:23 AM UTC 24 |
Oct 15 01:43:25 AM UTC 24 |
11155379 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.2517726004 |
|
|
Oct 15 01:43:03 AM UTC 24 |
Oct 15 01:43:26 AM UTC 24 |
436408159 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_regwen.1611713916 |
|
|
Oct 15 01:36:13 AM UTC 24 |
Oct 15 01:43:36 AM UTC 24 |
16616391567 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.887800913 |
|
|
Oct 15 01:40:16 AM UTC 24 |
Oct 15 01:43:41 AM UTC 24 |
246698804948 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.2687879121 |
|
|
Oct 15 01:28:03 AM UTC 24 |
Oct 15 01:43:43 AM UTC 24 |
21937140148 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.3705057220 |
|
|
Oct 15 01:34:48 AM UTC 24 |
Oct 15 01:43:44 AM UTC 24 |
23749254753 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_smoke.1883884108 |
|
|
Oct 15 01:43:26 AM UTC 24 |
Oct 15 01:43:44 AM UTC 24 |
690779456 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.2374338846 |
|
|
Oct 15 01:42:18 AM UTC 24 |
Oct 15 01:44:01 AM UTC 24 |
12094628788 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.3912385648 |
|
|
Oct 15 01:37:43 AM UTC 24 |
Oct 15 01:44:03 AM UTC 24 |
21112261298 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access.3020229054 |
|
|
Oct 15 01:43:43 AM UTC 24 |
Oct 15 01:44:14 AM UTC 24 |
2832351528 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.2274904313 |
|
|
Oct 15 01:44:02 AM UTC 24 |
Oct 15 01:44:31 AM UTC 24 |
769150681 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.1223752443 |
|
|
Oct 15 01:43:46 AM UTC 24 |
Oct 15 01:44:49 AM UTC 24 |
3123912583 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_regwen.4281310494 |
|
|
Oct 15 01:23:18 AM UTC 24 |
Oct 15 01:44:51 AM UTC 24 |
3846163180 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.1739017351 |
|
|
Oct 15 01:44:04 AM UTC 24 |
Oct 15 01:44:51 AM UTC 24 |
14471049576 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.823277802 |
|
|
Oct 15 01:44:52 AM UTC 24 |
Oct 15 01:44:58 AM UTC 24 |
346340476 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_executable.187468054 |
|
|
Oct 15 01:33:08 AM UTC 24 |
Oct 15 01:44:59 AM UTC 24 |
14297957266 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.118066687 |
|
|
Oct 15 01:39:26 AM UTC 24 |
Oct 15 01:45:01 AM UTC 24 |
24946929336 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_readback_err.1865412529 |
|
|
Oct 15 01:45:00 AM UTC 24 |
Oct 15 01:45:14 AM UTC 24 |
2773160081 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.1971564255 |
|
|
Oct 15 01:45:02 AM UTC 24 |
Oct 15 01:45:17 AM UTC 24 |
370454568 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_executable.2149477770 |
|
|
Oct 15 01:38:12 AM UTC 24 |
Oct 15 01:45:17 AM UTC 24 |
53407680217 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_alert_test.286683501 |
|
|
Oct 15 01:45:18 AM UTC 24 |
Oct 15 01:45:20 AM UTC 24 |
25025923 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.2755580926 |
|
|
Oct 15 01:41:13 AM UTC 24 |
Oct 15 01:45:20 AM UTC 24 |
7727993666 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.185899613 |
|
|
Oct 15 01:39:35 AM UTC 24 |
Oct 15 01:45:31 AM UTC 24 |
14453140902 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all.3799658017 |
|
|
Oct 15 01:29:09 AM UTC 24 |
Oct 15 01:45:34 AM UTC 24 |
42208031348 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_smoke.3320181725 |
|
|
Oct 15 01:45:18 AM UTC 24 |
Oct 15 01:45:39 AM UTC 24 |
1091565504 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.958855172 |
|
|
Oct 15 01:41:28 AM UTC 24 |
Oct 15 01:45:40 AM UTC 24 |
16513008407 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access.1464551280 |
|
|
Oct 15 01:45:35 AM UTC 24 |
Oct 15 01:45:46 AM UTC 24 |
496342017 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.1926455776 |
|
|
Oct 15 01:42:47 AM UTC 24 |
Oct 15 01:45:47 AM UTC 24 |
20362593813 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.200952798 |
|
|
Oct 15 01:30:34 AM UTC 24 |
Oct 15 01:45:56 AM UTC 24 |
27765277029 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.3371412885 |
|
|
Oct 15 01:45:42 AM UTC 24 |
Oct 15 01:45:59 AM UTC 24 |
696380396 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.3374077748 |
|
|
Oct 15 01:40:38 AM UTC 24 |
Oct 15 01:46:08 AM UTC 24 |
13812078758 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.3948546817 |
|
|
Oct 15 01:44:58 AM UTC 24 |
Oct 15 01:46:27 AM UTC 24 |
6848277126 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.3535785230 |
|
|
Oct 15 01:42:42 AM UTC 24 |
Oct 15 01:46:31 AM UTC 24 |
34544839085 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.381753457 |
|
|
Oct 15 01:46:28 AM UTC 24 |
Oct 15 01:46:36 AM UTC 24 |
1471222170 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/1.sram_ctrl_bijection.1054608922 |
|
|
Oct 15 01:11:52 AM UTC 24 |
Oct 15 01:47:03 AM UTC 24 |
86367840622 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.147571591 |
|
|
Oct 15 01:44:52 AM UTC 24 |
Oct 15 01:47:14 AM UTC 24 |
5368757403 ps |
| T39 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_readback_err.2428686219 |
|
|
Oct 15 01:47:04 AM UTC 24 |
Oct 15 01:47:15 AM UTC 24 |
674859818 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_executable.3090197815 |
|
|
Oct 15 01:44:32 AM UTC 24 |
Oct 15 01:47:26 AM UTC 24 |
3895854278 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.1346614371 |
|
|
Oct 15 01:45:48 AM UTC 24 |
Oct 15 01:47:29 AM UTC 24 |
69654848184 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_alert_test.609704032 |
|
|
Oct 15 01:47:27 AM UTC 24 |
Oct 15 01:47:29 AM UTC 24 |
61595845 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.1315046188 |
|
|
Oct 15 01:45:47 AM UTC 24 |
Oct 15 01:47:30 AM UTC 24 |
1614067478 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_smoke.1432968810 |
|
|
Oct 15 01:47:30 AM UTC 24 |
Oct 15 01:47:45 AM UTC 24 |
6702884694 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.644415630 |
|
|
Oct 15 01:43:27 AM UTC 24 |
Oct 15 01:47:59 AM UTC 24 |
2977641748 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_regwen.3365302573 |
|
|
Oct 15 01:42:28 AM UTC 24 |
Oct 15 01:48:20 AM UTC 24 |
24840835979 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access.1886591369 |
|
|
Oct 15 01:48:00 AM UTC 24 |
Oct 15 01:48:37 AM UTC 24 |
1387653232 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.794385393 |
|
|
Oct 15 01:38:08 AM UTC 24 |
Oct 15 01:48:41 AM UTC 24 |
51960404349 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_executable.823637345 |
|
|
Oct 15 01:46:00 AM UTC 24 |
Oct 15 01:49:12 AM UTC 24 |
5033367694 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.2784834225 |
|
|
Oct 15 01:48:42 AM UTC 24 |
Oct 15 01:49:16 AM UTC 24 |
2996445763 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_regwen.2873527948 |
|
|
Oct 15 01:38:15 AM UTC 24 |
Oct 15 01:49:28 AM UTC 24 |
12940885697 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_regwen.3012015792 |
|
|
Oct 15 01:40:24 AM UTC 24 |
Oct 15 01:49:34 AM UTC 24 |
55838239558 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.1089243077 |
|
|
Oct 15 01:46:36 AM UTC 24 |
Oct 15 01:49:35 AM UTC 24 |
6566178365 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.1573228281 |
|
|
Oct 15 01:49:35 AM UTC 24 |
Oct 15 01:49:41 AM UTC 24 |
691756616 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.1194638140 |
|
|
Oct 15 01:48:38 AM UTC 24 |
Oct 15 01:49:50 AM UTC 24 |
806939397 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.3884996504 |
|
|
Oct 15 01:49:17 AM UTC 24 |
Oct 15 01:49:56 AM UTC 24 |
14099665431 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_bijection.195551298 |
|
|
Oct 15 01:32:04 AM UTC 24 |
Oct 15 01:50:00 AM UTC 24 |
14919202698 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_readback_err.1348860425 |
|
|
Oct 15 01:49:51 AM UTC 24 |
Oct 15 01:50:03 AM UTC 24 |
3038334403 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_alert_test.1113258321 |
|
|
Oct 15 01:50:04 AM UTC 24 |
Oct 15 01:50:06 AM UTC 24 |
21876240 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.3708592999 |
|
|
Oct 15 01:43:42 AM UTC 24 |
Oct 15 01:50:07 AM UTC 24 |
10023313008 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_smoke.1757916143 |
|
|
Oct 15 01:50:07 AM UTC 24 |
Oct 15 01:50:27 AM UTC 24 |
1183642281 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.3933454055 |
|
|
Oct 15 01:46:31 AM UTC 24 |
Oct 15 01:50:33 AM UTC 24 |
7222675514 ps |
| T161 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/3.sram_ctrl_stress_all.3358390995 |
|
|
Oct 15 01:12:22 AM UTC 24 |
Oct 15 01:50:43 AM UTC 24 |
24791995179 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.748051633 |
|
|
Oct 15 01:45:31 AM UTC 24 |
Oct 15 01:50:41 AM UTC 24 |
3718538134 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/0.sram_ctrl_stress_all.2162273414 |
|
|
Oct 15 01:11:52 AM UTC 24 |
Oct 15 01:50:52 AM UTC 24 |
66439220347 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.1412897591 |
|
|
Oct 15 01:43:46 AM UTC 24 |
Oct 15 01:50:54 AM UTC 24 |
19795754019 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access.2012112070 |
|
|
Oct 15 01:50:42 AM UTC 24 |
Oct 15 01:50:57 AM UTC 24 |
823384539 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_executable.4067410315 |
|
|
Oct 15 01:49:26 AM UTC 24 |
Oct 15 01:50:57 AM UTC 24 |
5201869017 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.342522676 |
|
|
Oct 15 01:49:13 AM UTC 24 |
Oct 15 01:51:09 AM UTC 24 |
151797535482 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.1044467758 |
|
|
Oct 15 01:50:53 AM UTC 24 |
Oct 15 01:51:15 AM UTC 24 |
4604647368 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.2560898786 |
|
|
Oct 15 01:49:42 AM UTC 24 |
Oct 15 01:51:21 AM UTC 24 |
9389652934 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.954830048 |
|
|
Oct 15 01:50:55 AM UTC 24 |
Oct 15 01:51:26 AM UTC 24 |
723577290 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.2911415821 |
|
|
Oct 15 01:51:22 AM UTC 24 |
Oct 15 01:51:27 AM UTC 24 |
374823894 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_executable.3673186874 |
|
|
Oct 15 01:42:22 AM UTC 24 |
Oct 15 01:51:36 AM UTC 24 |
20954569569 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_readback_err.2798579884 |
|
|
Oct 15 01:51:37 AM UTC 24 |
Oct 15 01:51:47 AM UTC 24 |
2636693084 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.2358952874 |
|
|
Oct 15 01:49:57 AM UTC 24 |
Oct 15 01:51:51 AM UTC 24 |
3068262191 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.3793901933 |
|
|
Oct 15 01:45:39 AM UTC 24 |
Oct 15 01:52:01 AM UTC 24 |
89048221032 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.1737548086 |
|
|
Oct 15 01:51:48 AM UTC 24 |
Oct 15 01:52:01 AM UTC 24 |
315409566 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_alert_test.558340144 |
|
|
Oct 15 01:52:01 AM UTC 24 |
Oct 15 01:52:03 AM UTC 24 |
14245364 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.2665418999 |
|
|
Oct 15 01:45:57 AM UTC 24 |
Oct 15 01:52:08 AM UTC 24 |
16277913174 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.4013028144 |
|
|
Oct 15 01:47:45 AM UTC 24 |
Oct 15 01:52:17 AM UTC 24 |
12011300094 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.367379962 |
|
|
Oct 15 01:40:17 AM UTC 24 |
Oct 15 01:52:32 AM UTC 24 |
42930663092 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_stress_all.1730025908 |
|
|
Oct 15 01:22:23 AM UTC 24 |
Oct 15 01:52:36 AM UTC 24 |
32771682716 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.1645200923 |
|
|
Oct 15 01:41:12 AM UTC 24 |
Oct 15 01:52:39 AM UTC 24 |
22201875483 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.1593196574 |
|
|
Oct 15 01:50:57 AM UTC 24 |
Oct 15 01:52:48 AM UTC 24 |
10611501513 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access.1404211299 |
|
|
Oct 15 01:52:18 AM UTC 24 |
Oct 15 01:52:55 AM UTC 24 |
7264399589 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.3972362575 |
|
|
Oct 15 01:52:39 AM UTC 24 |
Oct 15 01:53:15 AM UTC 24 |
735819067 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.526572660 |
|
|
Oct 15 01:50:34 AM UTC 24 |
Oct 15 01:53:35 AM UTC 24 |
2460636557 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.3299992641 |
|
|
Oct 15 01:48:21 AM UTC 24 |
Oct 15 01:53:52 AM UTC 24 |
58042546052 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.2948136304 |
|
|
Oct 15 01:53:53 AM UTC 24 |
Oct 15 01:53:59 AM UTC 24 |
1702934234 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.2235914918 |
|
|
Oct 15 01:51:27 AM UTC 24 |
Oct 15 01:54:09 AM UTC 24 |
28861544656 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_regwen.3550486893 |
|
|
Oct 15 01:31:11 AM UTC 24 |
Oct 15 01:54:09 AM UTC 24 |
21390131968 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_executable.2656647505 |
|
|
Oct 15 01:40:19 AM UTC 24 |
Oct 15 01:54:15 AM UTC 24 |
13959896649 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_regwen.482118970 |
|
|
Oct 15 01:49:29 AM UTC 24 |
Oct 15 01:54:20 AM UTC 24 |
5037451037 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_readback_err.1482712112 |
|
|
Oct 15 01:54:10 AM UTC 24 |
Oct 15 01:54:22 AM UTC 24 |
692024296 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_alert_test.2064191777 |
|
|
Oct 15 01:54:23 AM UTC 24 |
Oct 15 01:54:25 AM UTC 24 |
38009344 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.1765911216 |
|
|
Oct 15 01:52:36 AM UTC 24 |
Oct 15 01:54:25 AM UTC 24 |
797985755 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.2765172114 |
|
|
Oct 15 01:54:15 AM UTC 24 |
Oct 15 01:54:37 AM UTC 24 |
1992257041 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_smoke.548320572 |
|
|
Oct 15 01:54:26 AM UTC 24 |
Oct 15 01:54:42 AM UTC 24 |
4640859856 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.1655835958 |
|
|
Oct 15 01:52:17 AM UTC 24 |
Oct 15 01:54:43 AM UTC 24 |
12087561246 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_bijection.2549433150 |
|
|
Oct 15 01:29:26 AM UTC 24 |
Oct 15 01:54:52 AM UTC 24 |
85250352942 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.680698490 |
|
|
Oct 15 01:51:28 AM UTC 24 |
Oct 15 01:54:58 AM UTC 24 |
5251305956 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_executable.1857387613 |
|
|
Oct 15 01:31:09 AM UTC 24 |
Oct 15 01:55:01 AM UTC 24 |
136067392983 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.276117306 |
|
|
Oct 15 01:52:48 AM UTC 24 |
Oct 15 01:55:05 AM UTC 24 |
14523379330 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access.709620628 |
|
|
Oct 15 01:54:44 AM UTC 24 |
Oct 15 01:55:06 AM UTC 24 |
1086725254 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/8.sram_ctrl_bijection.3996619548 |
|
|
Oct 15 01:18:33 AM UTC 24 |
Oct 15 01:55:09 AM UTC 24 |
234643357022 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.166042026 |
|
|
Oct 15 01:54:58 AM UTC 24 |
Oct 15 01:55:25 AM UTC 24 |
962240552 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.2181756785 |
|
|
Oct 15 01:49:36 AM UTC 24 |
Oct 15 01:55:25 AM UTC 24 |
5255995737 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.2209462854 |
|
|
Oct 15 01:55:26 AM UTC 24 |
Oct 15 01:55:32 AM UTC 24 |
1294595881 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/6.sram_ctrl_bijection.3553753167 |
|
|
Oct 15 01:15:08 AM UTC 24 |
Oct 15 01:55:36 AM UTC 24 |
62222380194 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.1702939807 |
|
|
Oct 15 01:50:44 AM UTC 24 |
Oct 15 01:55:54 AM UTC 24 |
5766659794 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.4035026753 |
|
|
Oct 15 01:55:03 AM UTC 24 |
Oct 15 01:55:59 AM UTC 24 |
964773589 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_readback_err.2644916057 |
|
|
Oct 15 01:55:55 AM UTC 24 |
Oct 15 01:56:09 AM UTC 24 |
2749873432 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.3936245433 |
|
|
Oct 15 01:39:25 AM UTC 24 |
Oct 15 01:56:10 AM UTC 24 |
51837813973 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_regwen.2713737544 |
|
|
Oct 15 01:55:26 AM UTC 24 |
Oct 15 01:56:12 AM UTC 24 |
2969177208 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_alert_test.1184899943 |
|
|
Oct 15 01:56:11 AM UTC 24 |
Oct 15 01:56:13 AM UTC 24 |
16726828 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_bijection.835719355 |
|
|
Oct 15 01:34:52 AM UTC 24 |
Oct 15 01:56:16 AM UTC 24 |
18111247509 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_executable.2770889226 |
|
|
Oct 15 01:51:09 AM UTC 24 |
Oct 15 01:56:19 AM UTC 24 |
8700359918 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.3191627211 |
|
|
Oct 15 01:47:30 AM UTC 24 |
Oct 15 01:56:27 AM UTC 24 |
4178367109 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.3238025929 |
|
|
Oct 15 01:56:00 AM UTC 24 |
Oct 15 01:56:34 AM UTC 24 |
3058410564 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_bijection.4264595573 |
|
|
Oct 15 01:25:52 AM UTC 24 |
Oct 15 01:56:39 AM UTC 24 |
245710930887 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.3145739531 |
|
|
Oct 15 01:54:00 AM UTC 24 |
Oct 15 01:56:39 AM UTC 24 |
7360504312 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_smoke.1897367409 |
|
|
Oct 15 01:56:12 AM UTC 24 |
Oct 15 01:56:49 AM UTC 24 |
426054475 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.3705141586 |
|
|
Oct 15 01:55:06 AM UTC 24 |
Oct 15 01:56:54 AM UTC 24 |
11208391201 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.3500940769 |
|
|
Oct 15 01:55:37 AM UTC 24 |
Oct 15 01:56:55 AM UTC 24 |
5787986062 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.3679787106 |
|
|
Oct 15 01:56:41 AM UTC 24 |
Oct 15 01:57:00 AM UTC 24 |
1465667630 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.1112796113 |
|
|
Oct 15 01:54:09 AM UTC 24 |
Oct 15 01:57:08 AM UTC 24 |
19619184719 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.932319393 |
|
|
Oct 15 01:57:08 AM UTC 24 |
Oct 15 01:57:14 AM UTC 24 |
1402224863 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all.1111207329 |
|
|
Oct 15 01:23:53 AM UTC 24 |
Oct 15 01:57:25 AM UTC 24 |
35845111339 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access.3417683206 |
|
|
Oct 15 01:56:27 AM UTC 24 |
Oct 15 01:57:41 AM UTC 24 |
1723694775 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_readback_err.654582752 |
|
|
Oct 15 01:57:42 AM UTC 24 |
Oct 15 01:57:49 AM UTC 24 |
678588697 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_bijection.2528581009 |
|
|
Oct 15 01:22:46 AM UTC 24 |
Oct 15 01:57:52 AM UTC 24 |
159869004248 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.3788509489 |
|
|
Oct 15 01:56:50 AM UTC 24 |
Oct 15 01:58:03 AM UTC 24 |
16737138347 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.990925799 |
|
|
Oct 15 01:56:40 AM UTC 24 |
Oct 15 01:58:04 AM UTC 24 |
1936984091 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.3855477632 |
|
|
Oct 15 01:56:55 AM UTC 24 |
Oct 15 01:58:05 AM UTC 24 |
4680450868 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_alert_test.2364636966 |
|
|
Oct 15 01:58:04 AM UTC 24 |
Oct 15 01:58:06 AM UTC 24 |
40946265 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.1359216767 |
|
|
Oct 15 01:57:50 AM UTC 24 |
Oct 15 01:58:16 AM UTC 24 |
1056851662 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_smoke.2347106750 |
|
|
Oct 15 01:58:05 AM UTC 24 |
Oct 15 01:58:19 AM UTC 24 |
2945424304 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_bijection.4247966045 |
|
|
Oct 15 01:24:06 AM UTC 24 |
Oct 15 01:59:35 AM UTC 24 |
122161601017 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.1506117977 |
|
|
Oct 15 01:52:33 AM UTC 24 |
Oct 15 01:58:25 AM UTC 24 |
76702130669 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access.2288905539 |
|
|
Oct 15 01:58:21 AM UTC 24 |
Oct 15 01:58:59 AM UTC 24 |
1728806013 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.3958473940 |
|
|
Oct 15 01:44:15 AM UTC 24 |
Oct 15 01:59:10 AM UTC 24 |
129540523725 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.1691611883 |
|
|
Oct 15 01:59:00 AM UTC 24 |
Oct 15 01:59:52 AM UTC 24 |
1483633629 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.3328391725 |
|
|
Oct 15 01:54:43 AM UTC 24 |
Oct 15 01:59:53 AM UTC 24 |
44758697242 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/9.sram_ctrl_bijection.2349973286 |
|
|
Oct 15 01:20:07 AM UTC 24 |
Oct 15 02:00:11 AM UTC 24 |
116700622875 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.199130457 |
|
|
Oct 15 01:55:33 AM UTC 24 |
Oct 15 02:00:17 AM UTC 24 |
13138662356 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.2395552581 |
|
|
Oct 15 02:00:19 AM UTC 24 |
Oct 15 02:00:26 AM UTC 24 |
706704523 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_regwen.2661560104 |
|
|
Oct 15 01:44:50 AM UTC 24 |
Oct 15 02:00:27 AM UTC 24 |
13391790289 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.2423296879 |
|
|
Oct 15 01:59:36 AM UTC 24 |
Oct 15 02:00:28 AM UTC 24 |
7016265613 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.3820542190 |
|
|
Oct 15 01:59:11 AM UTC 24 |
Oct 15 02:00:30 AM UTC 24 |
6939400346 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_regwen.4102342152 |
|
|
Oct 15 01:46:09 AM UTC 24 |
Oct 15 02:00:35 AM UTC 24 |
10142883275 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_readback_err.21677233 |
|
|
Oct 15 02:00:29 AM UTC 24 |
Oct 15 02:00:41 AM UTC 24 |
2632010924 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_executable.1450228606 |
|
|
Oct 15 01:56:56 AM UTC 24 |
Oct 15 02:00:43 AM UTC 24 |
7110503078 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_alert_test.3345867043 |
|
|
Oct 15 02:00:42 AM UTC 24 |
Oct 15 02:00:44 AM UTC 24 |
35381724 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.4206296315 |
|
|
Oct 15 01:45:21 AM UTC 24 |
Oct 15 02:00:44 AM UTC 24 |
73072433964 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all.3848208461 |
|
|
Oct 15 01:26:49 AM UTC 24 |
Oct 15 02:00:45 AM UTC 24 |
97483453691 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.2653646085 |
|
|
Oct 15 01:57:25 AM UTC 24 |
Oct 15 02:01:10 AM UTC 24 |
27892362981 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access.4048074227 |
|
|
Oct 15 02:01:11 AM UTC 24 |
Oct 15 02:01:22 AM UTC 24 |
2784291115 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.1985634157 |
|
|
Oct 15 02:00:31 AM UTC 24 |
Oct 15 02:01:40 AM UTC 24 |
5270416014 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.3506819361 |
|
|
Oct 15 02:00:28 AM UTC 24 |
Oct 15 02:01:40 AM UTC 24 |
5823805645 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.3930100419 |
|
|
Oct 15 01:59:53 AM UTC 24 |
Oct 15 02:01:47 AM UTC 24 |
2554035101 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_smoke.165911914 |
|
|
Oct 15 02:00:44 AM UTC 24 |
Oct 15 02:01:47 AM UTC 24 |
3815362038 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.1809497445 |
|
|
Oct 15 02:01:41 AM UTC 24 |
Oct 15 02:01:53 AM UTC 24 |
679827152 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.841995018 |
|
|
Oct 15 01:56:35 AM UTC 24 |
Oct 15 02:01:54 AM UTC 24 |
46940671166 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.3864135162 |
|
|
Oct 15 02:01:41 AM UTC 24 |
Oct 15 02:01:54 AM UTC 24 |
1310536044 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.2339093033 |
|
|
Oct 15 02:01:55 AM UTC 24 |
Oct 15 02:02:02 AM UTC 24 |
1407522642 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_regwen.2115950834 |
|
|
Oct 15 01:53:36 AM UTC 24 |
Oct 15 02:02:27 AM UTC 24 |
16871964194 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_bijection.3494474509 |
|
|
Oct 15 01:37:33 AM UTC 24 |
Oct 15 02:02:31 AM UTC 24 |
122345286367 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.779850752 |
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|
Oct 15 01:56:20 AM UTC 24 |
Oct 15 02:02:33 AM UTC 24 |
6205471362 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.1618317289 |
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|
Oct 15 01:54:53 AM UTC 24 |
Oct 15 02:02:38 AM UTC 24 |
13905482921 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_readback_err.180389995 |
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|
Oct 15 02:02:32 AM UTC 24 |
Oct 15 02:02:41 AM UTC 24 |
698742275 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_alert_test.1746606553 |
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|
Oct 15 02:02:42 AM UTC 24 |
Oct 15 02:02:44 AM UTC 24 |
12908405 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.3624518328 |
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|
Oct 15 01:57:15 AM UTC 24 |
Oct 15 02:03:06 AM UTC 24 |
27646603454 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_smoke.3517593788 |
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Oct 15 02:02:46 AM UTC 24 |
Oct 15 02:03:13 AM UTC 24 |
756442433 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.2378309577 |
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|
Oct 15 01:58:16 AM UTC 24 |
Oct 15 02:03:27 AM UTC 24 |
15526206472 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.646955917 |
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|
Oct 15 01:52:55 AM UTC 24 |
Oct 15 02:03:39 AM UTC 24 |
10218514905 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.3763083029 |
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|
Oct 15 02:01:47 AM UTC 24 |
Oct 15 02:03:42 AM UTC 24 |
14990874979 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.3831436294 |
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|
Oct 15 02:02:28 AM UTC 24 |
Oct 15 02:03:50 AM UTC 24 |
3982236228 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access.4222594971 |
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|
Oct 15 02:03:40 AM UTC 24 |
Oct 15 02:03:51 AM UTC 24 |
692852373 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.1741992081 |
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|
Oct 15 02:00:27 AM UTC 24 |
Oct 15 02:03:54 AM UTC 24 |
57684337632 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_10_14/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_multiple_keys.129941801 |
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Oct 15 02:03:07 AM UTC 24 |
Oct 15 02:03:59 AM UTC 24 |
1080432896 ps |