| T308 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access.3473925094 |
|
|
Feb 08 04:02:23 PM UTC 25 |
Feb 08 04:02:44 PM UTC 25 |
17989068411 ps |
| T309 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_multiple_keys.2518433741 |
|
|
Feb 08 03:55:31 PM UTC 25 |
Feb 08 04:02:47 PM UTC 25 |
18304664378 ps |
| T310 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_multiple_keys.1108207583 |
|
|
Feb 08 03:45:23 PM UTC 25 |
Feb 08 04:02:51 PM UTC 25 |
59238113726 ps |
| T311 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_multiple_keys.1396812355 |
|
|
Feb 08 03:51:56 PM UTC 25 |
Feb 08 04:02:59 PM UTC 25 |
49425582892 ps |
| T312 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_mem_walk.242041844 |
|
|
Feb 08 04:00:22 PM UTC 25 |
Feb 08 04:03:02 PM UTC 25 |
19742450088 ps |
| T313 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_max_throughput.4210634711 |
|
|
Feb 08 04:02:48 PM UTC 25 |
Feb 08 04:03:21 PM UTC 25 |
1440826935 ps |
| T314 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_partial_access_b2b.2581400067 |
|
|
Feb 08 03:56:38 PM UTC 25 |
Feb 08 04:03:32 PM UTC 25 |
80928816705 ps |
| T315 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_ram_cfg.1380560786 |
|
|
Feb 08 04:03:33 PM UTC 25 |
Feb 08 04:03:40 PM UTC 25 |
362858691 ps |
| T316 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_throughput_w_partial_write.2007903272 |
|
|
Feb 08 04:02:51 PM UTC 25 |
Feb 08 04:03:54 PM UTC 25 |
814113196 ps |
| T317 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_bijection.3653959149 |
|
|
Feb 08 03:52:17 PM UTC 25 |
Feb 08 04:03:56 PM UTC 25 |
9521266072 ps |
| T318 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_lc_escalation.4193505116 |
|
|
Feb 08 04:03:00 PM UTC 25 |
Feb 08 04:04:29 PM UTC 25 |
16905746913 ps |
| T319 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_alert_test.2647567853 |
|
|
Feb 08 04:04:30 PM UTC 25 |
Feb 08 04:04:32 PM UTC 25 |
32777197 ps |
| T320 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/4.sram_ctrl_stress_all.3423595225 |
|
|
Feb 08 03:12:30 PM UTC 25 |
Feb 08 04:04:35 PM UTC 25 |
168737962209 ps |
| T321 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_smoke.2203129494 |
|
|
Feb 08 04:04:33 PM UTC 25 |
Feb 08 04:05:05 PM UTC 25 |
3643988393 ps |
| T322 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.2930377377 |
|
|
Feb 08 04:03:57 PM UTC 25 |
Feb 08 04:05:07 PM UTC 25 |
3519453354 ps |
| T323 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_pipeline.3764138796 |
|
|
Feb 08 04:02:07 PM UTC 25 |
Feb 08 04:06:51 PM UTC 25 |
13631614562 ps |
| T324 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_partial_access.2763019866 |
|
|
Feb 08 04:03:55 PM UTC 25 |
Feb 08 04:06:53 PM UTC 25 |
4993916175 ps |
| T325 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access.3029527331 |
|
|
Feb 08 04:06:52 PM UTC 25 |
Feb 08 04:07:16 PM UTC 25 |
2501421152 ps |
| T326 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_access_during_key_req.2455111593 |
|
|
Feb 08 03:57:59 PM UTC 25 |
Feb 08 04:07:20 PM UTC 25 |
9882478228 ps |
| T327 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_throughput_w_partial_write.108175091 |
|
|
Feb 08 04:07:21 PM UTC 25 |
Feb 08 04:07:47 PM UTC 25 |
727457303 ps |
| T328 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_executable.1747912870 |
|
|
Feb 08 03:54:40 PM UTC 25 |
Feb 08 04:07:58 PM UTC 25 |
21524351444 ps |
| T329 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_max_throughput.1679523955 |
|
|
Feb 08 04:07:17 PM UTC 25 |
Feb 08 04:08:16 PM UTC 25 |
751421213 ps |
| T330 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_mem_walk.307723740 |
|
|
Feb 08 04:03:41 PM UTC 25 |
Feb 08 04:08:32 PM UTC 25 |
10714694617 ps |
| T331 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_ram_cfg.1957461836 |
|
|
Feb 08 04:08:32 PM UTC 25 |
Feb 08 04:08:38 PM UTC 25 |
354411268 ps |
| T332 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_pipeline.2217028620 |
|
|
Feb 08 04:05:07 PM UTC 25 |
Feb 08 04:09:23 PM UTC 25 |
5414571669 ps |
| T333 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_lc_escalation.1669223124 |
|
|
Feb 08 04:07:47 PM UTC 25 |
Feb 08 04:09:31 PM UTC 25 |
9815840227 ps |
| T334 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_regwen.4152493243 |
|
|
Feb 08 04:08:22 PM UTC 25 |
Feb 08 04:10:49 PM UTC 25 |
8259097677 ps |
| T335 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_partial_access.4030276632 |
|
|
Feb 08 04:09:24 PM UTC 25 |
Feb 08 04:10:55 PM UTC 25 |
4805429417 ps |
| T51 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.1376068376 |
|
|
Feb 08 04:09:33 PM UTC 25 |
Feb 08 04:10:56 PM UTC 25 |
2258052984 ps |
| T336 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_alert_test.3271092877 |
|
|
Feb 08 04:10:55 PM UTC 25 |
Feb 08 04:10:57 PM UTC 25 |
20683747 ps |
| T337 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_partial_access_b2b.475614018 |
|
|
Feb 08 04:06:54 PM UTC 25 |
Feb 08 04:11:16 PM UTC 25 |
3826974895 ps |
| T338 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_partial_access_b2b.873213847 |
|
|
Feb 08 04:02:45 PM UTC 25 |
Feb 08 04:11:45 PM UTC 25 |
35388827318 ps |
| T339 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_smoke.4077608749 |
|
|
Feb 08 04:10:57 PM UTC 25 |
Feb 08 04:12:00 PM UTC 25 |
2469463496 ps |
| T340 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_regwen.1946849061 |
|
|
Feb 08 03:59:27 PM UTC 25 |
Feb 08 04:12:03 PM UTC 25 |
13939482026 ps |
| T341 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_access_during_key_req.3397502713 |
|
|
Feb 08 04:03:02 PM UTC 25 |
Feb 08 04:12:23 PM UTC 25 |
9893960452 ps |
| T342 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_mem_walk.314563103 |
|
|
Feb 08 04:08:39 PM UTC 25 |
Feb 08 04:12:25 PM UTC 25 |
14020703161 ps |
| T343 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_multiple_keys.1907590734 |
|
|
Feb 08 04:00:40 PM UTC 25 |
Feb 08 04:12:30 PM UTC 25 |
9508854081 ps |
| T344 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_throughput_w_partial_write.1922725622 |
|
|
Feb 08 04:12:26 PM UTC 25 |
Feb 08 04:12:37 PM UTC 25 |
2424325552 ps |
| T345 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access.439782765 |
|
|
Feb 08 04:12:00 PM UTC 25 |
Feb 08 04:12:43 PM UTC 25 |
3716620377 ps |
| T346 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_regwen.4267815900 |
|
|
Feb 08 04:03:33 PM UTC 25 |
Feb 08 04:13:04 PM UTC 25 |
11421596518 ps |
| T347 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_max_throughput.2818437830 |
|
|
Feb 08 04:12:24 PM UTC 25 |
Feb 08 04:13:45 PM UTC 25 |
1598807078 ps |
| T348 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_ram_cfg.1959421898 |
|
|
Feb 08 04:13:46 PM UTC 25 |
Feb 08 04:13:53 PM UTC 25 |
694240035 ps |
| T349 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_lc_escalation.2293946912 |
|
|
Feb 08 04:12:31 PM UTC 25 |
Feb 08 04:14:03 PM UTC 25 |
26976848558 ps |
| T350 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_access_during_key_req.1619036853 |
|
|
Feb 08 03:54:37 PM UTC 25 |
Feb 08 04:14:04 PM UTC 25 |
14224970599 ps |
| T351 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.1701887998 |
|
|
Feb 08 04:14:04 PM UTC 25 |
Feb 08 04:14:33 PM UTC 25 |
2462350749 ps |
| T352 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_executable.4173575566 |
|
|
Feb 08 04:03:21 PM UTC 25 |
Feb 08 04:15:35 PM UTC 25 |
29140983581 ps |
| T353 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_alert_test.3800074078 |
|
|
Feb 08 04:15:36 PM UTC 25 |
Feb 08 04:15:38 PM UTC 25 |
32704405 ps |
| T354 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_smoke.2848360752 |
|
|
Feb 08 04:15:39 PM UTC 25 |
Feb 08 04:16:04 PM UTC 25 |
11741088810 ps |
| T355 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_multiple_keys.670582516 |
|
|
Feb 08 04:04:36 PM UTC 25 |
Feb 08 04:16:10 PM UTC 25 |
18557245733 ps |
| T356 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_executable.2523923232 |
|
|
Feb 08 04:12:44 PM UTC 25 |
Feb 08 04:16:12 PM UTC 25 |
10177340510 ps |
| T357 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_executable.3339438342 |
|
|
Feb 08 03:58:18 PM UTC 25 |
Feb 08 04:16:38 PM UTC 25 |
114400100702 ps |
| T358 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_partial_access.2430698417 |
|
|
Feb 08 04:14:04 PM UTC 25 |
Feb 08 04:16:44 PM UTC 25 |
3183821058 ps |
| T359 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access.3983123128 |
|
|
Feb 08 04:16:39 PM UTC 25 |
Feb 08 04:16:46 PM UTC 25 |
1563813108 ps |
| T360 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_max_throughput.564257791 |
|
|
Feb 08 04:16:47 PM UTC 25 |
Feb 08 04:17:15 PM UTC 25 |
2458199256 ps |
| T361 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_stress_pipeline.1695071188 |
|
|
Feb 08 04:11:46 PM UTC 25 |
Feb 08 04:18:07 PM UTC 25 |
18964741243 ps |
| T362 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_throughput_w_partial_write.1490493675 |
|
|
Feb 08 04:17:17 PM UTC 25 |
Feb 08 04:18:24 PM UTC 25 |
1590131962 ps |
| T363 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_access_during_key_req.3346420383 |
|
|
Feb 08 04:12:38 PM UTC 25 |
Feb 08 04:18:41 PM UTC 25 |
26534587567 ps |
| T364 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_partial_access_b2b.1881032162 |
|
|
Feb 08 04:12:04 PM UTC 25 |
Feb 08 04:20:02 PM UTC 25 |
34734373523 ps |
| T365 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_lc_escalation.2239116765 |
|
|
Feb 08 04:18:08 PM UTC 25 |
Feb 08 04:20:13 PM UTC 25 |
15121830028 ps |
| T366 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_ram_cfg.871181856 |
|
|
Feb 08 04:20:13 PM UTC 25 |
Feb 08 04:20:20 PM UTC 25 |
2807602205 ps |
| T367 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_bijection.3904537170 |
|
|
Feb 08 03:40:40 PM UTC 25 |
Feb 08 04:20:25 PM UTC 25 |
193169872121 ps |
| T368 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_pipeline.2259464727 |
|
|
Feb 08 04:16:12 PM UTC 25 |
Feb 08 04:21:02 PM UTC 25 |
14276616234 ps |
| T369 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.1659244547 |
|
|
Feb 08 04:20:39 PM UTC 25 |
Feb 08 04:21:32 PM UTC 25 |
3689107306 ps |
| T370 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_alert_test.3536831084 |
|
|
Feb 08 04:21:33 PM UTC 25 |
Feb 08 04:21:35 PM UTC 25 |
20339484 ps |
| T371 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_mem_walk.129685938 |
|
|
Feb 08 04:13:54 PM UTC 25 |
Feb 08 04:21:54 PM UTC 25 |
256130793136 ps |
| T372 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_access_during_key_req.3906958347 |
|
|
Feb 08 04:07:59 PM UTC 25 |
Feb 08 04:21:57 PM UTC 25 |
71925595099 ps |
| T373 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_smoke.2595455849 |
|
|
Feb 08 04:21:36 PM UTC 25 |
Feb 08 04:22:16 PM UTC 25 |
1973577066 ps |
| T374 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_partial_access.891281355 |
|
|
Feb 08 04:20:26 PM UTC 25 |
Feb 08 04:23:52 PM UTC 25 |
21886185708 ps |
| T375 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access.4039622189 |
|
|
Feb 08 04:23:52 PM UTC 25 |
Feb 08 04:24:03 PM UTC 25 |
399095650 ps |
| T376 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_bijection.1205519510 |
|
|
Feb 08 03:45:34 PM UTC 25 |
Feb 08 04:24:19 PM UTC 25 |
99619469363 ps |
| T377 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_executable.3014977184 |
|
|
Feb 08 04:08:17 PM UTC 25 |
Feb 08 04:25:00 PM UTC 25 |
139251137072 ps |
| T378 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_multiple_keys.3158971501 |
|
|
Feb 08 04:10:58 PM UTC 25 |
Feb 08 04:25:22 PM UTC 25 |
42538981681 ps |
| T379 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_executable.3078608206 |
|
|
Feb 08 04:18:42 PM UTC 25 |
Feb 08 04:25:23 PM UTC 25 |
60931210065 ps |
| T380 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_max_throughput.1505398663 |
|
|
Feb 08 04:24:19 PM UTC 25 |
Feb 08 04:25:24 PM UTC 25 |
1394342338 ps |
| T381 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_throughput_w_partial_write.661046712 |
|
|
Feb 08 04:25:02 PM UTC 25 |
Feb 08 04:25:25 PM UTC 25 |
1623152961 ps |
| T382 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_mem_walk.4225555521 |
|
|
Feb 08 04:20:20 PM UTC 25 |
Feb 08 04:26:21 PM UTC 25 |
55284455447 ps |
| T383 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_ram_cfg.3787019641 |
|
|
Feb 08 04:26:22 PM UTC 25 |
Feb 08 04:26:28 PM UTC 25 |
361198377 ps |
| T384 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_stress_all.4160915733 |
|
|
Feb 08 04:04:04 PM UTC 25 |
Feb 08 04:26:56 PM UTC 25 |
79697919762 ps |
| T385 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_lc_escalation.702486315 |
|
|
Feb 08 04:25:23 PM UTC 25 |
Feb 08 04:27:27 PM UTC 25 |
50348846268 ps |
| T386 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_pipeline.3241059855 |
|
|
Feb 08 04:22:16 PM UTC 25 |
Feb 08 04:27:44 PM UTC 25 |
5156280867 ps |
| T387 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_multiple_keys.2032322638 |
|
|
Feb 08 04:16:05 PM UTC 25 |
Feb 08 04:28:34 PM UTC 25 |
23771306814 ps |
| T388 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_alert_test.341680567 |
|
|
Feb 08 04:28:35 PM UTC 25 |
Feb 08 04:28:37 PM UTC 25 |
17636035 ps |
| T389 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_partial_access_b2b.59906225 |
|
|
Feb 08 04:16:44 PM UTC 25 |
Feb 08 04:28:51 PM UTC 25 |
9098407090 ps |
| T390 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/16.sram_ctrl_bijection.4041356965 |
|
|
Feb 08 04:05:05 PM UTC 25 |
Feb 08 04:28:59 PM UTC 25 |
230780375052 ps |
| T391 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.3888264033 |
|
|
Feb 08 04:27:28 PM UTC 25 |
Feb 08 04:29:13 PM UTC 25 |
1968579901 ps |
| T392 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_access_during_key_req.2389994782 |
|
|
Feb 08 04:18:25 PM UTC 25 |
Feb 08 04:29:26 PM UTC 25 |
13778393804 ps |
| T393 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_partial_access_b2b.3671545803 |
|
|
Feb 08 04:24:04 PM UTC 25 |
Feb 08 04:29:33 PM UTC 25 |
39945813207 ps |
| T394 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access.890104721 |
|
|
Feb 08 04:29:26 PM UTC 25 |
Feb 08 04:29:38 PM UTC 25 |
2853003107 ps |
| T395 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_regwen.1459033041 |
|
|
Feb 08 04:13:05 PM UTC 25 |
Feb 08 04:29:42 PM UTC 25 |
18129405148 ps |
| T396 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_multiple_keys.4106215328 |
|
|
Feb 08 04:21:55 PM UTC 25 |
Feb 08 04:29:55 PM UTC 25 |
19465657101 ps |
| T397 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_throughput_w_partial_write.3851454984 |
|
|
Feb 08 04:29:43 PM UTC 25 |
Feb 08 04:29:55 PM UTC 25 |
2827242391 ps |
| T398 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_smoke.3926879451 |
|
|
Feb 08 04:28:38 PM UTC 25 |
Feb 08 04:30:08 PM UTC 25 |
2525207185 ps |
| T399 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_partial_access.3071181467 |
|
|
Feb 08 04:26:56 PM UTC 25 |
Feb 08 04:30:10 PM UTC 25 |
10160956119 ps |
| T400 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_ram_cfg.697676401 |
|
|
Feb 08 04:30:10 PM UTC 25 |
Feb 08 04:30:16 PM UTC 25 |
364290977 ps |
| T401 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_executable.1305852750 |
|
|
Feb 08 04:29:57 PM UTC 25 |
Feb 08 04:30:22 PM UTC 25 |
1717848702 ps |
| T402 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_executable.1376258383 |
|
|
Feb 08 04:25:25 PM UTC 25 |
Feb 08 04:30:34 PM UTC 25 |
19267208551 ps |
| T403 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_max_throughput.1047446938 |
|
|
Feb 08 04:29:38 PM UTC 25 |
Feb 08 04:30:49 PM UTC 25 |
2548520023 ps |
| T404 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_lc_escalation.2659256972 |
|
|
Feb 08 04:29:56 PM UTC 25 |
Feb 08 04:30:55 PM UTC 25 |
37034357439 ps |
| T405 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_alert_test.4082437262 |
|
|
Feb 08 04:30:55 PM UTC 25 |
Feb 08 04:30:57 PM UTC 25 |
13875506 ps |
| T406 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_regwen.3544129916 |
|
|
Feb 08 04:20:03 PM UTC 25 |
Feb 08 04:31:30 PM UTC 25 |
12285033798 ps |
| T407 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.1707716493 |
|
|
Feb 08 04:30:35 PM UTC 25 |
Feb 08 04:31:32 PM UTC 25 |
1805915212 ps |
| T408 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_smoke.202243816 |
|
|
Feb 08 04:30:58 PM UTC 25 |
Feb 08 04:31:33 PM UTC 25 |
774221297 ps |
| T409 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_access_during_key_req.1593534526 |
|
|
Feb 08 04:25:24 PM UTC 25 |
Feb 08 04:31:41 PM UTC 25 |
5884780875 ps |
| T410 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access.2271289004 |
|
|
Feb 08 04:31:42 PM UTC 25 |
Feb 08 04:32:01 PM UTC 25 |
2043565090 ps |
| T411 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_partial_access_b2b.1230702389 |
|
|
Feb 08 04:29:33 PM UTC 25 |
Feb 08 04:32:12 PM UTC 25 |
9560461904 ps |
| T412 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_max_throughput.1463003018 |
|
|
Feb 08 04:32:13 PM UTC 25 |
Feb 08 04:32:28 PM UTC 25 |
1418455517 ps |
| T413 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_walk.3536855748 |
|
|
Feb 08 04:30:17 PM UTC 25 |
Feb 08 04:33:31 PM UTC 25 |
21110383599 ps |
| T414 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_mem_partial_access.3187013094 |
|
|
Feb 08 04:30:23 PM UTC 25 |
Feb 08 04:33:46 PM UTC 25 |
20827784848 ps |
| T415 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_mem_walk.4204365202 |
|
|
Feb 08 04:26:29 PM UTC 25 |
Feb 08 04:33:51 PM UTC 25 |
86195414326 ps |
| T416 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_throughput_w_partial_write.181049734 |
|
|
Feb 08 04:32:28 PM UTC 25 |
Feb 08 04:33:56 PM UTC 25 |
808674958 ps |
| T417 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_multiple_keys.3598653446 |
|
|
Feb 08 04:28:52 PM UTC 25 |
Feb 08 04:34:18 PM UTC 25 |
16434742928 ps |
| T418 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_ram_cfg.3521850667 |
|
|
Feb 08 04:34:19 PM UTC 25 |
Feb 08 04:34:24 PM UTC 25 |
353913235 ps |
| T419 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/14.sram_ctrl_bijection.4266314492 |
|
|
Feb 08 03:55:34 PM UTC 25 |
Feb 08 04:34:29 PM UTC 25 |
45566368355 ps |
| T420 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/13.sram_ctrl_stress_all.3605240697 |
|
|
Feb 08 03:55:17 PM UTC 25 |
Feb 08 04:34:39 PM UTC 25 |
88337537002 ps |
| T421 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.180531482 |
|
|
Feb 08 04:34:40 PM UTC 25 |
Feb 08 04:34:55 PM UTC 25 |
3078358875 ps |
| T422 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_lc_escalation.1523006655 |
|
|
Feb 08 04:33:31 PM UTC 25 |
Feb 08 04:35:28 PM UTC 25 |
16052851913 ps |
| T423 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_alert_test.264496142 |
|
|
Feb 08 04:35:29 PM UTC 25 |
Feb 08 04:35:31 PM UTC 25 |
11781374 ps |
| T424 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_regwen.773103343 |
|
|
Feb 08 04:33:57 PM UTC 25 |
Feb 08 04:35:39 PM UTC 25 |
2077827192 ps |
| T425 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_pipeline.2338173463 |
|
|
Feb 08 04:29:13 PM UTC 25 |
Feb 08 04:35:56 PM UTC 25 |
20901298483 ps |
| T426 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_partial_access.2074138514 |
|
|
Feb 08 04:34:30 PM UTC 25 |
Feb 08 04:36:08 PM UTC 25 |
2504453382 ps |
| T427 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/12.sram_ctrl_stress_all.2941794324 |
|
|
Feb 08 03:51:08 PM UTC 25 |
Feb 08 04:36:45 PM UTC 25 |
305292499530 ps |
| T428 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_mem_walk.1284632688 |
|
|
Feb 08 04:34:25 PM UTC 25 |
Feb 08 04:36:47 PM UTC 25 |
1977677921 ps |
| T429 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_smoke.577587643 |
|
|
Feb 08 04:35:32 PM UTC 25 |
Feb 08 04:36:59 PM UTC 25 |
3935255321 ps |
| T430 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_throughput_w_partial_write.3039367223 |
|
|
Feb 08 04:37:00 PM UTC 25 |
Feb 08 04:37:13 PM UTC 25 |
2809733354 ps |
| T431 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access.807790327 |
|
|
Feb 08 04:36:45 PM UTC 25 |
Feb 08 04:37:28 PM UTC 25 |
793699896 ps |
| T432 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_stress_pipeline.312658428 |
|
|
Feb 08 04:31:35 PM UTC 25 |
Feb 08 04:37:38 PM UTC 25 |
5060584533 ps |
| T433 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_max_throughput.1142370098 |
|
|
Feb 08 04:36:47 PM UTC 25 |
Feb 08 04:37:53 PM UTC 25 |
3164581086 ps |
| T434 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_lc_escalation.563910557 |
|
|
Feb 08 04:37:14 PM UTC 25 |
Feb 08 04:38:36 PM UTC 25 |
64455245011 ps |
| T435 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_ram_cfg.3214989818 |
|
|
Feb 08 04:38:37 PM UTC 25 |
Feb 08 04:38:43 PM UTC 25 |
353516407 ps |
| T436 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_access_during_key_req.4268818553 |
|
|
Feb 08 04:33:47 PM UTC 25 |
Feb 08 04:40:31 PM UTC 25 |
21384765467 ps |
| T437 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_pipeline.2726756606 |
|
|
Feb 08 04:36:09 PM UTC 25 |
Feb 08 04:41:10 PM UTC 25 |
4276336610 ps |
| T438 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_alert_test.2607246859 |
|
|
Feb 08 04:41:11 PM UTC 25 |
Feb 08 04:41:13 PM UTC 25 |
36183804 ps |
| T439 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_partial_access_b2b.1641555260 |
|
|
Feb 08 04:32:02 PM UTC 25 |
Feb 08 04:41:14 PM UTC 25 |
20358382763 ps |
| T440 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_multiple_keys.814259398 |
|
|
Feb 08 04:31:32 PM UTC 25 |
Feb 08 04:41:18 PM UTC 25 |
22067805413 ps |
| T441 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_executable.853739645 |
|
|
Feb 08 04:37:39 PM UTC 25 |
Feb 08 04:41:25 PM UTC 25 |
20917095585 ps |
| T442 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.291866210 |
|
|
Feb 08 04:40:11 PM UTC 25 |
Feb 08 04:41:38 PM UTC 25 |
1751375935 ps |
| T443 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_smoke.364990298 |
|
|
Feb 08 04:41:14 PM UTC 25 |
Feb 08 04:41:46 PM UTC 25 |
6698859404 ps |
| T444 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access.36518327 |
|
|
Feb 08 04:41:38 PM UTC 25 |
Feb 08 04:41:50 PM UTC 25 |
1941987434 ps |
| T445 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_throughput_w_partial_write.958340150 |
|
|
Feb 08 04:41:51 PM UTC 25 |
Feb 08 04:42:01 PM UTC 25 |
699872563 ps |
| T446 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_max_throughput.558046874 |
|
|
Feb 08 04:41:46 PM UTC 25 |
Feb 08 04:42:03 PM UTC 25 |
738080879 ps |
| T447 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_partial_access.1087795558 |
|
|
Feb 08 04:39:53 PM UTC 25 |
Feb 08 04:42:50 PM UTC 25 |
18724784558 ps |
| T448 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_executable.3993026649 |
|
|
Feb 08 04:33:52 PM UTC 25 |
Feb 08 04:42:56 PM UTC 25 |
41576556202 ps |
| T449 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/17.sram_ctrl_bijection.3934612706 |
|
|
Feb 08 04:11:16 PM UTC 25 |
Feb 08 04:42:59 PM UTC 25 |
442537233465 ps |
| T450 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_ram_cfg.791231624 |
|
|
Feb 08 04:43:00 PM UTC 25 |
Feb 08 04:43:07 PM UTC 25 |
2413158940 ps |
| T451 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_lc_escalation.2957923116 |
|
|
Feb 08 04:42:02 PM UTC 25 |
Feb 08 04:43:38 PM UTC 25 |
14353238871 ps |
| T452 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_mem_walk.1893068974 |
|
|
Feb 08 04:38:45 PM UTC 25 |
Feb 08 04:43:41 PM UTC 25 |
30717767678 ps |
| T453 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.1113781013 |
|
|
Feb 08 04:43:41 PM UTC 25 |
Feb 08 04:44:17 PM UTC 25 |
749729168 ps |
| T454 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_alert_test.4292836537 |
|
|
Feb 08 04:44:18 PM UTC 25 |
Feb 08 04:44:20 PM UTC 25 |
67960855 ps |
| T455 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_smoke.2270397679 |
|
|
Feb 08 04:44:21 PM UTC 25 |
Feb 08 04:44:34 PM UTC 25 |
1092334076 ps |
| T456 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/15.sram_ctrl_bijection.1039017364 |
|
|
Feb 08 04:01:02 PM UTC 25 |
Feb 08 04:44:39 PM UTC 25 |
473393432052 ps |
| T457 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_stress_pipeline.1702247889 |
|
|
Feb 08 04:41:25 PM UTC 25 |
Feb 08 04:45:06 PM UTC 25 |
3376708271 ps |
| T458 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/21.sram_ctrl_bijection.1058007079 |
|
|
Feb 08 04:31:33 PM UTC 25 |
Feb 08 04:45:09 PM UTC 25 |
72155484850 ps |
| T459 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_regwen.1644728314 |
|
|
Feb 08 04:25:26 PM UTC 25 |
Feb 08 04:45:14 PM UTC 25 |
183941692635 ps |
| T460 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access.1300093464 |
|
|
Feb 08 04:45:07 PM UTC 25 |
Feb 08 04:45:39 PM UTC 25 |
1813039724 ps |
| T461 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_access_during_key_req.1875802251 |
|
|
Feb 08 04:29:56 PM UTC 25 |
Feb 08 04:45:45 PM UTC 25 |
13101622489 ps |
| T462 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_max_throughput.4145732755 |
|
|
Feb 08 04:45:15 PM UTC 25 |
Feb 08 04:45:46 PM UTC 25 |
2732083968 ps |
| T463 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_partial_access.138140777 |
|
|
Feb 08 04:43:39 PM UTC 25 |
Feb 08 04:45:57 PM UTC 25 |
1597154406 ps |
| T464 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_bijection.860819515 |
|
|
Feb 08 04:16:11 PM UTC 25 |
Feb 08 04:46:22 PM UTC 25 |
24933300355 ps |
| T465 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_ram_cfg.3722342876 |
|
|
Feb 08 04:46:23 PM UTC 25 |
Feb 08 04:46:29 PM UTC 25 |
678114088 ps |
| T466 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_lc_escalation.2860937998 |
|
|
Feb 08 04:45:46 PM UTC 25 |
Feb 08 04:46:47 PM UTC 25 |
12826056315 ps |
| T467 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_access_during_key_req.924104294 |
|
|
Feb 08 04:37:29 PM UTC 25 |
Feb 08 04:46:54 PM UTC 25 |
20658137558 ps |
| T468 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_mem_walk.2520144515 |
|
|
Feb 08 04:43:07 PM UTC 25 |
Feb 08 04:46:54 PM UTC 25 |
8967830178 ps |
| T469 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_throughput_w_partial_write.1098038898 |
|
|
Feb 08 04:45:40 PM UTC 25 |
Feb 08 04:46:55 PM UTC 25 |
825876122 ps |
| T470 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_alert_test.3014014544 |
|
|
Feb 08 04:46:56 PM UTC 25 |
Feb 08 04:46:58 PM UTC 25 |
14240769 ps |
| T471 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.3502624170 |
|
|
Feb 08 04:46:55 PM UTC 25 |
Feb 08 04:47:22 PM UTC 25 |
2168499437 ps |
| T472 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_multiple_keys.3253975413 |
|
|
Feb 08 04:44:26 PM UTC 25 |
Feb 08 04:47:36 PM UTC 25 |
2193887569 ps |
| T473 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access.896632962 |
|
|
Feb 08 04:47:37 PM UTC 25 |
Feb 08 04:47:48 PM UTC 25 |
989626136 ps |
| T474 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_partial_access_b2b.3258041831 |
|
|
Feb 08 04:36:46 PM UTC 25 |
Feb 08 04:47:53 PM UTC 25 |
24710252052 ps |
| T475 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_regwen.208891690 |
|
|
Feb 08 04:46:10 PM UTC 25 |
Feb 08 04:48:00 PM UTC 25 |
1565852116 ps |
| T476 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_smoke.1656335315 |
|
|
Feb 08 04:46:59 PM UTC 25 |
Feb 08 04:48:00 PM UTC 25 |
4851920073 ps |
| T477 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_partial_access.2449435358 |
|
|
Feb 08 04:46:48 PM UTC 25 |
Feb 08 04:48:09 PM UTC 25 |
4019649131 ps |
| T478 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_lc_escalation.1830923504 |
|
|
Feb 08 04:48:01 PM UTC 25 |
Feb 08 04:48:23 PM UTC 25 |
8659204076 ps |
| T479 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_stress_all.1316192878 |
|
|
Feb 08 04:30:50 PM UTC 25 |
Feb 08 04:48:43 PM UTC 25 |
193684722245 ps |
| T480 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_ram_cfg.3409506414 |
|
|
Feb 08 04:48:44 PM UTC 25 |
Feb 08 04:48:50 PM UTC 25 |
1400127608 ps |
| T481 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_max_throughput.234319723 |
|
|
Feb 08 04:47:54 PM UTC 25 |
Feb 08 04:49:00 PM UTC 25 |
1077881766 ps |
| T482 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_mem_walk.1300487822 |
|
|
Feb 08 04:46:30 PM UTC 25 |
Feb 08 04:49:14 PM UTC 25 |
2102204761 ps |
| T483 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_throughput_w_partial_write.2728015103 |
|
|
Feb 08 04:48:01 PM UTC 25 |
Feb 08 04:49:21 PM UTC 25 |
795923938 ps |
| T484 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_stress_pipeline.3223928689 |
|
|
Feb 08 04:44:39 PM UTC 25 |
Feb 08 04:49:24 PM UTC 25 |
3193504527 ps |
| T485 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_alert_test.1613638518 |
|
|
Feb 08 04:49:25 PM UTC 25 |
Feb 08 04:49:27 PM UTC 25 |
27495672 ps |
| T486 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_multiple_keys.1964065219 |
|
|
Feb 08 04:35:39 PM UTC 25 |
Feb 08 04:49:30 PM UTC 25 |
17492298803 ps |
| T487 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_regwen.3380108000 |
|
|
Feb 08 04:30:09 PM UTC 25 |
Feb 08 04:49:38 PM UTC 25 |
21937425719 ps |
| T488 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_partial_access_b2b.777036438 |
|
|
Feb 08 04:41:43 PM UTC 25 |
Feb 08 04:49:40 PM UTC 25 |
296002852333 ps |
| T489 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_smoke.1108686583 |
|
|
Feb 08 04:49:28 PM UTC 25 |
Feb 08 04:49:49 PM UTC 25 |
880604273 ps |
| T490 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_partial_access_b2b.495705192 |
|
|
Feb 08 04:45:10 PM UTC 25 |
Feb 08 04:49:50 PM UTC 25 |
6384168304 ps |
| T111 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.3679478540 |
|
|
Feb 08 04:49:15 PM UTC 25 |
Feb 08 04:49:55 PM UTC 25 |
1586402803 ps |
| T491 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/22.sram_ctrl_regwen.2244390286 |
|
|
Feb 08 04:37:53 PM UTC 25 |
Feb 08 04:50:12 PM UTC 25 |
13354317207 ps |
| T492 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_executable.1278823189 |
|
|
Feb 08 04:45:58 PM UTC 25 |
Feb 08 04:50:21 PM UTC 25 |
3847824933 ps |
| T493 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access.78994632 |
|
|
Feb 08 04:49:49 PM UTC 25 |
Feb 08 04:50:24 PM UTC 25 |
1711532389 ps |
| T494 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_max_throughput.4002127719 |
|
|
Feb 08 04:49:56 PM UTC 25 |
Feb 08 04:50:28 PM UTC 25 |
2954006834 ps |
| T495 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/19.sram_ctrl_bijection.1545063513 |
|
|
Feb 08 04:21:57 PM UTC 25 |
Feb 08 04:50:45 PM UTC 25 |
83947984491 ps |
| T496 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_throughput_w_partial_write.1075463549 |
|
|
Feb 08 04:50:14 PM UTC 25 |
Feb 08 04:50:48 PM UTC 25 |
1557493840 ps |
| T497 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_ram_cfg.3229624080 |
|
|
Feb 08 04:50:48 PM UTC 25 |
Feb 08 04:50:54 PM UTC 25 |
364141326 ps |
| T498 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/24.sram_ctrl_access_during_key_req.3591746913 |
|
|
Feb 08 04:45:47 PM UTC 25 |
Feb 08 04:51:27 PM UTC 25 |
6354093485 ps |
| T499 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_walk.1653090270 |
|
|
Feb 08 04:48:51 PM UTC 25 |
Feb 08 04:51:46 PM UTC 25 |
27733640360 ps |
| T500 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_alert_test.1394574662 |
|
|
Feb 08 04:51:47 PM UTC 25 |
Feb 08 04:51:49 PM UTC 25 |
32385754 ps |
| T501 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.70583060 |
|
|
Feb 08 04:51:03 PM UTC 25 |
Feb 08 04:51:59 PM UTC 25 |
7196435765 ps |
| T502 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_lc_escalation.4282159634 |
|
|
Feb 08 04:50:22 PM UTC 25 |
Feb 08 04:52:02 PM UTC 25 |
8056911576 ps |
| T503 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_mem_partial_access.1778324584 |
|
|
Feb 08 04:49:01 PM UTC 25 |
Feb 08 04:52:04 PM UTC 25 |
10058674682 ps |
| T504 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_partial_access.2939108110 |
|
|
Feb 08 04:50:55 PM UTC 25 |
Feb 08 04:52:19 PM UTC 25 |
1386798360 ps |
| T505 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_smoke.3460436818 |
|
|
Feb 08 04:51:50 PM UTC 25 |
Feb 08 04:52:35 PM UTC 25 |
796198533 ps |
| T506 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_partial_access.3182463622 |
|
|
Feb 08 04:52:19 PM UTC 25 |
Feb 08 04:52:46 PM UTC 25 |
11636910984 ps |
| T507 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_max_throughput.2003222633 |
|
|
Feb 08 04:52:47 PM UTC 25 |
Feb 08 04:53:16 PM UTC 25 |
7105873484 ps |
| T508 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_partial_access_b2b.1590175637 |
|
|
Feb 08 04:49:51 PM UTC 25 |
Feb 08 04:53:18 PM UTC 25 |
15936714359 ps |
| T509 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_stress_pipeline.556560092 |
|
|
Feb 08 04:47:34 PM UTC 25 |
Feb 08 04:53:24 PM UTC 25 |
10024991483 ps |
| T510 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_throughput_w_partial_write.3982799406 |
|
|
Feb 08 04:52:53 PM UTC 25 |
Feb 08 04:53:29 PM UTC 25 |
2970315492 ps |
| T511 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_lc_escalation.938725075 |
|
|
Feb 08 04:53:16 PM UTC 25 |
Feb 08 04:54:02 PM UTC 25 |
5569424264 ps |
| T512 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/20.sram_ctrl_bijection.1601764341 |
|
|
Feb 08 04:29:00 PM UTC 25 |
Feb 08 04:54:08 PM UTC 25 |
240118465256 ps |
| T513 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_ram_cfg.693324603 |
|
|
Feb 08 04:54:02 PM UTC 25 |
Feb 08 04:54:09 PM UTC 25 |
356999046 ps |
| T514 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_partial_access_b2b.1326940537 |
|
|
Feb 08 04:47:49 PM UTC 25 |
Feb 08 04:54:37 PM UTC 25 |
6299286226 ps |
| T515 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_access_during_key_req.761724013 |
|
|
Feb 08 04:50:25 PM UTC 25 |
Feb 08 04:54:44 PM UTC 25 |
16493783454 ps |
| T516 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_alert_test.4166956930 |
|
|
Feb 08 04:54:49 PM UTC 25 |
Feb 08 04:54:51 PM UTC 25 |
34944128 ps |
| T517 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.1234350339 |
|
|
Feb 08 04:54:38 PM UTC 25 |
Feb 08 04:55:24 PM UTC 25 |
1110066735 ps |
| T518 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_smoke.1528514125 |
|
|
Feb 08 04:54:52 PM UTC 25 |
Feb 08 04:55:37 PM UTC 25 |
2992312510 ps |
| T519 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_multiple_keys.3413068769 |
|
|
Feb 08 04:52:00 PM UTC 25 |
Feb 08 04:55:43 PM UTC 25 |
5699882009 ps |
| T520 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_partial_access.397970082 |
|
|
Feb 08 04:54:10 PM UTC 25 |
Feb 08 04:55:50 PM UTC 25 |
9681459139 ps |
| T521 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_stress_pipeline.560936259 |
|
|
Feb 08 04:49:41 PM UTC 25 |
Feb 08 04:55:51 PM UTC 25 |
4349258163 ps |
| T522 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_partial_access.4100261914 |
|
|
Feb 08 04:55:44 PM UTC 25 |
Feb 08 04:55:56 PM UTC 25 |
729806596 ps |
| T523 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_throughput_w_partial_write.755350555 |
|
|
Feb 08 04:55:57 PM UTC 25 |
Feb 08 04:56:18 PM UTC 25 |
725220676 ps |
| T524 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/25.sram_ctrl_regwen.1567261925 |
|
|
Feb 08 04:48:24 PM UTC 25 |
Feb 08 04:56:25 PM UTC 25 |
4974948418 ps |
| T525 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_max_throughput.2171204607 |
|
|
Feb 08 04:55:52 PM UTC 25 |
Feb 08 04:56:40 PM UTC 25 |
745331609 ps |
| T526 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/11.sram_ctrl_stress_all.1194060171 |
|
|
Feb 08 03:44:46 PM UTC 25 |
Feb 08 04:56:51 PM UTC 25 |
280898063347 ps |
| T527 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/10.sram_ctrl_stress_all.262955438 |
|
|
Feb 08 03:40:22 PM UTC 25 |
Feb 08 04:56:54 PM UTC 25 |
43041181254 ps |
| T528 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_stress_pipeline.2243986551 |
|
|
Feb 08 04:52:04 PM UTC 25 |
Feb 08 04:56:56 PM UTC 25 |
10246416558 ps |
| T529 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_ram_cfg.2008616960 |
|
|
Feb 08 04:56:55 PM UTC 25 |
Feb 08 04:57:01 PM UTC 25 |
360298870 ps |
| T530 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_lc_escalation.3828143348 |
|
|
Feb 08 04:56:18 PM UTC 25 |
Feb 08 04:57:09 PM UTC 25 |
5449270888 ps |
| T531 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_executable.524446932 |
|
|
Feb 08 04:42:51 PM UTC 25 |
Feb 08 04:57:23 PM UTC 25 |
7757883223 ps |
| T112 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.3980835419 |
|
|
Feb 08 04:57:11 PM UTC 25 |
Feb 08 04:57:26 PM UTC 25 |
286081775 ps |
| T532 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_alert_test.3820249638 |
|
|
Feb 08 04:57:24 PM UTC 25 |
Feb 08 04:57:27 PM UTC 25 |
15893844 ps |
| T533 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_multiple_keys.732656468 |
|
|
Feb 08 04:55:24 PM UTC 25 |
Feb 08 04:57:48 PM UTC 25 |
15197451926 ps |
| T534 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_smoke.1458359028 |
|
|
Feb 08 04:57:27 PM UTC 25 |
Feb 08 04:57:56 PM UTC 25 |
1693983948 ps |
| T535 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_partial_access.2577716793 |
|
|
Feb 08 04:57:02 PM UTC 25 |
Feb 08 04:58:10 PM UTC 25 |
3676962135 ps |
| T536 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_regwen.1981688428 |
|
|
Feb 08 04:42:56 PM UTC 25 |
Feb 08 04:58:15 PM UTC 25 |
26129527534 ps |
| T537 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_mem_walk.2284241009 |
|
|
Feb 08 04:50:49 PM UTC 25 |
Feb 08 04:58:24 PM UTC 25 |
82827302497 ps |
| T538 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_max_throughput.849413580 |
|
|
Feb 08 04:58:25 PM UTC 25 |
Feb 08 04:58:41 PM UTC 25 |
704065763 ps |
| T539 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_partial_access.490328937 |
|
|
Feb 08 04:58:11 PM UTC 25 |
Feb 08 04:58:48 PM UTC 25 |
3716909086 ps |
| T540 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_access_during_key_req.4043194976 |
|
|
Feb 08 04:53:19 PM UTC 25 |
Feb 08 04:59:17 PM UTC 25 |
25516478787 ps |
| T541 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/18.sram_ctrl_stress_all.653016456 |
|
|
Feb 08 04:21:03 PM UTC 25 |
Feb 08 04:59:22 PM UTC 25 |
115453490462 ps |
| T542 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_mem_walk.2330491553 |
|
|
Feb 08 04:54:08 PM UTC 25 |
Feb 08 04:59:31 PM UTC 25 |
16421640939 ps |
| T543 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/23.sram_ctrl_access_during_key_req.2357544062 |
|
|
Feb 08 04:42:05 PM UTC 25 |
Feb 08 04:59:41 PM UTC 25 |
140619527280 ps |
| T544 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_ram_cfg.335770303 |
|
|
Feb 08 04:59:43 PM UTC 25 |
Feb 08 04:59:48 PM UTC 25 |
690165729 ps |
| T545 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/27.sram_ctrl_regwen.499536893 |
|
|
Feb 08 04:53:30 PM UTC 25 |
Feb 08 04:59:55 PM UTC 25 |
4867031504 ps |
| T546 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/26.sram_ctrl_multiple_keys.3962519157 |
|
|
Feb 08 04:49:31 PM UTC 25 |
Feb 08 04:59:55 PM UTC 25 |
143817696716 ps |
| T547 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_throughput_w_partial_write.3715391250 |
|
|
Feb 08 04:58:42 PM UTC 25 |
Feb 08 04:59:56 PM UTC 25 |
1536576357 ps |
| T548 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_lc_escalation.3064493123 |
|
|
Feb 08 04:58:49 PM UTC 25 |
Feb 08 05:00:21 PM UTC 25 |
24404093021 ps |
| T549 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_alert_test.2360063814 |
|
|
Feb 08 05:00:22 PM UTC 25 |
Feb 08 05:00:24 PM UTC 25 |
17666258 ps |
| T550 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/29.sram_ctrl_access_during_key_req.685609704 |
|
|
Feb 08 04:59:17 PM UTC 25 |
Feb 08 05:00:24 PM UTC 25 |
4608770815 ps |
| T551 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_mem_walk.928424194 |
|
|
Feb 08 04:56:57 PM UTC 25 |
Feb 08 05:00:26 PM UTC 25 |
28830106752 ps |
| T552 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/30.sram_ctrl_smoke.4020756833 |
|
|
Feb 08 05:00:25 PM UTC 25 |
Feb 08 05:00:36 PM UTC 25 |
3314499653 ps |
| T553 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_stress_pipeline.1735100084 |
|
|
Feb 08 04:55:38 PM UTC 25 |
Feb 08 05:01:10 PM UTC 25 |
4816956222 ps |
| T554 |
/workspaces/repo/scratch/os_regression/sram_ctrl_main-sim-vcs/coverage/default/28.sram_ctrl_access_during_key_req.2603254766 |
|
|
Feb 08 04:56:25 PM UTC 25 |
Feb 08 05:01:17 PM UTC 25 |
7867242168 ps |